Preparation method of back contact solar cell

Abstract

The invention discloses a preparation method of a back contact solar cell, which comprises the following steps of: depositing a first tunneling oxide layer, a non-activated amorphous silicon layer containing a first doping element and a silicon oxide layer on a second surface of a silicon substrate, removing the non-activated amorphous silicon layer containing the first doping element and the silicon oxide layer in an E2 region and an E3 region, and annealing to obtain the back contact solar cell. And forming a first doped polycrystalline silicon layer and a silica glass layer containing a first doping element on the surface of the E1 region. According to the preparation method provided by the invention, the process steps of the back contact solar cell, especially the TBC cell, can be effectively optimized, the process time is shortened, the production cost is reduced, and commercialized popularization of the TBC cell is facilitated.

Description

Technical Field

[0001] The invention relates to the technical field of photovoltaic cell production, and in particular to a method for preparing a back-contact solar cell. Background Art

[0002] With the rapid development of crystalline silicon solar cells, more and more researchers have begun to focus on applying TOPCon technology to IBC cells in order to further improve the efficiency of solar cells. However, the preparation process of the currently known TBC solar cells (i.e., Tunneling Oxide Passivated Contact Back Contact) has problems such as long process flow, high production cost and unstable process, which seriously affects the improvement of efficiency and the stability of mass production. Therefore, it is expected to obtain a TBC solar cell preparation process with simplified process, reduced cost and increased conversion efficiency.

[0003] In the existing TBC battery preparation process, during the process of depositing a p-type doped polysilicon layer on the back, a borosilicate glass (BSG) layer will naturally form on the surface after annealing. In the subsequent preparation process, it is necessary to remove the BSG layer on the n-region and the isolation region by laser grooving. When the doping concentration or thickness of the BSG layer is high, the energy required for laser grooving is large, which can easily cause damage to the silicon substrate by the laser. On the other hand, in the subsequent texturing process, the BSG layer has a good blocking effect. When the doping concentration or thickness of the BSG layer is insufficient, it is difficult to ensure a good velvet effect. Summary of the invention

[0004] One of the purposes of the present invention is to overcome the above-mentioned defects in the prior art and provide a method for preparing a back-contact solar cell, which can form a silicon glass layer containing doping elements with a higher doping concentration while reducing the laser grooving loss, which is beneficial for subsequent velvet removal. At the same time, it avoids the excessively long annealing and oxidation time required when forming a thicker silicon glass layer.

[0005] To this end, the present invention provides a method for preparing a back-contact solar cell, comprising:

[0006] Step (A), providing a silicon substrate having a first surface and a second surface opposite to each other, wherein the second surface comprises an E1 region, an E2 region and an E3 region arranged alternately, and the E3 region is located between the E1 region and the E2 region;

[0007] Step (B), depositing a first tunneling oxide layer, an unactivated amorphous silicon layer containing a first doping element, and a silicon oxide layer in sequence on the second surface of the silicon substrate;

[0008] Step (C), removing the silicon oxide layer in the E2 region and the E3 region by laser;

[0009] Step (D), removing the first tunneling oxide layer and the amorphous silicon layer containing the first doping element in the regions E2 and E3 of the second surface of the silicon substrate;

[0010] Step (E), annealing the silicon substrate in an inert gas atmosphere to activate the first doping element in the amorphous silicon layer containing the first doping element, so that the amorphous silicon layer is transformed into a first doped polysilicon layer, and at the same time, the silicon oxide layer is transformed into a silicon glass layer containing the first doping element;

[0011] Step (F), forming a second tunneling oxide layer and a second doped polysilicon layer in the E2 region of the second surface of the silicon substrate; the second doped polysilicon layer and the first doped polysilicon layer have opposite conductivity types;

[0012] Further, the first doping element is a Group III A element or a Group VA element;

[0013] Furthermore, the silicon substrate is an n-type silicon substrate or a p-type silicon substrate.

[0014] In some embodiments, the deposition method in step (B) is a PECVD method.

[0015] In some embodiments, the thickness of the silicon oxide layer deposited in step (B) is 10-50 nm.

[0016] In some embodiments, the thickness of the first tunnel oxide layer deposited in step (B) is 0.5-3 nm.

[0017] In some embodiments, step (F) specifically comprises:

[0018] Step (F1), depositing a second tunneling oxide layer, a second doped polysilicon layer, and a silicon glass layer containing a second doping element in sequence on a second surface of the silicon substrate;

[0019] Step (F2), removing the silicon glass layer containing the second doping element in the regions E1 and E3 of the second surface of the silicon substrate;

[0020] Step (F3), removing the second tunneling oxide layer and the second doped polysilicon layer in the second surface E1 region and E3 region of the silicon substrate, and forming a velvet surface in the second surface E3 region;

[0021] Step (F4), removing the silicon glass layer containing the first doping element in the region E1 and the silicon glass layer containing the second doping element in the region E2 of the second surface of the silicon substrate.

[0022] In some embodiments, in step (B), while the first tunneling oxide layer, the amorphous silicon layer containing the first doping element, and the silicon oxide layer are sequentially deposited on the second surface of the silicon substrate, the first tunneling oxide layer, the amorphous silicon layer containing the first doping element, and the silicon oxide layer are also sequentially deposited on the first surface of the silicon substrate;

[0023] In step (D), the first tunneling oxide layer, the amorphous silicon layer containing the first doping element and the silicon oxide layer on the first surface of the silicon substrate are removed simultaneously.

[0024] In some embodiments, in step (F1), while sequentially depositing a second tunneling oxide layer, a second doped polysilicon layer, and a silicon glass layer containing a second doping element on a second surface of the silicon substrate, sequentially depositing a second tunneling oxide layer, a second doped polysilicon layer, and a silicon glass layer containing a second doping element on a first surface of the silicon substrate;

[0025] In step (F2), the silicon glass layer containing the second doping element on the first surface of the silicon substrate is removed simultaneously.

[0026] In some embodiments, in step (F3), while removing the second tunneling oxide layer and the second doped polysilicon layer in the E1 region and the E3 region of the second surface of the silicon substrate, the second tunneling oxide layer and the second doped polysilicon layer on the first surface of the silicon substrate are removed, and a velvet surface is formed on the first surface of the silicon substrate.

[0027] In some embodiments, after step (E), the method further comprises:

[0028] Step (E'), removing the silicon oxide layer formed on the first surface and the E2 and E3 regions on the second surface of the silicon substrate during the annealing process;

[0029] Furthermore, in step (E'), HF acid cleaning is used to remove the silicon oxide layer, the concentration of HF is 0.1%-5%, and the processing time is 10-200s, preferably 10-30s.

[0030] In some embodiments, the silicon substrate is subjected to double-sided texturing and / or double-sided polishing before step (A).

[0031] In some embodiments, after step (F), the method further comprises:

[0032] Step (G), depositing a front passivation anti-reflection layer and a back passivation anti-reflection layer on the first surface and the second surface of the silicon substrate obtained in step (F), respectively;

[0033] Step (H), preparing metal electrodes, disposing a first metal electrode and a second metal electrode in the E1 region and the E2 region respectively, wherein the first metal electrode passes through the back passivation anti-reflection layer and is directly connected to the first doped polysilicon layer, and the second metal electrode passes through the back passivation anti-reflection layer and is directly connected to the second doped polysilicon layer;

[0034] Further, the front passivation anti-reflection layer comprises one or more of aluminum oxide, silicon oxide, gallium oxide, silicon nitride, aluminum nitride, and silicon oxynitride, and the back passivation anti-reflection layer comprises one or more of aluminum oxide, silicon oxide, gallium oxide, silicon nitride, aluminum nitride, and silicon oxynitride;

[0035] Furthermore, the first metal electrode and the second metal electrode are one or more stacks of silver electrodes, silver alloy electrodes, copper electrodes, copper alloy electrodes, and nickel / copper / silver multilayer electrodes.

[0036] In another aspect, the present invention provides a back-contact solar cell manufactured according to the aforementioned method for manufacturing a back-contact solar cell.

[0037] Compared with the prior art, the present invention has the following beneficial effects:

[0038] (1) In an embodiment of the present invention, a first tunneling oxide layer, an unactivated amorphous silicon layer and a silicon oxide layer containing a first doping element are formed on the second surface of the silicon substrate, and the unactivated amorphous silicon layer and the silicon oxide layer containing the first doping element are removed from regions E2 and E3. After annealing, a first doped polysilicon layer and a silicon glass layer containing the first doping element are formed on the surface of region E1. The silicon glass layer containing the first doping element serves as a barrier layer for subsequent texturing. On the one hand, compared with the existing method of forming a silicon glass layer containing the first doping element on the entire second surface of the silicon substrate and then removing the silicon glass layer in the E2 and E3 regions, the preparation method provided in the embodiment of the present invention requires lower laser energy to remove the unactivated amorphous silicon layer and silicon oxide layer containing the first doping element corresponding to the E2 and E3 regions, which can avoid damage to the silicon substrate; on the other hand, the silicon glass layer containing the first doping element is obtained by diffusing the doping element in the doped polycrystalline silicon layer during annealing. Compared with the existing method of forming the silicon glass containing the first doping element at the same time as the first doped polycrystalline silicon layer is formed, the method provided in the embodiment of the present invention is more conducive to forming a thicker silicon glass layer in a shorter time, and can ensure the subsequent velvet removal effect while reducing the annealing and oxidation time.

[0039] (2) The preparation method provided in the embodiment of the present invention can effectively optimize the process steps of back-contact solar cells, especially TBC cells, shorten the process time, reduce the production cost, and facilitate the commercialization of TBC cells. BRIEF DESCRIPTION OF THE DRAWINGS

[0040] Figure 1A schematic diagram of the back contact solar cell structure of the present invention is shown;

[0041] Figure 2 The schematic diagram of the structure of the silicon substrate 10 of Example 1 after step (A) is shown;

[0042] Figure 3 The schematic diagram of the structure of the silicon substrate 10 of Example 1 after the steps (A to B) is shown;

[0043] Figure 4 The schematic diagram of the structure of the silicon substrate 10 of Example 1 after the steps (A to C) is shown;

[0044] Figure 5 The schematic diagram of the structure of the silicon substrate 10 of Example 1 after going through steps (A to D) is shown;

[0045] Figure 6 The schematic diagram of the structure of the silicon substrate 10 of Example 1 after going through steps (A to E) is shown;

[0046] Figure 7 The schematic diagram of the structure of the silicon substrate 10 of Example 1 after going through steps (A to F) is shown;

[0047] Figure 8 The schematic diagram of the structure of the silicon substrate 10 of Example 1 after the steps (A to G) is shown;

[0048] Fig. 9 The schematic diagram of the structure of the silicon substrate 10 of Example 1 after going through steps (A to H) is shown;

[0049] Fig.10 The schematic diagram of the structure of the silicon substrate 10 of Example 1 after the steps (A to I) is shown;

[0050] Fig.11 The schematic diagram of the structure of the silicon substrate 10 of Example 1 after going through steps (A to J) is shown;

[0051] Fig.12 The schematic diagram of the structure of the silicon substrate 10 of Example 1 after going through steps (A to K) is shown.

[0052] Description of the drawings: 10 - silicon substrate; 20 - first tunneling oxide layer; 30 - p-type doped polysilicon layer; 31 - inactivated boron-containing amorphous silicon layer; 32 - silicon oxide layer; 33 - BSG layer (borosilicate glass layer); 40 - second tunneling oxide layer; 50 - n-type doped polysilicon layer; 51 - PSG layer (phosphosilicate glass layer); 60 - front passivation anti-reflection layer; 70 - back passivation anti-reflection layer; 80 - first metal electrode; 90 - second metal electrode; E1 - p region; E2 - n region; E3 - isolation region. DETAILED DESCRIPTION

[0053] The present invention is further described in detail below in conjunction with the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are only used to explain the present invention and are not used to limit the present invention.

[0054] In the existing TBC battery preparation process, during the process of depositing a p-type doped polysilicon layer on the back, a borosilicate glass (BSG) layer will naturally form on the surface after annealing. In the subsequent preparation process, it is necessary to remove the BSG layer on the n-region and the isolation region by laser grooving. When the doping concentration or thickness of the BSG layer is high, the energy required for laser grooving is large, which can easily cause damage to the silicon substrate by the laser. On the other hand, in the subsequent texturing process, the BSG layer has a good blocking effect. When the doping concentration or thickness of the BSG layer is insufficient, it is difficult to ensure a good velvet effect.

[0055] In order to solve this problem, the technical solution of the present invention is proposed.

[0056] An embodiment of the present invention provides a method for preparing a back-contact solar cell, comprising:

[0057] Step (A), providing a silicon substrate having a first surface and a second surface opposite to each other, wherein the second surface comprises an E1 region, an E2 region and an E3 region arranged alternately, and the E3 region is located between the E1 region and the E2 region;

[0058] Step (B), depositing a first tunneling oxide layer, an unactivated amorphous silicon layer containing a first doping element, and a silicon oxide layer in sequence on the second surface of the silicon substrate;

[0059] Step (C), removing the silicon oxide layer in the E2 region and the E3 region by laser;

[0060] Step (D), removing the first tunneling oxide layer and the amorphous silicon layer containing the first doping element in the regions E2 and E3 of the second surface of the silicon substrate;

[0061] Step (E), annealing the silicon substrate in an inert gas atmosphere to activate the first doping element in the amorphous silicon layer containing the first doping element, so that the amorphous silicon layer is transformed into a first doped polysilicon layer, and at the same time, the silicon oxide layer is transformed into a silicon glass layer containing the first doping element;

[0062] Step (F), forming a second tunneling oxide layer and a second doped polysilicon layer in the E2 region of the second surface of the silicon substrate; the second doped polysilicon layer and the first doped polysilicon layer have opposite conductivity types;

[0063] Further, the first doping element is a Group IIIA element, such as B, Al, Ga, In, etc., or a Group VA element, such as N, P, As, Sb, etc.; since the conductivity types of the second doped polysilicon layer and the first doped polysilicon layer are opposite, when the first doping element is a Group IIIA element, the second doping element contained in the second doped polysilicon layer is a Group VA element, and vice versa;

[0064] Furthermore, the silicon substrate is an n-type silicon substrate or a p-type silicon substrate.

[0065] In some embodiments, the "first surface" refers to the major surface of the back-contact solar cell facing the sunlight, and the "second surface" refers to the major surface of the back-contact solar cell facing away from the sunlight.

[0066] In some embodiments, the E1 region on the second surface represents a p-type region of a back-contact solar cell, and the E2 region represents an n-type region of a back-contact solar cell; or vice versa, the E1 region on the second surface represents an n-type region of a back-contact solar cell, and the E2 region represents a p-type region of a back-contact solar cell. In some embodiments, the E3 region on the second surface represents an isolation region between the n-type region and the p-type region of the contact solar cell.

[0067] In some embodiments, an amorphous silicon layer containing the first doping element is deposited in step (B), and since no annealing treatment is performed in step (B), an unactivated amorphous silicon layer containing the first doping element is formed.

[0068] In some embodiments, the deposition method in step (B) is a PECVD method.

[0069] In some embodiments, the thickness of the silicon oxide layer deposited in step (B) is 10-50 nm.

[0070] In some embodiments, the thickness of the first tunnel oxide layer deposited in step (B) is 0.5-3 nm. In some embodiments, the first tunnel oxide layer is silicon oxide.

[0071] In some embodiments, the inert gas used for annealing in step (E) is nitrogen or a rare gas.

[0072] In some embodiments, step (F) specifically comprises:

[0073] Step (F1), depositing a second tunneling oxide layer, a second doped polysilicon layer, and a silicon glass layer containing a second doping element in sequence on a second surface of the silicon substrate;

[0074] Step (F2), removing the silicon glass layer containing the second doping element in the regions E1 and E3 of the second surface of the silicon substrate;

[0075] Step (F3), removing the second tunneling oxide layer and the second doped polysilicon layer in the second surface E1 region and E3 region of the silicon substrate, and forming a velvet surface in the second surface E3 region;

[0076] Step (F4), removing the silicon glass layer containing the first doping element in the region E1 and the silicon glass layer containing the second doping element in the region E2 of the second surface of the silicon substrate.

[0077] In some embodiments, the second tunneling oxide layer and the second doped polysilicon layer are made by one or more deposition methods selected from LPCVD, PECVD, PVD and ALD. In some embodiments, when forming the second doped polysilicon layer, a silicon glass layer containing the second doping element is naturally formed.

[0078] In some embodiments, the second tunnel oxide layer is silicon oxide and has a thickness of 0.5-3.0 nm.

[0079] In some embodiments, in step (F3), the velvet surface is formed by alkali cleaning and alkali solution treatment.

[0080] In some embodiments, in step (B), while the first tunneling oxide layer, the amorphous silicon layer containing the first doping element, and the silicon oxide layer are sequentially deposited on the second surface of the silicon substrate, the first tunneling oxide layer, the amorphous silicon layer containing the first doping element, and the silicon oxide layer are also sequentially deposited on the first surface of the silicon substrate;

[0081] In step (D), the first tunneling oxide layer, the amorphous silicon layer containing the first doping element and the silicon oxide layer on the first surface of the silicon substrate are removed simultaneously.

[0082] In some embodiments, in step (F1), while sequentially depositing a second tunneling oxide layer, a second doped polysilicon layer, and a silicon glass layer containing a second doping element on a second surface of the silicon substrate, sequentially depositing a second tunneling oxide layer, a second doped polysilicon layer, and a silicon glass layer containing a second doping element on a first surface of the silicon substrate;

[0083] In step (F2), the silicon glass layer containing the second doping element on the first surface of the silicon substrate is removed simultaneously.

[0084] In some embodiments, in step (F3), while removing the second tunneling oxide layer and the second doped polysilicon layer in the E1 region and the E3 region of the second surface of the silicon substrate, the second tunneling oxide layer and the second doped polysilicon layer on the first surface of the silicon substrate are removed, and a velvet surface is formed on the first surface of the silicon substrate.

[0085] In some embodiments, after step (E), the method further comprises:

[0086] Step (E'), removing the silicon oxide layer formed in the E2 region and the E3 region of the first surface and the second surface of the silicon substrate during the annealing process.

[0087] During the annealing process of the aforementioned step E, a layer of silicon oxide may be formed on the first surface of the n-type silicon substrate 10 and the E2 region and the E3 region of the second surface of the n-type silicon substrate 10. Therefore, an HF acid cleaning may be added after step (E) to remove the silicon oxide layer using HF acid cleaning. The HF concentration is 0.1% to 5%, and the processing time is 10 to 200 seconds, preferably 10 to 30 seconds.

[0088] In some embodiments, during HF acid cleaning, the difference in reaction rates between the silicon glass layer containing the first doping element and silicon oxide in a low concentration hydrofluoric acid solution is utilized to remove the silicon oxide layer on the E2 region and the E3 region of the first surface and the second surface, while ensuring that the silicon glass layer containing the first doping element on the E1 region of the second surface remains intact.

[0089] In some embodiments, the silicon substrate is subjected to double-sided texturing and / or double-sided polishing before step (A). In some embodiments, the specific processing methods are rough polishing, texturing, and polishing to form a morphological structure with a tower base on the second surface.

[0090] In some embodiments, after step (F), the method further comprises:

[0091] Step (G), depositing a front passivation anti-reflection layer and a back passivation anti-reflection layer on the first surface and the second surface of the silicon substrate obtained in step (F), respectively;

[0092] Step (H), preparing metal electrodes, disposing a first metal electrode and a second metal electrode in the E1 region and the E2 region respectively, wherein the first metal electrode passes through the back passivation anti-reflection layer and is directly connected to the first doped polysilicon layer, and the second metal electrode passes through the back passivation anti-reflection layer and is directly connected to the second doped polysilicon layer;

[0093] Further, the front passivation anti-reflection layer comprises one or more of aluminum oxide, silicon oxide, gallium oxide, silicon nitride, aluminum nitride, and silicon oxynitride, and the back passivation anti-reflection layer comprises one or more of aluminum oxide, silicon oxide, gallium oxide, silicon nitride, aluminum nitride, and silicon oxynitride;

[0094] Furthermore, the first metal electrode and the second metal electrode are one or more stacks of silver electrodes, silver alloy electrodes, copper electrodes, copper alloy electrodes, and nickel / copper / silver multilayer electrodes.

[0095] In another aspect, the present invention provides a back-contact solar cell manufactured according to the aforementioned method for manufacturing a back-contact solar cell.

[0096] The preparation method provided in the embodiment of the present invention is further described below by taking an n-type silicon substrate, a p-type E1 region, and an n-type E2 region as examples.

[0097] Example 1: A method for preparing a back contact solar cell

[0098] A method for preparing a back-contact solar cell, comprising:

[0099] Step (A), providing an n-type silicon substrate 10, and performing double-sided texturing and / or double-sided polishing on the n-type silicon substrate 10, such as Figure 2 As shown; wherein the silicon substrate 10 has a relative first surface and a second surface, and the second surface includes alternatingly arranged E1 regions (p regions), E2 regions (n ​​regions) and E3 regions (isolation regions); the specific method is rough polishing, texturing, and polishing to form the desired morphological structure with a tower base on the second surface of the n-type silicon substrate 10.

[0100] Step (B), depositing the first tunneling oxide layer 20, the unactivated boron-containing amorphous silicon layer 31 and the silicon oxide layer 32 in sequence on the second surface of the n-type silicon substrate 10 by a PECVD method, such as Figure 3 As shown, the first tunneling oxide layer 20 is silicon oxide with a thickness of 0.5-3.0 nm; the silicon oxide layer 32 has a thickness of 10-50 nm. At the same time, the first tunneling oxide layer 20, the unactivated boron-containing amorphous silicon layer 31 and the silicon oxide layer 32 are sequentially deposited on the first surface of the n-type silicon substrate.

[0101] Step (C), laser removal of the silicon oxide layer 32 in the E2 region and the E3 region, such as Figure 4 shown.

[0102] Step (D), single-side etching, HF acid cleaning to remove the silicon oxide layer 32 on the first surface of the n-type silicon substrate 10; polishing, alkali cleaning to remove the first tunneling oxide layer 20 / unactivated boron-containing amorphous silicon 31 layer on the first surface of the silicon substrate and the first tunneling oxide layer 20 / unactivated boron-containing amorphous silicon 31 layer in the E2 region and the E3 region of the second surface of the n-type silicon substrate 10, such as Figure 5 As shown;

[0103] Step (E), annealing the n-type silicon substrate 10 in a nitrogen atmosphere to activate the boron atoms in the unactivated boron-containing amorphous silicon layer 31, so that the unactivated boron-containing amorphous silicon layer 31 is transformed into a p-type doped polysilicon layer 30, and at the same time, the silicon oxide layer 32 is transformed into a BSG layer 33, such as Figure 6As shown; thereafter, HF acid with a concentration of 0.1% to 5% is used for cleaning for 10 to 30 seconds, and the difference in reaction rates between the BSG layer 33 and silicon oxide in a low concentration hydrofluoric acid solution is utilized to remove silicon oxide on the first surface of the n-type silicon substrate 10 and the E2 region and the E3 region of the second surface of the n-type silicon substrate 10, while ensuring that the BSG layer 33 on the E1 region of the second surface of the n-type silicon substrate 10 remains intact.

[0104] Step (F), a second tunneling oxide layer 40 and an n-type doped polysilicon layer 50 are sequentially formed on the second surface of the n-type silicon substrate 10. During the process of forming the n-type doped polysilicon layer 50, a PSG layer 51 is naturally formed. Figure 7 As shown, the second tunnel oxide layer 40 is silicon oxide with a thickness of 0.5-3.0 nm. At the same time, the second tunnel oxide layer 40, the n-type doped polysilicon layer 50 and the PSG layer 51 are sequentially deposited on the first surface of the n-type silicon substrate.

[0105] Laser removes the PSG layer 51 in the E1 region and the E3 region of the second surface of the n-type silicon substrate, such as Figure 8 shown.

[0106] HF acid cleaning to remove the PSG layer 51 on the first surface of the n-type silicon substrate 10;

[0107] Alkaline cleaning and texturing, alkaline solution treatment, remove the second tunneling oxide layer 40 and the n-type doped polysilicon layer 50 in the second surface E1 area and E3 area of ​​the n-type silicon substrate 10 and the second tunneling oxide layer 40 and the n-type doped polysilicon layer 50 on the first surface of the n-type silicon substrate 10, and at the same time form a velvet surface on the first surface of the n-type silicon substrate 10 and the second surface E3 area, such as Fig. 9 shown.

[0108] HF pickling removes the BSG layer 33 in the E1 region and the PSG layer 51 in the E2 region of the second surface of the n-type silicon substrate 10. Fig.10 shown.

[0109] Step (G), depositing a front passivation anti-reflection layer 60 and a back passivation anti-reflection layer 70 on the first surface and the second surface of the n-type silicon substrate 10, respectively. Fig.11 As shown; wherein, the front passivation anti-reflection layer 60 includes one or more of aluminum oxide, silicon oxide, gallium oxide, silicon nitride, aluminum nitride, and silicon oxynitride, and the back passivation anti-reflection layer 70 includes one or more of aluminum oxide, silicon oxide, gallium oxide, silicon nitride, aluminum nitride, and silicon oxynitride.

[0110] Step (H), preparing metal electrodes, and setting a first metal electrode 80 and a second metal electrode 90 in the E1 region and the E2 region, respectively, wherein the first metal electrode 80 passes through the back passivation anti-reflection layer 70 and is directly connected to the p-type doped polysilicon layer 30, and the second metal electrode 90 passes through the back passivation anti-reflection layer 70 and is directly connected to the n-type doped polysilicon layer 50, as shown in FIG. Fig.12 As shown; wherein, the first metal electrode 80 and the second metal electrode 90 are one or more stacks of silver electrodes, silver alloy electrodes, copper electrodes, copper alloy electrodes, nickel / copper / silver multilayer electrodes.

[0111] Comparative Example 1: A method for preparing a back contact solar cell

[0112] A method for preparing a back-contact solar cell, comprising:

[0113] Step (A), providing an n-type silicon substrate 10, and performing double-sided texturing and / or double-sided polishing on the n-type silicon substrate 10; wherein the silicon substrate 10 has a first surface and a second surface relative to each other, and the second surface includes an E1 region (p region), an E2 region (n region) and an E3 region (isolation region) arranged alternately; the specific method is rough polishing, texturing, and polishing to form the desired morphological structure with a tower base on the second surface of the n-type silicon substrate 10.

[0114] Step (B), depositing and annealing in sequence on the second surface of the n-type silicon substrate 10 to form a first tunneling oxide layer 20 and a p-type doped polysilicon layer 30. During the annealing process of forming the p-type doped polysilicon layer 30, a BSG layer 33 is naturally formed; wherein the first tunneling oxide layer 20 and the p-type doped polysilicon layer 30 are prepared by one or more deposition methods selected from LPCVD, PECVD, PVD and ALD; the first tunneling oxide layer 20 is silicon oxide, and its thickness is 0.5 to 3.0 nm.

[0115] Step (C): removing the BSG layer 33 in the E2 and E3 regions by laser.

[0116] Step (D), single-side etching, HF acid cleaning to remove the BSG layer 51 on the first surface of the n-type silicon substrate 10; polishing, alkali cleaning to remove the first tunneling oxide layer 20 / p-type doped polysilicon layer 30 on the first surface of the silicon substrate and the first tunneling oxide layer 20 / p-type doped polysilicon layer 30 in the E2 region and the E3 region of the second surface of the n-type silicon substrate 10;

[0117] Step (E), forming a second tunneling oxide layer 40 and an n-type doped polysilicon layer 50 in sequence on the second surface of the n-type silicon substrate 10. In the process of forming the n-type doped polysilicon layer 50, a PSG layer 51 is naturally formed; wherein the second tunneling oxide layer 40 and the n-type doped polysilicon layer 50 are prepared by one or more deposition methods selected from LPCVD, PECVD, PVD and ALD; the second tunneling oxide layer 40 is silicon oxide, and its thickness is 0.5 to 3.0 nm.

[0118] Step (F): removing the PSG layer 51 in the E1 region and the E3 region by laser.

[0119] HF acid cleaning to remove the PSG layer 51 on the first surface of the n-type silicon substrate 10;

[0120] Alkaline cleaning and texturing, alkaline solution treatment, remove the second tunneling oxide layer 40 and the n-type doped polysilicon layer 50 in the E1 area and E3 area of ​​the second surface of the n-type silicon substrate 10 and the second tunneling oxide layer 40 and the n-type doped polysilicon layer 50 on the first surface of the n-type silicon substrate 10, and at the same time form a texture surface on the first surface of the n-type silicon substrate 10 and in the E3 area of ​​the second surface.

[0121] The HF pickling removes the BSG layer 33 in the region E1 and the PSG layer 51 in the region E2 of the second surface of the n-type silicon substrate 10 .

[0122] Step (G), depositing a front passivation anti-reflection layer 60 and a back passivation anti-reflection layer 70 on the first surface and the second surface of the n-type silicon substrate 10, respectively; wherein the front passivation anti-reflection layer 60 includes at least one of aluminum oxide, silicon oxide, gallium oxide, silicon nitride, aluminum nitride, and silicon oxynitride, and the back passivation anti-reflection layer 70 includes at least one of aluminum oxide, silicon oxide, gallium oxide, silicon nitride, aluminum nitride, and silicon oxynitride.

[0123] Step (H), preparing metal electrodes, and setting a first metal electrode 80 and a second metal electrode 90 in the E1 region and the E2 region respectively, wherein the first metal electrode 80 passes through the back passivation anti-reflection layer 70 and is directly connected to the p-type doped polysilicon layer 30, and the second metal electrode 90 passes through the back passivation anti-reflection layer 70 and is directly connected to the n-type doped polysilicon layer 50; wherein the first metal electrode 80 and the second metal electrode 90 are one or more stacks of silver electrodes, silver alloy electrodes, copper electrodes, copper alloy electrodes, nickel / copper / silver multilayer electrodes.

[0124] Example 2: Comparison of electrical performance data of back-contact solar cells of Example 1 and Comparative Example 1

[0125] The back-contact solar cells prepared according to Example 1 and Comparative Example 1 were subjected to electrical performance tests, including: short-circuit current density (Jsc), open-circuit voltage (Voc), fill factor (FF) and conversion efficiency (Eta).

[0126] The results are shown in Table 1:

[0127] Table 1: Comparison of electrical performance data of back-contact solar cells of Example 1 and Comparative Example 1

[0128] <![CDATA[Jsc(mA / cm 2 )]]> Voc(mV) FF(%) Eta(%) Embodiment 1 43.28 734.5 81.38 25.87 Comparative Example 1 43.27 734.5 81.01 25.74

[0129] It can be seen that the back-contact solar cell of Example 1 has a higher fill factor and a higher conversion efficiency than that of Comparative Example 1.

Claims

1. A method for preparing a back contact solar cell, characterized in that: Include: Step (A), providing a silicon substrate (10), wherein the silicon substrate (10) has a first surface and a second surface opposite to each other, wherein the second surface includes an E1 region, an E2 region and an E3 region that are alternately arranged, and the E3 region is located between the E1 region and the E2 region; Step (B), depositing a first tunneling oxide layer (20), an unactivated amorphous silicon layer (31) containing a first doping element, and a silicon oxide layer (32) in sequence on the second surface of the silicon substrate (10); Step (C), removing the silicon oxide layer (32) in the E2 region and the E3 region by laser; Step (D), removing the first tunneling oxide layer (20) and the amorphous silicon layer (31) containing the first doping element in the E2 region and the E3 region of the second surface of the silicon substrate (10); Step (E), annealing the silicon substrate (10) in an atmosphere containing an inert gas to activate the first doping element in the amorphous silicon layer (31) containing the first doping element, so that the amorphous silicon layer (31) is transformed into a first doped polysilicon layer (30), and at the same time, the silicon oxide layer (32) is transformed into a silicon glass layer (33) containing the first doping element; Step (F), forming a second tunneling oxide layer (40) and a second doped polysilicon layer (50) in the E2 region of the second surface of the silicon substrate; the second doped polysilicon layer and the first doped polysilicon layer (30) have opposite conductivity types.

2. The method for preparing a back contact solar cell according to claim 1, characterized in that: The deposition method in step (B) is PECVD; Preferably, the thickness of the silicon oxide layer (32) deposited in step (B) is 10-50 nm; Preferably, the thickness of the first tunneling oxide layer (20) is 0.5-3 nm; Preferably, the first doping element is a Group 1IIA element or a Group VA element; Preferably, the silicon substrate (10) is an n-type silicon substrate.

3. The method for preparing a back contact solar cell according to claim 1, characterized in that: Step (F) specifically comprises: Step (F1), depositing the second tunneling oxide layer (40), the second doped polysilicon layer (50), and the silicon glass layer (51) containing the second doping element in sequence on the second surface of the silicon substrate (10); Step (F2), removing the silicon glass layer (51) containing the second doping element in the second surface E1 region and E3 region of the silicon substrate (10); Step (F3), removing the second tunneling oxide layer (40) and the second doped polysilicon layer (50) in the second surface E1 region and E3 region of the silicon substrate (10), and forming a velvet surface in the second surface E3 region; Step (F4), removing the silicon glass layer (33) containing the first doping element in the region E1 and the silicon glass layer (51) containing the second doping element in the region E2 of the second surface of the silicon substrate (10).

4. The method for preparing a back contact solar cell according to claim 1, characterized in that: In step (B), while a first tunneling oxide layer (20), an amorphous silicon layer (31) containing a first doping element, and a silicon oxide layer (32) are sequentially deposited on the second surface of the silicon substrate (10), a first tunneling oxide layer (20), an amorphous silicon layer (31) containing a first doping element, and a silicon oxide layer (32) are also sequentially deposited on the first surface of the silicon substrate (10); In step (D), the first tunneling oxide layer (20), the amorphous silicon layer (31) containing the first doping element and the silicon oxide layer (32) on the first surface of the silicon substrate (10) are removed simultaneously.

5. The method for preparing a back contact solar cell according to claim 3, characterized in that: In step (F1), while the second tunneling oxide layer (40), the second doped polysilicon layer (50), and the silicon glass layer (51) containing the second doping element are sequentially deposited on the second surface of the silicon substrate (10), the second tunneling oxide layer (40), the second doped polysilicon layer (50), and the silicon glass layer (51) containing the second doping element are sequentially deposited on the first surface of the silicon substrate (10); In step (F2), the silicon glass layer (51) containing the second doping element on the first surface of the silicon substrate (10) is removed simultaneously.

6. The method for preparing a back contact solar cell according to claim 5, characterized in that: In step (F3), while removing the second tunneling oxide layer (40) and the second doped polysilicon layer (50) in the E1 region and the E3 region of the second surface of the silicon substrate (10), the second tunneling oxide layer (40) and the second doped polysilicon layer (50) on the first surface of the silicon substrate (10) are removed, and a velvet surface is formed on the first surface of the silicon substrate (10).

7. The method for preparing a back contact solar cell according to claim 1, characterized in that: After step (E), the method further comprises: Step (E'), removing the silicon oxide layer formed on the first surface and the E2 region and the E3 region on the second surface of the silicon substrate (10) during the annealing process; Preferably, in step (E'), the silicon oxide layer is removed by cleaning with HF acid, the concentration of HF is 0.1%-5%, and the treatment time is 10-200s; Preferably, the processing time is 10-30s.

8. The method for preparing a back contact solar cell according to claim 1, characterized in that: The silicon substrate (10) has been subjected to double-sided texturing and / or double-sided polishing treatment before step (A).

9. The method for preparing a back contact solar cell according to claim 1, characterized in that: After step (F), the method further comprises: Step (G), depositing a front passivation anti-reflection layer (60) and a back passivation anti-reflection layer (70) on the first surface and the second surface of the silicon substrate (10) obtained in step (F); Step (H), preparing metal electrodes, and arranging a first metal electrode (80) and a second metal electrode (90) in the E1 region and the E2 region respectively, wherein the first metal electrode (80) passes through the back passivation anti-reflection layer (70) and is directly connected to the first doped polysilicon layer (30), and the second metal electrode (90) passes through the back passivation anti-reflection layer (70) and is directly connected to the second doped polysilicon layer (50); Preferably, the front passivation anti-reflection layer (60) comprises one or more of aluminum oxide, silicon oxide, gallium oxide, silicon nitride, aluminum nitride, and silicon oxynitride, and the back passivation anti-reflection layer (70) comprises one or more of aluminum oxide, silicon oxide, gallium oxide, silicon nitride, aluminum nitride, and silicon oxynitride; Preferably, the first metal electrode (80) and the second metal electrode (90) are one or more stacks of silver electrodes, silver alloy electrodes, copper electrodes, copper alloy electrodes, nickel / copper / silver multilayer electrodes.

10. A back-contact solar cell, prepared according to the method for preparing a back-contact solar cell according to any one of claims 1 to 9.

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