Solar cell and preparation method thereof
By designing the patterned finger structure and stacked structure on the back of the solar cell, the problem of easy destruction of the doped polysilicon layer during the metallization process is solved, excellent contact performance and passivation performance are achieved, and the conversion efficiency of the solar cell is improved.
Patent Information
- Application Number
- CN202411626271.8
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2024-11-14
- Publication Date
- 2025-03-25
AI Technical Summary
The doped polysilicon layer of existing solar cells is easily destroyed during the metallization process, resulting in excessive contact resistance. The thicker doped polysilicon layer will produce parasitic absorption, reduce short-flow and passivation performance, and affect conversion efficiency.
A solar cell is designed, with a patterned finger structure on the back of the N-type silicon substrate, including stacking a first tunneled oxide layer, a first phosphorus doped polysilicon layer, a second phosphorus doped polysilicon layer and a second phosphorus doped polysilicon layer in turn on the back of the N-type silicon substrate, and forming a silicon dioxide mask layer through ultraviolet laser patterning treatment to achieve differentiation between the metallized region and the non-metalized region.
This design effectively improves the contact performance and passivation performance of solar cells, reduces the absorption of short-wave light, improves the selectivity of holes, and increases short flow, thereby achieving high cell conversion efficiency.
Smart Images
Figure CN119698127A_ABST
Abstract
Description
Technical Field
[0001] The present invention relates to the field of solar energy technology, and in particular to a solar cell and a preparation method thereof. Background Art
[0002] Solar cells are devices that convert light into electrical energy through the photovoltaic effect. As a clean, safe and convenient renewable energy source, they have been widely used. Tunneling oxide passivation contact (TOPCon) technology is the new technology for solar cells with the highest production capacity. Chemical passivation and field passivation are achieved through the stacking of tunneling oxide layer and doped polysilicon layer on the back of the cell.
[0003] However, when the doped polysilicon layer on the back is thin, it is easily damaged by high temperature during the subsequent metallization process, resulting in excessive contact resistance, while a thicker doped polysilicon layer will produce more parasitic absorption, reduce short circuit current, affect passivation performance, and further affect the conversion efficiency of the solar cell. Therefore, there is an urgent need for a solar cell that can take into account both contact performance and passivation performance. Summary of the invention
[0004] Based on this, it is necessary to provide a solar cell and a method for preparing the same in view of the above problems. The solar cell provided by the present invention has excellent contact performance and passivation performance and has a wide application prospect.
[0005] A solar cell comprises an N-type silicon substrate, the back side of the N-type silicon substrate having a metallized region and a non-metallized region, a back electrode being arranged in the metallized region, the back side of the N-type silicon substrate comprising a first tunneling oxide layer, a first phosphorus-doped polysilicon layer and a passivation anti-reflection layer which are sequentially stacked, wherein in the metallized region, between the first phosphorus-doped polysilicon layer and the passivation anti-reflection layer, there is also a second tunneling oxide layer and a second phosphorus-doped polysilicon layer which are sequentially stacked on the surface of the first phosphorus-doped polysilicon layer.
[0006] In one embodiment, the thickness of the first tunnel oxide layer is greater than the thickness of the second tunnel oxide layer;
[0007] And / or, the thickness of the second phosphorus-doped polysilicon layer is greater than the thickness of the first phosphorus-doped polysilicon layer.
[0008] In one embodiment, the thickness of the first tunnel oxide layer is 0.8 nm to 2 nm;
[0009] And / or, the second tunnel oxide layer has a thickness of 0.1 nm to 0.7 nm.
[0010] In one embodiment, the thickness of the first phosphorus-doped polysilicon layer is 9 nm to 50 nm;
[0011] And / or, the thickness of the second phosphorus-doped polysilicon layer is 40 nm to 100 nm.
[0012] In one embodiment, the phosphorus doping concentrations of the first phosphorus doped polysilicon layer and the second phosphorus doped polysilicon layer are each independently selected from 2E20cm -3 ~4E20cm -3 .
[0013] In one embodiment, the width of the metallized area is 50 μm to 300 μm, and the width of the non-metallized area is 0.4 mm to 1.2 mm.
[0014] A method for preparing the solar cell as described above comprises the following steps:
[0015] The N-type silicon substrate after texturing is subjected to boron diffusion to form a p+ emitter on the front side of the N-type silicon substrate;
[0016] A first tunneling oxide layer, a first intrinsic amorphous silicon layer, a second tunneling oxide layer and a second intrinsic amorphous silicon layer are sequentially formed on the back side of the N-type silicon substrate, and the first intrinsic amorphous silicon layer and the second intrinsic amorphous silicon layer are respectively formed into a first phosphorus-doped polysilicon layer and a second phosphorus-doped polysilicon layer by phosphorus doping;
[0017] Cleaning once to remove the phosphosilicate glass layer and the phosphosilicate glass layer deposited around the surface of the second phosphorus-doped polysilicon layer;
[0018] Performing ultraviolet laser patterning under oxygen conditions to form a silicon dioxide mask layer on the metallized region on the surface of the second phosphorus-doped polysilicon layer;
[0019] Secondary cleaning to remove the silicon dioxide mask layer in the metallized area, the second tunneling oxide layer and the second phosphorus-doped polysilicon layer in the non-metallized area;
[0020] A passivation anti-reflection layer is plated on the front and back sides of the N-type silicon substrate;
[0021] A front electrode and a back electrode are prepared on the front and back of the N-type silicon substrate respectively.
[0022] In one of the embodiments, the thickness of the silicon dioxide mask layer is 5 nm to 30 nm.
[0023] In one of the embodiments, during the ultraviolet laser patterning process, the laser power is 3W to 60W, the speed is 35000mm / s to 60000mm / s, and the frequency is 300kHz to 900kHz.
[0024] In one embodiment, in the step of forming the first tunnel oxide layer, the deposition temperature is 590° C. to 620° C., and the time is 400 s to 600 s;
[0025] and / or, in the step of forming the first intrinsic amorphous silicon layer, the deposition temperature is 590° C. to 620° C., and the deposition time is 200 s to 800 s;
[0026] and / or, in the step of forming the second tunnel oxide layer, the deposition temperature is 590° C. to 620° C., and the deposition time is 100 s to 200 s;
[0027] and / or, in the step of forming the second intrinsic amorphous silicon layer, the deposition temperature is 590° C. to 620° C., and the deposition time is 800 s to 1500 s;
[0028] And / or, in the phosphorus doping step, the phosphorus source flow rate is 1300sccm~1800sccm, the oxidation flow rate is 450sccm~900sccm, first the temperature is kept at 800℃~840℃ for 950s~1200s, then the temperature is pushed to 890℃~930℃ for 900s~1300s, and finally oxidation is performed at 850℃~900℃ for 1300s~1600s.
[0029] The solar cell provided by the present invention has a patterned finger structure on the back side, which realizes the differentiation of the structure of the metallized area and the non-metallized area, and has the following three performance advantages: first, the first tunneling oxide layer and the first phosphorus-doped polysilicon layer on the entire back side provide the solar cell with necessary chemical passivation effect and field passivation effect, effectively ensuring the passivation performance of the solar cell; second, the finger structure of the metallized area provides a large debugging window for the metallization process, which is conducive to avoiding the phosphorus-doped polysilicon layer from being damaged during the metallization process, effectively improving the ohmic contact, and improving the contact performance of the solar cell; third, compared with the thicker phosphorus-doped polysilicon layer on the entire surface, the absorption of short-wave light is significantly reduced, thereby ensuring the selectivity of holes, improving the passivation performance, increasing the short current, and thus achieving high battery conversion efficiency. BRIEF DESCRIPTION OF THE DRAWINGS
[0030] In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings required for use in the embodiments or the description of the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments recorded in the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying creative work.
[0031] Figure 1 A schematic diagram of a solar cell structure in one embodiment;
[0032] Figure 2is a flow chart of step S1 of preparing a solar cell in one embodiment;
[0033] Figure 3 is a flow chart of steps S2 to S4 of preparing a solar cell in one embodiment;
[0034] Figure 4 FIG. 1 is a flow chart of steps S5 to S7 of preparing a solar cell in one embodiment.
[0035] Figure numerals: 1, N-type silicon substrate; 2, p+ emitter; 31, first tunneling oxide layer; 32, second tunneling oxide layer; 41, first phosphorus-doped polysilicon layer; 42, second phosphorus-doped polysilicon layer; 51, passivation layer; 52, anti-reflection layer; 61, front electrode; 62, back electrode; 7, phosphosilicate glass layer; 8, silicon dioxide mask layer; 9, borosilicate glass layer. DETAILED DESCRIPTION
[0036] For ease of understanding of the present invention, the present invention will be described in more detail below. However, it should be understood that the present invention can be implemented in many different forms and is not limited to the embodiments or examples described herein. On the contrary, the purpose of providing these embodiments or examples is to make the understanding of the disclosure of the present invention more thorough and comprehensive.
[0037] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as those generally understood by those skilled in the art of the present invention. The terms used herein in the specification of the present invention are only for the purpose of describing specific implementation methods or embodiments, and are not intended to limit the present invention. The optional scope of the term "and / or" used herein includes any one of two or more related listed items, and also includes any and all combinations of related listed items, and the combinations include any two related listed items, any more related listed items, or all related listed items.
[0038] like Figure 1 As shown, it is a TOPCon cell having the solar cell structure of the present invention, which includes an N-type silicon substrate 1, the back side of the N-type silicon substrate 1 has a metallized area and a non-metallized area, the back electrode 62 is arranged in the metallized area, and the back side of the N-type silicon substrate 1 includes a first tunneling oxide layer 31, a first phosphorus-doped polysilicon layer 41 and a passivation anti-reflection layer stacked in sequence, wherein in the metallized area, between the first phosphorus-doped polysilicon layer 41 and the passivation anti-reflection layer, it also includes a second tunneling oxide layer 32 and a second phosphorus-doped polysilicon layer 42 stacked in sequence on the surface of the first phosphorus-doped polysilicon layer 41.
[0039] The solar cell provided by the present invention has a patterned finger structure on the back side, which realizes the differentiation of the structure of the metallized area and the non-metallized area, and has the following three performance advantages: first, the first tunneling oxide layer 31 and the first phosphorus-doped polycrystalline silicon layer 41 on the entire back side provide the solar cell with necessary chemical passivation effect and field passivation effect, effectively ensuring the passivation performance of the solar cell; second, the first tunneling oxide layer 31, the first phosphorus-doped polycrystalline silicon layer 41, the second tunneling oxide layer 32, and the second phosphorus-doped polycrystalline silicon layer 42 stacked in the metallized area form a finger structure, which provides a larger debugging window for the metallization process, is conducive to avoiding the phosphorus-doped polycrystalline silicon layer from being damaged during the metallization process, effectively improves the ohmic contact, and improves the contact performance of the solar cell; third, compared with the thicker phosphorus-doped polycrystalline silicon layer on the entire surface, the absorption of short-wave light is significantly reduced, thereby ensuring the selectivity of holes, improving the passivation performance, increasing the short current, and thus achieving high battery conversion efficiency.
[0040] In one embodiment, the thickness of the first tunnel oxide layer 31 is greater than the thickness of the second tunnel oxide layer 32 .
[0041] Specifically, the thickness of the first tunneling oxide layer 31 is 0.8 nm to 2 nm, which is beneficial to further ensure the passivation performance of the solar cell. The thickness of the first tunneling oxide layer 31 includes but is not limited to any point value among 0.8 nm, 1 nm, 1.3 nm, 1.5 nm, 1.8 nm, 2 nm or a range value between any two of them.
[0042] Specifically, the thickness of the second tunneling oxide layer 32 is 0.1nm to 0.7nm, which is beneficial to further ensure the passivation performance of the solar cell and further improve the contact performance of the solar cell. The thickness of the second tunneling oxide layer 32 includes but is not limited to any point value among 0.1nm, 0.15nm, 0.3nm, 0.5nm, 0.6nm, 0.7nm or any range value between two thereof.
[0043] In one embodiment, the thickness of the second phosphorus-doped polysilicon layer 42 is greater than the thickness of the first phosphorus-doped polysilicon layer 41 .
[0044] Specifically, the thickness of the first phosphorus-doped polysilicon layer 41 is 9nm to 50nm, which is beneficial to ensuring the passivation performance of the solar cell. The thickness of the first phosphorus-doped polysilicon layer 41 includes but is not limited to any point value among 9nm, 10nm, 20nm, 30nm, 40nm, and 50nm, or a range value between any two of them.
[0045] Specifically, the thickness of the second phosphorus-doped polysilicon layer 42 is 40nm to 100nm, which is beneficial to ensuring the passivation performance of the solar cell and further improving the contact performance of the solar cell. The thickness of the second phosphorus-doped polysilicon layer 42 includes but is not limited to any point value among 40nm, 45nm, 50nm, 60nm, 80nm, 100nm or a range value between any two of them.
[0046] In one embodiment, the phosphorus doping concentrations of the first phosphorus doped polysilicon layer 41 and the second phosphorus doped polysilicon layer 42 are each independently selected from 2E20cm -3 ~4E20cm -3 .
[0047] It can be understood that the phosphorus doping concentrations of the first phosphorus-doped polysilicon layer 41 and the second phosphorus-doped polysilicon layer 42 can be the same or different. When the doping concentrations of the first phosphorus-doped polysilicon layer 41 and the second phosphorus-doped polysilicon layer 42 are different, the doping concentration of the first phosphorus-doped polysilicon layer 41 is less than the doping concentration of the second phosphorus-doped polysilicon layer 42. Phosphorus doping also exists in the second tunneling oxide layer 32. Since the thickness of the second tunneling oxide layer 32 is extremely thin, its phosphorus doping concentration can be ignored.
[0048] Specifically, the width of the metallized area is 50 μm to 300 μm, and the width of the non-metallized area is 0.4 mm to 1.2 mm.
[0049] like Figure 1 As shown, in one embodiment, the front side of the N-type silicon substrate 1 includes a stacked p+ emitter 2, a passivation anti-reflection layer and a front electrode 61.
[0050] It should be noted that the present invention has no special restrictions on the doping concentration of the p+ emitter 2; the passivation anti-reflection layer on the front and back of the solar cell of the present invention can be a stacked passivation layer 51 and an anti-reflection layer 52, or a passivation layer 51 or an anti-reflection layer 52.
[0051] In one embodiment, the passivation layer 51 is selected from aluminum oxide, silicon nitride or silicon oxynitride; and the anti-reflection layer 52 is selected from silicon nitride or silicon oxynitride.
[0052] It should be noted that the material and thickness of the back passivation anti-reflection layer and the front passivation anti-reflection layer may be the same or different.
[0053] In one embodiment, the front electrode 61 and the back electrode 62 are silver electrodes.
[0054] It is understandable that the present invention has no special limitation on the front structure of the solar cell. For example, the front of the N-type silicon substrate 1 may also include a tunneling oxide layer and a boron-doped polysilicon layer.
[0055] The present invention also provides a method for preparing the solar cell as described above, Figure 2 to Figure 4 FIG. 1 is a process flow chart of preparing TOPCon solar cells using the preparation method of the present invention, comprising the following steps:
[0056] S1, performing boron diffusion on the textured N-type silicon substrate 1 to form a p+ emitter 2 on the front side of the N-type silicon substrate 1;
[0057] S2, sequentially forming a first tunneling oxide layer 31, a first intrinsic amorphous silicon layer, a second tunneling oxide layer 32 and a second intrinsic amorphous silicon layer on the back side of the N-type silicon substrate 1, and forming the first intrinsic amorphous silicon layer and the second intrinsic amorphous silicon layer into a first phosphorus-doped polysilicon layer 41 and a second phosphorus-doped polysilicon layer 42 respectively by phosphorus doping;
[0058] S3, cleaning once to remove the phosphosilicate glass layer 7 and the phosphosilicate glass layer 7 deposited around the surface of the second phosphorus-doped polysilicon layer 42;
[0059] S4, performing ultraviolet laser patterning treatment under oxygen conditions to form a silicon dioxide mask layer 8 on the metallized area on the surface of the second phosphorus-doped polysilicon layer 42;
[0060] S5, secondary cleaning, removing the silicon dioxide mask layer 8 in the metallized area, the second tunneling oxide layer 32 and the second phosphorus-doped polysilicon layer 42 in the non-metallized area;
[0061] S6, plating a passivation anti-reflection layer on the front and back sides of the N-type silicon substrate 1;
[0062] S7. Prepare a front electrode 61 and a back electrode 62 on the front and back of the N-type silicon substrate 1 respectively.
[0063] Specifically, Figure 2 As shown, step 1 also includes: texturing the N-type silicon substrate 1 (step S11), front boron diffusion to form a p+ emitter 2 (step S12), post-oxidation (step S13), cleaning and removing the borosilicate glass layer 9 plated on both sides of the battery (step S14) and polishing (step S15). The above preparation steps are commonly used process methods in this field, and the present invention will not elaborate on them.
[0064] like Figure 3 As shown, the preparation method of the present invention first forms a stacked first tunnel oxide layer 31, a first phosphorus-doped polysilicon layer 41, a second tunnel oxide layer 32 and a second phosphorus-doped polysilicon layer 42 on the back side of an N-type silicon substrate 1, and then grows a patterned silicon dioxide mask layer 8 on the surface of the second phosphorus-doped polysilicon layer 42 by ultraviolet laser induction. Figure 4As shown, the silicon dioxide mask layer 8 is used as a mask in the secondary cleaning, so that the corrosion of the metallized area stops on the surface of the second phosphorus-doped polysilicon layer 42, and the corrosion of the non-metallic area stops on the surface of the first phosphorus-doped polysilicon layer 41, effectively realizing the differentiation of the structure of the metallized area and the non-metallized area, and effectively improving the contact performance and passivation performance of the manufactured solar cell.
[0065] It should be noted that the first tunnel oxide layer 31, the first phosphorus-doped polysilicon layer 41, the second tunnel oxide layer 32 and the second phosphorus-doped polysilicon layer 42 in the present invention can be prepared by an in-situ deposition process or a non-in-situ deposition process, and the present invention does not limit this.
[0066] In one embodiment, the LPCVD non-in-situ deposition process is used, and in the step of forming the first tunnel oxide layer, the deposition temperature is 590° C. to 620° C., and the time is 400 s to 600 s.
[0067] Specifically, in the step of forming the first intrinsic amorphous silicon layer, the deposition temperature is 590° C. to 620° C., and the deposition time is 200 s to 800 s.
[0068] Specifically, in the step of forming the second tunnel oxide layer, the deposition temperature is 590° C. to 620° C., and the deposition time is 100 s to 200 s.
[0069] Specifically, in the step of forming the second intrinsic amorphous silicon layer, the deposition temperature is 590° C. to 620° C., and the deposition time is 800 s to 1500 s.
[0070] Specifically, in the phosphorus doping step, the phosphorus source flow rate is 1300sccm~1800sccm, the oxidation flow rate is 450sccm~900sccm, firstly, the temperature is kept at 800℃~840℃ for 950s~1200s, then the temperature is pushed to 890℃~930℃ for 900s~1300s, and finally, it is oxidized at 850℃~900℃ for 1300s~1600s.
[0071] In one embodiment, the thickness of the silicon dioxide mask layer 8 is 5 nm to 30 nm.
[0072] In one embodiment, during the ultraviolet laser patterning process, the laser power is 3W to 60W, the speed is 35000mm / s to 60000mm / s, and the frequency is 300kHz to 900kHz.
[0073] Specifically, during the ultraviolet laser patterning process, the width of the laser window is 50 μm to 300 μm, and the sub-grid spacing is 0.4 mm to 1.2 mm.
[0074] It should be noted that step S6 and step S7 can be prepared according to existing methods, which will not be described in detail in the present invention.
[0075] Hereinafter, the solar cell and the preparation method thereof will be further described through the following specific embodiments.
[0076] Example 1
[0077] Step 1, texturing an N-type silicon substrate, the reaction time is 280s, the reaction temperature is 62°C, and the volume fractions of NaOH, texturing additives, and H2O in the texturing solution are 1%, 0.1%, and 98.9%, respectively;
[0078] Step 2, the N-type silicon substrate after step 1 is subjected to boron diffusion, with a deposition temperature of 800°C, a deposition time of 400s, a boron source flow rate of 100sccm, an oxidation flow rate of 490sccm, a nitrogen flow rate of 2200sccm, a push temperature of 900°C, and a time of 820s;
[0079] Step 3, post-oxidizing the N-type silicon substrate after step 2, with the oxidation temperature being 1030° C. and the time being 4000 s;
[0080] Step 4, modifying the N-type silicon substrate after step 3 with a borosilicate glass layer, and performing a tank cleaning for 100 seconds with a 5% by mass HF solution to remove the borosilicate glass layer plated on the side and back;
[0081] Step 5, polishing the back side of the N-type silicon substrate after step 4, the reaction temperature is 60°C, the time is 200s, the volume fractions of NaOH, polishing additive and H2O in the polishing solution are 1.9%, 1.35% and 96.75% respectively, and then low concentration HF cleaning is performed, wherein the volume ratio of HF:H2O is 1:300;
[0082] Step 6: After step 5, a first tunneling oxide layer, a first phosphorus-doped polysilicon layer, a second tunneling oxide layer, and a second phosphorus-doped polysilicon layer are sequentially grown on the back side of the N-type silicon substrate. The LPCVD non-in-situ deposition process is adopted. The deposition temperature of the first tunneling oxide layer is 595°C and the deposition time is 410s. The deposition temperature of the first intrinsic amorphous silicon layer is 600°C and the deposition time is 600s. The deposition temperature of the second tunneling oxide layer is 595°C and the deposition time is 120s. The deposition temperature of the second intrinsic amorphous silicon layer is 600°C and the deposition time is 1200s. Then, a phosphorus source is introduced for phosphorus doping. , the deposition temperature is 810℃, the deposition time is 1000s, the phosphorus source flow rate is 1400sccm, the oxidation flow rate is 500sccm, the advancement temperature is 900℃, the advancement time is 1000s, and then oxygen is introduced for post-oxidation. The post-oxidation temperature is 860℃, and the post-oxidation time is 1350s. The thickness of the first tunneling oxide layer is 1.0nm, the thickness of the first phosphorus-doped polysilicon layer is 30nm, the thickness of the second tunneling oxide layer is 0.3nm, and the thickness of the second phosphorus-doped polysilicon layer is 60nm. The doping concentration of the first phosphorus-doped polysilicon layer is 2.2E20cm -3 The doping concentration of the second phosphorus-doped polysilicon layer is 2.3E20cm -3 ;
[0083] Step 7, de-PSG the front side of the N-type silicon substrate after step 6, perform RCA cleaning on the back side, remove the phosphorus silicon glass layer on the surface of the second phosphorus-doped polysilicon layer, and the phosphorus silicon glass layer and phosphorus-doped polysilicon layer plated on the side and front side, the reaction temperature is 30°C, the time is 180s, the volume fractions of NaOH, polishing additives, and H2O in the polishing solution are 3.7%, 1.1%, and 95.2%, respectively, and then perform low-concentration HF cleaning, wherein the volume ratio of HF:H2O is 1:300;
[0084] Step 8, the back side of the N-type silicon substrate after step 7 is patterned by ultraviolet picosecond laser under oxygen-permeable conditions, with a power of 15 W, a speed of 45000 mm / s, and a frequency of 600 kHz, and the thickness of the metal area on the surface of the second phosphorus-doped polysilicon layer is a SiO2 layer with a thickness of 12 nm, wherein the width of the metal area is 300 μm, and the width of the non-metal area is 500 μm;
[0085] Step 9, performing RCA cleaning on the back side of the N-type silicon substrate after step 8 to remove the SiO2 layer in the metallized area, as well as the non-metal second tunneling oxide layer and the second phosphorus-doped polysilicon layer, the reaction temperature is 30°C, the time is 230s, the volume fractions of NaOH, polishing additives, and H2O in the polishing solution are 3.7%, 1.1%, and 95.2%, respectively, and then performing low-concentration HF cleaning, wherein the volume ratio of HF:H2O is 1:300;
[0086] Step 10, coating the N-type silicon substrate after step 9 with a passivation anti-reflection film, so that a laminated aluminum oxide layer and a silicon nitride layer are formed on the front and back of the battery;
[0087] Step 11, screen printing the N-type silicon substrate after step 10, using silver paste as the electrode material on both the front and back sides, using a matching screen printing on the back side of the screen, with the wet weight controlled at 50 mg, and using a 180 grid screen printing on the front side, with the wet weight controlled at 50 mg, and rapid sintering at 810°C.
[0088] Example 2
[0089] The difference between Example 2 and Example 1 is that in step 6, an LPCVD non-in-situ deposition process is adopted, the deposition temperature of the first tunnel oxide layer is 605°C, the deposition time is 450s, the deposition temperature of the first intrinsic amorphous silicon layer is 610°C, the deposition time is 650s, the deposition temperature of the second tunnel oxide layer is 605°C, the deposition time is 150s, the deposition temperature of the second intrinsic amorphous silicon layer is 610°C, the deposition time is 1300s, and then a phosphorus source is introduced for phosphorus doping, the deposition temperature is 820°C, and the deposition time is 11 00s, the phosphorus source flow rate is 1400sccm, the oxidation flow rate is 500sccm, the advancement temperature is 910℃, the advancement time is 1100s, and then oxygen is introduced for post-oxidation. The post-oxidation temperature is 870℃ and the post-oxidation time is 1400s. The thickness of the first tunneling oxide layer is 1.2nm, the thickness of the first phosphorus-doped polysilicon layer is 35nm, the thickness of the second tunneling oxide layer is 0.4nm, the thickness of the second phosphorus-doped polysilicon layer is 70nm, and the doping concentration of the first phosphorus-doped polysilicon layer is 2.4E20cm -3 The doping concentration of the second phosphorus-doped polysilicon layer is 2.5E20cm -3 .
[0090] Example 3
[0091] The difference between Example 3 and Example 1 is that in step 6, an LPCVD non-in-situ deposition process is adopted, the deposition temperature of the first tunneling oxide layer is 615°C, the deposition time is 500s, the deposition temperature of the first intrinsic amorphous silicon layer is 615°C, the deposition time is 700s, the deposition temperature of the second tunneling oxide layer is 615°C, the deposition time is 180s, the deposition temperature of the second intrinsic amorphous silicon layer is 615°C, the deposition time is 1400s, and then a phosphorus source is introduced for phosphorus doping, the deposition temperature is 830°C, and the deposition time is 11 50s, the phosphorus source flow rate is 1400sccm, the oxidation flow rate is 500sccm, the advancement temperature is 920℃, the advancement time is 1200s, and then oxygen is introduced for post-oxidation. The post-oxidation temperature is 880℃ and the post-oxidation time is 1450s. The thickness of the first tunneling oxide layer is 1.4nm, the thickness of the first phosphorus-doped polysilicon layer is 40nm, the thickness of the second tunneling oxide layer is 0.5nm, the thickness of the second phosphorus-doped polysilicon layer is 80nm, and the doping concentration of the first phosphorus-doped polysilicon layer is 2.5E20cm -3 The doping concentration of the second phosphorus-doped polysilicon layer is 2.7E20cm -3 .
[0092] Example 4
[0093] The difference between Example 4 and Example 1 is that in step 8, the back side of the N-type silicon substrate after step 7 is patterned by ultraviolet picosecond laser under oxygen conditions, with a power of 20 W, a speed of 60,000 mm / s, and a frequency of 600 kHz, and the thickness of the metal area on the surface of the second phosphorus-doped polysilicon layer is a SiO2 layer with a thickness of 15 nm, wherein the width of the metal area is 300 μm, and the width of the non-metal area is 500 μm.
[0094] Comparative Example 1
[0095] The difference between Comparative Example 1 and Example 1 is that, in step 6, the first tunneling oxide layer and the first phosphorus-doped polysilicon layer are grown only on the back side of the N-type silicon substrate; in step 8, the back side of the N-type silicon substrate is patterned by ultraviolet picosecond laser under oxygen conditions to remove the SiO2 layer in the metallized area and the first tunneling oxide layer and the first phosphorus-doped polysilicon layer in the non-metallized area.
[0096] The solar cells prepared in all the embodiments and comparative examples were subjected to IV tests to measure the conversion efficiency (Eta), open circuit voltage (Uoc), short circuit current (Isc) and fill factor (FF).
[0097] The performance test results of the solar cells prepared in all the embodiments and comparative examples are shown in Table 1:
[0098] Table 1
[0099] Eta(%) Uoc(V) Isc(A) FF(%) Example 1 26.48 0.7437 14.023 85.01 Example 2 26.48 0.7438 14.016 85.01 Example 3 26.45 0.7424 14.050 84.89 Example 4 26.43 0.7431 14.025 84.90 Comparative Example 1 26.27 0.7402 13.931 85.26
[0100] According to the performance test results in Table 1, under the same test conditions, the short-circuit current (Isc) and open-circuit voltage (Uoc) of the solar cells prepared in all embodiments are improved compared with the solar cells prepared in all comparative examples, and thus, the conversion efficiency (Eta) of the solar cells prepared in all embodiments is higher than the conversion efficiency of the solar cells prepared in all comparative examples. Therefore, the solar cell provided by the present invention effectively improves the contact performance and passivation performance of the back of the cell, improves the conversion efficiency of the cell, and has broad application prospects.
[0101] The technical features of the above-described embodiments may be arbitrarily combined. To make the description concise, not all possible combinations of the technical features in the above-described embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.
[0102] The above-mentioned embodiments only express several implementation methods of the present invention, and the descriptions thereof are relatively specific and detailed, but they cannot be understood as limiting the scope of the invention patent. It should be pointed out that, for ordinary technicians in this field, several variations and improvements can be made without departing from the concept of the present invention, and these all belong to the protection scope of the present invention. Therefore, the protection scope of the patent of the present invention shall be subject to the attached claims.
Claims
1. A solar cell, comprising an N-type silicon substrate, wherein the back side of the N-type silicon substrate has a metallized region and a non-metallized region, and a back electrode is arranged in the metallized region, characterized in that: The back side of the N-type silicon substrate includes a first tunneling oxide layer, a first phosphorus-doped polysilicon layer and a passivation anti-reflection layer stacked in sequence, wherein in the metallization region, between the first phosphorus-doped polysilicon layer and the passivation anti-reflection layer, there is also a second tunneling oxide layer and a second phosphorus-doped polysilicon layer stacked in sequence on the surface of the first phosphorus-doped polysilicon layer.
2. The solar cell according to claim 1, characterized in that The thickness of the first tunnel oxide layer is greater than the thickness of the second tunnel oxide layer; And / or, the thickness of the second phosphorus-doped polysilicon layer is greater than the thickness of the first phosphorus-doped polysilicon layer.
3. The solar cell according to claim 1 or 2, characterized in that: The thickness of the first tunneling oxide layer is 0.8 nm to 2 nm; And / or, the second tunnel oxide layer has a thickness of 0.1 nm to 0.7 nm.
4. The solar cell according to claim 1 or 2, characterized in that: The thickness of the first phosphorus-doped polysilicon layer is 9 nm to 50 nm; And / or, the thickness of the second phosphorus-doped polysilicon layer is 40 nm to 100 nm.
5. The solar cell according to claim 1, characterized in that: The phosphorus doping concentrations of the first phosphorus-doped polysilicon layer and the second phosphorus-doped polysilicon layer are each independently selected from 2E20cm -3 ~4E20cm -3 .
6. The solar cell according to claim 1, characterized in that The width of the metallized area is 50 μm to 300 μm, and the width of the non-metallized area is 0.4 mm to 1.2 mm.
7. A method for preparing a solar cell according to any one of claims 1 to 6, characterized in that: The steps include: The N-type silicon substrate after texturing is subjected to boron diffusion to form a p+ emitter on the front side of the N-type silicon substrate; A first tunneling oxide layer, a first intrinsic amorphous silicon layer, a second tunneling oxide layer and a second intrinsic amorphous silicon layer are sequentially formed on the back side of the N-type silicon substrate, and the first intrinsic amorphous silicon layer and the second intrinsic amorphous silicon layer are respectively formed into a first phosphorus-doped polysilicon layer and a second phosphorus-doped polysilicon layer by phosphorus doping; Cleaning once to remove the phosphosilicate glass layer and the phosphosilicate glass layer deposited around the surface of the second phosphorus-doped polysilicon layer; Performing ultraviolet laser patterning under oxygen conditions to form a silicon dioxide mask layer on the metallized region on the surface of the second phosphorus-doped polysilicon layer; Secondary cleaning to remove the silicon dioxide mask layer in the metallized area, the second tunneling oxide layer and the second phosphorus-doped polysilicon layer in the non-metallized area; A passivation anti-reflection layer is plated on the front and back sides of the N-type silicon substrate; A front electrode and a back electrode are prepared on the front and back of the N-type silicon substrate respectively.
8. The method for preparing a solar cell according to claim 7, characterized in that: The thickness of the silicon dioxide mask layer is 5nm-30nm.
9. The method for preparing a solar cell according to claim 7, characterized in that: During the ultraviolet laser patterning process, the laser power is 3W to 60W, the speed is 35000mm / s to 60000mm / s, and the frequency is 300kHz to 900kHz.
10. The method for preparing a solar cell according to claim 7, characterized in that: In the step of forming the first tunnel oxide layer, the deposition temperature is 590° C. to 620° C., and the time is 400 s to 600 s; and / or, in the step of forming the first intrinsic amorphous silicon layer, the deposition temperature is 590° C. to 620° C., and the deposition time is 200 s to 800 s; and / or, in the step of forming the second tunnel oxide layer, the deposition temperature is 590° C. to 620° C., and the deposition time is 100 s to 200 s; and / or, in the step of forming the second intrinsic amorphous silicon layer, the deposition temperature is 590° C. to 620° C., and the deposition time is 800 s to 1500 s; And / or, in the phosphorus doping step, the phosphorus source flow rate is 1300sccm~1800sccm, the oxidation flow rate is 450sccm~900sccm, first the temperature is kept at 800℃~840℃ for 950s~1200s, then the temperature is pushed to 890℃~930℃ for 900s~1300s, and finally oxidation is performed at 850℃~900℃ for 1300s~1600s.