Solar cell and preparation method thereof

Abstract

The invention relates to a solar cell and a preparation method thereof, the solar cell comprises an N-type silicon substrate, the back of the N-type silicon substrate is provided with a metallization area and a non-metallization area, and a back electrode is arranged in the metallization area. The metalized region comprises a tunneling oxide layer, a phosphorus-doped polycrystalline silicon layer and a passivation anti-reflection layer which are arranged in a laminated manner, the non-metalized region comprises a passivation anti-reflection layer, the thickness of the N-type silicon substrate corresponding to the metalized region is greater than that of the N-type silicon substrate corresponding to the non-metalized region, and the thickness difference is 1-3 microns. According to the solar cell, the problems that the thickness of the doped polycrystalline silicon layer in the non-metallization area is not uniform and the doped polycrystalline silicon layer remains are solved, the short current of the solar cell is effectively improved, and the conversion efficiency of the solar cell is stably improved.

Description

Technical Field

[0001] The present invention relates to the technical field of solar cells, and in particular to a solar cell and a preparation method thereof. Background Art

[0002] Solar cells are devices that convert light into electrical energy through the photovoltaic effect. As a clean, safe and convenient renewable energy source, they have been widely used. Tunneling oxide passivation contact (TOPCon) technology is the new technology for solar cells with the highest production capacity. Chemical passivation and field passivation are achieved through the stacking of tunneling oxide layer and doped polysilicon layer on the back of the cell.

[0003] However, the doped polysilicon layer on the entire back side will produce serious parasitic absorption of long-wavelength light, resulting in poor optical effects, reduced short-circuit current, and thus reduced conversion efficiency of solar cells. The industry usually reduces the parasitic absorption on the back side of solar cells by thinning the thickness of the doped polysilicon layer in the non-metallized area. However, it is difficult to accurately control the thickness of the doped polysilicon layer in the non-metallized area to maintain uniformity, and the corrosion surface of the non-metallized area is uneven after wet etching, and the non-metallized area near the junction of the metallized area and the non-metallized area is not corroded cleanly, resulting in unstable improvement of the conversion efficiency of solar cells.

[0004] Therefore, there is an urgent need for a solar cell that can effectively reduce parasitic absorption on the back side of the solar cell and has excellent conversion efficiency. Summary of the invention

[0005] Based on this, it is necessary to provide a solar cell and a method for preparing the same in view of the above problems. The solar cell of the present invention solves the problem of uneven thickness of the doped polysilicon layer in the non-metallized area and residual doped polysilicon layer, effectively improves the short circuit of the solar cell, and stably improves the conversion efficiency of the solar cell.

[0006] The present invention provides a solar cell, comprising an N-type silicon substrate, wherein the back side of the N-type silicon substrate comprises a metallized region and a non-metallized region, a back electrode is arranged in the metallized region, the metallized region comprises a tunneling oxide layer, a phosphorus-doped polysilicon layer, a first passivation layer and a first anti-reflection layer arranged in layers, and the non-metallized region comprises a second passivation layer and a second anti-reflection layer arranged in layers, wherein the thickness of the N-type silicon substrate corresponding to the metallized region is greater than the thickness of the N-type silicon substrate corresponding to the non-metallized region, and the thickness difference is 1 μm to 3 μm.

[0007] In one embodiment, the thickness of the tunnel oxide layer is 0.1 nm to 2 nm.

[0008] In one of the embodiments, the thickness of the phosphorus-doped polysilicon layer is 150 nm to 160 nm.

[0009] In one embodiment, the thickness of the first passivation layer and the second passivation layer is selected from 3nm to 8nm;

[0010] And / or, the thickness of the first anti-reflection layer and the second anti-reflection layer is selected from 60 nm to 140 nm.

[0011] In one embodiment, the width of the non-metallized area is 200 μm to 700 μm.

[0012] In one embodiment, the width of the metallized area is 200 μm to 700 μm.

[0013] The present invention also provides a method for preparing the solar cell as described above, comprising the following steps:

[0014] The N-type silicon substrate after texturing is subjected to boron diffusion to form a p+ emitter on the front side of the N-type silicon substrate;

[0015] Depositing a tunnel oxide layer and an intrinsic amorphous silicon layer in sequence on the back side of an N-type silicon substrate, and forming a phosphorus-doped polysilicon layer from the intrinsic amorphous silicon layer by phosphorus doping;

[0016] The back side of the N-type silicon substrate is subjected to laser patterning, a groove is formed on the back side by wet cleaning, and the back side and the surrounding phosphosilicate glass layer and the front side borosilicate glass layer are removed, wherein the groove penetrates the phosphorus-doped polysilicon layer and the tunneling oxide layer in the non-metallized area and extends to the N-type silicon substrate at a thickness of 1 μm to 3 μm;

[0017] A passivation layer and an anti-reflection layer are plated on the front and back sides of the N-type silicon substrate;

[0018] A back electrode and a front electrode are prepared on the back metallization area and the front side of the N-type silicon substrate respectively.

[0019] In one embodiment, in the laser patterning step, the width ratio of the patterning area to the mask area is 2:7 to 7:2.

[0020] In one embodiment, in the laser patterning step, the laser frequency is 200kHz to 600kHz, the laser power is 40% to 80%, the spot width is 150μm to 200μm, and the spot overlap rate is 0% to 50%.

[0021] In one embodiment, in the wet cleaning step, the RAC cleaning time is 250s to 460s and the temperature is 68°C to 72°C.

[0022] The above-mentioned solar cell has a patterned poly-finger structure on the back, which realizes the differentiation of the structure of the metallized area and the non-metallized area. In addition, there is a thickness difference of 1μm to 3μm between the N-type silicon substrate corresponding to the metallized area and the N-type silicon substrate corresponding to the non-metallized area, which effectively solves the problems of uneven thickness of the doped polysilicon layer and residual doped polysilicon layer in the non-metallized area, effectively improves the short circuit resistance of the solar cell, and stably improves the conversion efficiency of the solar cell. BRIEF DESCRIPTION OF THE DRAWINGS

[0023] In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings required for use in the embodiments or the description of the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments recorded in the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying creative work.

[0024] Figure 1 A schematic diagram of the structure of a solar cell in one embodiment of the present invention;

[0025] Figure 2 Schematic diagram of the solar cell structure obtained in step S3 in one embodiment of the present invention.

[0026] Figure numerals: 1-N-type silicon substrate; 2-borosilicate glass layer; 3-tunneling oxide layer; 4-phosphorus-doped polysilicon layer; 5-phosphosilicate glass layer; 6-laser area; 71-first passivation layer; 72-second passivation layer; 73-front passivation layer; 81-first anti-reflection layer; 82-second anti-reflection layer; 83-front anti-reflection layer; 9-front electrode; 10-back electrode. DETAILED DESCRIPTION

[0027] For ease of understanding of the present invention, the present invention will be described in more detail below. However, it should be understood that the present invention can be implemented in many different forms and is not limited to the embodiments or examples described herein. On the contrary, the purpose of providing these embodiments or examples is to make the understanding of the disclosure of the present invention more thorough and comprehensive.

[0028] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as those generally understood by those skilled in the art of the present invention. The terms used herein in the specification of the present invention are only for the purpose of describing specific implementation methods or embodiments, and are not intended to limit the present invention. The optional scope of the term "and / or" used herein includes any one of two or more related listed items, and also includes any and all combinations of related listed items, and the combinations include any two related listed items, any more related listed items, or all related listed items.

[0029] After long and in-depth research, the applicant found that in the poly-finger structure on the back of the solar cell obtained by the traditional preparation method, the thinning thickness of the doped polysilicon layer in the non-metallized area is difficult to accurately control and maintain uniformity, and the corrosion surface of the non-metallized area is uneven after wet etching, and the non-metallized area near the junction of the metallized area and the non-metallized area is not corroded cleanly, resulting in unstable effect of improving the conversion efficiency of the solar cell.

[0030] Based on this, the present invention provides a solar cell, which forms a patterned poly-finger structure on the back of the solar cell, and at the same time, makes the N-type silicon substrate corresponding to the metallized area and the N-type silicon substrate corresponding to the non-metallized area have a thickness difference of 1μm to 3μm, effectively solving the problems of uneven thickness of the doped polysilicon layer and residual doped polysilicon layer in the non-metallized area, effectively improving the short circuit current of the solar cell, and stably improving the conversion efficiency of the solar cell.

[0031] like Figure 1 As shown, a TOPCon cell having the solar cell structure of the present invention comprises an N-type silicon substrate 1, the back side of the N-type silicon substrate 1 having a metallized region and a non-metallized region, a back electrode 10 is arranged in the metallized region, the metallized region comprises a tunneling oxide layer 3, a phosphorus-doped polysilicon layer 4, a first passivation layer 71 and a first anti-reflection layer 81 arranged in a stacked manner, and the non-metallized region comprises a second passivation layer 72 and a second anti-reflection layer 82 arranged in a stacked manner, wherein the thickness of the N-type silicon substrate 1 corresponding to the metallized region is greater than the thickness of the N-type silicon substrate 1 corresponding to the non-metallized region, and the thickness difference is 1 μm to 3 μm.

[0032] In the above-mentioned solar cell, the thickness difference between the N-type silicon substrate 1 corresponding to the metallized area and the N-type silicon substrate 1 corresponding to the non-metallized area includes but is not limited to any point value among 1μm, 1.2μm, 1.5μm, 1.8μm, 2μm, 2.2μm, 2.5μm, 2.8μm, 3μm or any range value between two of them, which is beneficial to solve the problems of uneven thickness of the doped polysilicon layer and residual doped polysilicon layer in the non-metallized area, improve the short circuit of the solar cell, and effectively prevent the fill factor of the solar cell from being too small, thereby steadily improving the conversion efficiency of the solar cell.

[0033] It can be understood that the N-type silicon substrate 1 used in the present invention is a conventional N-type silicon substrate 1 in the art, and there is no special limitation on the thickness of the N-type silicon substrate 1. For example, the thickness of the conventional N-type silicon substrate 1 is 5 μm to 7 μm, and the thickness of the N-type silicon substrate 1 in the metal area is 5 μm to 7 μm, and the thickness of the N-type silicon substrate 1 in the non-metal area is 2 μm to 6 μm.

[0034] In one embodiment, the thickness of the tunnel oxide layer 3 is 0.1 nm to 2 nm.

[0035] In one embodiment, the phosphorus-doped polysilicon layer 4 has a thickness of 150 nm to 160 nm.

[0036] It is understandable that the present invention has no special limitation on the phosphorus doping concentration of the phosphorus doped polysilicon layer 4, and those skilled in the art may select it according to actual needs. In one embodiment, the phosphorus doping concentration of the phosphorus doped polysilicon layer 4 is 2E20cm ～3 ~4E20cm ～3 .

[0037] It should be noted that the first passivation layer 71 and the second passivation layer 72 of the present invention have the same material and thickness, and the first anti-reflection layer 81 and the second anti-reflection layer 82 have the same material and thickness.

[0038] Specifically, the first passivation layer 71 and the second passivation layer 72 are selected from aluminum oxide, silicon nitride or silicon oxynitride; the first anti-reflection layer 81 and the second anti-reflection layer 82 are selected from silicon nitride or silicon oxynitride.

[0039] In one embodiment, the thickness of the first passivation layer 71 and the second passivation layer 72 is selected from 3 nm to 8 nm;

[0040] In one embodiment, the thickness of the first anti-reflection layer 81 and the second anti-reflection layer 82 is selected from 60 nm to 140 nm.

[0041] In one embodiment, the width of the non-metallized area is 200 μm to 700 μm, including but not limited to any point value among 200 μm, 400 μm, 500 μm, 600 μm, 700 μm or any range value between two of them, which is beneficial to further enhance the parasitic absorption on the back side of the solar cell, improve the short circuit resistance of the solar cell, and further enhance the conversion efficiency of the solar cell.

[0042] In one embodiment, the width of the metallized area is 200 μm to 700 μm, including but not limited to any point value among 700 μm, 600 μm, 500 μm, 400 μm, 200 μm or any range value between two of them, which is beneficial to further enhance the parasitic absorption on the back side of the solar cell, improve the short circuit resistance of the solar cell, and at the same time help to ensure the passivation performance of the solar cell, thereby further improving the conversion efficiency of the solar cell.

[0043] In one embodiment, the back electrode 10 is a silver electrode.

[0044] like Figure 1 As shown, in one embodiment, the front surface of the N-type silicon substrate 1 includes a front passivation layer 73 , a front anti-reflection layer 83 and a front electrode 9 which are stacked.

[0045] It can be understood that the front side of the N-type silicon substrate 1 also includes a p+ emitter, and the present invention has no special restrictions on the doping concentration of the p+ emitter; the material and thickness of the front passivation layer 73 of the present invention and the first passivation layer 71 and the second passivation layer 72 on the back side can be the same or different; the material and thickness of the front anti-reflection layer 83 of the present invention and the first anti-reflection layer 81 and the second anti-reflection layer 82 on the back side can be the same or different.

[0046] In one embodiment, the front electrode 9 is a silver-aluminum electrode.

[0047] It is understandable that the present invention has no special limitation on the front structure of the solar cell. For example, the front of the N-type silicon substrate 1 may also include a tunneling oxide layer and a boron-doped polysilicon layer.

[0048] The present invention also provides a method for preparing the solar cell as described above, comprising the following steps:

[0049] S1, performing boron diffusion on the textured N-type silicon substrate 1 to form a p+ emitter on the front side of the N-type silicon substrate 1;

[0050] S2, depositing a tunneling oxide layer 3 and an intrinsic amorphous silicon layer in sequence on the back side of the N-type silicon substrate 1, and forming a phosphorus-doped polysilicon layer 4 from the intrinsic amorphous silicon layer by phosphorus doping;

[0051] S3, performing laser patterning on the back side of the N-type silicon substrate 1, forming a groove on the back side by wet cleaning, and removing the back side and the phosphosilicate glass layer 5 coated around and the borosilicate glass layer 2 on the front side, wherein the groove penetrates the phosphorus-doped polysilicon layer 4 and the tunneling oxide layer 3 in the non-metallized area, and extends to the 1 μm to 3 μm thickness of the N-type silicon substrate 1;

[0052] S4, coating a passivation layer and an anti-reflection layer on the front and back sides of the N-type silicon substrate;

[0053] S5. Prepare a back electrode 10 and a front electrode 9 on the back metallization area and the front side of the N-type silicon substrate respectively.

[0054] The above preparation method combines laser patterning and wet cleaning to achieve complete removal of the phosphorus-doped polysilicon layer 4 and the tunnel oxide layer 3 in the non-metallized area, and makes the etching until the N-type silicon substrate 1, and the etching thickness of the N-type silicon substrate 1 is 1μm to 3μm, thereby effectively realizing the differentiation of the structure of the metallized area and the non-metallized area, and effectively solving the problem of uneven thickness of the doped polysilicon layer in the non-metallized area and residual doped polysilicon layer, effectively improving the short circuit of the solar cell, and stably improving the conversion efficiency of the solar cell. In addition, the preparation method is simple in process, low in cost, and has broad application prospects.

[0055] In one embodiment, in step S1, the temperature during texturing is 70°C to 85°C, the time is 30s to 470s, and the contents of alkali, texturing additive, and H2O in the texturing reaction liquid are 0.9% to 4%, 0.09% to 1.2%, and 94.8% to 99.01%, respectively. The alkali is selected from NaOH, KOH, etc.

[0056] Preferably, the size of the prepared pyramids is 1.35 μm to 1.4 μm.

[0057] In one embodiment, in step S1, during boron diffusion, high-temperature oxidation is performed after boron diffusion is performed on the front side of the N-type silicon substrate 1, wherein the deposition temperature is 820°C to 870°C, the deposition time is 380s to 480s, the boron source flow rate is 200sccm to 400sccm, the oxygen flow rate is 500sccm to 1000sccm, the nitrogen flow rate is 2400sccm to 3500sccm, the advancement temperature is 910°C to 940°C, the advancement time is 800s to 1000s, the oxidation temperature is 1035°C to 1050°C, and the oxidation time is 3900s to 4500s.

[0058] It can be understood that after step S1, the borosilicate glass layer 2 on the back and sides of the N-type silicon substrate 1 is removed by cleaning, and the borosilicate glass layer 2 on the front of the N-type silicon substrate 1 is retained, and then the back of the N-type silicon substrate 1 is subjected to alkali polishing, the polishing time is 150s to 300s, the polishing temperature is 55°C to 70°C, and the contents of alkali, polishing additives, and H2O in the polishing liquid are 1.7% to 2.8%, 1.1% to 1.7%, and 95.5% to 97.1%, respectively, and the alkali is selected from NaOH, KOH, etc.

[0059] Preferably, after polishing, the reflectivity of the back side of the N-type silicon substrate 1 is 39% to 40%.

[0060] In one embodiment, in step S2, a tunneling oxide layer 3 and an intrinsic amorphous silicon layer are sequentially deposited on the back side of the N-type silicon substrate 1, the deposition temperature of the tunneling oxide layer 3 is 600°C to 620°C, the deposition time is 400s to 600s, the deposition temperature of the intrinsic amorphous silicon layer is 590°C to 620°C, and the deposition time is 1500s to 2300s; during phosphorus diffusion, the deposition temperature is 800°C to 830°C, the time is 900s to 1100s, the boron source flow rate is 1400sccm to 1800sccm, the oxidation flow rate is 500sccm to 1000sccm, the advancement temperature is 900°C to 940°C, the advancement time is 1000s to 1400s, the oxidation temperature is 860°C to 900°C, and the oxidation time is 1300s to 1600s.

[0061] like Figure 2 FIG. 2 is a schematic diagram of the structure of a solar cell obtained in step S3 in one embodiment of the present invention, wherein step S3 comprises:

[0062] Step S31, laser grooving the phosphorus-doped polysilicon layer 4 by laser, so that the phosphorus-doped polysilicon layer 4 in the laser area 6 (i.e., the non-metallized area) becomes loose;

[0063] Step S32, remove the phosphosilicate glass layer 5 coated on the side of the N-type silicon substrate 1 by chain cleaning, and then form a groove by RAC cleaning (industrial standard wet cleaning), completely remove the phosphorus-doped polysilicon layer 4 and the tunneling oxide layer 3 in the non-metallized area, and remove part of the N-type silicon substrate 1, so that the N-type silicon substrate 1 corresponding to the metallized area and the non-metallized area forms a thickness difference of 1μm to 3μm, and at the same time, remove the phosphosilicate glass layer 5 on the back side of the N-type silicon substrate 1, the phosphosilicate glass layer 5 coated on the front side, and the borosilicate glass layer 2 on the front side of the N-type silicon substrate 1.

[0064] Preferably, in the laser patterning step, the laser used is a picosecond laser.

[0065] In one embodiment, in the laser patterning step, the opening ratio of the patterning area to the mask area is 2:7 to 7:2.

[0066] In one embodiment, in the laser patterning step, the laser frequency is 200kHz to 600kHz, the laser power is 40% to 80%, the spot width is 150μm to 200μm, and the spot overlap rate is 0% to 50%, which is beneficial to improve the uniformity of the laser spot energy and improve the removal effect of the phosphorus-doped polysilicon layer 4, thereby further improving the short circuit of the solar cell and stably improving the conversion efficiency of the solar cell.

[0067] In one embodiment, in the wet cleaning step, the RAC cleaning time is 250s to 460s and the temperature is 68°C to 72°C.

[0068] Specifically, in the RCA cleaning solution, the contents of alkali, RCA additive, and H2O are 3.5% to 4.5%, 0.8% to 1.5%, and 94% to 95.7%, respectively, and the alkali is selected from NaOH, KOH, and the like.

[0069] In one embodiment, during RAC pickling, high concentration HF cleaning is performed and low concentration HF dehydration is performed, wherein the concentration range of high concentration HF is 28% to 30%, and the cleaning time is 100s to 120s; the concentration range of low concentration HF is 8% to 10%, and the cleaning time is 100s to 120s.

[0070] It should be noted that step S4 and step S5 can be prepared according to existing methods, which will not be described in detail in the present invention.

[0071] The solar cell and the method for preparing the same will be further described below by the following specific examples. However, those skilled in the art will appreciate that the following examples are only used to illustrate the present invention and should not be considered to limit the scope of the present invention. If no specific conditions are specified in the examples, the conventional conditions or the conditions recommended by the manufacturer are followed. If the manufacturer of the reagents or instruments used is not specified, they are all conventional products that can be purchased commercially.

[0072] Example 1

[0073] Step 1: Texturing an N-type silicon substrate, the reaction time is 420s, the reaction temperature is 82°C, the contents of NaOH, texturing additives, and H2O in the texturing solution are 1.1%, 0.42%, and 98.48%, respectively, and the pyramid size of the velvet surface is 1.35μm to 1.4μm;

[0074] Step 2, the front side of the N-type silicon substrate obtained in step 1 is subjected to boron diffusion and then oxidation, the diffusion boron source is BCl3, the reaction temperature is 850°C, the reaction time is 410s, the oxidation temperature is 1049°C, and the reaction time is 4740s;

[0075] Step 3, remove BSG from the N-type silicon substrate obtained in step 2, and perform alkali polishing. The conductivity of the first cleaning solution for removing BSG is 260μs / cm-350μs / cm, and the conductivity of the second cleaning solution is 150μs / cm-220μs / cm. The alkali polishing reaction time is 120s, the reaction temperature is 61°C, the contents of NaOH, polishing additives, and H2O in the polishing solution are 2.4%, 0.3%, and 97.3%, respectively, and the reflectivity of the back of the N-type silicon substrate after alkali polishing is 39.93%;

[0076] Step 4, deposit a tunneling oxide layer, an intrinsic amorphous silicon layer and phosphorus diffusion on the N-type silicon substrate obtained in step 3. The deposition temperature of the tunneling oxide layer growth is 600°C, the reaction time is 400s, the deposition temperature of the intrinsic amorphous silicon layer is 606°C, the reaction time is 1500s, the thickness of the tunneling oxide layer is 0.1nm~2nm, and the thickness of the amorphous silicon layer is 150nm. The deposition temperature of phosphorus diffusion is 800°C, the time is 900s, the boron source flow rate is 1400sccm, the oxidation flow rate is 500sccm, the advancement temperature is 900°C, the time is 1000s, the oxidation temperature is 860°C, and the time is 1300s;

[0077] Step 5, laser patterning the N-type silicon substrate obtained in step 4. Using a picosecond laser, the laser frequency is 333kHz, the laser power is 50%, the spot width is 150μm, the spot overlap rate is 50%, the slot ratio of the patterned area to the mask area is 7:2, the width of the non-metallized area is 700μm, and the width of the metallized area is 200μm;

[0078] Step 6, wet-cleaning the N-type silicon substrate obtained in step 5. The conductivity of the cleaning solution for removing the PSG layer is 30μs / cm-40μs / cm, the RCA cleaning time is 310s, the temperature is 70°C, and the contents of NaOH, RCA additive, and H2O in the RAC cleaning solution are 3.9%, 0.76%, and 95.34%, respectively, so that a height difference of 3μm is formed between the metallized area and the non-metallized area of ​​the N-type silicon substrate;

[0079] Step 7: The N-type silicon substrate obtained in step 6 is subjected to passivation layer coating, and a 3.5nm aluminum oxide layer and a 75nm silicon nitride layer are formed on the front side of the battery, and a 3.5nm aluminum oxide layer and an 85nm silicon nitride layer are formed on the back side;

[0080] Step 8: Screen print the N-type silicon substrate obtained in step 7, use silver-aluminum paste to form a positive electrode on the front side of the battery, and use silver paste to form a negative electrode on the back side.

[0081] Example 2

[0082] Step 1: Texturing an N-type silicon substrate, the reaction time is 420s, the reaction temperature is 82°C, the contents of NaOH, texturing additives, and H2O in the texturing solution are 1.1%, 0.42%, and 98.48%, respectively, and the pyramid size of the velvet surface is 1.35μm to 1.4μm;

[0083] Step 2, the front side of the N-type silicon substrate obtained in step 1 is subjected to boron diffusion and then oxidation, the diffusion boron source is BCl3, the reaction temperature is 850°C, the reaction time is 410s, the oxidation temperature is 1049°C, and the reaction time is 4740s;

[0084] Step 3, remove BSG from the N-type silicon substrate obtained in step 2, and perform alkali polishing. The conductivity of the first cleaning solution for removing BSG is 260μs / cm-350μs / cm, and the conductivity of the second cleaning solution is 150μs / cm-220μs / cm. The alkali polishing reaction time is 120s, the reaction temperature is 61°C, the contents of NaOH, polishing additives, and H2O in the polishing solution are 2.4%, 0.3%, and 97.3%, respectively, and the reflectivity of the back of the N-type silicon substrate after alkali polishing is 39.93%;

[0085] Step 4, deposit a tunneling oxide layer, an intrinsic amorphous silicon layer and phosphorus diffusion on the N-type silicon substrate obtained in step 3. The deposition temperature of the tunneling oxide layer growth is 600°C, the reaction time is 400s, the deposition temperature of the intrinsic amorphous silicon layer is 609°C, the reaction time is 1500s, the thickness of the tunneling oxide layer is 0.1nm~2nm, and the thickness of the amorphous silicon layer is 160nm. The deposition temperature of phosphorus diffusion is 800°C, the time is 900s, the boron source flow rate is 1400sccm, the oxidation flow rate is 500sccm, the advancement temperature is 900°C, the time is 1000s, the oxidation temperature is 860°C, and the time is 1300s;

[0086] Step 5, laser patterning the N-type silicon substrate obtained in step 4. Using a picosecond laser, the laser frequency is 600kHz, the laser power is 80%, the spot width is 150μm, the laser overlap rate is 0, the grooving ratio of the patterned area to the mask area is 6:3, the width of the non-metallized area is 600μm, and the width of the metallized area is 300μm;

[0087] Step 6, wet-cleaning the N-type silicon substrate obtained in step 5. The conductivity of the cleaning solution for removing the PSG layer is 30-40 μs / cm, the RCA cleaning time is 250 s, the temperature is 71°C, and the contents of NaOH, RCA additive, and H2O in the RAC cleaning solution are 3.9%, 0.76%, and 95.34%, respectively, so that a height difference of 2 μm is formed between the metallized area and the non-metallized area of ​​the N-type silicon substrate;

[0088] Step 7: The N-type silicon substrate obtained in step 6 is subjected to passivation layer coating, and a 3.5nm aluminum oxide layer and a 75nm silicon nitride layer are formed on the front side of the battery, and a 3.5nm aluminum oxide layer and a 90nm silicon nitride layer are formed on the back side;

[0089] Step 8: Screen print the N-type silicon substrate obtained in step 7. Use silver-aluminum paste to form the positive electrode on the front side of the battery, and use silver paste to form the negative electrode on the back side.

[0090] Example 3

[0091] Step 1: Texturing an N-type silicon substrate, the reaction time is 420s, the reaction temperature is 82°C, the contents of NaOH, texturing additives, and H2O in the texturing solution are 1.1%, 0.42%, and 98.48%, respectively, and the pyramid size of the velvet surface is 1.35μm to 1.4μm;

[0092] Step 2, the front side of the N-type silicon substrate obtained in step 1 is subjected to boron diffusion and then oxidation, the diffusion boron source is BCl3, the reaction temperature is 850°C, the reaction time is 410s, the oxidation temperature is 1049°C, and the reaction time is 4740s;

[0093] Step 3, remove BSG from the N-type silicon substrate obtained in step 2, and perform alkali polishing. The conductivity of the first cleaning solution for removing BSG is 260μs / cm-350μs / cm, and the conductivity of the second cleaning solution is 150μs / cm-220μs / cm. The alkali polishing reaction time is 120s, the reaction temperature is 61°C, and the contents of NaOH, polishing additives, and H2O in the polishing solution are 2.4%, 0.3%, and 97.3%, respectively. The reflectivity of the N-type silicon substrate after alkali polishing is 39.93%;

[0094] Step 4, deposit a tunneling oxide layer, an intrinsic amorphous silicon layer and phosphorus diffusion on the N-type silicon substrate obtained in step 3. The deposition temperature of the tunneling oxide layer growth is 600°C, the reaction time is 400s, the deposition temperature of the intrinsic amorphous silicon layer is 606°C, the reaction time is 1500s, the thickness of the tunneling oxide layer is 0.1nm~2nm, and the thickness of the amorphous silicon layer is 150nm. The deposition temperature of phosphorus diffusion is 800°C, the time is 900s, the boron source flow rate is 1400sccm, the oxidation flow rate is 500sccm, the advancement temperature is 900°C, the time is 1000s, the oxidation temperature is 860°C, and the time is 1300s;

[0095] Step 5, laser patterning the N-type silicon substrate obtained in step 4. Using a picosecond laser, the laser frequency is 600 kHz, the laser power is 55%, the spot width is 150 μm, the laser overlap rate is 50%, the grooving ratio of the patterned area to the mask area is 5:4, the width of the non-metallized area is 500 μm, and the width of the metallized area is 400 μm;

[0096] Step 6, wet-cleaning the N-type silicon substrate obtained in step 5. The conductivity of the cleaning solution for removing the PSG layer is 30μs / cm-40μs / cm, the RCA cleaning time is 310s, the temperature is 70°C, and the contents of NaOH, RCA additive, and H2O in the RAC cleaning solution are 3.9%, 0.76%, and 95.34%, respectively, so that a height difference of 3μm is formed between the metallized area and the non-metallized area of ​​the N-type silicon substrate;

[0097] Step 7: The N-type silicon substrate obtained in step 6 is subjected to passivation layer coating, and a 3.5nm aluminum oxide layer and a 75nm silicon nitride layer are formed on the front side of the battery, and a 3.5nm aluminum oxide layer and an 85nm silicon nitride layer are formed on the back side;

[0098] Step 8: Screen print the N-type silicon substrate obtained in step 7. Use silver-aluminum paste to form the positive electrode on the front side of the battery, and use silver paste to form the negative electrode on the back side.

[0099] Example 4

[0100] Step 1: Texturing an N-type silicon substrate, the reaction time is 420s, the reaction temperature is 82°C, the contents of NaOH, texturing additives, and H2O in the texturing solution are 1.1%, 0.42%, and 98.48%, respectively, and the pyramid size of the velvet surface is 1.35μm to 1.4μm;

[0101] Step 2, the front side of the N-type silicon substrate obtained in step 1 is subjected to boron diffusion and then oxidation, the diffusion boron source is BCl3, the reaction temperature is 850°C, the reaction time is 410s, the oxidation temperature is 1049°C, and the reaction time is 4740s;

[0102] Step 3, remove BSG from the N-type silicon substrate obtained in step 2, and perform alkali polishing. The conductivity of the first cleaning solution for removing BSG is 260μs / cm-350μs / cm, and the conductivity of the second cleaning solution is 150μs / cm-220μs / cm. The alkali polishing reaction time is 120s, the reaction temperature is 61°C, the contents of NaOH, polishing additives, and H2O in the polishing solution are 2.4%, 0.3%, and 97.3%, respectively. The reflectivity of the back of the N-type silicon substrate after alkali polishing is 39.87%;

[0103] Step 4, deposit a tunneling oxide layer, an intrinsic amorphous silicon layer and phosphorus diffusion on the N-type silicon substrate obtained in step 3. The deposition temperature of the tunneling oxide layer growth is 600°C, the reaction time is 400s, the deposition temperature of the intrinsic amorphous silicon layer is 606°C, the reaction time is 1500s, the thickness of the tunneling oxide layer is 0.1nm~2nm, and the thickness of the amorphous silicon layer is 150nm. The deposition temperature of phosphorus diffusion is 800°C, the time is 900s, the boron source flow rate is 1400sccm, the oxidation flow rate is 500sccm, the advancement temperature is 900°C, the time is 1000s, the oxidation temperature is 860°C, and the time is 1300s;

[0104] Step 5, laser patterning the N-type silicon substrate obtained in step 4. Using a picosecond laser, the laser frequency is 333kHz, the laser power is 60%, the spot width is 150μm, the spot overlap rate is 50%, the slot ratio of the patterned area to the mask area is 2:7, the width of the non-metallized area is 200μm, and the width of the metallized area is 700μm;

[0105] Step 6, wet-cleaning the N-type silicon substrate obtained in step 5. The conductivity of the cleaning solution for removing the PSG layer is 30μs / cm-40μs / cm, the RCA cleaning time is 460s, the temperature is 70°C, and the contents of NaOH, RCA additive, and H2O in the RAC cleaning solution are 3.9%, 0.76%, and 95.34%, respectively, so that a height difference of 3μm is formed between the metallized area and the non-metallized area of ​​the N-type silicon substrate;

[0106] Step 7: The N-type silicon substrate obtained in step 6 is subjected to passivation layer coating, and a 3.5nm aluminum oxide layer and a 75nm silicon nitride layer are formed on the front side of the battery, and a 90nm silicon nitride layer is formed on the back side;

[0107] Step 8: Screen print the N-type silicon substrate obtained in step 6. Use silver-aluminum paste to form the positive electrode on the front side of the battery, and use silver paste to form the negative electrode on the back side.

[0108] Comparative Example 1

[0109] The difference between Comparative Example 1 and Example 1 is that laser patterning is not performed, and the wet cleaning only removes the phosphosilicate glass layer, and does not remove the polysilicon layer, the tunnel oxide layer and the N-type silicon substrate in the non-metallized area.

[0110] Comparative Example 2

[0111] The difference between Comparative Example 2 and Example 1 is that in step 6, a height difference of 4 μm is formed between the metallized area and the non-metallized area of ​​the N-type silicon substrate.

[0112] The solar cells prepared in all embodiments and comparative examples were subjected to IV tests to measure the conversion efficiency (Eta), open circuit voltage (Uoc), short circuit current (Isc), fill factor (FF), series resistance (Rser), parallel resistance (Rsh) and reverse leakage current (IRev2).

[0113] The performance test results of all embodiments and comparative examples are shown in Table 1.

[0114] Table 1

[0115] Eta(%) Uoc(V) Isc(A) FF(%) Rser(Ω) Rsh(Ω) Irev2(A) Example 1 26.40 0.7423 14.236 84.58 0.000979 2928 0.014 Example 2 26.26 0.7417 14.245 84.14 0.000995 3133 0.008 Example 3 26.41 0.7422 14.269 84.42 0.000988 3058 0.023 Example 4 26.23 0.7411 14.253 84.07 0.000995 3058 0.012 Comparative Example 1 26.15 0.741 14.129 84.58 0.000995 3054 0.008 Comparative Example 2 26.22 0.742 14.274 83.80 0.001046 3389 0.0042

[0116] According to the results in Table 1, the solar cells prepared in all embodiments of the present invention have higher conversion efficiency, open circuit voltage, short circuit current and fill factor than the solar cells in all comparative examples. Therefore, the solar cell of the present invention solves the problem of uneven thickness of the doped polysilicon layer in the non-metallized area and residual doped polysilicon layer, effectively improves the short circuit current of the solar cell, and stably improves the conversion efficiency of the solar cell.

[0117] The technical features of the above-described embodiments may be arbitrarily combined. To make the description concise, not all possible combinations of the technical features in the above-described embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

[0118] The above-mentioned embodiments only express several implementation methods of the present invention, and the descriptions thereof are relatively specific and detailed, but they cannot be understood as limiting the scope of the invention patent. It should be pointed out that, for ordinary technicians in this field, several variations and improvements can be made without departing from the concept of the present invention, and these all belong to the protection scope of the present invention. Therefore, the protection scope of the patent of the present invention shall be subject to the attached claims.

Claims

1. A solar cell, comprising an N-type silicon substrate, wherein the back side of the N-type silicon substrate has a metallized region and a non-metallized region, and a back electrode is arranged in the metallized region, characterized in that: The metallized region includes a stacked tunneling oxide layer, a phosphorus-doped polysilicon layer, a first passivation layer and a first anti-reflection layer, and the non-metallized region includes a stacked second passivation layer and a second anti-reflection layer, wherein the thickness of the N-type silicon substrate corresponding to the metallized region is greater than the thickness of the N-type silicon substrate corresponding to the non-metallized region, and the thickness difference is 1 μm to 3 μm.

2. The solar cell according to claim 1, characterized in that The thickness of the tunnel oxide layer is 0.1 nm to 2 nm.

3. The solar cell according to claim 1, characterized in that The thickness of the phosphorus-doped polysilicon layer is 150nm-160nm.

4. The solar cell according to claim 1, characterized in that The thickness of the first passivation layer and the second passivation layer is selected from 3nm to 8nm; And / or, the thickness of the first anti-reflection layer and the second anti-reflection layer is selected from 60 nm to 140 nm.

5. The solar cell according to claim 1, characterized in that: The width of the non-metallized area is 200 μm to 700 μm.

6. The solar cell according to claim 1, characterized in that The width of the metallized area is 200 μm to 700 μm.

7. A method for preparing a solar cell according to any one of claims 1 to 6, characterized in that: The steps include: The N-type silicon substrate after texturing is subjected to boron diffusion to form a p+ emitter on the front side of the N-type silicon substrate; Depositing a tunneling oxide layer and an intrinsic amorphous silicon layer in sequence on the back side of an N-type silicon substrate, and forming a phosphorus-doped polysilicon layer from the intrinsic amorphous silicon layer by phosphorus doping; The back side of the N-type silicon substrate is subjected to laser patterning, a groove is formed on the back side by wet cleaning, and the back side and the surrounding phosphosilicate glass layer and the front side borosilicate glass layer are removed, wherein the groove penetrates the phosphorus-doped polysilicon layer and the tunneling oxide layer in the non-metallized area and extends to the N-type silicon substrate at a thickness of 1 μm to 3 μm; A passivation layer and an anti-reflection layer are plated on the front and back sides of the N-type silicon substrate; A back electrode and a front electrode are prepared on the back metallization area and the front side of the N-type silicon substrate respectively.

8. The method for preparing a solar cell according to claim 7, characterized in that: In the laser patterning process, the opening ratio of the patterning area to the mask area is 2:7 to 7:

2.

9. The method for preparing a solar cell according to claim 7, characterized in that: In the laser patterning process, the laser frequency is 200kHz to 600kHz, the laser power is 40% to 80%, the spot width is 150μm to 200μm, and the spot overlap rate is 0% to 50%.

10. The method for preparing a solar cell according to claim 7, characterized in that: In the wet cleaning step, the RAC cleaning time is 250s to 460s and the temperature is 68°C to 72°C.

Images