A solar cell

Abstract

The present invention provides a solar cell. It includes: a silicon substrate; a first tunneling layer, the first tunneling layer has a plurality of first notches; a first crystalline conductive layer, the first crystalline conductive layer extends into at least one first notch and contacts the silicon substrate; a second tunneling layer, the second tunneling layer has a plurality of second notches; a second crystalline conductive layer, the first crystalline conductive layer and / or the second crystalline conductive layer extends into at least one second notch, so that the second crystalline conductive layer contacts the first crystalline conductive layer; the density of the second notches in the second tunneling layer is greater than the density of the first notches in the first tunneling layer. The design of the solar cell not only effectively reduces the carrier recombination of the solar cell and improves the passivation effect of the cell, but also increases the carrier transmission channel, improves the carrier transmission efficiency of the cell, and thus improves the efficiency of the solar cell.

Description

Technical Field

[0001] The invention belongs to the technical field of solar energy and relates to a solar cell. Background Art

[0002] In the prior art, a tunneling oxide layer and a doped polysilicon layer are used to form a passivation contact on the back of a solar cell. For example, CN115863452A discloses a solar cell and a preparation method thereof, and a photovoltaic module. The solar cell includes a silicon substrate; a first oxide layer, a semiconductor layer, a second oxide layer, a polysilicon layer and a first passivation layer are stacked on the silicon substrate, the first oxide layer and the second oxide layer both have through holes, and the through hole density in the first oxide layer is greater than the through hole density in the second oxide layer; the first electrode penetrates the first passivation layer and is electrically connected to the polysilicon layer, or the first electrode penetrates the first passivation layer, the polysilicon layer and the second oxide layer in sequence and is electrically connected to the semiconductor layer; the silicon substrate includes a base region and an emitter; a second passivation layer is provided on the side of the emitter away from the base region; the second electrode penetrates the second passivation layer and is electrically connected to the emitter. This patent uses through holes in different oxide layers to increase the density of resonant states and improve the probability of resonant tunneling. It is still pore tunneling rather than contact transmission, and the through hole density of the first oxide layer close to the surface of the silicon substrate is greater than the through hole density of the second oxide layer, which is not conducive to the passivation of the silicon substrate interface. In addition, the distance between the first oxide layer and the second oxide layer in the quantum well structure must be very close (i.e., the thickness of the semiconductor layer is less than 3nm) to achieve the effect of resonant tunneling, which easily leads to excessive diffusion of dopants in the polycrystalline silicon layer to the silicon substrate. CN118299432A discloses a back structure of a solar cell and a preparation method thereof, which relates to the field of photovoltaic technology, including: a single crystal silicon substrate, a laminated polycrystalline silicon passivation layer structure, a metal electrode body located on the side of the laminated polycrystalline silicon passivation layer away from the single crystal silicon substrate; two different types of silver particles type I and silver particles type II are precipitated on the side of the metal electrode body facing the laminated polycrystalline silicon passivation layer, wherein the silver particles type II break through the second tunneling oxide layer and contact the first doped polycrystalline silicon layer. The above-mentioned cell structure has a low efficiency of carrier transmission at the tunneling layer interface, which hinders the improvement of cell efficiency.

[0003] Therefore, how to improve the carrier transfer efficiency at the tunneling layer interface in the battery structure, thereby improving the efficiency of solar cells, is a technical problem that needs to be solved urgently. Summary of the invention

[0004] In view of the deficiencies in the prior art, the purpose of the present invention is to provide a solar cell. In the solar cell structure provided by the present invention, the first tunneling layer and the second tunneling layer are both provided with notches, the first crystalline conductive layer extends into at least one first notch and contacts the silicon substrate, and the first crystalline conductive layer and / or the second crystalline conductive layer extends into at least one second notch, so that the second crystalline conductive layer contacts the first crystalline conductive layer. Moreover, the density of the second notches is greater than the density of the first notches. This design not only effectively reduces the carrier recombination of the solar cell and improves the passivation effect of the battery, but also increases the carrier transmission channel, improves the carrier transmission efficiency, and thus improves the efficiency of the solar cell.

[0005] To achieve this object, the present invention adopts the following technical solutions:

[0006] In a first aspect, the present invention provides a solar cell, comprising:

[0007] Silicon substrate.

[0008] A first tunneling layer, a first crystalline conductive layer, a second tunneling layer and a second crystalline conductive layer are stacked on the back side of the silicon substrate.

[0009] The first tunneling layer has a plurality of first gaps.

[0010] The first crystalline conductive layer extends into at least one of the first gaps and contacts the silicon substrate.

[0011] The second tunneling layer has a plurality of second gaps.

[0012] The first crystalline conductive layer and / or the second crystalline conductive layer extends into at least one of the second notches, so that the second crystalline conductive layer contacts the first crystalline conductive layer.

[0013] The density of the second gaps in the second tunneling layer is greater than the density of the first gaps in the first tunneling layer.

[0014] In the solar cell structure provided by the present invention, the first tunneling layer and the second tunneling layer are both provided with notches, the first crystalline conductive layer extends into at least one first notch and contacts the silicon substrate, and the first crystalline conductive layer and / or the second crystalline conductive layer extends into at least one second notch, so that the second crystalline conductive layer contacts the first crystalline conductive layer. Moreover, the density of the second notches is greater than the density of the first notches. This design not only effectively reduces the carrier recombination of the solar cell and improves the passivation effect of the battery, but also increases the carrier transmission channel, improves the battery carrier transmission efficiency, and thus improves the efficiency of the solar cell.

[0015] Preferably, the density of the first gaps is 5×105 -5×10 10 cm -2 .

[0016] Preferably, the density of the second gaps is 1×10 8 -1×10 13 cm -2 .

[0017] Preferably, the width of the first gap and / or the width of the second gap is less than 200 nm.

[0018] Preferably, the first crystalline conductive layer and the second crystalline conductive layer each include a plurality of grains; wherein at least one of the grains penetrates at least one of the second notches and extends into at least one of the first notches, so that the second crystalline conductive layer contacts the silicon substrate.

[0019] Preferably, the thickness of the first crystalline conductive layer is denoted as d3, the thickness of the second crystalline conductive layer is denoted as d4, and d3<d4.

[0020] Preferably, the ratio of d3 to d4 is 1:10 to 7:10.

[0021] Preferably, the value range of d3 is 10-50 nm.

[0022] Preferably, the value range of d4 is 20-90 nm.

[0023] Preferably, the value range of d3 is 15-40 nm.

[0024] Preferably, the value range of d4 is 30-80 nm.

[0025] Preferably, the first crystalline conductive layer and the second crystalline conductive layer each independently include a polysilicon layer or a silicon carbide layer.

[0026] Preferably, the silicon substrate has a first conductivity type.

[0027] Preferably, the conductivity types of the first crystalline conductive layer and the second crystalline conductive layer are both the first conductivity type or the second conductivity type.

[0028] Preferably, the first crystalline conductive layer and the second crystalline conductive layer both contain first conductive type doping elements or second conductive type doping elements, and the doping concentration of the doping elements in the first crystalline conductive layer is lower than the doping concentration of the doping elements in the second crystalline conductive layer.

[0029] Preferably, the doping concentration of the doping element in the first crystalline conductive layer is 1×10 18 -5×10 20cm -3 .

[0030] Preferably, the doping concentration of the doping element in the second crystalline conductive layer is 3×10 19 -1×10 22 cm -3 .

[0031] Preferably, the first tunneling layer and the second tunneling layer each independently include at least one of a silicon oxide layer, a silicon nitride layer, a silicon oxynitride layer and an aluminum oxide layer.

[0032] Preferably, the thickness of the first tunneling layer is denoted as d1, the thickness of the second tunneling layer is denoted as d2, and d2≤d1.

[0033] Preferably, the value ranges of d1 and d2 are independently 1-10 nm.

[0034] Preferably, the value ranges of d1 and d2 are independently 2-5 nm.

[0035] Preferably, the value ranges of d1 and d2 are independently 2.5-5 nm.

[0036] Preferably, the solar cell further comprises a first passivation layer, the first passivation layer is arranged on a surface of the second crystalline conductive layer on a side away from the back side of the silicon substrate, and a first anti-reflection layer is arranged on the first passivation layer.

[0037] Preferably, the first passivation layer includes at least one of a silicon oxynitride layer, a silicon nitride layer and a silicon oxide layer.

[0038] Preferably, the first anti-reflection layer includes a hydrogenated silicon nitride layer and / or a silicon oxynitride layer.

[0039] Preferably, the first passivation layer is a silicon oxynitride passivation layer.

[0040] Preferably, the first anti-reflection layer comprises a hydrogenated silicon nitride layer and a silicon oxynitride layer stacked in sequence in a direction away from the back side of the silicon substrate.

[0041] Preferably, the solar cell further comprises an emitter, which is located on the front side of the silicon substrate and has a conductivity type opposite to that of the silicon substrate; or, the solar cell further comprises a front surface field, which is located on the front side of the silicon substrate and has the same conductivity type as that of the silicon substrate.

[0042] Preferably, the emitter or the front surface field is located on the inner side or the outer side of the front side of the silicon substrate.

[0043] Preferably, the solar cell further comprises a second passivation layer, and the second passivation layer is located on the emitter or the front surface field.

[0044] Preferably, the second passivation layer includes at least one of an aluminum oxide layer, a silicon oxide layer and a silicon nitride layer.

[0045] Preferably, a second anti-reflection layer is disposed on the second passivation layer.

[0046] Preferably, the second anti-reflection layer includes at least one of a silicon nitride layer, a silicon oxynitride layer, a silicon oxide layer and a magnesium fluoride layer.

[0047] Preferably, the solar cell further comprises:

[0048] A back electrode passes through the first passivation layer and contacts at least the second crystalline conductive layer.

[0049] A front electrode is provided, wherein the front electrode passes through the second passivation layer and contacts the emitter or the front surface field.

[0050] Preferably, both the first crystalline conductive layer and the second crystalline conductive layer include polycrystalline conductive layers formed by crystallizing an amorphous conductive layer through heat treatment.

[0051] Preferably, a plurality of first conductivity type regions and a plurality of second conductivity type regions are provided on the back side of the silicon substrate, and the plurality of first conductivity type regions and the plurality of second conductivity type regions are arranged spaced apart from each other in a horizontal direction along the back side of the silicon substrate.

[0052] The first tunneling layer, the first crystalline conductive layer, the second tunneling layer, and the second crystalline conductive layer are disposed in the first conductive type region or the second conductive type region.

[0053] Preferably, the solar cell also includes a back passivation layer, which is arranged on the second conductive type region and the first conductive type region, and a first electrode is provided on the back passivation layer in the first conductive type region, and the first electrode passes through the back passivation layer and contacts at least the second crystalline conductive layer.

[0054] Preferably, a second electrode is provided on the back passivation layer located in the second conductive type region, the second electrode passes through the back passivation layer and enters into the silicon substrate, and the second electrode has a second conductive type contact portion in the silicon substrate.

[0055] Preferably, the second electrode is an aluminum electrode, and the second conductive type contact portion is an aluminum-silicon alloy contact portion.

[0056] Preferably, a doped passivation layer is provided on the front side of the silicon substrate, and a front passivation layer and / or a front anti-reflection layer is stacked on the doped passivation layer in a direction away from the silicon substrate.

[0057] The numerical range described in the present invention not only includes the point values ​​listed above, but also includes any point values ​​between the above numerical ranges that are not listed. Due to space limitations and for the sake of simplicity, the present invention no longer exhaustively lists the specific point values ​​included in the range.

[0058] Compared with the prior art, the present invention has the following beneficial effects:

[0059] In the solar cell structure provided by the present invention, notches are provided on the first tunneling layer and the second tunneling layer, the first crystalline conductive layer extends into at least one first notch and contacts the silicon substrate, and the first crystalline conductive layer and / or the second crystalline conductive layer extends into at least one second notch, so that the second crystalline conductive layer contacts the first crystalline conductive layer. This design not only effectively reduces the carrier recombination of the solar cell and improves the passivation effect of the battery, but also increases the carrier transmission channel, improves the battery carrier transmission efficiency, and thus improves the efficiency of the solar cell. BRIEF DESCRIPTION OF THE DRAWINGS

[0060] Figure 1 This is a schematic diagram of the structure of a solar cell provided in Example 1 of the present invention.

[0061] Figure 2 This is a TEM scan of the back side of the solar cell provided in Example 1 of the present invention.

[0062] Figure 3 This is a schematic diagram of the partial structure of the solar cell provided in Example 3 of the present invention.

[0063] Figure 4 This is a schematic diagram of the first tunneling layer in the solar cell provided in Example 1, Example 2, and Example 3 of the present invention.

[0064] Figure 5 This is a schematic diagram of the second tunneling layer in the solar cell provided in Example 1, Example 2, and Example 3 of the present invention.

[0065] Figure 6 This is a schematic diagram of the structure of a solar cell provided in Example 4 of the present invention.

[0066] Figure 7 This is a schematic diagram of the structure of a solar cell provided in Example 5 of the present invention.

[0067] Wherein, 100-n-type silicon wafer; 101-first tunneling layer; 102-first crystalline conductive layer; 103-second tunneling layer; 104-second crystalline conductive layer; 105-first passivation layer; 106-hydrogenated silicon nitride layer; 107-silicon oxynitride layer; 108-back electrode; 109-p-type emitter; 110-second passivation layer; 111-second anti-reflection layer; 112-front electrode; 113-first notch; 114-second notch; 102A-n-region first crystalline conductive layer; 102B-p-region first crystalline conductive layer; 103A-n-region second tunneling layer; 103B-p-region second tunneling layer; 104A-n-region second crystalline conductive layer; 104B-p-region second crystalline conductive layer; 105 '-back passivation layer; 106'-back hydrogenated silicon nitride layer; 107'-back silicon oxynitride layer; 109'-doped passivation layer; 110'-front passivation layer; 111'-front anti-reflection layer; 115-metal negative electrode; 116-metal positive electrode; 600-P-type silicon wafer; 601-first tunneling oxide layer; 602a-first n-type phosphorus-doped polysilicon layer; 602b-second n-type phosphorus-doped polysilicon layer; 603-second tunneling oxide layer; 604-interface passivation layer; 605-hydrogenated silicon nitride film; 606-silicon oxynitride film; 607-second electrode; 608-first electrode; 609-boron-doped layer; 610-front passivation layer; 611-front reflection layer; 612-p-type contact. DETAILED DESCRIPTION

[0068] It should be understood that, in the description of the present invention, the terms "center", "longitudinal", "lateral", "up", "down", "front", "back", "left", "right", "vertical", "horizontal", "top", "bottom", "inside", "outside", etc., indicating the orientation or positional relationship are based on the orientation or positional relationship shown in the drawings, and are only for the convenience of describing the present invention and simplifying the description, rather than indicating or implying that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation, and therefore cannot be understood as a limitation on the present invention. In addition, the terms "first", "second", etc. are only used for descriptive purposes, and cannot be understood as indicating or implying relative importance or implicitly indicating the number of technical features indicated. Therefore, the features defined as "first", "second", etc. may explicitly or implicitly include one or more of the features. In the description of the present invention, unless otherwise specified, "multiple" means two or more.

[0069] It should be noted that in the description of the present invention, unless otherwise clearly specified and limited, the terms "disposed", "connected", and "connected" should be understood in a broad sense, for example, it can be a fixed connection, a detachable connection, or an integral connection; it can be a mechanical connection or an electrical connection; it can be a direct connection, or it can be indirectly connected through an intermediate medium, or it can be the internal communication of two elements. For ordinary technicians in this field, the specific meanings of the above terms in the present invention can be understood by specific circumstances.

[0070] The technical solution of the present invention is further described below with reference to the accompanying drawings and through specific implementation methods.

[0071] In a specific embodiment, the present invention provides a solar cell, the structural schematic diagram and the back TEM scanning image of which are as follows: Figure 1 and Figure 2 As shown, including:

[0072] A silicon substrate (for example, an n-type silicon wafer 100 ) is used.

[0073] The first tunneling layer 101 is located on the back side of the silicon substrate, and the first tunneling layer 101 has a plurality of first gaps.

[0074] The first crystalline conductive layer 102 is disposed on the first tunneling layer 101 , and the first crystalline conductive layer 102 extends into at least one of the first gaps and contacts the silicon substrate.

[0075] The second tunneling layer 103 is disposed on the first crystalline conductive layer 102 , and the second tunneling layer 103 has a plurality of second gaps.

[0076] The second crystalline conductive layer 104 is disposed on the second tunneling layer 103 , and the first crystalline conductive layer 102 and / or the second crystalline conductive layer 104 extend into at least one of the second gaps, so that the second crystalline conductive layer 104 contacts the first crystalline conductive layer 102 .

[0077] The density of the second gaps in the second tunneling layer 103 is greater than the density of the first gaps in the first tunneling layer 101 .

[0078] In the solar cell structure provided by the present invention, the first tunneling layer 101 and the second tunneling layer 103 are both provided with notches, the first crystalline conductive layer 102 extends into at least one first notch and contacts the silicon substrate, and the first crystalline conductive layer 102 and / or the second crystalline conductive layer 104 extends into at least one second notch, so that the second crystalline conductive layer 104 contacts the first crystalline conductive layer 102. In addition, the density of the second notches is greater than the density of the first notches. This design not only effectively reduces the carrier recombination of the solar cell and improves the passivation effect of the battery, but also increases the carrier transmission channel, improves the battery carrier transmission efficiency, and thus improves the efficiency of the solar cell.

[0079] In the present invention, the first crystalline conductive layer 102 and the second crystalline conductive layer 104 are in direct contact through the notch on the second tunneling layer 103, thereby reducing the density of polysilicon grain boundaries, and reducing carrier scattering and recombination losses. The second tunneling layer 103 acts as a buffer layer, which has a buffering effect on the diffusion of doping elements in the polysilicon layer, thereby achieving a stepped doping distribution with a low doping concentration in the first crystalline conductive layer 102 and a high doping concentration in the second crystalline conductive layer 104, and reducing the carrier transmission barrier effect of the second tunneling layer 103.

[0080] It should be noted that the “density of the gaps” refers to the number of gaps per unit area, such as the number of gaps per square centimeter, which is essentially an indicator used to quantitatively describe the density of defect distribution in a layered structure. The same applies to the following.

[0081] It should be noted that, in the present invention, the first crystalline conductive layer 102, the second crystalline conductive layer 104, the first tunnel layer 101 and the second tunnel layer 103 can be arranged on substantially the entire back side of the silicon substrate, or can be arranged on a part of the back side of the silicon substrate, for example, similar to the attached Figure 6 , Attachment Figure 7 Or other local designs also belong to the protection scope of the present invention.

[0082] In the present invention, in order to avoid the influence on carrier transmission, the surface passivation of the first tunneling layer 101 plays an important role, and the second crystalline conductive layer 104 requires higher conductivity, so the density of the second notches in the second tunneling layer 103 is greater than the density of the first notches in the first tunneling layer 101, that is, the density of the second tunneling layer 103 is less than the density of the first tunneling layer 101. Therefore, the second tunneling layer 103 has a higher density of second notches, which can reduce the carrier transmission loss. At the same time, the second notches increase the diffusion channel of the high-concentration phosphorus-doped elements in the second crystalline conductive layer 104, reduce the accumulation of phosphorus elements on the surface of the second tunneling layer 103, and improve the doping concentration distribution.

[0083] In the present invention, the first crystalline conductive layer 102 and / or the second crystalline conductive layer 104 extends into at least one second gap, so that the second crystalline conductive layer 104 contacts the first crystalline conductive layer 102. The following possible situations exist:

[0084] The first crystalline conductive layer 102 and the second crystalline conductive layer 104 extend into the same second notch together; the first crystalline conductive layer 102 and the second crystalline conductive layer 104 extend into different second notches respectively; a portion of the first crystalline conductive layer 102 and the second crystalline conductive layer 104 extend into the same second notch together, and the other portions extend into different second notches respectively.

[0085] Furthermore, the density of the first gaps is 5×10 5 -5×10 10 cm -2 , for example, it can be 5×10 5 cm -2 , 5×10 6 cm -2 , 5×10 7 cm -2 , 5×10 8 cm -2 , 5×10 9 cm -2 or 5×10 10 cm -2 etc., preferably 5×10 6 -5×10 8 cm -2 .

[0086] In the present invention, if the density of the first gaps is less than 5×10 5 cm -2 , the junction resistance is too high, the carrier transfer efficiency is low, and the passivation effect does not change much; if the density of the first gap is greater than 5×10 10 cm -2 , which will lead to excessive interface carrier recombination losses and reduced passivation effect.

[0087] Furthermore, the density of the second gaps is 1×10 8 -1×10 13 cm -2 , for example, it can be 1×10 8 cm -2 , 1×10 9 cm -2 , 1×10 10 cm -2 , 1×10 11 cm -2 , 1×10 12 cm-2 or 1×10 13 cm -2 etc., preferably 1×10 9 -1×10 11 cm -2 .

[0088] In the present invention, if the density of the second gaps is less than 1×10 8 cm -2 , the junction resistance is too high, the carrier blocking of the first crystalline conductive layer 102 is serious, and the carrier transmission efficiency is low; if the density of the second gap is greater than 1×10 13 cm -2 , it is insufficient to buffer the diffusion of high-concentration dopants in the second crystalline conductive layer 104, resulting in excessive diffusion of dopants in the silicon substrate, excessive interface carrier recombination losses, and reduced passivation effect.

[0089] Furthermore, the width of the first gap and / or the width of the second gap is less than 200 nm, for example, it may be 1 nm, 10 nm, 20 nm, 30 nm, 40 nm, 50 nm, 60 nm, 70 nm, 80 nm, 90 nm or 100 nm.

[0090] It should be noted that, in the first tunneling layer 101, since the widths of the multiple notches are not completely consistent, the selection of the multiple notch width parameters needs to be limited to the condition that the above-mentioned notch density range is met to avoid including unrealizable technical features.

[0091] It should be noted that, in the second tunneling layer 103, since the widths of the multiple notches are not completely consistent, the selection of the multiple notch width parameters needs to be limited to the condition that the above-mentioned notch density range is met to avoid including unrealizable technical features.

[0092] Furthermore, the first notch and the second notch may be prepared by the following method:

[0093] A first tunneling layer, a first amorphous conductive layer, a second tunneling layer and a second amorphous conductive layer are sequentially deposited on the back side of a silicon substrate; then, heat treatment is performed to crystallize the first amorphous conductive layer and the second amorphous conductive layer to form a first crystalline conductive layer and a second crystalline conductive layer, and a plurality of gaps are formed in the first tunneling layer and the second tunneling layer; wherein the amorphous conductive layer may include amorphous silicon, and the first crystalline conductive layer and the second crystalline conductive layer formed after heat treatment and crystallization may include polycrystalline silicon; wherein, excessive hydrogen is introduced into the second tunneling layer during the deposition process, so that the hydrogen in the second tunneling layer is released in a subsequent process, thereby introducing more gaps in the second tunneling layer.

[0094] It should be noted that by adjusting the temperature and atmosphere of the heat treatment and controlling the crystallization of the first amorphous silicon layer and the second amorphous silicon layer, the density of the first notches can be made smaller than the density of the second notches. Exemplarily, the heat treatment temperature is 800-1200°C, such as 800°C, 850°C, 950°C, 1050°C, 1100°C, 1150°C or 1200°C.

[0095] Specifically, a cooling treatment step is performed after the heat treatment, wherein the cooling treatment step adopts a rapid cooling or gradient cooling method, and its purpose is to introduce more second gaps in the second tunneling layer.

[0096] Furthermore, the method of forming the plurality of gaps includes any one of plasma etching, wet etching or laser etching.

[0097] Furthermore, the first crystalline conductive layer 102 and the second crystalline conductive layer 104 are prepared by an in-situ doping process, the purpose of which is to control the doping concentration distribution of the first crystalline conductive layer 102 and the second crystalline conductive layer 104, and the process can be prepared in the same chamber, simplifying the preparation process flow.

[0098] Furthermore, the first crystalline conductive layer 102 and the second crystalline conductive layer 104 each include a plurality of crystal grains; wherein at least one of the crystal grains penetrates at least one of the second notches and extends into at least one of the first notches, so that the second crystalline conductive layer 104 contacts the silicon substrate.

[0099] In the present invention, at least one grain in the second crystalline conductive layer 104 passes through at least one second notch and extends into at least one first notch, that is, there is a complete grain between the notches of the upper and lower tunnel layers, and there is no grain boundary between the notches of the upper and lower tunnel layers along the thickness direction of the silicon substrate (for example, vertically grown grains are induced, or high-temperature treatment is performed to move the grain boundaries, and the grains of the first crystalline conductive layer and the second crystalline conductive layer are mutually swallowed up to form grains larger than the thickness size of the first crystalline conductive layer). This can reduce the grain boundary density and further improve the carrier transmission efficiency.

[0100] Furthermore, the deposition methods of the first crystalline conductive layer 102 and the second crystalline conductive layer 104 are independently vapor deposition methods.

[0101] Furthermore, the thickness of the first crystalline conductive layer 102 is recorded as d3, and the thickness of the second crystalline conductive layer 104 is recorded as d4, and d3<d4.

[0102] Furthermore, the ratio of d3 to d4 is 1:10 to 7:10, for example, it can be 1:10, 2:10, 3:10, 4:10, 5:10, 6:10 or 7:10.

[0103] In the present invention, the ratio of d3 to d4 is limited to 1:10-7:10, which is beneficial to the concentration gradient diffusion of the doping elements in the second crystalline conductive layer 104, forming a high-low junction, and reducing the diffusion of impurities in the silicon substrate, thereby improving the passivation effect.

[0104] Furthermore, the value range of d3 is 10-50 nm, for example, it can be 10 nm, 20 nm, 30 nm, 40 nm or 50 nm.

[0105] In the present invention, if the thickness of the first crystalline conductive layer 102 is greater than 50nm, it is not conducive to the gradient diffusion of the doping elements in the second crystalline conductive layer 104; if the thickness of the first crystalline conductive layer 102 is less than 10nm, the buffering effect is poor, resulting in excessive diffusion of the doping elements into the silicon substrate.

[0106] Furthermore, the value range of d4 is 20-90 nm, for example, it can be 20 nm, 30 nm, 40 nm, 50 nm, 60 nm, 70 nm, 80 nm or 90 nm.

[0107] Furthermore, the value range of d3 is 15-40nm.

[0108] Furthermore, the value range of d4 is 30-80nm.

[0109] Further, the first crystalline conductive layer 102 and the second crystalline conductive layer 104 each independently include a polysilicon layer or a silicon carbide layer.

[0110] Furthermore, the silicon substrate has a first conductivity type, for example, it may be an n-type silicon wafer 100 .

[0111] Furthermore, the conductivity types of the first crystalline conductive layer 102 and the second crystalline conductive layer 104 are both the first conductivity type or the second conductivity type.

[0112] It should be noted that there are two types of conductivity types of semiconductors, namely N-type and P-type. In N-type semiconductors, the majority carriers are electrons and the minority carriers are holes, and its conductivity is mainly achieved by the movement of electrons; in P-type semiconductors, the majority carriers are holes and the minority carriers are electrons, and the movement of holes dominates the current conduction. For the convenience of research, the present invention defines one of the N-type or P-type as the "first conductivity type", and the remaining one is the "second conductivity type". For example, if the first conductivity type is set to N-type and the second conductivity type is set to P-type, then the silicon substrate is N-type silicon, the first crystalline conductive layer and the second crystalline conductive layer are N-type semiconductors, and the emitter is P-type. The same applies to the following.

[0113] Furthermore, both the first crystalline conductive layer 102 and the second crystalline conductive layer 104 have first conductive type doping elements or second conductive type doping elements, and the doping concentration of the doping elements in the first crystalline conductive layer 102 is lower than the doping concentration of the doping elements in the second crystalline conductive layer 104 .

[0114] In the present invention, the doping concentration of the doping element in the first crystalline conductive layer 102 is limited to be less than the doping concentration of the doping element in the second crystalline conductive layer 104, which is conducive to maintaining a higher doping concentration in the second crystalline conductive layer 104 and improving the carrier transmission efficiency. The lower doping concentration of the first crystalline conductive layer 102 is conducive to reducing the excessive diffusion of phosphorus doping elements into the silicon substrate, and the first notch density in the first tunneling layer 101 is less than the notch density in the second tunneling layer 103, which further reduces the doping concentration between the first crystalline conductive layer 102 and the silicon substrate, and reduces the interface carrier recombination. The second crystalline conductive layer 104 requires high-concentration phosphorus doping. When the phosphorus doping element of the second crystalline conductive layer 104 expands inward, it is easy to accumulate on the surface of the second tunneling layer 103, introducing undesirable band bending. When the notch density in the second tunneling layer 103 is greater than the first notch density in the first tunneling layer 101, while reducing the carrier transmission loss, the diffusion channel of the high-concentration phosphorus doping element in the second crystalline conductive layer 104 is increased, which can improve the doping concentration distribution of the first crystalline conductive layer 102 and the second crystalline conductive layer 104.

[0115] Furthermore, the doping elements in the first crystalline conductive layer 102 and the second crystalline conductive layer 104 are both phosphorus elements.

[0116] Furthermore, the doping concentration of phosphorus in the first crystalline conductive layer 102 is 1×10 18 cm -3 -5×10 20 cm -3 , for example, it can be 1×10 18 cm -3 , 5×10 18 cm -3 , 1×10 19 cm -3 , 5×10 19 cm -3 , 1×10 20 cm -3 or 5×10 20 cm -3 wait.

[0117] Furthermore, the doping concentration of phosphorus in the second crystalline conductive layer 104 is 3×10 19 cm -3 -1×10 22 cm-3 , for example, it can be 3×10 19 cm -3 , 5×10 19 cm -3 , 1×10 20 cm -3 , 5×10 20 cm -3 , 1×10 21 cm -3 or 1×10 22 cm -3 wait.

[0118] Further, the first tunneling layer 101 and the second tunneling layer 103 each independently include at least one of a silicon oxide layer, a silicon nitride layer, a silicon oxynitride layer and an aluminum oxide layer.

[0119] In the present invention, the silicon oxide layer is beneficial to the selective tunneling of carriers.

[0120] It should be noted that the material of the silicon oxynitride layer is silicon oxynitride.

[0121] Furthermore, the preparation methods of the first tunneling layer 101 and the second tunneling layer 103 independently include any one of thermal oxidation, chemical oxidation or vapor deposition.

[0122] Furthermore, the thickness of the first tunneling layer 101 is recorded as d1, and the thickness of the second tunneling layer 103 is recorded as d2, where d2≤d1.

[0123] In the present invention, d2≤d1, which can avoid excessive inhibition of diffusion of the doping elements in the second crystalline conductive layer 104 during the annealing process and reduce the barrier to carrier transmission.

[0124] Furthermore, the value ranges of d1 and d2 are independently 1-10 nm, for example, 1 nm, 3 nm, 5 nm, 7 nm, 9 nm or 10 nm.

[0125] In the present invention, when d1 is less than 1 nm, the interface passivation effect is poor; when d1 is greater than 10 nm, carrier transmission is severely blocked and the efficiency is significantly reduced.

[0126] In the present invention, when d2 is less than 1 nm, the interface passivation effect is poor; when d2 is greater than 10 nm, there is a serious obstruction to carrier transmission and the efficiency decreases significantly.

[0127] Furthermore, the value ranges of d1 and d2 are independently 2-5 nm.

[0128] Furthermore, the value ranges of d1 and d2 are independently 2.5-5 nm.

[0129] Slight changes in the thickness of the tunneling layer have a great impact on the junction resistance. Generally, the thickness of the tunneling layer needs to be less than 2nm, but a too thin tunneling layer leads to poor passivation effect. In the present invention, the thickness of the first tunneling layer 101 is greater than 2nm, and the thickness of the tunneling layer is further allowed to be greater than 2.5nm, which significantly improves the surface passivation effect and reduces the inward expansion effect of the first crystalline conductive layer 102 on the silicon substrate. At the same time, since the first crystalline conductive layer 102 is in local contact with the silicon substrate through the gap, the carrier transmission channel is increased, which effectively suppresses the problem of increased junction resistance caused by the thicker tunneling layer.

[0130] Furthermore, the solar cell further comprises a first passivation layer 105 . The first passivation layer 105 is disposed on a surface of the second crystalline conductive layer 104 which is away from the back surface of the silicon substrate. A first anti-reflection layer is disposed on the first passivation layer 105 .

[0131] In the present invention, the first anti-reflection layer has a passivation effect.

[0132] Furthermore, the first passivation layer 105 includes at least one of a silicon oxynitride passivation layer, a silicon nitride layer and a silicon oxide layer.

[0133] Further, the first anti-reflection layer includes a hydrogenated silicon nitride layer and / or a silicon oxynitride layer.

[0134] Furthermore, the first passivation layer 105 is a silicon oxynitride passivation layer.

[0135] In the present invention, the silicon oxynitride passivation layer has a fixed positive charge. In addition, due to the presence of oxygen atoms, the electrical properties of the first passivation layer 105 can be adjusted, the n-type surface state density can be reduced, and carrier recombination can be reduced.

[0136] Furthermore, the first anti-reflection layer includes a hydrogenated silicon nitride layer 106 and a silicon oxynitride layer 107 stacked in sequence.

[0137] In the present invention, in the hydrogenated silicon nitride layer 106, hydrogen is diffused into the first passivation layer 105 and the silicon substrate through heat treatment, which is beneficial to passivating surface defects.

[0138] Furthermore, the first passivation layer 105 and the first anti-reflection layer are both prepared by vapor deposition.

[0139] Furthermore, the thickness of the first passivation layer 105 is less than 10 nm, for example, may be 8 nm, 6 nm, 4 nm or 2 nm.

[0140] In the present invention, the thickness of the first passivation layer 105 is less than 10 nm, which is beneficial to the diffusion of hydrogen atoms in the first anti-reflection layer and further improves the passivation effect.

[0141] Furthermore, the thickness of the hydrogenated silicon nitride layer 106 is 30-70 nm, for example, 30 nm, 40 nm, 50 nm, 60 nm or 70 nm.

[0142] In the present invention, if the thickness of the hydrogenated silicon nitride layer 106 is less than 30 nm, the passivation effect is poor; if the thickness of the hydrogenated silicon nitride layer 106 is greater than 70 nm, the optical performance is reduced.

[0143] Furthermore, the silicon oxynitride layer 107 has a thickness of 20-60 nm, for example, 20 nm, 30 nm, 40 nm, 50 nm or 60 nm.

[0144] In the present invention, if the thickness of the silicon oxynitride layer 107 is less than 20 nm, the passivation effect is poor; if the thickness of the silicon oxynitride layer 107 is greater than 60 nm, the optical performance is degraded.

[0145] Furthermore, the solar cell also includes an emitter, which is located on the front side of the silicon substrate and has a conductivity type opposite to that of the silicon substrate (for example, it can be a p-type emitter 109); or, the solar cell also includes a front surface field, which is located on the front side of the silicon substrate and has the same conductivity type as that of the silicon substrate.

[0146] Furthermore, the emitter or the front surface field is located on the inner side or the outer side of the front side of the silicon substrate.

[0147] In the present invention, the emitter is formed by diffusing an n-type dopant or a p-type dopant into the front side of the silicon substrate. The p-type dopant may be a boron dopant, for example.

[0148] Furthermore, the emitter preparation method includes thermal diffusion or ion implantation.

[0149] Furthermore, the solar cell further includes a second passivation layer 110 , and the second passivation layer 110 is located on the emitter or the front surface field.

[0150] Furthermore, the second passivation layer 110 includes at least one of an aluminum oxide layer, a silicon oxide layer and a silicon nitride layer.

[0151] In the present invention, the aluminum oxide layer has a high density of fixed negative charges and has a good passivation effect on the p-type surface.

[0152] Furthermore, a second anti-reflection layer 111 is disposed on the second passivation layer 110 .

[0153] Further, the second anti-reflection layer 111 includes at least one of a silicon nitride layer, a silicon oxynitride layer, a silicon oxide layer and a magnesium fluoride layer.

[0154] Furthermore, the second passivation layer 110 and the second anti-reflection layer 111 are both prepared by vapor deposition.

[0155] Furthermore, the solar cell further comprises:

[0156] A back electrode 108 passes through the first passivation layer 105 and contacts at least the second crystalline conductive layer 104 .

[0157] A front electrode 112 passes through the second passivation layer 110 and contacts the emitter or the front surface field.

[0158] It should be noted that “at least in contact with the second crystalline conductive layer 104 ” means that the back electrode 108 may be in contact with the second crystalline conductive layer 104 or the first crystalline conductive layer 102 .

[0159] It should be noted that, when the back electrode 108 penetrates the second tunneling layer 103 , the notch of the second tunneling layer 103 refers to a position other than the penetration opening of the back electrode 108 .

[0160] Furthermore, the back electrode 108 includes any one of a silver electrode, an aluminum electrode, a copper electrode, a nickel electrode, a platinum electrode, a gold electrode or a palladium electrode.

[0161] Furthermore, the front electrode 112 includes any one of a silver electrode, an aluminum electrode, a copper electrode, a nickel electrode, a platinum electrode, a gold electrode, a palladium electrode or a silver-aluminum electrode, preferably a silver-aluminum electrode.

[0162] Furthermore, the first crystalline conductive layer and the second crystalline conductive layer both include a polycrystalline conductive layer formed by crystallizing an amorphous conductive layer through heat treatment.

[0163] In another specific embodiment, the present invention provides a solar cell, which is different from the above-mentioned solar cell in that the silicon substrate has a first conductivity type, the first crystalline conductive layer and the second crystalline conductive layer have a second conductivity type, and the front side of the silicon substrate is a front surface field of the same conductivity type as the silicon substrate.

[0164] In the solar cell structure provided by the present invention, the first crystalline conductive layer and the second crystalline conductive layer are arranged as emitter layers on the back side of the silicon substrate, and the first notch density of the first tunneling layer is greater than the second notch density of the second tunneling layer. This structure can effectively inhibit excessive diffusion of dopants into the silicon substrate and reduce carrier recombination near the back PN junction, thereby having a relatively high open circuit voltage.

[0165] In another specific embodiment, the structural schematic diagram of the solar cell provided by the present invention is as follows Figure 7 As shown, including:

[0166] A silicon substrate, wherein the silicon substrate has a first conductivity type or a second conductivity type (exemplarily, for example, it may be a P-type silicon wafer 600 ).

[0167] A plurality of first conductive type regions and a plurality of second conductive type regions are disposed on the back side of the silicon substrate, and the plurality of first conductive type regions and the plurality of second conductive type regions are arranged spaced apart from each other in a horizontal direction along the back side of the silicon substrate.

[0168] The first conductive type region is provided with a first tunneling layer (exemplarily, such as a first tunneling oxide layer 601 ), and the first tunneling layer has a plurality of first gaps.

[0169] and a first crystalline conductive layer (exemplarily, such as a first n-type phosphorus-doped polysilicon layer 602a), wherein the first crystalline conductive layer is disposed on the first tunneling layer and has a first conductivity type, and the first crystalline conductive layer extends into at least one of the first notches and contacts the silicon substrate.

[0170] and a second tunneling layer (exemplarily, such as a second tunneling oxide layer 603 ), wherein the second tunneling layer is disposed on the first crystalline conductive layer, the second tunneling layer has a plurality of second gaps, and a density of the second gaps is greater than a density of the first gaps.

[0171] And a second crystalline conductive layer (exemplarily, for example, it can be a second n-type phosphorus-doped polysilicon layer 602b), the second crystalline conductive layer is arranged on the second tunneling layer and has a first conductivity type, the first crystalline conductive layer and / or the second crystalline conductive layer extends into at least one of the second notches, so that the second crystalline conductive layer is in contact with the first crystalline conductive layer.

[0172] In the solar cell structure, notches are provided on the first tunneling layer and the second tunneling layer, the first crystalline conductive layer extends into at least one first notch and contacts the silicon substrate, and the first crystalline conductive layer and / or the second crystalline conductive layer extends into at least one second notch, so that the second crystalline conductive layer contacts the first crystalline conductive layer. This design not only effectively reduces the carrier recombination of the solar cell and improves the passivation effect of the cell, but also increases the carrier transmission channel and improves the carrier transmission efficiency at the interface of the first tunneling layer in the cell structure, thereby improving the efficiency of the solar cell.

[0173] Furthermore, the solar cell also includes a back passivation layer (i.e., an interface passivation layer 604), the back passivation layer is arranged on the second conductive type region and the first conductive type region, and a first electrode 608 is provided on the back passivation layer located in the first conductive type region, and the first electrode 608 passes through the back passivation layer and contacts at least the second crystalline conductive layer.

[0174] It should be noted that “at least in contact with the second crystalline conductive layer” means that the first electrode 608 may be in contact with the second crystalline conductive layer or the first crystalline conductive layer.

[0175] Furthermore, the solar cell further comprises a back anti-reflection layer, and the back anti-reflection layer is arranged on the back passivation layer.

[0176] Furthermore, a second electrode 607 is provided on the back passivation layer in the second conductive type region. The second electrode 607 penetrates the back passivation layer and enters into the silicon substrate. The second electrode 607 has a second conductive type contact portion in the silicon substrate.

[0177] Further, the first electrode 608 includes any one of a silver electrode, an aluminum electrode, a copper electrode, a nickel electrode, a platinum electrode, a gold electrode or a palladium electrode.

[0178] Further, the second electrode 607 is an aluminum electrode, and the second conductive type contact portion is an aluminum-silicon alloy contact portion.

[0179] Furthermore, the back anti-reflection layer includes a stacked hydrogenated silicon nitride film 605 and a silicon oxynitride film 606 along a direction away from the silicon substrate.

[0180] Furthermore, a doped passivation layer (exemplarily, for example, a boron-doped layer 609) is provided on the front side of the silicon substrate, and a front passivation layer (i.e., front passivation layer 610) and / or a front anti-reflection layer (i.e., front reflection layer 611) are stacked on the doped passivation layer in a direction away from the silicon substrate.

[0181] In the present invention, the doping type of the doped passivation layer can be n-type or p-type, which is beneficial to reducing the carrier recombination on the surface of the silicon substrate.

[0182] Furthermore, a front passivation layer 610 and a front reflection layer 611 are sequentially stacked on the doped passivation layer in a direction away from the silicon substrate.

[0183] Furthermore, the silicon substrate is an n-type silicon wafer or a p-type silicon wafer.

[0184] Example 1

[0185] This embodiment provides a solar cell, and its structural schematic diagram is as follows Figure 1 As shown, it includes an n-type silicon wafer 100, on the front side (i.e., the light-receiving side), along the direction away from the n-type silicon wafer 100, a p-type emitter 109, a second passivation layer 110, and a second anti-reflection layer 111 are sequentially stacked; on the back side, along the direction away from the n-type silicon wafer 100, a first tunneling layer 101, a first crystalline conductive layer 102, a second tunneling layer 103, a second crystalline conductive layer 104, a first passivation layer 105, and a second anti-reflection layer are sequentially stacked; wherein the first tunneling layer 101 is a silicon oxide layer with a thickness d1 equal to 3 nm; the second tunneling layer 103 is a silicon oxide layer with a thickness d2 equal to 2 nm; the first crystalline conductive layer 102 is an n-type phosphorus-doped polysilicon layer with a thickness d3 equal to 30 nm, and the doping concentration is 5×10 19 cm -3 The second crystalline conductive layer 104 is an n-type phosphorus-doped polysilicon layer with a thickness d4 equal to 50 nm and a doping concentration of 5×10 20 cm -3 , the ratio of d3 to d4 is 6:10; the second passivation layer 110 is an aluminum oxide layer with a thickness of 5 nm, the first passivation layer 105 is a silicon oxynitride layer with a thickness of 5 nm, the second anti-reflection layer 111 is a silicon nitride layer with a thickness of 70 nm, and the first anti-reflection layer includes a hydrogenated silicon nitride layer 106 with a thickness of 50 nm and a silicon oxynitride layer 107 with a thickness of 40 nm stacked in sequence; the p-type emitter 109 is doped with boron at a doping concentration of 3×10 20 cm -3 .

[0186] See also Figure 2 It can be seen that the first tunneling layer 101 has a plurality of first notches, and the second tunneling layer 103 has a plurality of second notches, and the density of the second notches is greater than that of the first notches. As shown in the red circle, the first crystalline conductive layer 102 extends into at least one first notch and contacts the n-type silicon wafer 100, and the second crystalline conductive layer 104 extends into at least one second notch, so that the second crystalline conductive layer 104 contacts the first crystalline conductive layer 102; the density of the first notches is 5×10 5 -5×10 10 cm -2 (Optionally, the density can be 5×10 5 cm -2 , 5×10 6 cm -2 , 5×10 7 cm -2 , 5×10 8 cm -2 , 5×10 9 cm -2 or 5×10 10 cm -2The density of the second gap is 1×10 8 -1×10 13 cm -2 (Optionally, the density can be 1×10 8 cm -2 , 1×10 9 cm -2 , 1×10 10 cm -2 , 1×10 11 cm -2 , 1×10 12 cm -2 or 1×10 13 cm -2 The width of the first gap is 1-50nm, and the width of the second gap is 1-200nm.

[0187] A back electrode 108 is disposed on the second anti-reflection layer. The back electrode 108 passes through the first anti-reflection layer, the first passivation layer 105, the second crystalline conductive layer 104 and the second tunneling layer 103 and contacts the first crystalline conductive layer 102. The back electrode 108 is a Ag electrode.

[0188] A front electrode 112 is provided on the second anti-reflection layer 111, and the front electrode 112 passes through the second anti-reflection layer 111 and the second passivation layer 110 to contact the p-type emitter 109 of the n-type silicon wafer 100; the front electrode 112 is a silver-aluminum electrode, and the silver-aluminum electrode contacts the p-type emitter 109 to form a p+ doped region.

[0189] The emitter is located on the front surface of the silicon substrate.

[0190] Example 2

[0191] The difference between this embodiment and embodiment 1 is that the first crystalline conductive layer is a p-type boron-doped polysilicon layer, and the second crystalline conductive layer is also a p-type boron-doped polysilicon layer, and the p-type emitter is replaced by an n-type phosphorus-doped front surface field.

[0192] The rest of the structure remains the same as that of Example 1.

[0193] Example 3

[0194] The difference between this embodiment and embodiment 1 is that the thickness d1 of the first tunneling layer is equal to 3 nm, the thickness d2 of the second tunneling layer is equal to 2.2 nm, d2<d1; the density of the second notches is greater than that of the first notches, and the density of the first notches is 5×10 5 -5×10 10 cm -2 , the density of the second gap is 1×10 8 -1×10 13cm -2 .

[0195] The second crystalline conductive layer includes a plurality of crystal grains, at least one crystal grain passes through at least one second notch and extends into at least one first notch, so that the second crystalline conductive layer contacts the n-type silicon wafer.

[0196] The remaining structures and parameters remain the same as those in Example 1.

[0197] Figure 3 A partial structural schematic diagram of the solar cell provided in this embodiment is shown, wherein 100 is an n-type silicon wafer, 101 is a first tunneling layer, 102 is a first crystalline conductive layer, 103 is a second tunneling layer, 104 is a second crystalline conductive layer, 113 is a first notch, and 114 is a second notch. At the second notch 114, the grains of the second crystalline conductive layer 104 pass through the second notch and extend into the first notch of the first tunneling layer 101, that is, there are complete grains (such as induced vertically grown grains) between the notches of the upper and lower tunneling layers, which reduces the grain boundary density and further improves the carrier transmission efficiency. The arrow indicates the flow direction of the carriers at the first notch.

[0198] Figure 4 and Figure 5 Schematic diagrams of the first tunnel layer and the second tunnel layer in the solar cells provided in Example 1, Example 2 and Example 3 are respectively shown. By comparison, it can be seen that the first tunnel layer is denser than the second tunnel layer, that is, the density of the gaps in the second tunnel layer is greater than the density of the gaps in the first tunnel layer.

[0199] Example 4

[0200] This embodiment provides a solar cell, and its structural schematic diagram is as follows Figure 6 As shown, including:

[0201] N-type silicon wafer 100 .

[0202] The back side of the N-type silicon wafer 100 is provided with a first tunneling layer 101 with a thickness of 3 nm, and the material is silicon oxide. The first tunneling layer 101 has a plurality of first notches, and the density of the first notches is 5×10 5 -5×10 10 cm -2 (Optionally, the density can be 5×10 5 cm -2 , 5×10 6 cm -2 , 5×10 7 cm -2 , 5×10 8 cm -2 , 5×10 9 cm-2 or 5×10 10 cm -2 The first tunneling layer 101 is provided with a plurality of n-type regions and a plurality of p-type regions, the plurality of n-type regions and the plurality of p-type regions are arranged horizontally in a spaced relationship from each other along the back side of the N-type silicon wafer 100, and a partition region is provided between adjacent n-type regions and p-type regions.

[0203] The n-type region includes a stacked n-region first crystalline conductive layer 102A, an n-region second tunneling layer 103A, and an n-region second crystalline conductive layer 104A along a direction away from the first tunneling layer 101, and the p-type region includes a stacked p-region first crystalline conductive layer 102B, a p-region second tunneling layer 103B, and a p-region second crystalline conductive layer 104B along a direction away from the first tunneling layer 101; wherein the thickness of the n-region first crystalline conductive layer 102A and the p-region first crystalline conductive layer 102B are both 30 nm, and the n-region first crystalline conductive layer 102A is an n-type phosphorus-doped multilayer. The first crystalline conductive layer 102B in the p region is a p-type boron-doped polycrystalline silicon layer; the second tunneling layer 103A in the n region and the second tunneling layer 103B in the p region are both 2 nm thick and made of silicon oxide; the second crystalline conductive layer 104A in the n region and the second crystalline conductive layer 104B in the p region are both 50 nm thick, the second crystalline conductive layer 104A in the n region is an n-type phosphorus-doped polycrystalline silicon layer, and the second crystalline conductive layer 104B in the p region is a p-type boron-doped polycrystalline silicon layer; the second tunneling layer 103A in the n region and the second tunneling layer 103B in the p region are both provided with a plurality of second notches, and the density of the notches is 1×10 8 -1×10 13 cm -2 (Optionally, the density can be 1×10 8 cm -2 , 1×10 9 cm -2 , 1×10 10 cm -2 , 1×10 11 cm -2 , 1×10 12 cm -2 or 1×10 13 cm -2 wait).

[0204] The back passivation layer 105 ′ is disposed on the outer surfaces of the n-type region, the p-type region, and the partition region, has a thickness of 5 nm, and is made of silicon oxynitride.

[0205] The back anti-reflection layer is arranged on the outer surface of the back passivation layer 105', and includes a back hydrogenated silicon nitride layer 106' with a thickness of 50nm and a back silicon oxynitride layer 107' with a thickness of 40nm stacked in sequence.

[0206] The doped passivation layer 109' is provided on the front surface of the n-type silicon wafer 100, and the doping element is boron, and the doping concentration is 3×10 20 cm -3 A front passivation layer 110 ′ with a thickness of 5 nm and a front anti-reflection layer 111 ′ with a thickness of 70 nm are sequentially stacked on the doped passivation layer 109 ′. The front passivation layer 110 ′ is an aluminum oxide layer, and the front anti-reflection layer 111 ′ is a silicon nitride layer.

[0207] The metal negative electrode 115 is disposed in the n-type region and contacts the n-region first crystalline conductive layer 102A through the back anti-reflection layer, the back passivation layer 105', the n-region second crystalline conductive layer 104A and the n-region second tunneling layer 103A. The material of the metal negative electrode 115 is silver.

[0208] The metal positive electrode 116 is disposed in the p-type region and contacts the p-region first crystalline conductive layer 102B through the back anti-reflection layer, the back passivation layer 105 ′, the p-region second crystalline conductive layer 104B and the p-region second tunneling layer 103B. The material of the metal positive electrode 116 is silver.

[0209] Example 6

[0210] This embodiment provides a solar cell, and its structural schematic diagram is as follows Figure 7 As shown, including:

[0211] P-type silicon wafer 600.

[0212] A plurality of n-type regions and p-type regions are disposed on the back side of the P-type silicon wafer 600 , and the plurality of n-type regions and p-type regions are spaced apart from each other in a horizontal direction along the back side of the P-type silicon wafer 600 .

[0213] The n-type region is provided with a first tunneling layer, which is a first tunneling oxide layer 601 having a plurality of first notches, a thickness of 3 nm, and a material of silicon oxide. The density of the first notches is 5×10 5 -5×10 10 cm -2 (Optionally, the density can be 5×10 5 cm -2 , 5×10 6 cm -2 , 5×10 7 cm -2 , 5×10 8 cm -2 , 5×10 9 cm -2 or 5×10 10 cm -2 wait).

[0214] and a first crystalline conductive layer, wherein the first crystalline conductive layer is a first n-type phosphorus-doped polysilicon layer 602a, having a thickness of 30 nm, disposed on the first tunneling oxide layer 601, and having a doping concentration of 5×10 19 cm -3 The first n-type phosphorus-doped polysilicon layer 602a extends into at least one of the first gaps and contacts the P-type silicon wafer 600 .

[0215] and a second tunneling layer, wherein the second tunneling layer is a second tunneling oxide layer 603, which is disposed on the first n-type phosphorus-doped polysilicon layer 602a, has a thickness of 2nm, is made of silicon oxide, and has a plurality of second notches, wherein the density of the second notches is greater than that of the first notches, and the density of the second notches is 1×10 8 -1×10 13 cm -2 (Optionally, the density can be 1×10 8 cm -2 , 1×10 9 cm -2 , 1×10 10 cm -2 , 1×10 11 cm -2 , 1×10 12 cm -2 or 1×10 13 cm -2 wait).

[0216] And a second crystalline conductive layer, the second crystalline conductive layer is a second n-type phosphorus-doped polysilicon layer 602b, which is disposed on the second tunneling oxide layer 603 and has a thickness of 50nm, and the second n-type phosphorus-doped polysilicon layer 602b extends into at least one of the second notches, so that the second n-type phosphorus-doped polysilicon layer 602b is in contact with the first n-type phosphorus-doped polysilicon layer 602a.

[0217] The preparation method of the p-type region and the n-type region comprises: firstly depositing a complete first tunneling layer, a first n-type phosphorus-doped polysilicon layer, a second tunneling layer and a second n-type phosphorus-doped polysilicon layer in sequence on the back side of the p-type silicon wafer; then using a laser or mask etching method to partially remove the above functional layers deposited on the back side of the p-type silicon wafer, thereby forming a plurality of spaced openings on the above functional layers, the plurality of openings expose the p-type silicon wafer to form a p-type region, and the above functional layer regions retained outside the openings are n-type regions.

[0218] The solar cell further includes a back passivation layer, which is an interface passivation layer 604 and is disposed on the n-type region and the p-type region. The interface passivation layer 604 is a silicon oxynitride layer with a thickness of 5 nm.

[0219] The solar cell further includes a back anti-reflection layer, which is an interface anti-reflection layer and is disposed on the interface passivation layer 604. The interface anti-reflection layer includes a hydrogenated silicon nitride film 605 with a thickness of 50 nm and a silicon oxynitride film 606 with a thickness of 40 nm stacked in sequence.

[0220] A first electrode 608 is disposed on the interface anti-reflection layer in the n-type region. The first electrode 608 passes through the interface anti-reflection layer and the interface passivation layer 604 and contacts at least the second n-type phosphorus-doped polysilicon layer 602 b . The first electrode 608 is an Ag electrode.

[0221] A second electrode 607 is provided on the interface anti-reflection layer located in the p-type region. The second electrode 607 passes through the interface anti-reflection layer and the interface passivation layer 604 (the opening passing through the interface anti-reflection layer and the interface passivation layer 604 can be a laser opening or an opening formed by sintering and penetrating aluminum paste) and enters the P-type silicon wafer 600. The second electrode 607 has a p-type contact portion 612 in the P-type silicon wafer 600. The second electrode 607 is an aluminum electrode. The p-type contact portion 612 is an aluminum-silicon alloy contact portion, which is formed by sintering the aluminum electrode into the P-type silicon wafer 600 and reacting with the P-type silicon wafer 600 to form a p+ layer of Al-Si alloy, thereby realizing ohmic contact.

[0222] The front side of the P-type silicon wafer 600 is provided with a doped passivation layer, which is a boron doped layer 609 with a doping concentration of 3×10 20 cm -3 A front passivation layer 610 and a front reflective layer 611 are sequentially stacked on the boron-doped layer 609 in a direction away from the P-type silicon wafer 600. The front passivation layer 610 is an aluminum oxide layer with a thickness of 5 nm, and the front anti-reflective layer 611 is a silicon nitride layer with a thickness of 70 nm.

[0223] In this embodiment, the p-type region does not have a first tunneling layer, a first crystalline conductive layer, a second tunneling layer, and a second crystalline conductive layer, but directly forms a back passivation layer and a back anti-reflection layer, and the aluminum electrode is directly sintered to achieve ohmic contact, which reduces the isolation process steps and is beneficial to industrial manufacturing. In addition, the aluminum electrode has a lower cost, and the p+ layer of the Al-Si alloy forms an ohmic contact, which improves the carrier transmission efficiency.

[0224] The applicant declares that the above is only a specific implementation mode of the present invention, but the protection scope of the present invention is not limited thereto. Those skilled in the art should understand that any changes or substitutions that can be easily thought of by those skilled in the art within the technical scope disclosed by the present invention shall fall within the protection scope and disclosure scope of the present invention.

Claims

1. A solar cell, characterized in that: include: Silicon substrate; The back side of the silicon substrate is stacked with a first tunneling layer, a first crystalline conductive layer, a second tunneling layer, and a second crystalline conductive layer; The first tunneling layer has a plurality of first gaps; The first crystalline conductive layer extends into at least one of the first gaps and contacts the silicon substrate; The second tunneling layer has a plurality of second gaps; The first crystalline conductive layer and / or the second crystalline conductive layer extends into at least one of the second notches, so that the second crystalline conductive layer contacts the first crystalline conductive layer; The density of the second gaps in the second tunneling layer is greater than the density of the first gaps in the first tunneling layer.

2. The solar cell according to claim 1, characterized in that The density of the first gaps in the first tunneling layer is 5×10 5 -5×10 10 cm -2 The density of the second gaps in the second tunneling layer is 1×10 8 -1×10 13 cm -2 .

3. The solar cell according to claim 1, characterized in that The width of the first gap and / or the width of the second gap is less than 200 nm.

4. The solar cell according to claim 1, characterized in that The first crystalline conductive layer and the second crystalline conductive layer each include a plurality of crystal grains; wherein at least one of the crystal grains penetrates at least one of the second notches and extends into at least one of the first notches, so that the second crystalline conductive layer contacts the silicon substrate.

5. The solar cell according to claim 1, characterized in that: The thickness of the first crystalline conductive layer is denoted as d3, and the thickness of the second crystalline conductive layer is denoted as d4, where d3<d4.

6. The solar cell according to claim 5, characterized in that: The ratio of d3 to d4 is 1:10 to 7:

10.

7. The solar cell according to claim 5, characterized in that: The value range of d3 is 10-50nm; the value range of d4 is 20-90nm.

8. The solar cell according to claim 7, characterized in that: The value range of d3 is 15-40nm, and the value range of d4 is 30-80nm.

9. The solar cell according to claim 1, characterized in that: The first crystalline conductive layer and the second crystalline conductive layer each independently include a polysilicon layer or a silicon carbide layer.

10. The solar cell according to claim 1, characterized in that: The silicon substrate has a first conductivity type; the first crystalline conductive layer and the second crystalline conductive layer have the first conductivity type or the second conductivity type.

11. The solar cell according to claim 10, characterized in that The first crystalline conductive layer and the second crystalline conductive layer both have a first conductive type doping element or a second conductive type doping element, and a doping concentration of the doping element in the first crystalline conductive layer is lower than a doping concentration of the doping element in the second crystalline conductive layer.

12. The solar cell according to claim 11, characterized in that: The doping concentration of the doping element in the first crystalline conductive layer is 1×10 18 -5×10 20 cm -3 The doping concentration of the doping element in the second crystalline conductive layer is 3×10 19 -1×10 22 cm -3 .

13. The solar cell according to claim 1, characterized in that The first tunnel layer and the second tunnel layer each independently include at least one of a silicon oxide layer, a silicon nitride layer, a silicon oxynitride layer, and an aluminum oxide layer.

14. The solar cell according to claim 1, characterized in that The thickness of the first tunneling layer is denoted as d1, and the thickness of the second tunneling layer is denoted as d2, where d2≤d1.

15. The solar cell according to claim 14, characterized in that: The value ranges of d1 and d2 are independently 1-10 nm.

16. The solar cell according to claim 15, characterized in that: The value ranges of d1 and d2 are independently 2-5 nm.

17. The solar cell according to claim 16, characterized in that: The value ranges of d1 and d2 are independently 2.5-5 nm.

18. The solar cell according to claim 10, characterized in that: The solar cell further comprises a first passivation layer, which is arranged on a surface of the second crystalline conductive layer on a side away from the back side of the silicon substrate, and a first anti-reflection layer is arranged on the first passivation layer.

19. The solar cell according to claim 18, characterized in that The first passivation layer includes at least one of a silicon oxynitride layer, a silicon nitride layer and a silicon oxide layer; and the first anti-reflection layer includes a hydrogenated silicon nitride layer and / or a silicon oxynitride layer.

20. The solar cell according to claim 19, characterized in that The first passivation layer is a silicon oxynitride layer; the first anti-reflection layer comprises a hydrogenated silicon nitride layer and a silicon oxynitride layer which are sequentially stacked in a direction away from the back side of the silicon substrate.

21. The solar cell according to claim 18, characterized in that The solar cell further includes an emitter, which is located on the front side of the silicon substrate and has a conductivity type opposite to that of the silicon substrate; or, the solar cell further includes a front surface field, which is located on the front side of the silicon substrate and has the same conductivity type as that of the silicon substrate.

22. The solar cell according to claim 21, characterized in that The emitter or the front surface field is located on the inner side or the outer side of the front surface of the silicon substrate.

23. The solar cell according to claim 21, characterized in that The solar cell further includes a second passivation layer located on the emitter or the front surface field.

24. The solar cell according to claim 23, characterized in that The second passivation layer includes at least one of an aluminum oxide layer, a silicon oxide layer and a silicon nitride layer.

25. The solar cell according to claim 23, characterized in that A second anti-reflection layer is disposed on the second passivation layer.

26. The solar cell according to claim 25, characterized in that The second anti-reflection layer includes at least one of a silicon nitride layer, a silicon oxynitride layer, a silicon oxide layer, and a magnesium fluoride layer.

27. The solar cell according to claim 23, characterized in that The solar cell further comprises: a back electrode, the back electrode passing through the first passivation layer and contacting at least the second crystalline conductive layer; A front electrode is provided, wherein the front electrode passes through the second passivation layer and contacts the emitter or the front surface field.

28. The solar cell according to claim 1, characterized in that The first crystalline conductive layer and the second crystalline conductive layer each include a polycrystalline conductive layer formed by crystallizing an amorphous conductive layer through heat treatment.

29. The solar cell according to claim 1, characterized in that A plurality of first conductive type regions and a plurality of second conductive type regions are provided on the back side of the silicon substrate, and the plurality of first conductive type regions and the plurality of second conductive type regions are arranged spaced apart from each other in a horizontal direction along the back side of the silicon substrate; The first tunneling layer, the first crystalline conductive layer, the second tunneling layer, and the second crystalline conductive layer are disposed in the first conductive type region or the second conductive type region.

30. The solar cell according to claim 29, characterized in that The solar cell also includes a back passivation layer, which is arranged on the second conductive type region and the first conductive type region. A first electrode is arranged on the back passivation layer in the first conductive type region, and the first electrode passes through the back passivation layer and contacts at least the second crystalline conductive layer.

31. The solar cell according to claim 30, characterized in that A second electrode is disposed on the back passivation layer in the second conductive type region. The second electrode passes through the back passivation layer and enters the silicon substrate. The second electrode has a second conductive type contact portion in the silicon substrate.

32. The solar cell according to claim 31, characterized in that The second electrode is an aluminum electrode, and the second conductive type contact portion is an aluminum-silicon alloy contact portion.

33. The solar cell according to claim 29, characterized in that A doped passivation layer is disposed on the front side of the silicon substrate, and a front passivation layer and / or a front anti-reflection layer is stacked on the doped passivation layer in a direction away from the silicon substrate.

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