HVIC adaptive dead time test circuit and method

Abstract

The application provides an adaptive dead time test circuit and method of an HVIC. The method tests each group of upper and lower bridge input complementary dead time-free driving signals at different temperatures, tests whether the upper and lower bridge driving signals will output different dead times according to different loads, and determines whether the corresponding dead time is qualified by matching the relationship between different loads and dead times due to different loads and different falling times of the to-be-tested circuit VS, so as to achieve the effect of testing the function of the adaptive dead time circuit of the HVIC. The test method can improve the efficiency of circuit testing and avoid the flow of unqualified products with adaptive dead time function into the market.

Description

Technical Field

[0001] The present invention relates to the technical field of integrated circuits, and in particular to an HVIC adaptive dead time test circuit and method. Background Art

[0002] With the rapid development of industry, IPM intelligent power modules (IPMs) are widely used in various fields. As a key component within the IPM, the performance of the driver IC (HVIC) determines its performance. The adaptive dead-band circuit is a crucial circuit within the HVIC. When LIN and HIN are complementary signals with no dead-band, the circuit sets an appropriate dead-band time based on changes in the application system load to prevent direct conduction of the upper and lower bridges, which could damage the IGBT. Therefore, when HVICs are off the production line, their performance indicators must be tested to ensure they meet standards.

[0003] However, the existing HVIC adaptive dead time circuit test process is not unified, the detection process does not have a relatively complete standard, and the test results are relatively incomplete. Summary of the Invention

[0004] The present invention provides an HVIC adaptive dead time test circuit and method, aiming to solve the problems of non-standard dead time test process and incomplete test results of the existing HVIC circuit.

[0005] To solve the above technical problems, in a first aspect, the present invention provides an HVIC adaptive dead time test circuit for testing the dead time of an HVIC circuit to be tested. The HVIC adaptive dead time test circuit includes a DC power supply, a filter capacitor, a signal generator interface, and an oscilloscope port, wherein:

[0006] A first end of the DC power supply is connected to a power supply end of the HVIC circuit to be tested, and a second end of the DC power supply is connected to a ground end of the HVIC circuit to be tested;

[0007] The first end of the filter capacitor is connected to the first end of the DC power supply, and the second end of the filter capacitor is connected to the second end of the DC power supply;

[0008] The signal generator interface includes a first interface and a second interface, wherein a first end of the first interface is connected to a high-level input end of the HVIC circuit to be tested, and a second end of the first interface is connected to a ground end of the HVIC circuit to be tested; a first end of the second interface is connected to a low-level input end of the HVIC circuit to be tested, and a second end of the second interface is connected to a ground end of the HVIC circuit to be tested;

[0009] The oscilloscope port includes a first port and a second port, wherein a first end of the first port is connected to a high-level output end of the HVIC circuit to be tested, and a second end of the first port is connected to a ground end of the HVIC circuit to be tested; a first end of the second port is connected to a low-level output end of the HVIC circuit to be tested, and a second end of the second port is connected to a ground end of the HVIC circuit to be tested;

[0010] The HVIC adaptive dead time test circuit further includes a first capacitor, a second capacitor, a third capacitor, a first transistor, a second transistor, a first inductor, a first resistor, a second resistor, a third resistor, a first switch and a second switch, wherein:

[0011] A first end of the first capacitor is connected to the VB end of the HVIC circuit to be tested, and a second end of the first capacitor is connected to the VS end of the HVIC circuit to be tested;

[0012] The first end of the first inductor is connected to the second end of the first capacitor, the second end of the first inductor is connected to the first end of the second capacitor; the second end of the second capacitor is connected to the ground terminal of the HVIC circuit to be tested;

[0013] A first end of the third capacitor is connected to a high-voltage DC power supply, and a second end of the third capacitor is connected to a ground terminal of the HVIC circuit to be tested;

[0014] The gate of the first transistor is connected to the high-level output terminal of the HVIC circuit to be tested, the drain of the first transistor is connected to the high-voltage DC power supply, and the gate of the first transistor is connected to the first end of the first inductor;

[0015] The gate of the second transistor is connected to the low-level output terminal of the HVIC circuit to be tested, the drain of the second transistor is connected to the ground terminal of the HVIC circuit to be tested, and the gate of the second transistor is connected to the first end of the first inductor;

[0016] The first resistor, the second resistor, and the third resistor are connected in series in sequence, a first end of the first resistor is connected to the second end of the first inductor, and a second end of the third resistor is connected to the ground end of the HVIC circuit to be tested;

[0017] The first end of the first switch is connected to the first end of the second resistor, and the second end of the first switch is connected to the second end of the second resistor; the first end of the second switch is connected to the first end of the third resistor, and the second end of the second switch is connected to the second end of the third resistor.

[0018] Furthermore, the maximum output voltage of the DC power supply is greater than 20V, and the maximum output current is greater than 0.5A.

[0019] Furthermore, the output voltage range of the signal generator interface is 0-15V.

[0020] Furthermore, both the first transistor and the second transistor are gallium nitride field effect transistors.

[0021] In a second aspect, the present invention further provides an HVIC adaptive dead time testing method implemented based on the HVIC adaptive dead time testing circuit as described above, comprising the following steps:

[0022] S101, determining a dead time T1 when a preset first resistor is loaded in the HVIC circuit to be tested, a dead time T2 when the first resistor and the second resistor are loaded, and a dead time T3 when the first resistor, the second resistor, and the third resistor are loaded;

[0023] S102, setting the test temperature of the HVIC circuit to be tested;

[0024] S103, closing the first switch and the second switch, turning on the DC power supply and the high-voltage DC power supply;

[0025] S104, starting a signal generator to output a signal, and recording, by an oscilloscope, the time from the output voltage value of the high-level output end of the HVIC circuit to be tested to the maximum value to 50% of the output interval as a first test time a1, or recording, by an oscilloscope, the time from the output voltage value of the low-level output end of the HVIC circuit to be tested to the minimum value to 50% of the output interval as a second test time a2;

[0026] S105, Judgment T1 (95%) <a1<T1(1+5%)、或T1(95%)<a2<T1(1+5%)是否成立,若否,退出测试;

[0027] S106, turning off the DC power supply and the high-voltage DC power supply;

[0028] S107: Open the first switch, close the second switch, and turn on the DC power supply and the high-voltage DC power supply;

[0029] S108, starting the signal generator to output a signal, and recording, by the oscilloscope, the time from the output voltage value of the high-level output end of the HVIC circuit to be tested to the maximum value to 50% of the output interval as a third test time a3, or recording, by the oscilloscope, the time from the output voltage value of the low-level output end of the HVIC circuit to be tested to the minimum value to 50% of the output interval as a fourth test time a4;

[0030] S109, judgement T2 (95%) <a3<T2(1+5%)、或T2(95%)<a4<T2(1+5%)是否成立,若否,退出测试;

[0031] S1010, turning off the DC power supply and the high-voltage DC power supply;

[0032] S1011. Turn on the first switch and the second switch, and turn on the DC power supply and the high-voltage DC power supply;

[0033] S1012, starting the signal generator to output a signal, and recording, by the oscilloscope, the time from the output voltage value of the high-level output end of the HVIC circuit to be tested to the maximum value to 50% of the output interval as a fifth test time a5, or recording, by the oscilloscope, the time from the output voltage value of the low-level output end of the HVIC circuit to be tested to the minimum value to 50% of the output interval as a sixth test time a6;

[0034] S1013, judge T3 (95%) <a5<T3(1+5%)、或T3(95%)<a6<T3(1+5%)是否成立,若否,退出测试;若是,输出所述待测HVIC电路的死区时间测试结果。

[0035] Furthermore, the HVIC adaptive dead time testing method further includes the steps of:

[0036] S1014: Determine the operating temperature of the HVIC circuit to be tested, change the current test temperature through the temperature control box, and then return to step S103.

[0037] Furthermore, in steps S103, S107, and S1011, the output of the DC power supply is set to 15V, and the output of the high-voltage DC power supply is set to 300V.

[0038] The beneficial effect achieved by the present invention lies in proposing an HVIC adaptive dead time test circuit and method implemented using different loads. The method tests each group of upper and lower bridge input complementary, dead-time-free drive signals at different temperatures, and tests whether the upper and lower bridge drive signals output different dead times according to different loads. Due to different loads, the fall time of the circuit to be tested VS is different. By matching the relationship between different loads and dead times, it is determined whether the corresponding dead time is qualified, thereby achieving the effect of testing the function of the HVIC adaptive dead time circuit. The test method of the present invention can improve the efficiency of circuit testing and prevent products with unqualified adaptive dead time functions from entering the market. BRIEF DESCRIPTION OF THE DRAWINGS

[0039] Figure 11 is a schematic structural diagram of an HVIC adaptive dead time test circuit provided by an embodiment of the present invention;

[0040] Figure 2 1 is a schematic diagram of complementary PWM waves of an HVIC circuit to be tested provided by an embodiment of the present invention;

[0041] Figure 3 Schematic diagram of the dead time test provided by an embodiment of the present invention. DETAILED DESCRIPTION

[0042] In order to make the purpose, technical solutions and advantages of the present invention more clearly understood, the present invention will be further described in detail below with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are only used to explain the present invention and are not intended to limit the present invention.

[0043] Please refer to Figure 1 , Figure 1 1 is a schematic diagram of the structure of an HVIC adaptive dead time test circuit 200 provided in an embodiment of the present invention. The HVIC adaptive dead time test circuit 200 is used to test the dead time of an HVIC circuit 201 to be tested. The HVIC adaptive dead time test circuit 200 includes a DC power supply 202, a filter capacitor 203, a signal generator interface, and an oscilloscope port, wherein:

[0044] A first end of the DC power supply 202 is connected to a power supply terminal VCC of the HVIC circuit to be tested, and a second end of the DC power supply 202 is connected to a ground terminal GND of the HVIC circuit to be tested;

[0045] A first end of the filter capacitor 203 is connected to a first end of the DC power supply 202 , and a second end of the filter capacitor 203 is connected to a second end of the DC power supply 202 ;

[0046] The signal generator interface includes a first interface 204 and a second interface 205, wherein a first end of the first interface 204 is connected to a high-level input terminal HIN of the HVIC circuit to be tested, and a second end of the first interface 204 is connected to a ground terminal GND of the HVIC circuit to be tested; a first end of the second interface 205 is connected to a low-level input terminal LIN of the HVIC circuit to be tested, and a second end of the second interface 205 is connected to a ground terminal GND of the HVIC circuit to be tested;

[0047] The oscilloscope port includes a first port 206 and a second port 207, wherein a first end of the first port 206 is connected to a high-level output terminal HO of the HVIC circuit to be tested, and a second end of the first port 206 is connected to a ground terminal GND of the HVIC circuit to be tested; a first end of the second port 207 is connected to a low-level output terminal LO of the HVIC circuit to be tested, and a second end of the second port 207 is connected to a ground terminal GND of the HVIC circuit to be tested;

[0048] The HVIC adaptive dead time test circuit 200 further includes a first capacitor C1, a second capacitor C2, a third capacitor C3, a first transistor GaN FET1, a second transistor GaN FET2, a first inductor L1, a first resistor R1, a second resistor R2, a third resistor R3, a first switch K1, and a second switch K2, wherein:

[0049] A first end of the first capacitor C1 is connected to the VB end of the HVIC circuit to be tested, and a second end of the first capacitor C1 is connected to the VS end of the HVIC circuit to be tested;

[0050] The first end of the first inductor L1 is connected to the second end of the first capacitor C1, and the second end of the first inductor L1 is connected to the first end of the second capacitor C2; the second end of the second capacitor C2 is connected to the ground terminal GND of the HVIC circuit to be tested;

[0051] A first end of the third capacitor C3 is connected to a high-voltage direct current power supply DC, and a second end of the third capacitor C3 is connected to a ground terminal GND of the HVIC circuit to be tested;

[0052] The gate of the first transistor GaN FET1 is connected to the high-level output terminal HO of the HVIC circuit to be tested, the drain of the first transistor GaN FET1 is connected to the high-voltage direct current power supply DC, and the gate of the first transistor GaN FET1 is connected to the first end of the first inductor L1;

[0053] The gate of the second transistor GaN FET2 is connected to the low-level output terminal LO of the HVIC circuit to be tested, the drain of the second transistor GaN FET2 is connected to the ground terminal GND of the HVIC circuit to be tested, and the gate of the second transistor GaN FET2 is connected to the first end of the first inductor L1;

[0054] The first resistor R1, the second resistor R2, and the third resistor R3 are connected in series in sequence, a first end of the first resistor R1 is connected to the second end of the first inductor L1, and a second end of the third resistor R3 is connected to the ground terminal GND of the HVIC circuit to be tested;

[0055] A first end of the first switch K1 is connected to a first end of the second resistor R2, and a second end of the first switch K1 is connected to a second end of the second resistor R2; a first end of the second switch K2 is connected to a first end of the third resistor R3, and a second end of the second switch K2 is connected to a second end of the third resistor R3.

[0056] Furthermore, the maximum output voltage of the DC power supply 202 is greater than 20V, and the maximum output current is greater than 0.5A.

[0057] Furthermore, the output voltage range of the signal generator interface is 0-15V.

[0058] Furthermore, both the first transistor GaN FET1 and the second transistor GaN FET2 are gallium nitride field effect transistors.

[0059] The complementary PWM wave of the HVIC circuit 201 to be tested is as follows: Figure 2 As shown, the adaptive dead zone circuit sets the corresponding dead zone time according to the load condition to prevent the upper bridge power device and the lower bridge power device from being damaged by direct conduction. The embodiment of the present invention tests the dead zone time of this function by the following method.

[0060] An embodiment of the present invention further provides an HVIC adaptive dead time testing method implemented based on the HVIC adaptive dead time testing circuit 200 as described above, comprising the following steps:

[0061] S101, determining a dead time T1 when a preset first resistor R1 is loaded in the HVIC circuit 201 to be tested, a dead time T2 when the first resistor R1 and the second resistor R2 are loaded, and a dead time T3 when the first resistor R1, the second resistor R2 and the third resistor R3 are loaded;

[0062] S102, setting the test temperature of the HVIC circuit 201 to be tested;

[0063] S103, close the first switch K1 and the second switch K2, and turn on the DC power supply 202 and the high-voltage DC power supply DC;

[0064] S104, start the signal generator to output a signal, and record the time from the maximum value to 50% of the output interval of the output voltage value of the high-level output terminal HO of the HVIC circuit 201 to be tested by the oscilloscope as the first test time a1, or record the time from the minimum value to 50% of the output interval of the output voltage value of the low-level output terminal LO of the HVIC circuit 201 to be tested by the oscilloscope as the second test time a2; the schematic diagram of the test dead time is shown in FIG. Figure 3 As shown;

[0065] S105, Judgment T1 (95%) <a1<T1(1+5%)、或T1(95%)<a2<T1(1+5%)是否成立,若否,退出测试;

[0066] S106, turning off the DC power supply 202 and the high-voltage DC power supply DC;

[0067] S107, opening the first switch K1, closing the second switch K2, and turning on the DC power supply 202 and the high-voltage DC power supply DC;

[0068] S108, starting the signal generator to output a signal, and recording, by the oscilloscope, the time from the output voltage value of the high-level output terminal HO of the HVIC circuit 201 to be tested to the maximum value to 50% of the output interval as a third test time a3, or recording, by the oscilloscope, the time from the output voltage value of the low-level output terminal LO of the HVIC circuit 201 to be tested to the minimum value to 50% of the output interval as a fourth test time a4;

[0069] S109, judgement T2 (95%) <a3<T2(1+5%)、或T2(95%)<a4<T2(1+5%)是否成立,若否,退出测试;

[0070] S1010, turning off the DC power supply 202 and the high-voltage DC power supply DC;

[0071] S1011, turning on the first switch K1 and the second switch K2, and turning on the DC power supply 202 and the high-voltage DC power supply DC;

[0072] S1012, starting the signal generator to output a signal, and recording, by the oscilloscope, the time from the output voltage value of the high-level output terminal HO of the HVIC circuit 201 to be tested to the maximum value to 50% of the output interval as a fifth test time a5, or recording, by the oscilloscope, the time from the output voltage value of the low-level output terminal LO of the HVIC circuit 201 to be tested to the minimum value to 50% of the output interval as a sixth test time a6;

[0073] S1013, judge T3 (95%) <a5<T3(1+5%)、或T3(95%)<a6<T3(1+5%)是否成立,若否,退出测试;若是,输出所述待测HVIC电路201的死区时间测试结果。

[0074] Furthermore, the HVIC adaptive dead time testing method further includes the steps of:

[0075] S1014: Determine the operating temperature of the HVIC circuit 201 to be tested, change the current test temperature via the temperature control box, and then return to step S103. Generally, the operating temperature of the HVIC circuit 201 to be tested is between -40°C and 125°C. During implementation, a test cycle can be defined to complete the test process for specific temperatures within this operating range, such as cycling through tests at -40°C, 25°C, and 125°C.

[0076] Furthermore, in steps S103, S107, and S1011, the output of the DC power supply 202 is set to 15V, and the output of the high-voltage DC power supply DC is set to 300V.

[0077] In the above process, if the HVIC circuit 201 to be tested can completely execute the process of the HVIC adaptive dead time testing method provided by the embodiment of the present invention, it can be considered that the adaptive dead time circuit of the circuit functions normally; if the test is exited at any step in the process, the functional test fails.

[0078] The beneficial effect achieved by the present invention lies in proposing an HVIC adaptive dead time test circuit and method implemented using different loads. The method tests each group of upper and lower bridge input complementary, dead-time-free drive signals at different temperatures, and tests whether the upper and lower bridge drive signals output different dead times according to different loads. Due to different loads, the fall time of the circuit to be tested VS is different. By matching the relationship between different loads and dead times, it is determined whether the corresponding dead time is qualified, thereby achieving the effect of testing the function of the HVIC adaptive dead time circuit. The test method of the present invention can improve the efficiency of circuit testing and prevent products with unqualified adaptive dead time functions from entering the market.

[0079] Those skilled in the art will appreciate that all or part of the processes in the above-described method embodiments can be implemented by instructing related hardware through a computer program. The program can be stored in a computer-readable storage medium, and when executed, the program can include the processes in the above-described method embodiments. The storage medium can be a magnetic disk, an optical disk, a read-only memory (ROM), or a random access memory (RAM).

[0080] It should be noted that, in this document, the terms "comprises," "includes," or any other variations thereof are intended to encompass non-exclusive inclusion, such that a process, method, article, or apparatus comprising a series of elements includes not only those elements but also other elements not explicitly listed, or elements inherent to such process, method, article, or apparatus. In the absence of further limitations, an element defined by the phrase "comprising a ..." does not exclude the presence of other identical elements in the process, method, article, or apparatus comprising the element.

[0081] Through the above description of the embodiments, those skilled in the art will clearly understand that the methods of the above embodiments can be implemented using software plus the necessary general-purpose hardware platform. Of course, hardware can also be used, but in many cases the former is a more preferred implementation method. Based on this understanding, the technical solution of the present invention, or the portion that contributes to the prior art, can be embodied in the form of a software product. This computer software product is stored in a storage medium (such as ROM / RAM, magnetic disk, or optical disk) and includes a number of instructions for enabling a terminal (which can be a mobile phone, computer, server, air conditioner, or network device, etc.) to execute the methods described in the various embodiments of the present invention.

[0082] The embodiments of the present invention are described above in conjunction with the accompanying drawings. What is disclosed is only a preferred embodiment of the present invention. However, the present invention is not limited to the above-mentioned specific implementation methods. The above-mentioned specific implementation methods are merely illustrative and not restrictive. Under the guidance of the present invention, ordinary technicians in this field can also make many forms and equivalent changes without departing from the scope of protection of the purpose of the present invention and the claims, which are all within the protection of the present invention.

Claims

1. An HVIC adaptive dead time test circuit for testing the dead time of an HVIC circuit to be tested, characterized in that: The HVIC adaptive dead time test circuit includes a DC power supply, a filter capacitor, a signal generator interface and an oscilloscope port, wherein: A first end of the DC power supply is connected to a power supply end of the HVIC circuit to be tested, and a second end of the DC power supply is connected to a ground end of the HVIC circuit to be tested; The first end of the filter capacitor is connected to the first end of the DC power supply, and the second end of the filter capacitor is connected to the second end of the DC power supply; The signal generator interface includes a first interface and a second interface, wherein a first end of the first interface is connected to a high-level input end of the HVIC circuit to be tested, and a second end of the first interface is connected to a ground end of the HVIC circuit to be tested; a first end of the second interface is connected to a low-level input end of the HVIC circuit to be tested, and a second end of the second interface is connected to a ground end of the HVIC circuit to be tested; The oscilloscope port includes a first port and a second port, wherein a first end of the first port is connected to a high-level output end of the HVIC circuit to be tested, and a second end of the first port is connected to a ground end of the HVIC circuit to be tested; a first end of the second port is connected to a low-level output end of the HVIC circuit to be tested, and a second end of the second port is connected to a ground end of the HVIC circuit to be tested; The HVIC adaptive dead time test circuit further includes a first capacitor, a second capacitor, a third capacitor, a first transistor, a second transistor, a first inductor, a first resistor, a second resistor, a third resistor, a first switch and a second switch, wherein: A first end of the first capacitor is connected to the VB end of the HVIC circuit to be tested, and a second end of the first capacitor is connected to the VS end of the HVIC circuit to be tested; The first end of the first inductor is connected to the second end of the first capacitor, the second end of the first inductor is connected to the first end of the second capacitor; the second end of the second capacitor is connected to the ground terminal of the HVIC circuit to be tested; A first end of the third capacitor is connected to a high-voltage DC power supply, and a second end of the third capacitor is connected to a ground terminal of the HVIC circuit to be tested; The gate of the first transistor is connected to the high-level output terminal of the HVIC circuit to be tested, the drain of the first transistor is connected to the high-voltage DC power supply, and the gate of the first transistor is connected to the first end of the first inductor; The gate of the second transistor is connected to the low-level output terminal of the HVIC circuit to be tested, the drain of the second transistor is connected to the ground terminal of the HVIC circuit to be tested, and the gate of the second transistor is connected to the first end of the first inductor; The first resistor, the second resistor, and the third resistor are connected in series in sequence, a first end of the first resistor is connected to the second end of the first inductor, and a second end of the third resistor is connected to the ground end of the HVIC circuit to be tested; The first end of the first switch is connected to the first end of the second resistor, and the second end of the first switch is connected to the second end of the second resistor; the first end of the second switch is connected to the first end of the third resistor, and the second end of the second switch is connected to the second end of the third resistor.

2. The HVIC adaptive dead time test circuit according to claim 1, characterized in that: The maximum output voltage of the DC power supply is greater than 20V, and the maximum output current is greater than 0.5A.

3. The HVIC adaptive dead time test circuit according to claim 1, wherein: The output voltage range of the signal generator interface is 0 - 15V.

4. The HVIC adaptive dead time test circuit according to claim 1, characterized in that: Both the first transistor and the second transistor are gallium nitride field effect transistors.

5. A method for testing HVIC adaptive dead time implemented based on the HVIC adaptive dead time testing circuit according to any one of claims 1 to 4, characterized in that: It includes the following steps: S101. Determine the dead time T1 when the preset load first resistor is in the待测 HVIC circuit, the dead time T2 when the load first resistor and the second resistor are in the circuit, and the dead time T3 when the load first resistor, the second resistor, and the third resistor are in the circuit; S102. Set the test temperature of the待测 HVIC circuit; S103. Close the first switch and the second switch, and turn on the DC power supply and the high - voltage DC power supply; S104. Start the signal generator to output a signal, and record, using an oscilloscope, the time it takes for the output voltage value at the high - level output terminal of the待测 HVIC circuit to reach 50% of the output range from the highest value as the first test time a1, or record, using an oscilloscope, the time it takes for the output voltage value at the low - level output terminal of the待测 HVIC circuit to reach 50% of the output range from the lowest value as the second test time a2; S105. Judge whether T1(95%) < a1 < T1(1 + 5%), or T1(95%) < a2 < T1(1 + 5%) holds. If not, exit the test; S106. Turn off the DC power supply and the high - voltage DC power supply; S107. Open the first switch, close the second switch, and turn on the DC power supply and the high - voltage DC power supply; S108. Start the signal generator to output a signal, and record, using the oscilloscope, the time it takes for the output voltage value at the high - level output terminal of the待测 HVIC circuit to reach 50% of the output range from the highest value as the third test time a3, or record, using the oscilloscope, the time it takes for the output voltage value at the low - level output terminal of the待测 HVIC circuit to reach 50% of the output range from the lowest value as the fourth test time a4; S109. Judge whether T2(95%) < a3 < T2(1 + 5%), or T2(95%) < a4 < T2(1 + 5%) holds. If not, exit the test; S1010. Turn off the DC power supply and the high - voltage DC power supply; S1011. Open the first switch and the second switch, and turn on the DC power supply and the high - voltage DC power supply; S1012. Start the signal generator to output a signal, and record, using the oscilloscope, the time it takes for the output voltage value at the high - level output terminal of the待测 HVIC circuit to reach 50% of the output range from the highest value as the fifth test time a5, or record, using the oscilloscope, the time it takes for the output voltage value at the low - level output terminal of the待测 HVIC circuit to reach 50% of the output range from the lowest value as the sixth test time a6; S1013. Judge whether T3(95%) < a5 < T3(1 + 5%), or T3(9�%) < a6 < T3(1 + 5%) holds. If not, exit the test; if so, output the dead - time test result of the待测 HVIC circuit.

6. The HVIC adaptive dead time testing method according to claim 5, characterized in that: The HVIC adaptive dead - time test method further includes the steps: S1014: Determine the operating temperature of the HVIC circuit to be tested, change the current test temperature through the temperature control box, and then return to step S103.

7. The HVIC adaptive dead time testing method according to claim 5, characterized in that: In steps S103, S107, and S1011, the output of the DC power supply is set to 15V, and the output of the high-voltage DC power supply is set to 300V.

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