Memory system, operating method thereof, and readable storage medium

Abstract

The embodiment of the invention provides a memory system, an operation method thereof and a readable storage medium. The memory system comprises a memory device; the memory controller is coupled with the memory device and is configured to compress a first mapping table to obtain a second mapping table; the first mapping table comprises a corresponding relation between an exponential part of each element in all elements corresponding to the error correction coding equation and an equation coefficient, and the exponential parts of all the elements are a group of continuous data; the second mapping table comprises corresponding relations between exponential parts of partial elements in all the elements and equation coefficients, and the exponential parts of the partial elements are multiple pieces of node data extracted from the continuous data; and utilizing the node data in the second mapping table to obtain an equation coefficient corresponding to the index part of any element in all the elements through segmented query.

Description

Technical Field

[0001] The embodiments of the present disclosure relate to the field of semiconductor technology, and more particularly to a memory system and an operating method thereof, and a readable storage medium. Background Art

[0002] Memory devices are storage devices used to store information in modern information technology. As a typical non-volatile semiconductor memory, NAND memory has gradually become a mainstream product in the storage market due to its high storage density, controllable production cost, suitable editing and erasing speed and retention characteristics. However, as people's requirements for storage devices continue to increase, there is still much room for improvement in memory devices and their systems. Summary of the invention

[0003] According to some aspects of the embodiments of the present disclosure, there is provided a memory system, including:

[0004] Memory device;

[0005] a memory controller coupled to the memory device and configured to:

[0006] The first mapping table is compressed to obtain a second mapping table; the first mapping table includes the corresponding relationship between the exponential part of each element in all the elements corresponding to the error correction coding equation and the equation coefficient, and the exponential part of all the elements is a group of continuous data; the second mapping table includes the corresponding relationship between the exponential part of some elements in all the elements and the equation coefficient, and the exponential part of the some elements is a plurality of node data extracted from the continuous data; using the node data in the second mapping table, through segmented query, the equation coefficient corresponding to the exponential part of any element in all the elements is obtained.

[0007] In some embodiments, all the elements and the corresponding equation coefficients are finite fields; the memory controller is configured to: generate all the elements corresponding to the error correction coding equation; generate the first mapping table based on all the elements; group the exponential part of each element and the corresponding equation coefficient of all the elements in the first mapping table, and select the exponential part of a fixed element in each group as the node data; use the node data and the equation coefficients corresponding to the node data to obtain the second mapping table.

[0008] In some embodiments, the total number of elements contained in each group is substantially the same, the exponential part of all elements contained in each group is a set of continuous data, and the exponential part of a fixed element in each group is the first data in the continuous data in each group.

[0009] In some embodiments, the memory controller is further configured to: when an error occurs in reading the stored data in the memory device, obtain an error correction decoding inverse matrix by querying the node data in the second mapping table and the corresponding bias calculation; and use the error correction decoding inverse matrix to correct the error.

[0010] In some embodiments, the memory controller is specifically configured to:

[0011] When an error occurs in reading the storage data in the memory device, obtaining a plurality of elements corresponding to the erroneous storage data;

[0012] Using a plurality of elements corresponding to the erroneous stored data, a first matrix is ​​obtained;

[0013] Obtaining the equation coefficient corresponding to the exponential part of each element in the first matrix to obtain a second matrix;

[0014] An inverse matrix of the second matrix is ​​calculated to obtain the error correction decoding inverse matrix.

[0015] In some embodiments, the memory controller is specifically configured to:

[0016] For the exponent part of each element in the first matrix, determine the group into which the exponent part of the corresponding element falls and the offset value between the exponent part of the corresponding element and the exponent part of the fixed element falling into the corresponding group; and

[0017] Obtaining equation coefficients corresponding to the exponential part of the fixed elements falling into the group by querying the second mapping table;

[0018] The obtained equation coefficients and the offset value are used to calculate the equation coefficients corresponding to the exponential part of the corresponding element.

[0019] In some embodiments, the memory controller further includes: an encoding circuit, wherein the encoding circuit is configured to:

[0020] According to all the elements, a corresponding equation coefficient matrix is ​​generated;

[0021] Using the equation coefficient matrix, generating a coding matrix;

[0022] The encoding matrix is ​​used to perform encoding operation on the storage data to be written into the memory device to obtain verification data corresponding to the storage data.

[0023] In some embodiments, the memory controller further includes: a decoding circuit, wherein the decoding circuit is configured to:

[0024] The inverse error correction decoding matrix, the remaining storage data without errors, and the check data corresponding to the storage data are used to perform a decoding operation to obtain restored storage data.

[0025] In some embodiments, the encoding circuit and / or the decoding circuit both include a linear feedback shift register circuit (Linear Feedback Shift Register, LFSR).

[0026] In some embodiments, the memory controller is further configured to:

[0027] Performing a read operation on the stored data in the memory device:

[0028] When an error occurs in the read storage data, the erroneous storage data is re-read;

[0029] When the stored data still has errors after the rereading process, soft decoding is performed on the stored data still having errors;

[0030] When errors still occur in the stored data after the soft decoding process, the errors are corrected by using the error correction decoding inverse matrix.

[0031] In some embodiments, the second mapping table is stored in a read-only memory (ROM) of the memory device or the memory controller.

[0032] According to some aspects of the embodiments of the present disclosure, a method for operating a memory system is provided, including:

[0033] The first mapping table is compressed to obtain a second mapping table; the first mapping table includes a correspondence between the exponential part of each element of all elements corresponding to the error correction coding equation and the coefficient of the equation, and the exponential part of all elements is a set of continuous data; the second mapping table includes a correspondence between the exponential part of some elements of all elements and the coefficient of the equation, and the exponential part of the some elements is a plurality of node data extracted from the continuous data;

[0034] The node data in the second mapping table is used to obtain the equation coefficient corresponding to the exponential part of any element in all the elements through segmented query.

[0035] In some embodiments, all the elements and the corresponding equation coefficients are finite fields; the method further comprises:

[0036] Generate all elements corresponding to the error correction coding equation;

[0037] Generate the first mapping table according to all the elements;

[0038] In the process of compressing the first mapping table, the exponential part of each element and the corresponding equation coefficient of all elements in the first mapping table are grouped, and the exponent of a fixed element in each group is selected as the node data;

[0039] The second mapping table is obtained by using the node data and the corresponding equation coefficients.

[0040] In some embodiments, the total number of elements contained in each group is substantially the same, the exponential part of all elements contained in each group is a set of continuous data, and the exponential part of a fixed element in each group is the first data in the continuous data in each group.

[0041] In some embodiments, the method further comprises:

[0042] When an error occurs when reading the stored data in the memory device, an error correction decoding inverse matrix is ​​obtained by querying the node data in the second mapping table and the corresponding offset calculation;

[0043] The error correction is performed using the inverse error correction decoding matrix.

[0044] In some embodiments, obtaining the error correction decoding inverse matrix by querying the node data in the second mapping table and the corresponding offset calculation includes:

[0045] When an error occurs in reading the storage data in the memory device, obtaining a plurality of elements corresponding to the erroneous storage data;

[0046] Using a plurality of elements corresponding to the erroneous stored data, a first matrix is ​​obtained;

[0047] Obtaining the equation coefficient corresponding to the exponential part of each element in the first matrix to obtain a second matrix;

[0048] An inverse matrix of the second matrix is ​​calculated to obtain the error correction decoding inverse matrix.

[0049] In some embodiments, obtaining the equation coefficient corresponding to the exponential part of each element in the first matrix includes:

[0050] For each partial exponent of the element in the first matrix, determine the group into which the exponent part of the corresponding element falls and the offset value between the exponent part of the corresponding element and the exponent part of the fixed element falling into the corresponding group; and

[0051] Obtaining equation coefficients corresponding to power exponents of fixed elements falling into the group by querying the second mapping table;

[0052] The obtained equation coefficients and the offset value are used to calculate the equation coefficients corresponding to the exponential part of the corresponding element.

[0053] In some embodiments, the method further comprises:

[0054] According to all the elements, a corresponding equation coefficient matrix is ​​generated;

[0055] Using the equation coefficient matrix, generating a coding matrix;

[0056] The encoding matrix is ​​used to perform encoding operation on the storage data to be written into the memory device to obtain verification data corresponding to the storage data.

[0057] In some embodiments, the using the inverse error correction matrix to perform error correction includes:

[0058] The inverse error correction decoding matrix, the remaining storage data without errors, and the check data corresponding to the storage data are used to perform a decoding operation to obtain restored storage data.

[0059] In some embodiments, the method further comprises:

[0060] Performing a read operation on the stored data in the memory device:

[0061] When an error occurs in the read storage data, the erroneous storage data is re-read;

[0062] When the stored data still has errors after the rereading process, soft decoding is performed on the stored data still having errors;

[0063] When errors still occur in the stored data after the soft decoding process, the errors are corrected by using the error correction decoding inverse matrix.

[0064] According to some aspects of the embodiments of the present disclosure, a memory controller is provided, wherein the memory controller is configured to:

[0065] The first mapping table is compressed to obtain a second mapping table; the first mapping table includes a correspondence between the exponential part of each element of all elements corresponding to the error correction coding equation and the coefficient of the equation, and the exponential part of all elements is a set of continuous data; the second mapping table includes a correspondence between the exponential part of some elements of all elements and the coefficient of the equation, and the exponential part of the some elements is a plurality of node data extracted from the continuous data;

[0066] The node data in the second mapping table is used to obtain the equation coefficient corresponding to the exponential part of any element in all the elements through segmented query.

[0067] According to some aspects of the embodiments of the present disclosure, a readable storage medium is provided, wherein the readable storage medium stores a computer program, and the computer program implements the operating method when executed.

[0068] The disclosed embodiment compresses the first mapping table to generate a second mapping table, the second mapping table includes the correspondence between the exponential part of some elements in all elements and the coefficients of the equation, the exponential part of the some elements is a plurality of node data extracted from the continuous data; the node data in the second mapping table is used to obtain the coefficients of the equation corresponding to the exponential part of any element in all elements through segmented query. In this way, the second mapping table can achieve the acquisition of any equation coefficient; at the same time, the amount of data included in the second mapping table is smaller than that in the first mapping table, and storing the second mapping table can reduce the storage capacity occupied by the mapping table. BRIEF DESCRIPTION OF THE DRAWINGS

[0069] Figure 1 A schematic diagram of an exemplary system having a memory system according to an embodiment of the present disclosure;

[0070] Figure 2a A schematic diagram of an exemplary memory card having a memory system according to an embodiment of the present disclosure;

[0071] Figure 2b A schematic diagram of an exemplary solid-state drive having a memory system according to an embodiment of the present disclosure;

[0072] Figure 3 is a schematic diagram of an exemplary memory device including a peripheral circuit according to an embodiment of the present disclosure;

[0073] Figure 4 A cross-sectional schematic diagram of a memory cell array including a NAND memory string according to an embodiment of the present disclosure;

[0074] Figure 5 A schematic diagram of an exemplary memory device including a memory cell array and a peripheral circuit according to an embodiment of the present disclosure;

[0075] Figure 6 A schematic diagram of a read operation flow including a reread operation according to an embodiment of the present disclosure;

[0076] Figure 7 A block diagram of a memory controller including an error correction module according to an embodiment of the present disclosure is applied in a memory system;

[0077] Figures 8a to 8d A schematic diagram of equation coefficients according to an embodiment of the present disclosure;

[0078] Fig. 9 A schematic diagram of a mapping table according to an embodiment of the present disclosure;

[0079] Fig.10a is a schematic diagram of a first mapping table according to an embodiment of the present disclosure;

[0080] Fig.10b is a schematic diagram of a second mapping table according to an embodiment of the present disclosure;

[0081] Fig.10c A schematic diagram of a table lookup calculation method according to an embodiment of the present disclosure;

[0082] Figures 11a to 11e A schematic diagram of error correction coding and error correction decoding according to an embodiment of the present disclosure;

[0083] Figures 12a to 12d A schematic diagram of decoding using an inverse matrix according to an embodiment of the present disclosure;

[0084] Figure 13a to Figure 13b It is a schematic diagram of another decoding method using an inverse matrix according to an embodiment of the present disclosure;

[0085] Fig.14 The present invention is a schematic diagram of an operation method of a memory system according to an embodiment of the present invention.

[0086] In the above drawings (which are not necessarily drawn to scale), similar reference numerals may describe similar components in different views. Similar reference numerals with different letter suffixes may represent different examples of similar components. The accompanying drawings generally illustrate various embodiments discussed herein by way of example and not limitation. DETAILED DESCRIPTION

[0087] The following will be combined with the embodiments of the present disclosure and the accompanying drawings to clearly and completely describe the technical solutions in the embodiments of the present disclosure. Obviously, the described embodiments are only part of the embodiments of the present disclosure, not all of the embodiments. Based on the embodiments of the present disclosure, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present disclosure.

[0088] The purpose of the terms used herein is only to describe specific embodiments and is not intended to be a limitation of the present disclosure. When used herein, the singular forms "one", "an" and "said / the" are also intended to include plural forms, unless the context clearly indicates otherwise. It should also be understood that the terms "consisting of" and / or "comprising", when used in this specification, determine the presence of the features, integers, steps, operations, elements and / or parts, but do not exclude the presence or addition of one or more other features, integers, steps, operations, elements, parts and / or groups. When used herein, the term "and / or" includes any and all combinations of the relevant listed items.

[0089] In order to enable a more detailed understanding of the features and technical contents of the embodiments of the present disclosure, the implementation of the embodiments of the present disclosure is described in detail below in conjunction with the accompanying drawings. The attached drawings are for reference only and are not used to limit the embodiments of the present disclosure.

[0090] It should be understood that "one embodiment" or "an embodiment" mentioned throughout the specification means that specific features, structures or characteristics related to the embodiment are included in at least one embodiment of the present disclosure. Therefore, "in one embodiment" or "in an embodiment" appearing throughout the specification does not necessarily refer to the same embodiment. In addition, these specific features, structures or characteristics can be combined in one or more embodiments in any suitable manner. It should be understood that in the various embodiments of the present disclosure, the size of the serial number of the above-mentioned processes does not mean the order of execution. The execution order of each process should be determined by its function and internal logic, and should not constitute any limitation on the implementation process of the embodiments of the present disclosure. The serial numbers of the embodiments of the present disclosure are for description only and do not represent the advantages and disadvantages of the embodiments.

[0091] The methods disclosed in several method embodiments provided in the present disclosure can be arbitrarily combined without conflict to obtain new method embodiments.

[0092] The memory device in the embodiments of the present disclosure includes but is not limited to a three-dimensional NAND memory. For ease of understanding, the three-dimensional NAND memory is taken as an example for description.

[0093] Figure 1 A block diagram of an exemplary system 100 having a memory device according to some aspects of the present disclosure is shown. The system 100 may be a mobile phone, a desktop computer, a laptop computer, a tablet computer, a vehicle computer, a game console, a printer, a positioning device, a wearable electronic device, a smart sensor, a virtual reality (VR) device, an augmented reality (AR) device, or any other suitable electronic device having a memory therein. Figure 1 As shown in , system 100 may include a host 108 and a memory system 102, the memory system 102 having one or more memory devices 104 and a memory controller 106. The host 108 may be a processor (e.g., a central processing unit (CPU)) or a system on chip (SoC) (e.g., an application processor (AP)) of an electronic device. The host 108 may be configured to send data to the memory device 104 or receive data from the memory device 104.

[0094] According to some embodiments, the memory controller 106 is coupled to the memory device 104 and the host 108, and is configured to control the memory device 104. The memory controller 106 can manage data stored in the memory device 104 and communicate with the host 108. In some embodiments, the memory controller 106 is designed to operate in a low duty cycle environment, such as a secure digital (SD) card, a compact flash (CF) card, a universal serial bus (USB) flash drive, or other media for use in electronic devices such as personal computers, digital cameras, mobile phones, etc. In some embodiments, the memory controller 106 is designed to operate in a high duty cycle environment SSD or embedded multimedia card (eMMC), which is used as a data storage for mobile devices such as smart phones, tablet computers, laptop computers, etc. and enterprise storage arrays.

[0095] The memory controller 106 may be configured to control the operation of the memory device 104, such as read, erase, and program operations. The memory controller 106 may also be configured to manage various functions regarding data stored or to be stored in the memory device 104, including but not limited to bad block management, garbage collection, logical to physical address translation, wear leveling, etc. In some embodiments, the memory controller 106 is also configured to process error correction codes (ECC) regarding data read from or written to the memory device 104. The memory controller 106 may also perform any other suitable functions, such as formatting the memory device 104. The memory controller 106 may communicate with an external device (e.g., a host 108) according to a specific communication protocol. For example, the memory controller 106 can communicate with external devices through at least one of various interface protocols, such as USB protocol, MMC protocol, peripheral component interconnect (PCI) protocol, PCI Express (PCI-E) protocol, advanced technology attachment (ATA) protocol, serial ATA protocol, parallel ATA protocol, small computer mini interface (SCSI) protocol, enhanced small disk interface (ESDI) protocol, integrated drive electronics (IDE) protocol, Firewire protocol, etc.

[0096] The memory controller 106 and the one or more memory devices 104 may be integrated into various types of storage devices, for example, included in the same package (e.g., a universal flash storage (UFS) package or an eMMC package). That is, the memory system 102 may be implemented and packaged into different types of terminal electronic products. Figure 2aIn one example shown in , the memory controller 106 and the single memory device 104 can be integrated into a memory card 202. The memory card 202 may include a PC card (PCMCIA, Personal Computer Memory Card International Association), a CF card, a Smart Media (SM) card, a memory stick, a multimedia card (MMC, RS-MMC, MMCmicro), an SD card (SD, miniSD, microSD, SDHC), UFS, etc. The memory card 202 may also include a processor that connects the memory card 202 to a host (e.g., Figure 1 The memory card connector 204 is coupled to the host 108 in the embodiment. Figure 2b In another example shown in , the memory controller 106 and the plurality of memory devices 104 may be integrated into the SSD 206. The SSD 206 may also include a processor that interfaces the SSD 206 with a host (e.g., Figure 1 In some implementations, the storage capacity and / or operating speed of the SSD 206 is greater than the storage capacity and / or operating speed of the memory card 202.

[0097] Figure 3 1 is a schematic circuit diagram of an exemplary memory device 300 including peripheral circuits according to some aspects of the present disclosure. The memory device 300 may be Figure 1 300 is an example of a memory device 104 in FIG. The memory device 300 may include a memory cell array 301 and a peripheral circuit 302 coupled to the memory cell array 301. The memory cell array 301 is taken as a three-dimensional NAND-type memory cell array for illustration, wherein the memory cells 306 are provided in the form of an array of NAND memory strings 308, each NAND memory string 308 extending vertically above a substrate (not shown). In some embodiments, each NAND memory string 308 includes a plurality of memory cells 306 coupled in series and stacked vertically. Each memory cell 306 may hold a continuous analog value, such as a voltage or charge, which depends on the number of electrons trapped in the region of the memory cell 306. Each memory cell 306 may be a floating gate type memory cell including a floating gate transistor, or a charge trapping type memory cell including a charge trapping transistor.

[0098] In some embodiments, each memory cell 306 is a single-level cell (SLC) having two possible memory states and can therefore store one bit of data. For example, a first memory state "0" can correspond to a first voltage range, and a second memory state "1" can correspond to a second voltage range. In some embodiments, each memory cell 306 is a multi-level cell (MLC) capable of storing more than a single bit of data in more than four memory states. For example, an MLC can store two bits per cell, three bits per cell (also known as a three-level cell (TLC)), or four bits per cell (also known as a quad-level cell (QLC)). Each MLC can be programmed to take a range of possible nominal storage values. In one example, if each MLC stores two bits of data, the MLC can be programmed by writing one of three possible nominal storage values ​​to the cell, and a fourth nominal storage value in addition to the three nominal storage values ​​can be used to represent an erased state.

[0099] like Figure 3 As shown in , each NAND memory string 308 may include a lower select gate (BSG) 310 at its source terminal and an upper select gate (TSG) 312 at its drain terminal. BSG 310 and TSG 312 may be configured to activate a selected NAND memory string 308 during read and program operations. In some embodiments, the sources of the NAND memory strings 308 in the same memory block 304 are coupled by the same source line (SL) 314 (e.g., a common SL). In other words, according to some embodiments, all NAND memory strings 308 in the same memory block 304 have an array common source (ACS). According to some embodiments, the TSG 312 of each NAND memory string 308 is coupled to a corresponding bit line (BL) 316, and data can be read from or written to the bit line 316 via an output bus (not shown). In some embodiments, each NAND memory string 308 is configured to be selected or deselected by applying a select voltage (e.g., higher than the threshold voltage of a transistor having TSG 312) or a deselect voltage (e.g., 0 V) ​​to a corresponding TSG 312 via one or more TSG lines 313 and / or by applying a select voltage (e.g., higher than the threshold voltage of a transistor having BSG 310) or a deselect voltage (e.g., 0 V) ​​to a corresponding BSG 310 via one or more BSG lines 315.

[0100] like Figure 3As shown in , the NAND memory string 308 can be organized into a plurality of memory blocks 304, each of which can have a common source line 314 (e.g., coupled to ground). In some embodiments, each memory block 304 is a basic data unit for an erase operation, that is, all memory cells 306 on the same memory block 304 are erased at the same time. In order to erase the memory cells 306 in the selected memory block 304a, the source lines 314 coupled to the selected memory block 304a and the unselected memory blocks 304b in the same plane as the selected memory block 304a can be biased with an erase voltage (Vers) (e.g., a high positive voltage (e.g., 20V or higher)). It should be understood that in some examples, the erase operation can be performed at the half-memory block level, at the quarter-memory block level, or at a level with any suitable number of memory blocks or any suitable fraction of memory blocks. The memory cells 306 of adjacent NAND memory strings 308 can be coupled by word lines 318, which select which row of memory cells 306 is affected by read and program operations.

[0101] Figure 4 1 shows a cross-sectional schematic diagram of an exemplary memory cell array 301 including NAND memory strings 308 according to some aspects of the present disclosure. Figure 4 As shown, the NAND memory string 308 may include a stacked structure 410, which includes a plurality of gate layers 411 and a plurality of insulating layers 412 that are alternately stacked in sequence, and a memory string 308 that vertically penetrates the gate layers 411 and the insulating layers 412. The gate layers 411 and the insulating layers 412 may be alternately stacked, and two adjacent gate layers 411 are separated by a layer of insulating layer 412. The number of pairs of gate layers 411 and insulating layers 412 in the stacked structure 410 may determine the number of memory cells included in the memory cell array 301.

[0102] The constituent material of the gate layer 411 may include a conductive material. Conductive materials include, but are not limited to, tungsten (W), cobalt (Co), copper (Cu), aluminum (Al), polysilicon, doped silicon, silicide, or any combination thereof. In some embodiments, each gate layer 411 includes a metal layer, for example, a tungsten layer. In some embodiments, each gate layer 411 includes a doped polysilicon layer. Each gate layer 411 may include a control gate surrounding a memory cell. The gate layer 411 at the top of the stacked structure 410 may extend laterally as an upper selection gate line, the gate layer 411 at the bottom of the stacked structure 410 may extend laterally as a lower selection gate line, and the gate layer 411 extending laterally between the upper selection gate line and the lower selection gate line may serve as a word line layer.

[0103] In some embodiments, the stacked structure 410 may be disposed on a substrate 401. The substrate 401 may include silicon (e.g., single crystal silicon), silicon germanium (SiGe), gallium arsenide (GaAs), germanium (Ge), silicon on insulator (SOI), germanium on insulator (GOI), or any other suitable material.

[0104] In some embodiments, the NAND memory string 308 includes a channel structure extending vertically through the stacked structure 410. In some embodiments, the channel structure includes a channel hole filled with (one or more) semiconductor materials (e.g., as a semiconductor channel) and (one or more) dielectric materials (e.g., as a memory film). In some embodiments, the semiconductor channel includes silicon, for example, polysilicon. In some embodiments, the memory film is a composite dielectric layer including a tunneling layer, a storage layer (also referred to as a "charge trapping / storage layer"), and a barrier layer. The channel structure may have a cylindrical shape (e.g., a column shape). According to some embodiments, the semiconductor channel, the tunneling layer, the storage layer, and the barrier layer are arranged radially from the center of the column toward the outer surface of the column in this order. The tunneling layer may include silicon oxide, silicon oxynitride, or any combination thereof. The storage layer may include silicon nitride, silicon oxynitride, or any combination thereof. The barrier layer may include silicon oxide, silicon oxynitride, a high dielectric constant (high-k) dielectric, or any combination thereof. In one example, the memory film may include a composite layer of silicon oxide / silicon oxynitride / silicon oxide (ONO).

[0105] Return to reference Figure 3 , the peripheral circuit 302 may be coupled to the memory cell array 301 through the bit line 316, the word line 318, the source line 314, the BSG line 315, and the TSG line 313. The peripheral circuit 302 may include any suitable analog, digital, and mixed signal circuits for facilitating the operation of the memory cell array 301 by applying a voltage signal and / or a current signal to each target memory cell 306 and sensing a voltage signal and / or a current signal from each target memory cell 306 via the bit line 316, the word line 318, the source line 314, the BSG line 315, and the TSG line 313. The peripheral circuit 302 may include various types of peripheral circuits formed using metal-oxide-semiconductor (MOS) technology. For example, Figure 5 Some exemplary peripheral circuits are shown, and the peripheral circuit 302 includes a page buffer / sense amplifier 504, a column decoder / bit line driver 506, a row decoder / word line driver 508, a voltage generator 510, a control logic 512, a register 514, an interface 516, and a data bus 518. It should be understood that in some examples, it may also include Figure 5 Additional peripheral circuits not shown.

[0106] The page buffer / sense amplifier 504 may be configured to read data from the memory cell array 301 and program (write) data to the memory cell array 301 according to a control signal from the control logic 512. In one example, the page buffer / sense amplifier 504 may store programming data (write data) to be programmed into the memory cell array 301. In another example, the page buffer / sense amplifier 504 may perform a program verification operation to ensure that the data has been correctly programmed into the memory cell 306 coupled to the selected word line 318. In yet another example, the page buffer / sense amplifier 504 may also sense a low-power signal from the bit line 316 representing a data bit stored in the memory cell 306, and amplify a small voltage swing to a recognizable logic level in a read operation. The column decoder / bit line driver 506 may be configured to be controlled by the control logic 512, and select one or more NAND memory strings 308 by applying a bit line voltage generated from the voltage generator 510.

[0107] The row decoder / word line driver 508 may be configured to be controlled by the control logic 512 and select / deselect the memory block 304 of the memory cell array 301 and select / deselect the word line 318 of the memory block 304. The row decoder / word line driver 508 may also be configured to drive the word line 318 using the word line voltage generated from the voltage generator 510. In some embodiments, the row decoder / word line driver 508 may also select / deselect and drive the BSG line 315 and the TSG line 313. As described in detail below, the row decoder / word line driver 508 is configured to perform a programming operation on the memory cell 306 coupled to the (one or more) selected word lines 318. The voltage generator 510 may be configured to be controlled by the control logic 512 and generate a word line voltage (e.g., a read voltage, a program voltage, a pass voltage, a channel boosting voltage, a verification voltage, etc.), a bit line voltage, and a source line voltage to be supplied to the memory cell array 301.

[0108] In some specific embodiments, the programming operation may include multiple stages. For example, the programming operation may include a channel precharge stage, a channel boosting stage, a programming pulse stage, and a recovery stage. In the channel precharge stage, the voltage generator may generate the voltage required for the next stage, such as the voltage applied to each gate, the channel boosting voltage, etc.; in the channel boosting stage, the channel boosting voltage may be applied to the selected word line; in the programming pulse stage, the target voltage for each programming may be applied to the selected word line. In the recovery stage, the voltage of both the unselected word line and the selected word line may be reduced to the corresponding voltage, such as Vcc, Vdd. In the recovery stage, the voltage may be reduced to the corresponding voltage by one or more step-by-step steps, such as first reducing the voltage to an intermediate voltage, and maintaining the intermediate voltage for a period of time, and then reducing the voltage to the corresponding voltage.

[0109] The control logic 512 may be coupled to each peripheral circuit described above and configured to control the operation of each peripheral circuit. The register 514 may be coupled to the control logic 512 and include a status register, a command register, and an address register for storing status information, a command operation code (OP code), and a command address for controlling the operation of each peripheral circuit. The interface 516 may be coupled to the control logic 512 and act as a control buffer to buffer control commands received from a host (not shown) and relay them to the control logic 512, as well as buffer status information received from the control logic 512 and relay them to the host. The interface 516 may also be coupled to the column decoder / bit line driver 506 via a data bus 518 and act as a data I / O interface and a data buffer to buffer data and relay them to the memory cell array 301 or relay or buffer data from the memory cell array 301.

[0110] In some embodiments, the memory cells of the NAND memory can be divided into single-layer memory cells (one-bit memory cells), double-layer memory cells (two-bit memory cells), three-layer memory cells (three-bit memory cells), four-layer memory cells (four-bit memory cells), and five-layer memory cells (five-bit memory cells) according to the storage density. However, regardless of the single-layer memory cells or multi-layer memory cells, the read operation can be performed in units of pages. Specifically, when performing a read operation, a read voltage is applied to the word line (i.e., the selected word line) coupled to the selected page in the memory device 104. When the read voltage reaches the threshold voltage of multiple memory cells coupled to the selected word line, or the number of memory cells that have not reached the threshold voltage is within the allowable range, the read operation of the entire page ends. The memory cell can be an M-bit memory cell, and the memory cell has 2 including an erased state. M storage states, through 2 M-1 level read voltage reads M bits of stored data. Exemplarily, for example, the first level read voltage is between the threshold voltages of the erased state and the first storage state, and when the first level read voltage is applied to the word line, the storage cell in the erased state is turned on, and the storage cell in the first storage state is not turned on, and the erased state and the first storage state are distinguished and read out.

[0111] It should be noted that in the process of executing the read operation, the storage unit that has not reached the target threshold voltage is marked as an error bit. In order to prevent read errors, an error correction code (ECC) is introduced. When the number of error bits is less than or equal to the maximum number of failed bits that the error correction code can correct, the error bits in the read operation can be corrected. In this way, the correct reading of data can be achieved.

[0112] In some embodiments, the host 108 sends a read command (or a read instruction, a read request) to the memory controller 106 according to the current user command requirements; the memory controller 106 transmits the read control command including information such as the logical address-physical address mapping table to the memory device 104 through the interface 516, controls the memory device 104 to perform a read operation on the storage unit corresponding to the corresponding physical address, and the memory device 104 sends the read data to the memory controller 106 through the interface 516, and the memory controller 106 feeds the data back to the host 108 through the interface such as PCIe or SATA. Specifically, the memory controller 106 sends the read control command to the control logic of the memory device through the interface 516, and the control logic applies the relevant operating voltage to the selected word line or bit line according to the relevant physical address, thereby performing a read operation on the corresponding storage unit. The operating voltage can be generated by the control logic according to the relevant read voltage mapping table to control the voltage generator to generate the relevant operating voltage, and then applied to the word line of the corresponding address through the row decoder, or applied to the bit line of the corresponding address through the column decoder.

[0113] In some other embodiments, when the memory device 104 reads the corresponding storage unit under the control of the memory controller 106, a read error occurs. At this time, the memory controller 106 responds to the failure of the read operation and controls the memory (or the error correction module in the memory controller 106). The error correction mode may include ECC error correction. According to some aspects of the embodiments of the present disclosure, Figure 6 FIG. 1 is a schematic diagram showing an exemplary read operation flow of a memory system 102. Figure 6As shown, when the memory controller 106 controls the memory device 104 to perform a read operation, a default read operation (FW default read) is first performed on the storage unit of the corresponding physical address. After the default read fails, a reread operation (Read retry) is performed after the default read operation fails. After the reread operation fails, a soft decoding operation (Soft decode) is performed. After the soft decoding fails, a redundant array data recovery (RAID) operation is performed. After the RAID operation fails, the read operation stops and the read fails because the error cannot be corrected. The memory controller 106 sends a read fail signal to the host 108. The reread operation and the default read operation can be applied to hard decoding.

[0114] Error correction operations such as reread operation, soft decoding and RAID can be controlled by the error correction module 1064 (e.g., ECC module) in the memory controller 106 to perform the memory device 104. The control command is sent by the memory controller 106 to the memory device 104 via the interface 516, and the memory device 104 feeds back the read information to the memory controller 106 via the interface 516. It should be noted that after any one of the reread operation, soft decoding and RAID operation is read successfully, the subsequent operation can be stopped. It should be noted that Figure 6 The illustrated example is only an example of a read operation flow. In some other embodiments, the memory controller 106 may control the memory device 104 to perform a reread operation, soft decoding, and RAID operation in any order. The present disclosure does not limit the execution order. According to some aspects of the embodiments of the present disclosure, Figure 7 A block diagram of a memory system 102 including a memory controller 106 including an error correction module 1064 is provided. Figure 7 As shown, the memory system 102 includes: a memory controller 106 and a memory, and the memory controller 106 and the memory device 104 can be coupled in any suitable manner. In the embodiment of the present disclosure, the memory controller 106 includes a host I / F 1061, a memory I / F 1062, a control unit 1063, an error correction (ECC) module 1064, a data buffer 1067, and an internal bus 1060, wherein the error correction module 1064 includes an encoding unit 1065 and a decoding unit 1066. The host I / F 1061 outputs the command, user data (write data), etc. received from the host 108 to the internal bus 1060, and sends the user data (read data) read from the memory device 104, the response from the control unit 1063, etc. to the host 108.

[0115] The memory I / F controls the process of writing user data and the like to the memory device 104 and the process of reading from the memory device 104 based on the instruction of the control unit 1063. The control unit 1063 controls the memory system 102 as a whole, and the control unit 1063 is, for example, a central processing unit (CPU), a microprocessor (MPU), etc. When the control unit 1063 receives a command from the host 108 via the host I / F 1061, it performs control according to the command. For example, the control unit 1063 instructs the memory I / F to write user data and parity check to the memory device 104 according to the command from the host 108. In addition, the control unit 1063 instructs the memory I / F to read user data and parity check from the memory device 104 according to the command from the host 108.

[0116] The error correction module 1064 includes an encoding unit 1065 and a decoding unit 1066. The encoding unit 1065 encodes user data of a predetermined size written in the same page to generate parity data. The parity data is written in the page where the user data that is the basis of the encoding has been written, and the decoding unit 1066 uses the parity data for decoding. The data buffer 1067 temporarily stores the user data received from the host 108 before storing it in the memory device 104, and temporarily stores the data read from the memory device 104 before sending it to the host 108. The encoding unit 1065 includes an encoding circuit for encoding, and the decoding unit 1066 includes a decoding circuit for decoding.

[0117] In some specific embodiments, the soft decoding operation can be understood as re-decoding the data through a decoding unit (e.g., a soft decoder) in the memory controller 106, and performing a re-reading operation based on the re-decoded data. The RAID operation can be understood as implementing data mirroring through secondary encoding, and reconstructing the stored data and its parity check data, wherein the re-encoding of the redundant array of the stored data is usually performed in the data buffer of the memory controller 106.

[0118] Regarding the RAID error correction operation, when writing to a certain area of ​​the memory device, the written data will be encoded according to the relevant RAID encoding method, and the verification data generated according to the written data will be stored while writing the data. When the data reading error needs to perform the RAID error correction operation, the correct data is reversed according to the verification data and other non-erroneous data. The data written into the memory device can be grouped, each data group is recorded as a source data group, and each source data group write data is operated through the same encoding equation (for example, each group of write data is XORed), so as to obtain corresponding multiple groups of verification data (Parity), wherein the multiple groups of write data can correspond to the multiple groups of verification data one by one. When a data error or failure occurs, each group of verification data can correct and restore one or more erroneous data in the corresponding group of data, that is, the essence of this method is to solve a one-dimensional linear equation through verification data. If you want to obtain a higher error correction capability, you need to construct multiple different error correction coding equations, so as to generate multiple groups of verification data for a group of write data, and by solving the equation group, you can correct and restore the erroneous data in a group of write data. In some embodiments, RAID error correction can be implemented by a memory controller to correct the data that reads errors. Each group of data may include data written by multiple storage units, or data written by multiple pages. The memory controller may include an encoding unit 1065 and a decoding unit 1066. The encoding unit 1065 includes an encoding circuit, and the encoding unit 1065 performs a RAID encoding operation; the decoding unit 1066 includes a decoding circuit, and performs a RAID decoding operation, and exchanges data with the memory device through the memory I / F 1062.

[0119] In some embodiments, for example, a source data group may include data stored in a storage unit coupled to one or more word lines, for example, may include P data written by one or more word lines, where P is a positive integer. The corresponding coefficients applied to RAID encoding are also P. In some embodiments, the memory device has a higher degree of integration, and a source data group may include 2 ^ Writing data to 16 pages requires 2 ^ 16 equation coefficients or more.

[0120] The coding coefficients of the RAID of the disclosed embodiment can be matrix-operated with the source data group during encoding to obtain check data, and multiple coding coefficients constitute an error correction coding equation, and one error correction coding equation is operated with the source data group to obtain one check data, and multiple error correction coding equations are operated with the source data multiple times to obtain multiple check data, and the number of check data is the maximum amount of data recovered by subsequent RAID decoding. The equation coefficients are the coding coefficients, and the equation coefficients corresponding to the multiple error correction coding equations are linearly independent, so that the data recovered by RAID decoding has a unique solution.

[0121] In some embodiments, Figure 8a A schematic diagram of encoding verification data according to an embodiment of the present disclosure is shown. Figure 8a As shown, the source data set includes 2 ^ 16-1 data blocks, D0 to D(2 ^ 16-1), each data block may include data in a storage unit or data written in a page. D0 to D(2 ^ 16-1) forms a column vector (which can also be considered as a matrix with only one column), the number of rows of the column vector is 2 ^ 16. The matrix used for matrix multiplication with the column vector is the equation coefficient matrix. The number of columns in the equation coefficient matrix is ​​n = 2. ^ 16, each row represents an error correction coding equation, each error correction coding equation includes 2 ^ 16 equation coefficients, equal to the number of data blocks in the source data set. The number of rows in the equation coefficient matrix, that is, the number of error correction coding equations, is equal to the number of generated check data. Figure 8a The number of rows of the equation coefficient matrix shown in is k=4, that is, there are 4 error correction coding equations multiplied by the source data set to obtain 4 check data, Parity1 to Parity4. The equation matrix is ​​a linearly independent matrix. The equation coefficients of the first row can all be 1, and the equation coefficients of the first column can all be 1. When D0 to D(2 ^ When no more than 4 data blocks in 16-1) are erroneous at the same time, the same number of check data as the erroneous data blocks can be arbitrarily selected for decoding and recovery.

[0122] In some embodiments, in combination Figure 8a As shown, when RAID decoding reverses the source data, it is necessary to perform matrix calculation on the check data and the inverse matrix of the equation coefficient matrix to reversely resolve the source data group, thereby recovering the erroneous data. Alternatively, the row data corresponding to the erroneous data is selected from the equation coefficient matrix to form a matrix, and its inverse matrix is ​​used to reversely resolve the erroneous data. The equation coefficient matrix of the embodiment of the present disclosure can set coefficients with reference to the Vandermonde matrix, so that the equation coefficient matrix is ​​a full rank matrix, the entire equation coefficient matrix is ​​reversible, and any m rows taken from the equation coefficient matrix to form an m-order matrix are all reversible. Refer to Figure 8b As shown, each row of the Vandermonde matrix of the embodiment of the present disclosure can be mapped to an exponential term, for example, the first row of data can correspond to 1^0, the second row of data can correspond to an exponent of 1, and the third row of data can correspond to an exponent of 2; the first column of data is all 1, and any m rows taken from the matrix to form an m-order matrix are all reversible and can be linearly independent matrices. Figure 8c As shown, Figure 8b When the Vandermonde matrix is ​​applied to the equation coefficient matrix, the individual equation coefficients of the equation coefficient matrix are Figure 8b The Vandermonde matrices in the GF(1) correspond one to one, for example, GF(1) corresponds to x^1, GF(2) corresponds to x^2, and GF((k-1)(n-1)) corresponds to (x^(n-1))^(k-1).

[0123] In some embodiments, based on Figure 8a The equation coefficient matrix in is processed to obtain a new matrix, which can be recorded as a coding matrix. For example, a unit matrix (the data on the diagonal are all 1, and the other data are 0) can be added to the equation coefficient matrix. The number of data in each row of the unit matrix is ​​equal to the number of row data in the equation coefficient matrix, so that the data obtained after matrix multiplication includes both the check data and D0 to D(2 ^ 16-1), the data can be stored as a whole later to reduce the loss of source data.

[0124] In the embodiments of the present disclosure, refer to Figures 8a to 8c As shown, the equation coefficients in the equation coefficient matrix can be taken from a data domain, the data domain contains non-zero numbers, and the number of data in the data domain is greater than or equal to the number of D in the source data set. Figure 8a In the source data set D0 to D(2 ^ 16-1) as an example, including at least 2 ^ 16 data. Corresponding to the computer binary algorithm, Figure 8b If x in is 2, then Figure 8c The coefficients of the equations in can be recorded as 1, GF(2^1), GF(2^2), GF(2^3), GF(2^(n-1)). 2^(n-1) can be used as an element recorded or mapped in the relevant mapping table, and can be recorded as element 2^i in the mapping table, where the exponential part of the element is i, and the coefficients of the relevant equations are recorded as GF(2^i).

[0125] Reference Figure 8d , Figure 8d A schematic diagram of a portion of the equation coefficient matrix is ​​shown, only GF(2^1) to GF(2^10), i.e., the exponents 1 to 10, are shown, and more exponents are not shown. The equation coefficients can be associated with a mapping table to facilitate firmware calls or calculations to generate equation coefficients. The more equation coefficients there are, the larger the amount of data in the mapping table. An embodiment of the present disclosure provides a memory system that reduces the amount of data in a related mapping table and reduces the storage space occupied by the related mapping table while satisfying a RAID error correction encoding operation or a RAID error correction decoding operation with the same amount of written data.

[0126] According to some aspects of the embodiments of the present disclosure, there is provided a memory system, including:

[0127] Memory device;

[0128] a memory controller coupled to the memory device and configured to:

[0129] The first mapping table is compressed to obtain a second mapping table; the first mapping table includes a correspondence between the exponential part of each element of all elements corresponding to the error correction coding equation and the coefficient of the equation, and the exponential part of all elements is a set of continuous data; the second mapping table includes a correspondence between the exponential part of some elements of all elements and the coefficient of the equation, and the exponential part of the some elements is a plurality of node data extracted from the continuous data;

[0130] The node data in the second mapping table is used to obtain the equation coefficient corresponding to the exponential part of any element in all the elements through segmented query.

[0131] Combination Figure 8d As shown, an error correction coding equation can be Figure 8d A row in the equation coefficient matrix, the elements corresponding to the error correction coding equation include: 2^i, i is a natural number, i is the exponential part of each element, and the equation coefficient is the value in a row of the equation coefficient matrix. i is a natural number, when i is 0, the corresponding equation coefficient is 1, when i is a non-zero number, the corresponding equation coefficient is GF(2^i).

[0132] Combination Figure 8b As shown, the equation coefficient matrix formed by the equation coefficients of the embodiment of the present disclosure can be a linearly independent matrix and a reversible full-rank matrix, and the values ​​of the equation coefficients can be associated with the exponents to satisfy the above-mentioned matrix properties. Figure 8b The equation coefficient matrix is ​​shown. The value of a high-index equation coefficient can be obtained by multiplying or adding other low-index equation coefficients, or the value of a high-index equation coefficient can be factored to obtain the values ​​of other low-index equation coefficients. Based on this, refer to Fig. 9 , Fig. 9 A schematic diagram of a mapping table according to an embodiment of the present disclosure is shown, taking i taking continuous values ​​from 0 to 15 as an example. Fig. 9 The value of gfilog[i] in the equation can be used as the value of an equation coefficient. The value of i represents the exponential part of the equation coefficient. When constructing the equation coefficient matrix, the value of gfilog[i] can be used as the value of an equation coefficient. Fig. 9 For example, Figure 8d The 1 in GF(2^1) corresponds to the value of gfilog[0] when i=0, which is 1. The value of gfilog[1] when i=1 is 2. The highest exponent has no corresponding value. Fig. 9The value of gfilog[i] of high index i in the mapping table can be calculated from gfilog[i] of low index i. When i is large, such as i=2^16-1, there are at least 2^16-1 data, each of which occupies 2Bytes of storage. A row of data in the mapping table requires 2^18B=256KB. For a 32-bit LFSR circuit, the required storage space is about 16GB. If other items need to be mapped, the storage capacity will increase further.

[0133] Fig. 9 The mapping table also shows the gflog[i] item, and the data volume of the mapping table will double to 32GB. gflog maps the binary form to the element exponential form, and gfilog maps the element exponential form to the binary form, providing data sources for different error correction coding and error correction decoding methods.

[0134] Fig. 9 The mapping table in can be set based on a finite field as an example to limit the value of gfilog[i] to its value range. Fig. 9 The elements of the mapping table in can be mapped to primitive polynomials, and the value range of gfilog[i] can be recorded as GF(2^w), w=i+1. For the primitive polynomials P(x) commonly used in the GF(2^w) domain, they can include:

[0135] When w=4, x^4+x+1;

[0136] When w=8, x^8+x^4+x^3+x^2+1;

[0137] When w=16, x^16+x^12+x^3+x+1;

[0138] When w=32, x^32+x^22+x^2+x+1;

[0139] When w=64, x^64+x^4+x^3+x+1.

[0140] Fig. 9 The original polynomial P(x) corresponding to the mapping table is P(x)=x^4+x+1. When i=0, 1, 2, 3, the exponent part does not exceed 4, and gfilog[i]=x^i(2^i) value.

[0141] i=4, gfilog[4]=x^4=x^3*x=x^4mod P(x)=x+1=2+1=3;

[0142] i=5, gfilog[5]=x^5=x^4*x=(x+1)*x=x^2+x=4+2=6;

[0143] i=6, gfilog[6]=x^6=x^5*x=(x^2+x)*x=x^3+x^2=8+4=12;

[0144] i=7, gfilog[7]=x^7=(x^3+x^2)*x=(x^4+x^3mod P(x))=x^3+x+1=8+2+1=11. Subsequent gfilog[i] values ​​are generated in sequence and will not be described in detail.

[0145] It can be understood that as the value of i increases, the source polynomial corresponding to the gfilog[i] value of the next i is the source polynomial corresponding to the gfilog[i] value of the previous i multiplied by x, for example, gfilog[4]=x^4=x^3*xgfilog[5]=x^5=x^4*x. That is to say, after the algorithm for forming the source polynomial is fixed, for the current i and gfilog[i] values, they can be calculated based on the previous i and gfilog[i] values.

[0146] It should be pointed out that Fig. 9 The gfilog[i] and gflog[i] values ​​shown in the mapping table do not increase with the increase of i value, nor do they decrease with the decrease of i value. Taking the gfilog[i] value as an example, its value can be calculated modulo a polynomial to fix its value within a finite field, and its value does not have a positive or negative correlation with the i value. The values ​​of i, gfilog[i] and gflog[i] in the entire mapping table are limited to a similar range, such as Fig. 9 The value range of i is 0-15, the value range of gflog[i] is 0-14, and the value range of gfilog[i] is 1-15. The embodiment of the present disclosure can compress the mapping table, retain part of the mapping table data, and other data can be calculated based on known data, so as to reduce the size of the mapping table and reduce the storage capacity occupied.

[0147] In some embodiments, reference Fig.10a , Fig.10a A schematic diagram of a first mapping table is shown, and the first mapping table may only include gfilog[i] values. The first mapping table records or maps the numerical correspondence between the exponential part (i) and the equation coefficient (gfilog[i]), Fig.10a When including the continuous exponent part 0 to (2^16-1), the first mapping table for all corresponding gfilog[i] values ​​is an uncompressed mapping table. As mentioned above, the gfilog value of the high index can be calculated based on one or more gfilog values ​​of the low index, and the calculation method may include multiplication, addition, or the inverse operation of multiplication and addition. Accordingly, referring to Fig.10bAs shown, the first mapping table is compressed, and several indexes (several i values) in the first mapping table are selected as all i value nodes, and several corresponding gfilog[i] values ​​are selected as node data of all gfilog[i] values. A value interval can be provided between every two i values ​​to divide all gfilog[i] values ​​in the first mapping table into several data segments. When the gfilog[i] value corresponding to a certain i value is needed, the gfilog[i] value corresponding to the required i value can be calculated according to the node interval where the i value is located and the gfilog[i] values ​​before and after it.

[0148] Specifically, in Fig.10b For example, i=256, gfilog

[256] is a node data; i=521, gfilog

[521] is another node data. When 256<i<521, the gfilog[i] value corresponding to any value of 256<i<521 is calculated through the value of gfilog

[256] . For example, i=288, it is determined that i falls between 256 and 521, and the second mapping table is accessed to obtain that the gfilog

[256] corresponding to the value of 256 is 2863. At this time, offset is 288-256=32. According to the generation method of gfilog[i] in the previous text, gfilog

[288] =59187 is calculated through offset. Similarly, by segmented query of relevant node data in the second mapping table, the gfilog[i] values ​​of all or any multiple first mapping tables can be restored, thereby obtaining all equation coefficients required for constructing the equation coefficient matrix. The compressed second mapping table can obtain any equation coefficient or restore the first mapping table, and the amount of data it includes is smaller than the first mapping table before compression, which reduces the amount of data in the mapping table and reduces the storage occupancy of the mapping table. It should be noted that Fig.10a The first mapping table in can be based on Fig. 9 Add elements to the mapping table in . Fig.10a i=15 in is no longer the last element, and gfilog

[15] is valid data.

[0149] by Fig. 9 The mapping table is an example, i takes 0 to 15, and a finite field GF field is recorded as all values ​​from 0 to 15, and all its elements are 16; the corresponding gfilog[i] all values ​​will also fall within the GF field, that is, any gfilog[i] value will be equal to a value between 0 and 15. The GF field can be selected or set according to the Galois field. In the Galois field, each element can be generated according to the exponential polynomial, and the addition, subtraction, multiplication and division results of the numerical values ​​all fall within the field, so the Galois field can meet the equation coefficient setting characteristics in the embodiment of the present disclosure, and when performing related operations, the operation results can be obtained by checking the numerical values ​​in the Galois field, which simplifies the calculation and saves computing power.

[0150] Reference Fig. 9 As shown, according to the calculation rules of the Galois field, the gfilog[i] value is set, and the high-index gfilog[i] value can be calculated through one or more low-index gfilog[i] values, and the value of gfilog[i] falls within the value range of all i values. gfilog[i] can be the inverse table of the mapping table associated with the Galois field, indicating that the element exponential form is mapped to the binary form; gfilog[i] can be the positive table of the mapping table associated with the Galois field, indicating that the binary form is mapped to the element exponential form. According to the setting rules of the Galois field, there is an association between the positive table and the inverse table. When gfilog[i=n]=m, gflog[i=m]=n. Exemplarily, gfilog[4]=3, gflog[3]=4. The inverse table can be obtained based on the positive table, and the positive table can be obtained based on the inverse table. As mentioned above, the first mapping table in the embodiment of the present disclosure may include gfilog[i]. In some other embodiments, the first mapping table may also include gflog[i], which is used for table lookup calculation, simplifies the algorithm, and saves computing power.

[0151] Reference Fig.10b As shown, the first mapping table may also include gflog[i] values, and the mapping table composed of gflog[i] values ​​may also be compressed, or the first mapping table does not include gflog[i] values, and the gflog[i] values ​​may be calculated from the gfilog[i] values ​​in the first mapping table, or calculated from the compressed second mapping table. As mentioned above, when gfilog[i=n]=m, gflog[i=m]=n, and the calculation of the gflog[i] value by the uncompressed first mapping table will not be repeated. Fig.10c The example calculates the value of gflog[i] through the compressed second mapping table. For example, if gflog

[2863] is calculated, that is, the value of i when giflog[i]=2863 is calculated, the table query shows that giflog

[256] =2863 is recorded in the second mapping table, that is, gflog

[2863] =256. For another example, if gflog

[288] is calculated, giflog[i]=288 is not recorded in the second mapping table. At this time, when gfilog[i]=288, the value of i needs to be reversed. The algorithm here is that gfilog[i+i_offset]=N, so that N can be found in the gfilog[i] table, and the value from i_offset is recorded, and finally gflog

[288] =33422 is obtained; gfilog[i=256*131=33536]=N=1282, i_offset=-114.

[0152] The mapping table in the embodiment of the present disclosure is presented in decimal for ease of explanation, but in the actual storage, calling and calculation process of the memory system, it is performed in binary.

[0153] In some embodiments, all the elements and the corresponding equation coefficients are finite fields; and the memory controller is configured to:

[0154] Generate all elements corresponding to the error correction coding equation;

[0155] Generate the first mapping table according to all the elements;

[0156] Grouping the exponential part of each element and the corresponding equation coefficient of all elements in the first mapping table, and selecting the exponential part of a fixed element in each group as the node data;

[0157] The second mapping table is obtained by using the node data and equation coefficients corresponding to the node data.

[0158] In the embodiment of the present disclosure, all elements corresponding to the error correction coding equation are generated. If the corresponding source data group includes D0, D1, D2 to D(2 ^ i) Data block, the corresponding optional elements are 0 to 2 ^ i, i is the exponential part of the element, and the equation coefficient can be gfilog[i].

[0159] For example, Fig. 9 In the example, the source data group to be encoded includes D0, D1, D2 to D(2 ^ 4-1), the total number of elements is 16, and the elements can be represented as 2 ^ i, i takes all natural numbers from 0 to 15, and generates 2 ^ 0, 2 ^ 1 till 2 ^ For all elements of 15, the corresponding first mapping table may at least include gfilog[0], gfilog[1] to gfilog

[15] , and the value of gfilog

[15] is invalid.

[0160] For example, Fig.10a As shown, the source data group to be encoded includes D0, D1, D2 to D(2 ^ 16-1), the total number of elements is 2 ^ 16-1, the element can be represented as 2 ^ i, i takes all natural numbers from 0 to (256*256-1), and generates 2 ^ 0, 2 ^ 1 till 2 ^For all elements of (256*256-1), the corresponding first mapping table may at least include gfilog[0], gfilog[1] to gfilog[256*256-1], and the value of gfilog[256*256-1] is invalid.

[0161] Will Fig.10a The first mapping table in is grouped according to the i value of the exponential part, and each group includes a range of i values. An i value in each group is used as node data, and the gfilog[i] value corresponding to the i value is the equation coefficient corresponding to the node data. For example, i values ​​0 to 255 are grouped as a group, 256 to 511 are grouped as a group, until all elements from 0 to (256*256-1) are divided. One or more node data and the corresponding gfilog[i] values ​​in each group are recorded in the second mapping table. The i value intervals of the group can be arbitrarily large, and the number of i values ​​included in each group can be the same or different.

[0162] In some embodiments, the total number of elements contained in each group is substantially the same, the exponential part of all elements contained in each group is a set of continuous data, and the exponential part of a fixed element in each group is the first data in the continuous data in each group.

[0163] For example, in Fig.10a In the example, 256 i values ​​are used as a group, and the elements from 0 to (256*256-1) are divided into 256 groups. The total number of elements in each group can be equal, and the first element of each group is recorded as a fixed element in the second mapping table. Some groups may record a smaller number of other elements, and the total number is basically the same. For example, in addition to recording the first fixed element, the first group also records the second element, and the exponent is 0 as the coefficient of the equation. Figure 8d The coefficient matrix of the equation in the example may be used repeatedly, or the negative value 1 may be directly set without accessing the mapping table, so i=1 will also be recorded as the second element of the first group, that is, i=0 and i=1 are recorded at the same time. Other groups can only record the first element of each group, such as recording i=256, 512, 256*254, 256*255. In addition to recording the first fixed element, the last group can also record the last element 256*256-1, and its corresponding gfilog[i] value is invalid.

[0164] In some embodiments, the memory controller further includes: an encoding circuit, wherein the encoding circuit is configured to:

[0165] According to all the elements, a corresponding equation coefficient matrix is ​​generated;

[0166] Using the equation coefficient matrix, generating a coding matrix;

[0167] The encoding matrix is ​​used to perform encoding operation on the storage data to be written into the memory device to obtain verification data corresponding to the storage data.

[0168] In some embodiments, the memory controller further includes: a decoding circuit, wherein the decoding circuit is configured to:

[0169] The inverse error correction decoding matrix, the remaining storage data without errors, and the check data corresponding to the storage data are used to perform a decoding operation to obtain restored storage data.

[0170] Reference Figure 7 As shown, the memory controller 106 may include an encoding unit 1065 and a decoding unit 1066 .

[0171] The encoding unit 1065 includes an encoding circuit that can use encoding to generate an encoding matrix and perform encoding operations on the stored data to generate verification data; the decoding unit 1066 may include a decoding circuit that uses the verification data to perform decoding to restore erroneous stored data.

[0172] by Figure 8d Take the generated equation coefficient matrix as an example, Figure 8d The equation coefficient matrix of can be a complete equation coefficient matrix encoding D0, D1, D2 to D5, or a partial example of an equation coefficient matrix encoding more data. Figure 8d Add the identity matrix (all the data on the diagonal are 1 and the rest are 0) to the coefficient matrix of the example equation to generate Fig.11a The number of data in each row of the unit matrix is ​​equal to the number of row data in the equation coefficient matrix, so that the data obtained after the matrix multiplication calculation includes both the check data P1, P2 and P3 and the source data of D0, D1, D2 to D5, which can be used to recover up to any 3 errors in D0 to D5.

[0173] Reference Fig.11b As shown in the figure, taking three data blocks with errors as an example, when D0, D2, and D5 are erroneous, the coefficient matrix multiplied by the column vector containing the erroneous data is a 6×6 matrix. For ease of understanding, the 6×6 square matrix is ​​called the R matrix. The R matrix is Fig.11a The R matrix retains the three rows of equation coefficients corresponding to P1 to P3, that is, it retains the original equation coefficient matrix part and also retains the three rows of equation coefficients corresponding to the error-free data.

[0174] Reference Fig.11c As shown, the inverse matrix R' of the R matrix is ​​generated. R' can be recorded as the inverse matrix of error correction decoding. Multiplying both sides of the equal sign R', the equation still holds. Fig.11c After transforming the equation, we get Fig.11d The equation shown in the figure can be used to recover the erroneous D0, D2 and D5. If the data of two data blocks D are to be recovered, any two of P1 to P3 can be selected at will, similar to Fig.11c The encoding circuit involved in the embodiment of the present disclosure can execute Fig.11a In addition to the encoding operation, other encoding operations can be performed. The decoding circuit performs Fig.11d In addition to the above-mentioned decoding operation, other decoding operations may also be performed.

[0175] In some embodiments, the memory controller is further configured to:

[0176] When an error occurs when reading the stored data in the memory device, an error correction decoding inverse matrix is ​​obtained by querying the node data in the second mapping table and the corresponding offset calculation;

[0177] The error correction is performed using the inverse error correction decoding matrix.

[0178] Reference Fig.11e As shown, Figures 11a to 11c The coefficients of the equation shown are GF(2 ^ 2 of i) ^ i corresponds to Fig. 9 and Fig.10a The index i of the mapping table corresponds to the value i of the mapping table. The gfilog[i] value of the mapping table is found according to the value i to obtain GF(2 ^ i) value to generate the required equation coefficient matrix and coding matrix, select the data row corresponding to the coding matrix according to the position of the restored data in the source data group, form a new R matrix, calculate the inverse of the R matrix offset, and obtain the error correction decoding inverse matrix, and use the error correction decoding matrix to solve the source data.

[0179] In some embodiments, the memory controller is specifically configured to:

[0180] When an error occurs in reading the storage data in the memory device, obtaining a plurality of elements corresponding to the erroneous storage data;

[0181] Using a plurality of elements corresponding to the erroneous stored data, a first matrix is ​​obtained;

[0182] Obtaining the equation coefficient corresponding to the exponential part of each element in the first matrix to obtain a second matrix;

[0183] An inverse matrix of the second matrix is ​​calculated to obtain the error correction decoding inverse matrix.

[0184] Reference Fig.12a The first matrix with the exponential part, x, is shown with Fig. 9 The i in the mapping table has the same meaning, x can be 2, and the second matrix is ​​the query Fig. 9 The matrix after the mapping table is taken, the inverse matrix is ​​the inverse matrix of the second matrix. Taking D0, D2 and D5 as an example of reading errors, the first matrix is ​​a trivalent matrix, D0 corresponds to Figure 8d The first column of data shown in the figure is 1, 1, 1; D2 corresponds to the third column of data 1, GF (2 ^ 2), and GF(2 ^ 4); D5 corresponds to 1, GF(2 ^ 5) and GF(2 ^ 10).

[0185] Reference Figure 12b As shown, during the encoding process, a matrix operation is performed on the first matrix and erroneous D0, D2 and D5 to obtain a third matrix.

[0186] go through Fig.11a The matrix operation shown can be expressed in exponential form with reference to the first matrix:

[0187] P1=D0+D1+D2+D3+D4+D5

[0188] P2=D0+x ^ 1*D1+x ^ 2*D2+x ^ 3*D3+x ^ 4*D4+x ^ 5*D5

[0189] P3=D0+x ^ 2*D1+x ^ 4*D2+x ^ 6*D3+x ^ 8*D4+x ^ 10*D5

[0190] The values ​​of P1, P2, and P3 are represented by the correct values ​​of D1, D3, and D4, and then substituted into Figure 12b The third matrix value of D0, D2 and D5 is equal to the product of the inverse matrix and the third matrix. For example, D0+D2+D5=P1-D1-D3-D4. As mentioned above, the mapping table values ​​of the embodiment of the present disclosure are limited to the closed domain, and the addition and subtraction operations are binary XOR calculations. Addition and subtraction are the same. In this embodiment, addition and subtraction can be unified into addition operations, which can be recorded as D0+D2+D5=P1+D1+D3+D4. The inverse matrix can be Fig.11c Part of the data of the inverse matrix R' of the error correction decoding. Fig.12c Shows the search based on the index part Fig. 9 , Fig.10aor Fig.10b The mapping table in the matrix operation is used to solve D0, D2, and D5. The specific values ​​are shown in Fig.12c The corresponding specific values ​​are mapped to the elements with exponential parts as shown in the table. Fig.12d In some embodiments, when D1 and D4 are read incorrectly, a first matrix is ​​constructed, the first matrix is ​​a 2nd-order matrix, and D1 corresponds to Figure 8d 1, GF(2 ^ 1); D4 corresponds to 1 of the fifth column data, GF(2 ^ 4). The first matrix and the inverse matrix of the first matrix are as follows Fig.13a As shown, the process of solving D1 and D4 using the inverse matrix is ​​similar to that of solving D0, D2 and D5, and will not be repeated. Fig.12c And the calculation of each specific value of the matrix in 12b can be performed according to the calculation rules of the closed domain of the embodiment of the present disclosure, rather than the conventional decimal operation, thereby limiting the calculated values ​​in the closed domain, limiting the number of bits and size of the calculation data.

[0191] Still Fig. 9 Taking the mapping table in as an example, examples of addition, subtraction, multiplication and division operations on the data obtained from the table are as follows:

[0192] Addition 6+7=b0110 xor b0111=b0001=1 (decimal); xor is the binary exclusive OR calculation, the same value in the corresponding digits is 0, and different values ​​are 1.

[0193] Subtraction, 9-3=b1001 xor b0011=b1010=10 (decimal).

[0194] Multiplication, 7*9=gfilog[gflog[7]+gflog[9]]=gfilog[10+14]=gfilog[24mod15]=gfilog[9]=10; gfilog[9] value check Fig. 9 The mapping table is obtained.

[0196] Division, 13 / 11 = gfilog[gflog

[13] -gflog

[11] ] = gfilog[13-7] = gfilog[6] = 12; gfilog[6] value check Fig. 9 The addition and subtraction operations have the same result. Fig.12c and Fig.13b The subtractions involved can be replaced by additions.

[0197] In some embodiments, the memory controller is specifically configured to:

[0198] For the exponent part of each element in the first matrix, determine the group into which the exponent part of the corresponding element falls and the offset value between the exponent part of the corresponding element and the exponent part of the fixed element falling into the corresponding group; and

[0199] Obtaining equation coefficients corresponding to the exponential part of the fixed elements falling into the group by querying the second mapping table;

[0200] The obtained equation coefficients and the offset value are used to calculate the equation coefficients corresponding to the exponential part of the corresponding element.

[0201] When the second mapping table is a compressed mapping table, for each value of the first matrix, refer to Fig.10b As shown, it is determined which group the index falls into, and the values ​​of the first matrix are calculated based on the fixed element values ​​recorded in the second mapping table of the group.

[0202] In some embodiments, the encoding circuit and / or the decoding circuit both include a linear feedback shift register circuit for caching the first mapping table or the second mapping table. The linear feedback shift register circuit may be located at Figure 7 The encoding circuit in the encoding unit 1065 and / or the decoding circuit in the decoding unit 1066.

[0203] Here, the linear feedback shift register circuit refers to a shift register that, given the output of the previous state, uses a linear function of the output as input. The linear feedback shift register circuit can perform an XOR operation, where certain bits of the register are XORed as input and then all bits in the register are shifted as a whole.

[0204] In some embodiments, the memory controller is further configured to:

[0205] Performing a read operation on the stored data in the memory device:

[0206] When an error occurs in the read storage data, the erroneous storage data is re-read;

[0207] When the stored data still has errors after the rereading process, soft decoding is performed on the stored data still having errors;

[0208] When errors still occur in the stored data after the soft decoding process, the errors are corrected by using the error correction decoding inverse matrix.

[0209] Reference Figure 6As shown, when the memory controller 106 controls the memory device 104 to perform a read operation, a default read operation is first performed on the storage unit of the corresponding physical address. After the default read fails, a reread operation is performed when the default read operation fails. After the reread operation fails, a soft decoding operation is performed. After the soft decoding fails, a redundant array data recovery operation is performed. After the RAID operation fails, the read operation stops and the read fails because the error cannot be corrected. The memory controller 106 sends a read failure signal to the host 108. The reread operation and the default read operation can be applied to hard decoding.

[0210] In some embodiments, the second mapping table is stored in a read-only memory ROM of the memory device or the memory controller. When the memory device is not powered on, the second mapping table can be stored in a storage cell array of the memory device, and written to the read-only memory ROM of the memory device or the memory controller when the memory device is powered on.

[0211] According to some aspects of the embodiments of the present disclosure, a memory controller 106 is provided, wherein the memory controller 106 is configured to: compress a first mapping table to obtain a second mapping table; the first mapping table includes a correspondence between an exponential part of each element of all elements corresponding to an error correction coding equation and an equation coefficient, and the exponential part of all elements is a set of continuous data; the second mapping table includes a correspondence between an exponential part of some elements of all elements and an equation coefficient, and the exponential part of the some elements is a plurality of node data extracted from the continuous data;

[0212] The node data in the second mapping table is used to obtain the equation coefficient corresponding to the exponential part of any element in all the elements through segmented query.

[0213] According to some aspects of the embodiments of the present disclosure, Fig.14 A method for operating a memory system is provided, the method comprising:

[0214] The first mapping table is compressed to obtain a second mapping table; the first mapping table includes a correspondence between the exponential part of each element of all elements corresponding to the error correction coding equation and the coefficient of the equation, and the exponential part of all elements is a set of continuous data; the second mapping table includes a correspondence between the exponential part of some elements of all elements and the coefficient of the equation, and the exponential part of the some elements is a plurality of node data extracted from the continuous data;

[0215] The node data in the second mapping table is used to obtain the equation coefficient corresponding to the exponential part of any element in all the elements through segmented query.

[0216] In some embodiments, all the elements and the corresponding equation coefficients are finite fields; the method further comprises:

[0217] Generate all elements corresponding to the error correction coding equation;

[0218] Generate the first mapping table according to all the elements;

[0219] In the process of compressing the first mapping table, the exponential part of each element and the corresponding equation coefficient of all elements in the first mapping table are grouped, and the exponent of a fixed element in each group is selected as the node data;

[0220] The second mapping table is obtained by using the node data and the corresponding equation coefficients.

[0221] In some embodiments, the total number of elements contained in each group is substantially the same, the exponential part of all elements contained in each group is a set of continuous data, and the exponential part of a fixed element in each group is the first data in the continuous data in each group.

[0222] In some embodiments, the method further comprises:

[0223] When an error occurs when reading the stored data in the memory device, an error correction decoding inverse matrix is ​​obtained by querying the node data in the second mapping table and the corresponding offset calculation;

[0224] The error correction is performed using the inverse error correction decoding matrix.

[0225] In some embodiments, obtaining the error correction decoding inverse matrix by querying the node data in the second mapping table and the corresponding offset calculation includes:

[0226] When an error occurs in reading the storage data in the memory device, obtaining a plurality of elements corresponding to the erroneous storage data;

[0227] Using a plurality of elements corresponding to the erroneous stored data, a first matrix is ​​obtained;

[0228] Obtaining the equation coefficient corresponding to the exponential part of each element in the first matrix to obtain a second matrix;

[0229] An inverse matrix of the second matrix is ​​calculated to obtain the error correction decoding inverse matrix.

[0230] In some embodiments, obtaining the equation coefficient corresponding to the exponential part of each element in the first matrix includes:

[0231] For each partial exponent of the element in the first matrix, determine the group into which the exponent part of the corresponding element falls and the offset value between the exponent part of the corresponding element and the exponent part of the fixed element falling into the corresponding group; and

[0232] Obtaining equation coefficients corresponding to power exponents of fixed elements falling into the group by querying the second mapping table;

[0233] The obtained equation coefficients and the offset value are used to calculate the equation coefficients corresponding to the exponential part of the corresponding element.

[0234] In some embodiments, the method further comprises:

[0235] According to all the elements, a corresponding equation coefficient matrix is ​​generated;

[0236] Using the equation coefficient matrix, generating a coding matrix;

[0237] The encoding matrix is ​​used to perform encoding operation on the storage data to be written into the memory device to obtain verification data corresponding to the storage data.

[0238] In some embodiments, the using the inverse error correction matrix to perform error correction includes:

[0239] The inverse error correction decoding matrix, the remaining storage data without errors, and the check data corresponding to the storage data are used to perform a decoding operation to obtain restored storage data.

[0240] In some embodiments, the method further comprises:

[0241] Performing a read operation on the stored data in the memory device:

[0242] When an error occurs in the read storage data, the erroneous storage data is re-read;

[0243] When the stored data still has errors after the rereading process, soft decoding is performed on the stored data still having errors;

[0244] When errors still occur in the stored data after the soft decoding process, the errors are corrected by using the error correction decoding inverse matrix.

[0245] According to some aspects of the embodiments of the present disclosure, a readable storage medium is provided, wherein the readable storage medium stores a computer program, and the computer program implements the operating method when executed.

[0246] The memory device may include a NAND memory, and a memory cell of the NAND memory may be a floating gate type memory cell including a floating gate transistor, or a charge trap type memory cell including a charge trap transistor.

[0247] The storage medium may be a magnetic random access memory (FRAM), a read-only memory (ROM), a programmable read-only memory (PROM), an erasable programmable read-only memory (EPROM), an electrically erasable programmable read-only memory (EEPROM), a flash memory, a magnetic surface storage, an optical disk, or a compact disc read-only memory (CD-ROM); it may also be various devices including one or any combination of the above-mentioned storage devices.

[0248] In some embodiments, executable instructions may be in the form of a program, software, software module, script or code, written in any form of programming language (including compiled or interpreted languages, or declarative or procedural languages), and may be deployed in any form, including as a stand-alone program or as a module, component, subroutine or other unit suitable for use in a computing environment.

[0249] As an example, executable instructions may, but need not, correspond to a file in a file system, may be stored as part of a file that stores other programs or data, such as in one or more scripts in a HyperText Markup Language (HTML) document, in a single file dedicated to the program in question, or in multiple coordinated files (e.g., files storing one or more modules, subroutines, or code portions).

[0250] As an example, the executable instructions may be deployed to be executed on one electronic device, or on multiple electronic devices located at one site, or on multiple electronic devices distributed at multiple sites and interconnected by a communication network.

[0251] The above description is only a preferred embodiment of the present disclosure, and does not limit the patent scope of the present disclosure. All equivalent structural changes made by using the contents of the present disclosure and the drawings under the inventive concept of the present disclosure, or directly / indirectly applied in other related technical fields are included in the patent protection scope of the present disclosure.

Claims

1. A memory system, characterized in that: include: Memory device; a memory controller coupled to the memory device and configured to: The first mapping table is compressed to obtain a second mapping table; the first mapping table includes a correspondence between the exponential part of each element of all elements corresponding to the error correction coding equation and the coefficient of the equation, and the exponential part of all elements is a set of continuous data; the second mapping table includes a correspondence between the exponential part of some elements of all elements and the coefficient of the equation, and the exponential part of the some elements is a plurality of node data extracted from the continuous data; The node data in the second mapping table is used to obtain the equation coefficient corresponding to the exponential part of any element in all the elements through segmented query.

2. The memory system according to claim 1, wherein: All elements and corresponding equation coefficients are finite fields; the memory controller is configured as follows: Generate all elements corresponding to the error correction coding equation; Generate the first mapping table according to all the elements; Grouping the exponential part of each element and the corresponding equation coefficient of all elements in the first mapping table, and selecting the exponential part of a fixed element in each group as the node data; The second mapping table is obtained by using the node data and equation coefficients corresponding to the node data.

3. The memory system according to claim 2, wherein: The total number of elements contained in each group is substantially the same, the exponent parts of all elements contained in each group are a group of continuous data, and the exponent part of a fixed element in each group is the first data in the continuous data in each group.

4. The memory system according to claim 2, wherein: The memory controller is further configured to: When an error occurs when reading the stored data in the memory device, an error correction decoding inverse matrix is ​​obtained by querying the node data in the second mapping table and the corresponding offset calculation; The error correction is performed using the inverse error correction decoding matrix.

5. The memory system according to claim 4, characterized in that: The memory controller is specifically configured as follows: When an error occurs in reading the storage data in the memory device, obtaining a plurality of elements corresponding to the erroneous storage data; Using a plurality of elements corresponding to the erroneous stored data, a first matrix is ​​obtained; Obtaining the equation coefficient corresponding to the exponential part of each element in the first matrix to obtain a second matrix; An inverse matrix of the second matrix is ​​calculated to obtain the error correction decoding inverse matrix.

6. The memory system according to claim 5, characterized in that: The memory controller is specifically configured as follows: For the exponential part of each element in the first matrix, determine the group into which the exponential part of the corresponding element falls and the offset value between the exponential part of the corresponding element and the exponential part of the fixed element falling into the corresponding group; as well as Obtaining equation coefficients corresponding to the exponential part of the fixed elements falling into the group by querying the second mapping table; The obtained equation coefficients and the offset value are used to calculate the equation coefficients corresponding to the exponential part of the corresponding element.

7. The memory system according to claim 4, characterized in that: The memory controller further includes: an encoding circuit, wherein the encoding circuit is configured to: According to all the elements, a corresponding equation coefficient matrix is ​​generated; Using the equation coefficient matrix, generating a coding matrix; The encoding matrix is ​​used to perform encoding operation on the storage data to be written into the memory device to obtain verification data corresponding to the storage data.

8. The memory system according to claim 4, characterized in that: The memory controller further includes: a decoding circuit, wherein the decoding circuit is configured to: The inverse error correction decoding matrix, the remaining storage data without errors, and the check data corresponding to the storage data are used to perform a decoding operation to obtain restored storage data.

9. The memory system according to claim 7 or 8, characterized in that: The encoding circuit and / or the decoding circuit both include a linear feedback shift register circuit LFSR.

10. The memory system according to claim 4, wherein: The memory controller is also configured to: Performing a read operation on the stored data in the memory device: When an error occurs in the read storage data, the erroneous storage data is re-read; When the stored data still has errors after the rereading process, soft decoding is performed on the stored data still having errors; When errors still occur in the stored data after the soft decoding process, the errors are corrected by using the error correction decoding inverse matrix.

11. The memory system according to claim 1, wherein: The second mapping table is stored in a read-only memory ROM of the memory device or the memory controller.

12. A method for operating a memory system, characterized in that: include: The first mapping table is compressed to obtain a second mapping table; the first mapping table includes a correspondence between the exponential part of each element of all elements corresponding to the error correction coding equation and the coefficient of the equation, and the exponential part of all elements is a set of continuous data; the second mapping table includes a correspondence between the exponential part of some elements of all elements and the coefficient of the equation, and the exponential part of the some elements is a plurality of node data extracted from the continuous data; The node data in the second mapping table is used to obtain the equation coefficient corresponding to the exponential part of any element in all the elements through segmented query.

13. The operating method according to claim 12, characterized in that: All the elements and the corresponding equation coefficients are finite fields; the method further includes: Generate all elements corresponding to the error correction coding equation; Generate the first mapping table according to all the elements; In the process of compressing the first mapping table, the exponential part of each element and the corresponding equation coefficient of all elements in the first mapping table are grouped, and the exponent of a fixed element in each group is selected as the node data; The second mapping table is obtained by using the node data and the corresponding equation coefficients.

14. The operating method according to claim 13, characterized in that: The total number of elements contained in each group is substantially the same, the exponent parts of all elements contained in each group are a group of continuous data, and the exponent part of a fixed element in each group is the first data in the continuous data in each group.

15. The operating method according to claim 13, characterized in that: The method further comprises: When an error occurs when reading the stored data in the memory device, an error correction decoding inverse matrix is ​​obtained by querying the node data in the second mapping table and the corresponding offset calculation; The error correction is performed using the inverse error correction decoding matrix.

16. The operating method according to claim 15, characterized in that: The step of obtaining an error correction decoding inverse matrix by querying the node data in the second mapping table and the corresponding offset calculation includes: When an error occurs in reading the storage data in the memory device, obtaining a plurality of elements corresponding to the erroneous storage data; Using a plurality of elements corresponding to the erroneous stored data, a first matrix is ​​obtained; Obtaining the equation coefficient corresponding to the exponential part of each element in the first matrix to obtain a second matrix; An inverse matrix of the second matrix is ​​calculated to obtain the error correction decoding inverse matrix.

17. The operating method according to claim 16, characterized in that: The obtaining the equation coefficient corresponding to the exponential part of each element in the first matrix includes: For each partial exponent of the element in the first matrix, determine the group into which the exponent part of the corresponding element falls and the offset value between the exponent part of the corresponding element and the exponent part of the fixed element falling into the corresponding group; and Obtaining equation coefficients corresponding to power exponents of fixed elements falling into the group by querying the second mapping table; The obtained equation coefficients and the offset value are used to calculate the equation coefficients corresponding to the exponential part of the corresponding element.

18. The operating method according to claim 15, characterized in that: The method further comprises: According to all the elements, a corresponding equation coefficient matrix is ​​generated; Using the equation coefficient matrix, generating a coding matrix; The encoding matrix is ​​used to perform encoding operation on the storage data to be written into the memory device to obtain verification data corresponding to the storage data.

19. The operating method according to claim 15, characterized in that: The using the inverse error correction matrix to perform error correction includes: The inverse error correction decoding matrix, the remaining storage data without errors, and the check data corresponding to the storage data are used to perform a decoding operation to obtain restored storage data.

20. The operating method according to claim 15, characterized in that: The method further comprises: Performing a read operation on the stored data in the memory device: When an error occurs in the read storage data, the erroneous storage data is re-read; When the stored data still has errors after the rereading process, soft decoding is performed on the stored data still having errors; When errors still occur in the stored data after the soft decoding process, the errors are corrected by using the error correction decoding inverse matrix.

21. A memory controller, characterized in that: The memory controller is configured to: The first mapping table is compressed to obtain a second mapping table; the first mapping table includes a correspondence between the exponential part of each element of all elements corresponding to the error correction coding equation and the coefficient of the equation, and the exponential part of all elements is a set of continuous data; the second mapping table includes a correspondence between the exponential part of some elements of all elements and the coefficient of the equation, and the exponential part of the some elements is a plurality of node data extracted from the continuous data; The node data in the second mapping table is used to obtain the equation coefficient corresponding to the exponential part of any element in all the elements through segmented query.

22. A readable storage medium, characterized in that: The readable storage medium stores a computer program, and when the computer program is executed, the operating method according to any one of claims 12 to 20 is implemented.

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