Platform elastic authority mechanism

Abstract

Systems and methods are disclosed for a platform resilient authority that may be used to identify component capabilities to manage one or more update requests using an on-component fabric. When an update request is received, a component capability level may be determined and, if the component is unable to perform each of on-component protection, detection, and recovery operations, additional update information may be identified and used to install an update for the component.

Description

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This application claims priority to and the benefit of U.S. Provisional Patent Application No. 63 / 585,683, filed on September 27, 2023, the entire contents of which are incorporated herein by reference. Technical Field

[0003] At least one embodiment is directed to managing and monitoring security in a hardware platform based on component capabilities for protecting, detecting, and recovering firmware. Background Art

[0004] Computing devices may be constructed from a variety of different components produced by different manufacturers. Some or all of these components may include firmware that is critical to the operation of the component, including parameters or features that may be updated at a later time, such as an update that may be associated with the component and / or transmitted from a remote location. Depending on the complexity of the device, each device may be classified by its ability to protect, detect, and recover its firmware, critical parameters, and data from malicious attacks and / or unintentional changes or corruption. Often devices are not designed with each of these capabilities, so they are unable to perform the necessary tasks to prevent issues related to exploitation of potential security vulnerabilities, capability issues, and / or compatibility issues. BRIEF DESCRIPTION OF THE DRAWINGS

[0005] Various embodiments according to the present disclosure will be described with reference to the accompanying drawings, in which:

[0006] Figure 1A and Figure 1B A schematic diagram showing a computing device including a platform and software according to at least one embodiment is shown;

[0007] Figure 2A shows a schematic representation of a device capability hierarchy according to at least one embodiment;

[0008] Figure 2B shows a schematic representation of device capabilities with respect to protection, detection, and recovery operations according to at least one embodiment;

[0009] Figure 3 An exemplary environment of a platform resiliency authority is shown in accordance with at least one embodiment;

[0010] Figure 4 shows a schematic representation of a platform elasticity authority according to at least one embodiment;

[0011] Figure 5A An exemplary process for performing a firmware update using a platform resilience authority in accordance with at least one embodiment is shown;

[0012] Figure 5B An exemplary process for establishing a platform resilience authority according to at least one embodiment is shown;

[0013] Figure 5C An exemplary process for performing corrective actions in response to platform component errors in accordance with at least one embodiment is shown;

[0014] Figure 6 Components of a distributed system that may be used to update or perform inference using a machine learning model according to at least one embodiment are shown;

[0015] Figure 7 An example data center system is shown in accordance with at least one embodiment;

[0016] Figure 8 A computer system according to at least one embodiment is shown;

[0017] Fig. 9 A computer system according to at least one embodiment is shown;

[0018] Fig.10 illustrates at least a portion of a graphics processor according to one or more embodiments; and

[0019] Fig.11 At least a portion of a graphics processor is shown in accordance with one or more embodiments. DETAILED DESCRIPTION

[0020] In the following description, various embodiments will be described. For the purpose of explanation, specific configurations and details are proposed in order to provide a thorough understanding of the embodiments. However, it will be apparent to those skilled in the art that the embodiments may be practiced without the specific details. In addition, well-known features may be omitted or simplified in order not to obscure the described embodiments.

[0021] The systems and methods described herein may be used for, but are not limited to, non-autonomous vehicles, semi-autonomous vehicles (e.g., in one or more advanced driver assistance systems (ADAS)), manned and unmanned robots or robotic platforms, warehouse vehicles, off-road vehicles, vehicles connected to one or more trailers, flying boats, boats, shuttles, emergency vehicles, motorcycles, electric or motorized bicycles, aircraft, construction vehicles, trains, underwater vessels, remotely operated vehicles such as drones, and / or other types of vehicles. In addition, the systems and methods described herein may be used for a variety of purposes, such as, but not limited to, for machine control, machine motion, machine driving, synthetic data generation, model training or updating, perception, augmented reality, virtual reality, mixed reality, robotics, security and surveillance, simulation and digital twins, autonomous or semi-autonomous machine applications, deep learning, environmental simulation, object or role simulation and / or digital twins, data center processing, conversational artificial intelligence (AI), generative AI with a large language model (LLM), light transport simulation (e.g., ray tracing, path tracing, etc.), collaborative content creation of 3D assets, cloud computing, and / or any other suitable application.

[0022] The disclosed embodiments may include a variety of different systems, such as automotive systems (e.g., control systems for autonomous or semi-autonomous machines, perception systems for autonomous or semi-autonomous machines), systems implemented using robots, aerial systems, medical systems, boating systems, smart area monitoring systems, systems for performing deep learning operations, systems for performing simulation operations, systems for performing digital twin operations, systems implemented using edge devices, systems including one or more virtual machines (VMs), systems for performing synthetic data generation operations, systems implemented at least in part in a data center, systems for performing conversational AI operations, systems for performing generative AI operations using LLMs, systems for performing light transport simulations, systems for performing 3D asset collaborative content creation, systems implemented at least in part using cloud computing resources, and / or other types of systems.

[0023] Methods according to various embodiments may be used to provide a resilient authority for managing and monitoring the security of a hardware (HW) platform. Such a central authority may be implemented to detect, protect, and recover from security threats and vulnerabilities to reduce the risk of device damage or data leakage. Various embodiments deploy a local HW platform resiliency authority to ensure that the hardware platform is secure, resilient, and able to resist various security threats. Systems and methods may be used to manage firmware (FW) of various subcomponents that make up a HW system, which may include components with different capabilities ranging from full reliance (e.g., lack of basic security capabilities) to full sufficiency (e.g., security capabilities on a chip or on a component). Various embodiments may provide platform resiliency that complies with certain standard organizations such as, but not limited to, NIST SP800-193. In addition, systems and methods support tracking, addressing, and managing different types of FW for different components associated with the platform.

[0024] In at least one embodiment, the system and method solve the FW management for various intelligent components (e.g., components including firmware) used to form a platform, which can be composed of one or more devices that can be assembled and work together to deliver specific computing capabilities, but does not include other software other than FW that is part of the device in the platform. In other words, the platform is composed of the HW and FW required to boot the system to the point where the software or operating system can be loaded. Taking an example without limitation, the platform can refer to a computing device such as a laptop, a desktop computer, a server, a network slide, a blade, a wearable device, a car, a personal mobile device, an appliance, and / or the like. In addition, various devices may include multiple different platforms. It is necessary to protect the FW on each component of the platform to ensure remote confidentiality, integrity, availability, and local confidentiality and integrity. However, different components may have different protection capabilities, which may be based on the supplier of the component, the cost of the component, the function of the component and / or a combination thereof, and / or determined by the supplier of the component, the cost of the component, the function of the component and / or a combination thereof. For example, some components may be completely sufficient, while other components may be partially sufficient, and some components may be completely dependent. In addition, some components may not have persistent FW storage and therefore rely on other entities to provide such FW for them. In at least one embodiment, some devices may lack the ability to store and / or persist their own FW, even if they include the ability to persist key parameters or data. The systems and methods of the present disclosure provide a security authority for managing the FW of each of these types of components regardless of the capabilities of the components, and provide status by indexing each component, its associated update key, detection key, recovery key, and the location of each component in at least one embodiment. In at least one embodiment, a platform resilience authority is used to establish the status of the component for the platform and then execute one or more workflows in response to updating the FW of the component.

[0025] Various embodiments of the present disclosure may provide improvements in both supply chain security and platform security, as well as various other benefits. In addition, by implementing systems and methods for improving protection, detection and recovery, embodiments may provide one or more solutions to comply with one or more industry standards including but not limited to NIST 800-193. For example, systems and methods may be used to manage and implement security updates, authentication updates and version control so as to roll back components when one or more errors occur. In addition, various embodiments may be deployed at other times (not just during updates) to authenticate FW. In at least one embodiment, component capabilities are tracked and monitored, and workflows are initiated based at least in part on the capabilities of the component receiving the update when an update request is received. For example, a fully adequate component may be able to receive the update itself, verify the authenticity of the update by means such as but not limited to digital signatures, apply the update when the update is verified to be authentic, measure and verify the firmware at runtime, and the fully adequate component may also include its own recovery storage. On the other hand, a partially adequate component may be able to receive and verify updates, but may then require off-device recovery storage. Other components may still have different capabilities, and systems and methods may use this information to establish different workflows for updates based at least in part on capabilities. It should be appreciated that while embodiments may describe certain operations as being performed in response to an update request, the systems and methods of the present disclosure are not limited to updates. That is, embodiments of the present disclosure may be implemented to measure and verify any FW in the system at any time, not just when there is an update. In addition, while authentication may be described with reference to signatures, embodiments of the present disclosure are not limited to such authentication processes and may include various other measurement techniques that may be used for authentication and / or verification, including but not limited to hashing, cryptography (e.g., public and / or private keys), challenge-response authentication, and / or similar techniques.

[0026] Figure 1A A schematic diagram of a system 100 including a platform 102 and software 104 is shown. In this example, the platform 102 includes various components and / or subcomponents 106. It should be appreciated that Figure 1AThe components 106 shown are non-limiting examples and are not intended to limit or otherwise define the present disclosure, as there may be more, fewer or different components that can be selected based at least in part on the capabilities of the devices associated with the platform. Such examples include certain components such as embedded controllers (EC) / super input / output (SIO) that may be associated with different mobile platforms (for EC) or associated with desktop-based platforms (SIO). These controllers typically control the functions of the platform and may be the first system board device in the platform for executing code. A trusted platform module (TPM) may include a secure coprocessor that can securely store and use cryptographic keys and measurements. The TPM may also include non-volatile memory storage that persistently stores critical data. Various embodiments may also include a baseboard management controller (BMC) / management engine (ME) associated with a server and / or client platform as an out-of-band management device that enables a platform administrator to manage the platform without running a host operating system. Host processors such as a central processing unit (CPU) and a network interface controller (NIC) are also shown. The NIC may enable connection to other devices and may include a read-only memory (ROM) FW that is loaded during boot and executed by the host processor. A graphics processing unit (GPU) is also illustrated in this example, as well as a hard disk drive (HDD), a solid-state drive (SDD), a keyboard, a mouse, a power supply, a memory, a host controller for a storage device, a serial peripheral interface (SPI) flash memory, an embedded multimedia card (eMMC) / universal flash memory (UFS) / non-volatile memory expression (NVMe), a boot FW, and internally connected devices such as a webcam, a fingerprint scanner, and the like. As previously mentioned, various other components such as fans and the like may also be included in embodiments of the present disclosure.

[0027] After startup, software 104 is executed, which can use the underlying components of platform 102 to complete one or more tasks. As will be appreciated, various FWs associated with the underlying components 106 can be initialized, verified, and then started before executing any software 104 such as an operating system. In the event of a security violation or failure, the startup operation may fail, thereby stopping or otherwise preventing the execution of one or more related operations of the software 104 and the device. For example, if a malicious actor is able to damage one or more components 106, such as by causing it to install and load an inoperable FW version, the remaining components may be "stuck" or otherwise unable to start, at least without further intervention. The likelihood that different components 106 will receive or otherwise use such malicious code increases as the capabilities of the components 106 decrease. The systems and methods of the present disclosure solve this problem, as well as other problems, by tracking and monitoring the capabilities of the components, and then initiating updates or other FW changes based on the different capabilities to provide enhanced security and monitoring for the components 106 that need help the most.

[0028] As described herein, various embodiments of the present disclosure are directed to a platform security authority that can be used to index, track, and facilitate updates of various different components that make up a platform, even when the components may be provided by different manufacturers and have different capabilities. Embodiments can index or otherwise determine the capabilities of the different components that make up the platform, and then determine, in response to an update request, whether one or more interventions or supplemental assistance are required to improve the confidentiality, integrity, and availability of the components.

[0029] Figure 1B A schematic representation of a system 110 including a platform 102 and software 104 is shown. In this example, the system and method are illustrated in terms of the operation of devices such as multi-chip modules, chiplets, and / or dielet packages. In this example, the system 110 includes a chip package 112, which may include various components 106. As described herein, various embodiments may include more or fewer components than those shown, and certain components have been removed for clarity and ease of discussion. In such an example, the components include many memory devices, multiple processors (e.g., CPUs, GPUs, DPUs, etc.), memory and input / output controllers, accelerators, and supporting components such as radio frequency (RF) devices, modems, optical devices, and analog devices.

[0030] Figure 2A2 is a schematic diagram of a component capability classification that can be used with an embodiment of the present disclosure. In such an example, there are five different levels or layers of classification, but it should be noted that more or fewer classification levels can be defined and / or used. The first level 202 (e.g., the first layer) is called "completely sufficient", the second level 204 (e.g., the second layer) is called "partially sufficient", the third level 206 (e.g., the third layer) is called "supplicant", the fourth level 208 (e.g., the fourth layer) is called "completely dependent", and the fifth level 210 (e.g., the fifth layer) is called "virtual". As mentioned above, these labels are only used for illustrative purposes to facilitate the current discussion. Each of the different 202-210 levels includes different attributes or parameters related to protection (e.g., protect), detection (e.g., detect), and recovery (e.g., recover), represented by "P", "D", and "R", respectively. In one or more embodiments, protection may refer to ensuring that the FW update is performed securely, such as by verifying a digital signature to ensure authenticity. If successful, the current FW is replaced with the updated FW. In one or more embodiments, detection may refer to ensuring that the current FW that the component is about to execute can be verified before execution. This can be achieved by using digital signatures or other security measures, as described herein. If verification fails, the code will not be executed, and then the recovery process may take over to try to restore the component to a valid operating state. In one or more embodiments, recovery refers to replacing invalid (e.g., unable to authenticate) code with a valid backup version to restore the component to a valid operating state.

[0031] In at least one embodiment, protection may refer to the ability of a component to receive security updates and verify that the security updates are authentic, detection may refer to the ability of a component to verify that the current FW is authentic, and recovery may refer to the ability of a component to roll back to a previous version when an error occurs or the current FW cannot be authenticated. For example, a component may attempt to authenticate the current FW (e.g., detect) and discover that the current FW has been maliciously or unintentionally damaged and cannot pass authentication. In this case, the component can be restored using a backup version of the FW. Although each component may have the ability to satisfy each of P, D, and R, the system and method may target the capabilities of each of P, D, and R components, where a device is considered capable of completing a task if it is able to complete the task on the device, and may be considered unable to complete the task if intervention or assistance outside the device is required.

[0032] In this example, the first level 202 includes the ability to satisfy each of P, D, and R by virtue of a fully sufficient component receiving a signed blob update of the FW, measuring and verifying the FW at runtime, and also by including onboard recovery storage. Such a component may not require any further assistance or functionality from a resiliency authority, but in various embodiments, the presence of the components considered at the first level 202 may still be tracked to ensure integrity and provide knowledge of the complete platform. In other words, a "fully sufficient device" at the first level 202 may refer to a device that has the ability to implement all necessary capabilities internally to provide its own protection, detection, and recovery functions. As described in at least one example embodiment herein, an index may record and track components associated with the first level 202, but various cells or related values ​​may be considered "blank" or not filled in because off-device components may not be required to complete various tasks.

[0033] The second level 204 may include some of the same capabilities as the first level 202, such as signature zone points and measurement and verification, but in this example, the second level components do not include onboard recovery storage and may instead require assistance from an off-device recovery storage service. As will be described herein, the systems and methods of the present disclosure may identify this missing piece (e.g., a recovery piece) and provide assistance or access to different recovery options that may be protected or otherwise verified. For example, various embodiments may track and index components associated with the second level 204 and then store a secure location associated with the recovery operation for use in a workflow associated with a FW update and / or current FW certification. In operation, the second level 204 needs to recover if the FW is not certified, but if there is a FW update, the elastic engine may need to update the recovery image if the FW update is successful so that it has the latest FW version available for recovery. As previously described, recovery can be performed in a variety of ways, such as but not limited to working directly with partially sufficient components, or having an authority provide a FW update to the component. In at least one embodiment, a "partially sufficient device" of the second level 204 may refer to a device that has protection and detection capabilities, but requires an external source to provide recovery capabilities.

[0034] The third level 206 may also include certain features of the first level 202 and the second level 204, such as measurement and verification at runtime, but in this example, off-device verification is used with off-device recovery storage. Therefore, the third level 206 lacks the protection and recovery portions sought by the embodiments of the present disclosure. By identifying these missing portions, systems and methods can be implemented to provide further protection and resilience to the third level components. For example, an index can provide information for recovery storage, and EC for protection features can also be implemented. In at least one embodiment, the "requesting device" of the third level 206 can refer to a device that has detection capabilities but relies on external sources to provide protection and recovery functions.

[0035] The fourth level 208 is described as lacking each of the protection, detection, and recovery parts by using off-device verification, off-device measurement, and off-device recovery storage. Similarly, the fifth level 210 also lacks the desired measures to verify the integrity of the FW by including driver loading FW, local storage, and relying on software such as an operating system. The system and method can be used to provide additional features by identifying components that are components of the fourth level 208 and the fifth level 210 and implementing enhanced security features. In other words, the "completely dependent device" of the fourth level 208 may refer to a device that does not have any internal capabilities and relies entirely on external sources to provide protection, detection, and recovery functions. In addition, the "virtual device" of the fifth level 210 may refer to a software-based device that has the ability to provide its own detection capabilities but relies on software such as drivers in the operating system to provide protection and recovery capabilities. These devices may include devices that do not have local persistent storage for maintaining their FW so that the FW is loaded from other locations based on software such as device drivers in the OS. These devices may or may not have their own detection capabilities and may require assistance from the elastic engine to help provide such detection if they need to be detected. Depending on the nature of how these FW images are delivered, protection and recovery services may begin to be provided by drivers in the OS and managed as OS driver software is managed. Referring to the OS by way of example, as described herein, various embodiments may refer to the fifth level 210 devices as devices associated with software and not necessarily just the OS. For example, a software application executed on an operating system may be used for one or more of P, D, and R.

[0036] Figure 2BA schematic representation 220 of various components 106 with different capability levels 202-210 that can be used in embodiments of the present disclosure is shown. In this example, different components are shown grouped into different corresponding levels or layers 202-210. For example, the first level 202 includes BIOS, embedded controller (EC), and management unit (MU). In addition, flash memory (e.g., persistent storage of FW) can be used to host FW or other information. Therefore, these components can be configured to manage and support their own detection, protection, and recovery capabilities.

[0037] As described herein, the additional levels 204-210 may be less capable than the first level 202. For example, the second level 204 may include components such as integrated graphics (iGFX), NICs, and various other components that rely on external storage (such as through an extensible firmware interface (EFI) partition on a system storage device to provide recovery capabilities). Similarly, the third level 206 may include components such as a mouse or power supply and also require an EFI storage partition to implement recovery capabilities. However, as noted herein, the third level 206 may also lack the ability to manage its own protection capabilities, and therefore, the EC may be used to provide such functionality. Such a configuration is also shown in the fourth level 208, which may include components such as electronic SIO (eSIO) or other components, and such a configuration now also integrates detection capabilities into the EC. Similarly, the fifth level 210 also lacks protection and recovery capabilities and may use drivers associated with software (SW) such as an operating system or various other software applications to facilitate such functions. However, as described herein, various embodiments may include fifth level devices that may or may not have detection capabilities. For example, in some embodiments, WiFi and dGPU may have detection capabilities, but other types may not have detection capabilities. Accordingly, the device may provide detection capabilities in some embodiments associated with the fifth level 210, and the elastic engine may provide detection capabilities in some embodiments associated with the fifth level 210.

[0038] Embodiments of the present disclosure may identify the various capabilities of components in order to track how to implement various upgrades, including which components are capable of handling which operations and / or which components require additional security and assistance. In this way, the systems and methods of the present disclosure provide a central authority to manage FW resiliency for each component across the platform without relying on integrated FW resiliency capabilities.

[0039] Figure 3An exemplary environment 300 that can be used with embodiments of the present disclosure is shown. In this example, the platform 102 is shown to include a plurality of different components 106A-106N. As described herein, components can be separate devices that are combined to provide functionality for the platform 102. The components 106A-106N may have different levels of capabilities in terms of detection, protection, and recovery operations. The systems and methods of the present disclosure may include a platform elasticity authority 302, which may be executed on a component of the platform such as a system on a chip (SoC) or EC to record and manage, and in one or more embodiments, determine the capabilities for various components 106A-106N and / or manage component capabilities to facilitate update, execution, and recovery operations. For example, the platform elasticity authority 302 can utilize the system designer's prior knowledge of the components that have been selected in the platform 102 to understand what capabilities these components have and how the recovery engine needs to manage each component. In such an example, the elasticity manager 304 can manage incoming requests and / or outgoing messages. For example, the elasticity manager 304 may receive information about FW updates from different components 106A-106N, as one option and various other embodiments may be directed to certify existing FW and / or other operations. As another example, in at least one embodiment, the elasticity manager 304 may query one or more components 106A-106N to determine information associated with various capabilities of the components 106A-106N, such as information to determine the tier associated with the components 106A-106N. For example, with respect to the platform 102, one or more components 106A-106N may be removable or upgradeable, and when a new component is installed, the elasticity manager 304 may send a request for information about its capabilities to the newly installed component, and may then update one or more indexes or data repositories in response to the information from the new component, as described herein.

[0040] In at least one embodiment, a component data repository 306 may be maintained by the platform resilience authority 302 to identify the components 106A-106N and their associated capabilities that make up the platform 102. For example, a "type" may be assigned to a given component that is associated with a level or classification of the component. In addition, the component data repository 306 may also index or otherwise track different components 106A-106N to allow cross-references across various different types of information and / or values. For example, different keys (e.g., update keys, detection keys, etc.) may be stored in a key data repository 308, and recovery image locations may be stored in a recovery data repository 310. As described herein, these data repositories 306-310 are provided by way of non-limiting examples, and there may be more or fewer data repositories. For example, all information may be stored in a single data repository. Another example is that there may be additional data repositories categorized by level and / or capability, location, and the like.

[0041] In operation, the component data store 306 may be pre-populated based on information relevant to the developer of the platform 102. For example, the developer may know each component 106A-106N being added to the platform 102, its associated capabilities, and the like. Thus, when the platform 102 is built, the component data store 306 may be populated with the known information. Later, if changes are made (e.g., components are added), systems and methods may be implemented that allow the elasticity manager 304 to update or revise the component data store 306. For example, when a new component is installed (such as upgrading a hard drive), the elasticity manager 304 may query the new component to obtain information and / or the user may update the component data store 306 and other options. In at least one embodiment, upon receiving a FW update request, the elasticity manager 304 may query the component data store 306 to determine which component is associated with the update and the component capabilities, and identify locations in the various data stores 308, 310 to obtain information to facilitate the update, if necessary. As another example, when a new component is installed, the platform 102 can obtain the model or identification information, and then the elasticity manager 304 can query the remote data repository that may include information about the capabilities of different components, and find a matching component, and then update the various data repositories 306-310. In this way, as new components are developed, platform developers can continuously update the remote index to allow the platform 102 to continuously update and manage different upgrades.

[0042] In at least one embodiment, systems and methods may deploy one or more techniques or applications to prevent subversion of the platform resilience authority 302. For example, the platform resilience authority 302 may have its own root of trust 312. The root of trust 312 may own or otherwise control update permissions for different applications associated with the platform 102. In at least one embodiment, the root of trust 312 may be populated by an authority (e.g., a platform owner) during manufacturing and / or assembly. As a non-limiting example, if the platform 102 is a personal computer, the computer manufacturer will populate and control the root of trust 312 by including information related to the components 106A-106N installed in the personal computer. In addition, the computer manufacturer will also add other components that are known to be compatible or can be included, such as different types of memory, different peripherals, and / or the like.

[0043] However, in at least one embodiment, building in a pre-set list may not provide sufficient flexibility to change and / or modify the platform 102. For example, it may be necessary to replace components 106A-106N and / or add new components. Over time, even if the manufacturer adds additional options to the root of trust 312, these options may not capture components manufactured even in the short future. Accordingly, the system and method can implement one or more dynamic updates to the root of trust. For example, the manufacturer can provide an updated authorization list, such as a list of new components 106A-106N and the associated keys and / or the like for these components. In addition, when a new component is added, one or more connections may be established with the manufacturer to verify the new component and then securely update the root of trust 312 for the platform resilience authority 302. Similarly, one or more embodiments can also be used to update an existing root of trust 312 and / or change stored keys and the like. For example, if it is found that the authorized update is corrupted, one or more authorities can be used to update the root of trust 312. In this way, the platform 102 can be updated and / or modified while maintaining the security provided by the platform resilience authority 302. In at least one embodiment, the manufacturer can be the authority associated with the update. However, in other examples, the authority may include the platform owner, the enterprise supporting the platform, and / or a combination thereof.

[0044] In at least one implementation, the system and method may provide a resilient engine that will include or incorporate its own root of trust. For example, an authority may be used to "own" or "control" the permissions of the engine or otherwise establish permissions for the engine. As an example, the FW inside the device may be controlled by the device manufacturer, so updates to the FW can only be issued by the device manufacturer. The system and method may include one or more authorities associated with the resilient engine to manage and provide updates associated with different components. One or more authorities may identify specific components that can be added to the platform and provide relevant information about the components, which may enable the resilient engine to add the component to a list of components associated with the platform. As discussed herein, while the initial build of the platform 102 may be populated with relevant components, additional devices or capabilities such as plug-in devices or the like may need to be added. For example, the platform 102 may include one or more ports that allow connection to different external components (such as an external graphics processor or memory device) that can be used to perform different operations. The system and method may enable these external devices to be added to the resilient engine, thereby allowing the resilient engine to incorporate responsibility for additional devices that may now be part of the platform 102 but were not part of the platform when it was originally delivered and / or manufactured.

[0045] As discussed herein, a variety of different authorities may be deployed to "own" or "control" the elastic engine, and in some embodiments, different levels or controls may be implemented. For example, a first authority may have more control over critical underlying hardware while a second authority has control over peripherals. In addition, embodiments of the present disclosure may be used to securely update and / or modify the elastic engine. As an example, an authority such as a platform manager may be the only entity allowed to modify and / or update the elastic engine. For example, there may be a pre-stored set of keys or the like to allow updates from a particular authority. However, in another example, one or more additional or alternative authorities may update the elastic engine. In at least one embodiment, new components may be added and / or existing keys or other credentials may be changed to, for example, respond to security updates such as key leaks or other events. Therefore, future updates will be provided with updated keys and / or use updated keys, thereby allowing rapid updates and dynamic changes to the elastic engine. In addition, it should be recognized that authorities may transfer control at different times. For example, when delivering the platform, the manufacturer may transfer control to the buyer or owner and allow the buyer or owner to manage and control the elastic engine internally.

[0046] Figure 4An example environment 400 that can be used with an embodiment of the present disclosure is shown. In such an example, the platform elasticity authority 302 may query one or more data repositories such as the component data repository 306 to identify the capabilities of a given component of the platform. In such an example, the component data repository 306 may maintain an index for a single component that includes a component identification, type or classification, and index. Depending on the type / classification of the component, different information may be stored in other data repositories 308, 310. For example, because the component identified as ABC123 is a "completely sufficient" or first-level component, there is no entry in the key data repository 308 or the recovery data repository 310, because as a first-level component, component ABC123 can manage the full functionality of the component itself without auxiliary or supplementary help. In contrast, the component identified as CBA125 is a "solicitation" or third-level component, and therefore lacks both protection and recovery capabilities. Therefore, the index associated with component CBA125 includes entries associated with updated keys and recovery locations, but does not include detection keys, because as a third-level component, component CBA125 is able to achieve this function by itself. The requested updates can then be implemented using information obtained from the data repositories 306-310. Thus, the systems and methods can track and maintain the functionality of components so that when different update requests are received, the platform elasticity authority 302 can determine the appropriate keys and restore locations to implement the updates in a secure environment.

[0047] Figure 5AA process 500 is shown that can be used to implement FW updates based on component capabilities. It should be understood that within the scope of various embodiments, unless otherwise specifically stated, there may be additional, fewer or alternative operations that are performed in a similar or alternative order, or at least partially in parallel, for this process and other processes proposed herein. In addition, although such examples refer to ports, it should be understood that various other components can also use such processes within the scope of various embodiments. In such an example, a FW update to a platform component is received 502. The update may be associated with a component that forms part of a platform, in which the component has one of various different levels or capabilities for protection, detection and recovery operations. In such an example, one or more capabilities of the component are determined 504. For example, it can be determined whether the component is "fully sufficient" or "partially sufficient" and other such options. Information about capabilities can be stored in one or more data repositories. Supplemental update information 506 can then be determined based at least on one or more capabilities of the component. For example, if the component is determined to be a "partially sufficient" component, the supplemental update information may include the location of the recovery image and various other options as discussed herein. Then, supplemental update information may be obtained 508 and used to cause the FW update to be installed 510. In this way, FW updates may be performed with increased security because less than fully adequate components may receive additional support from other platform components to implement various updates.

[0048] Figure 5B An example process 520 for generating an index associated with component capabilities is shown. In such an example, components that make up a platform are identified 522. A capability classification of the component is determined 524 based at least on one or more component attributes. The component can then be stored in an index of components that make up the platform, wherein the index can include an identification of the component and at least a capability classification 526. It can be determined whether the component is classified as a fully sufficient component 528. If not, one or more supplemental update entries may be populated. For example, a different key may be added or a storage location may be restored for a component that is not fully sufficient. If the component is fully sufficient, the process may continue to determine whether there are additional components for the platform 532. If so, the process may be repeated to identify different capabilities and populate the index. If not, the index entry and one or more supplemental update entries 534 may be stored.

[0049] Figure 5CAn example process 540 for generating a corrective action to be performed in response to an error is shown. In such an example, a request 542 associated with an operation of a platform component is received. As an example, the operation may be a FW operation. For example, the component may be providing an indication that the FW version will be verified. In addition, the FW operation may point to a run failure, a recovery operation, and / or the like. One or more capabilities 544 of the platform component may be determined. The capability may be associated with a level or hierarchy of capabilities that can be performed on a platform component such as a fully sufficient component or a solicitation component, and other such options. Errors 546 associated with the operation such as an inability to verify the FW version, an update error, a recovery error, a run failure, and / or the like may be determined. In at least one embodiment, the platform component does not have sufficient capabilities to recover from the error, and as an option, corrective measures 548 for the error may be performed. For example, a backup version of the FW may be provided to the component. In another example, in the case where the error is related to the inability of the component to perform authentication, the corrective action may be used to authenticate the version of the FW. In this way, the platform resilience authority can provide assistance to the platform component based on the on-device capabilities of the platform component.

[0050] As previously mentioned, aspects of the various methods presented herein may be sufficiently lightweight to be performed in real time on a device such as a client device (such as a personal computer or a game console). Such processing may be performed on content generated on that client device, received by that client device, or received from an external source (such as streaming data or other content received over at least one network). In some cases, processing and / or determining such content may be performed by one of these other devices, systems, or entities and then provided to the client device (or other such recipient) for presentation or other such use.

[0051] As an example, Figure 6An example network configuration 600 is shown that can be used to provide, generate, modify, encode, process and / or transmit image data or other such content. In at least one embodiment, a client device 602 can generate or receive data for a session using components of a control application 604 on the client device 602 and data stored locally on the client device. In at least one embodiment, a content application 624 executing on a server 620 (e.g., a cloud server or edge server) can initialize a session associated with at least one client device 602, as a session manager and user data stored in a user database 636 can be utilized, and content such as one or more digital assets (e.g., object representations) from an asset repository 634 can be determined by a content manager 626. The content manager 626 can work with an image synthesis module 628 to generate or synthesize new objects, digital assets, or other such content to be provided for presentation by the client device 602. In at least one embodiment, such an image synthesis module 628 can use one or more neural networks or machine learning models, which can be trained or updated using a training module 632 or system on or in communication with the server 620. This may include training and / or using a diffusion model 630 to generate content tiles that may be used by an image synthesis module 628, for example, to apply a non-repeating texture to an area of ​​an environment where image or video data is to be presented by a client device 602. At least a portion of the generated content may be transmitted to the client device 602 using an appropriate transmission manager 622 for transmission via download, streaming, or other such transmission channels. Prior to transmission to the client device 602, at least some of such data may be encoded and / or compressed using an encoder. In at least one embodiment, a client device 602 receiving such content may provide the content to a corresponding control application 604, which may also or alternatively include a graphical user interface 610, a content manager 612, and an image synthesis or diffusion module 614 for providing, synthesizing, modifying, or using content presented (or for other purposes) on or by the client device 602. The decoder may also be used to decode data received over the network 640 for presentation by the client device 602, such as images or video content through a display 606 and audio (such as sounds and music) through at least one audio playback device 608 (such as a speaker or headphones). In at least one embodiment, at least some of such content may already be stored, rendered, or accessible to the client device 602, such that transmission over the network 640 is not required for at least that portion of the content, such as where that content may have been pre-downloaded or stored locally on a hard drive or optical disk.In at least one embodiment, such content may be delivered from the server 620 or user database 636 to the client device 602 using a transmission mechanism such as data streaming. In at least one embodiment, at least a portion of such content may be obtained, enhanced, and / or streamed from other sources such as third-party services 660 or other client devices 650, which may also include content applications 662 for generating, enhancing, or providing content. In at least one embodiment, portions of such functionality may be performed using multiple computing devices, such as a combination of a CPU and a GPU, or multiple processors in one or more computing devices.

[0052] In such examples, the client devices may include any appropriate computing devices, such as computing devices may include desktop computers, laptops, set-top boxes, streaming devices, game consoles, smart phones, tablet computers, VR headsets, AR goggles, wearable computers, or smart TVs. Each client device may submit a request through at least one wired or wireless network such as the Internet, Ethernet, local area network (LAN) or cellular network, and other such options. In such examples, the requests may be submitted to an address associated with a cloud provider, and the cloud provider may operate or control one or more electronic resources in the cloud provider environment, such as one data center or server farm. In at least one embodiment, the request may be received or processed by at least one edge server located at the edge of the network and outside of at least one security layer associated with the cloud provider environment. In this way, latency can be reduced by enabling the client device to interact with a server that is closer, while also improving the security of resources in the cloud provider environment.

[0053] In at least one embodiment, such a system can be used to perform graphics rendering operations. In other embodiments, such a system can be used for other purposes such as for providing image or video content to test or verify autonomous machine applications or for performing deep learning operations. In at least one embodiment, such a system can be implemented using an edge device, or such a system can include one or more virtual machines (VMs). In at least one embodiment, such a system can be implemented at least partially in a data center or at least partially using cloud computing resources.

[0054] Data Center

[0055] Figure 7 An example data center 700 is shown in which at least one embodiment may be used. In at least one embodiment, data center 700 includes a data center infrastructure layer 710, a framework layer 720, a software layer 730, and an application layer 740.

[0056] In at least one embodiment, Figure 7 As shown, the data center infrastructure layer 710 may include a resource coordinator 712, grouped computing resources 714, and node computing resources ("node CRs") 716(1)-716(N), where "N" represents any positive integer. In at least one embodiment, the node CRs 716(1)-716(N) may include, but are not limited to, any number of central processing units ("CPUs") or other processors (including accelerators, field programmable gate arrays (FPGAs), graphics processors, etc.), memory devices (e.g., dynamic read-only memories), storage devices (e.g., solid-state drives or disk drives), network input / output ("NWI / O") devices, network switches, virtual machines ("VMs"), power modules, and cooling modules, etc. In at least one embodiment, one or more of the node CRs 716(1)-716(N) may be a server having one or more of the above-mentioned computing resources.

[0057] In at least one embodiment, the computing resources 714 of the grouping can include a separate grouping of node CRs housed in one or more racks (not shown), or many racks housed in data centers of various geographic locations (also not shown). The separate grouping of node CRs in the computing resources 714 of the grouping can include computing, networks, memory or storage resources that can be configured or assigned to support the grouping of one or more workloads. In at least one embodiment, several node CRs including a CPU or a processor can be grouped in one or more racks to provide computing resources to support one or more workloads. In at least one embodiment, one or more racks can also include any number of power modules, cooling modules and network switches in any combination.

[0058] In at least one embodiment, resource coordinator 712 may configure or otherwise control one or more nodes CR 716(1)-716(N) and / or grouped computing resources 714. In at least one embodiment, resource coordinator 712 may include a software design infrastructure ("SDI") management entity for data center 700. In at least one embodiment, resource coordinator 107 may include hardware, software, or some combination thereof.

[0059] In at least one embodiment, Figure 7As shown, the framework layer 720 includes a job scheduler 722, a configuration manager 724, a resource manager 726, and a distributed file system 728. In at least one embodiment, the framework layer 720 may include a framework for supporting software 732 of the software layer 730 and / or one or more applications 742 of the application layer 740. In at least one embodiment, the software 732 or the application 742 may include web-based service software or applications, such as those provided by Amazon Web Services, Google Cloud, and Microsoft Azure. In at least one embodiment, the framework layer 720 may be, but is not limited to, a free and open source software web application framework, such as Apache Spark, which can utilize the distributed file system 728 for large-scale data processing (e.g., "big data"). TM (hereinafter referred to as "Spark"). In at least one embodiment, the job scheduler 722 may include a Spark driver to facilitate scheduling of workloads supported by various layers of the data center 700. In at least one embodiment, the configuration manager 724 may be able to configure different layers, such as the software layer 730 and the framework layer 720 including Spark and a distributed file system 728 for supporting large-scale data processing. In at least one embodiment, the resource manager 726 can manage cluster or group computing resources mapped to or allocated to support the distributed file system 728 and the job scheduler 722. In at least one embodiment, the cluster or group computing resources may include group computing resources 714 on the data center infrastructure layer 710. In at least one embodiment, the resource manager 726 can coordinate with the resource coordinator 712 to manage these mapped or allocated computing resources.

[0060] In at least one embodiment, software 732 included in software layer 730 may include software used by at least a portion of node CRs 716(1)-716(N), grouped computing resources 714, and / or distributed file system 728 of framework layer 720. One or more types of software may include, but are not limited to, Internet web page search software, email virus scanning software, database software, and streaming video content software.

[0061] In at least one embodiment, one or more applications 742 included in the application layer 740 may include one or more types of applications used by at least a portion of the node CRs 716(1)-716(N), the grouped computing resources 714, and / or the distributed file system 728 of the framework layer 720. The one or more types of applications may include, but are not limited to, any number of genomics applications, cognitive computing, and machine learning applications, including training or inference software, machine learning framework software (e.g., PyTorch, TensorFlow, Caffe, etc.), or other machine learning applications used in conjunction with one or more embodiments.

[0062] In at least one embodiment, any of the configuration manager 724, resource manager 726, and resource coordinator 712 can implement any number and type of self-modification measures based on any number and type of data acquired in any technically feasible manner. In at least one embodiment, the self-modification measures can relieve a data center operator of the data center 700 from making potentially bad configuration decisions and can avoid underutilized and / or poorly performing portions of the data center.

[0063] In at least one embodiment, the data center 700 may include tools, services, software, or other resources to train one or more machine learning models or predict or infer information using one or more machine learning models according to one or more embodiments described herein. For example, in at least one embodiment, the machine learning model may be trained by calculating weight parameters according to a neural network architecture using the software and computing resources described above with respect to the data center 700. In at least one embodiment, by using weight parameters calculated by one or more training techniques described herein, a trained machine learning model corresponding to one or more neural networks may be used to infer or predict information using the resources described above with respect to the data center 700.

[0064] In at least one embodiment, the data center can use a CPU, an application-specific integrated circuit (ASIC), a GPU, an FPGA, or other hardware to use the above resources to perform training and / or reasoning. In addition, one or more of the above software and / or hardware resources can be configured as a service such as image recognition, speech recognition, or other artificial intelligence services to allow users to train or perform information reasoning.

[0065] Reasoning and / or training logic 715 is used to perform reasoning and / or training operations related to one or more embodiments. In at least one embodiment, reasoning and / or training logic 715 can be used to Figure 7A system in which an inference or prediction operation is performed based at least in part on weight parameters computed using a neural network training operation, a neural network function and / or architecture described herein, or using a neural network use case.

[0066] Such components can be used for platform resiliency.

[0067] Computer Systems

[0068] Figure 8 800 is a block diagram illustrating an exemplary computer system according to at least one embodiment, which may be a system of interconnected devices and components, a system on a chip (SOC), or some combination thereof formed with a processor, which may include an execution unit to execute instructions. In at least one embodiment, according to the present disclosure, such as the embodiments described herein, the computer system 800 may include, but is not limited to, components, such as a processor 802, whose execution unit includes logic to execute algorithms for process data. In at least one embodiment, the computer system 800 may include a processor, such as a processor available from Intel Corporation of Santa Clara, California. Processor family, Xeon TM , XScale TM and / or StrongARM TM , Core TM or Nervana TM microprocessor, although other systems (including PCs with other microprocessors, engineering workstations, set-top boxes, etc.) may also be used. In at least one embodiment, computer system 800 may execute a version of the WINDOWS operating system available from Microsoft Corporation of Redmond, Wash., although other operating systems (e.g., UNIX and Linux), embedded software, and / or graphical user interfaces may also be used.

[0069] Embodiments may be used in other devices, such as handheld devices and embedded applications. Some examples of handheld devices include cellular phones, Internet Protocol (Internet Protocol) devices, digital cameras, personal digital assistants ("PDAs"), and handheld PCs. In at least one embodiment, the embedded application may include a microcontroller, a digital signal processor ("DSP"), a system on a chip, a network computer ("NetPC"), a set-top box, a network hub, a wide area network ("WAN") switch, or any other system that can execute one or more instructions according to at least one embodiment.

[0070] In at least one embodiment, the computer system 800 may include, but is not limited to, a processor 802, which may include, but is not limited to, one or more execution units 808 to perform machine learning model training and / or reasoning according to the techniques described herein. In at least one embodiment, the computer system 800 is a single-processor desktop or server system, but in another embodiment, the computer system 800 may be a multi-processor system. In at least one embodiment, the processor 802 may include, but is not limited to, a complex instruction set computer ("CISC") microprocessor, a reduced instruction set computing ("RISC") microprocessor, a very long instruction word ("VLIW") microprocessor, a processor that implements an instruction set combination, or any other processor device, such as a digital signal processor. In at least one embodiment, the processor 802 may be coupled to a processor bus 810, which may transmit data signals between the processor 802 and other components in the computer system 800.

[0071] In at least one embodiment, processor 802 may include, but is not limited to, a level 1 ("L1") internal cache memory ("cache") 804. In at least one embodiment, processor 802 may have a single internal cache or multiple levels of internal cache. In at least one embodiment, the cache memory may reside external to processor 802. Other embodiments may also include a combination of internal and external caches, depending on the particular implementation and needs. In at least one embodiment, register file 806 may store different types of data in various registers, including, but not limited to, integer registers, floating point registers, status registers, and instruction pointer registers.

[0072] In at least one embodiment, logic execution unit 808 that performs integer and floating point operations is also located in processor 802, including, but not limited to, performing integer and floating point operations. In at least one embodiment, processor 802 may also include a microcode ("ucode") read-only memory ("ROM") for storing microcode for certain macroinstructions. In at least one embodiment, execution unit 808 may include logic for processing a packed instruction set 809. In at least one embodiment, by including a packed instruction set 809 in the instruction set of a general purpose processor, and associated circuitry to execute the instructions, operations used by many multimedia applications may be performed using packed data in processor 802. In one or more embodiments, many multimedia applications may be executed faster and more efficiently by using the full width of the processor's data bus to perform operations on packed data, which may not require the transfer of smaller units of data on the processor's data bus to perform one or more operations one data element at a time.

[0073] In at least one embodiment, execution unit 808 may also be used in microcontrollers, embedded processors, graphics devices, DSPs, and other types of logic circuits. In at least one embodiment, computer system 800 may include, but is not limited to, memory 820. In at least one embodiment, memory 820 may be implemented as a dynamic random access memory ("DRAM") device, a static random access memory ("SRAM") device, a flash memory device, or other storage device. In at least one embodiment, memory 820 may store instructions 819 and / or data 821 represented by data signals that may be executed by processor 802.

[0074] In at least one embodiment, the system logic chip can be coupled to the processor bus 810 and the memory 820. In at least one embodiment, the system logic chip can include, but is not limited to, a memory controller hub ("MCH") 816, and the processor 802 can communicate with the MCH 816 via the processor bus 810. In at least one embodiment, the MCH 816 can provide a high-bandwidth memory path 818 to the memory 820 for instruction and data storage and for storage of graphics commands, data, and textures. In at least one embodiment, the MCH 816 can initiate data signals between the processor 802, the memory 820, and other components in the computer system 800, and bridge data signals between the processor bus 810, the memory 820, and the system I / O 822. In at least one embodiment, the system logic chip can provide a graphics port for coupling to a graphics controller. In at least one embodiment, the MCH 816 can be coupled to the memory 820 via a high-bandwidth memory path 818, and the graphics / video card 812 can be coupled to the MCH 816 via an Accelerated Graphics Port ("AGP") interconnect 814.

[0075] In at least one embodiment, the computer system 800 may use a system I / O 822, which is a proprietary hub interface bus, to couple the MCH 816 to an I / O controller hub ("ICH") 830. In at least one embodiment, the ICH 830 may provide direct connections to certain I / O devices through a local I / O bus. In at least one embodiment, the local I / O bus may include, but is not limited to, a high-speed I / O bus used to connect peripheral devices to the memory 820, the chipset, and the processor 802. Examples may include, but are not limited to, an audio controller 828, a firmware hub ("Flash BIOS") 828, a wireless transceiver 826, a data store 824, a traditional I / O controller 823 including a user input and keyboard interface, a serial expansion port 827 (e.g., a universal serial bus (USB) port), and a network controller 834. The data store 824 may include a hard drive, a floppy drive, a CD-ROM device, a flash memory device, or other mass storage device.

[0076] In at least one embodiment, Figure 8 A system comprising interconnected hardware devices or "chips" is shown, while in other embodiments, Figure 8An exemplary system on chip (SoC) may be shown. In at least one embodiment, the devices may be interconnected with a proprietary interconnect, a standardized interconnect (e.g., PCIe), or some combination thereof. In at least one embodiment, one or more components of computer system 800 are interconnected using a compute express link (CXL) interconnect.

[0077] Reasoning and / or training logic 715 is used to perform reasoning and / or training operations related to one or more embodiments. In at least one embodiment, reasoning and / or training logic 715 can be used to Figure 8 A system in which an inference or prediction operation is performed based at least in part on weight parameters computed using a neural network training operation, a neural network function and / or architecture described herein, or using a neural network use case.

[0078] Such components can be used for platform resiliency.

[0079] Fig. 9 is a block diagram illustrating an electronic device 900 for utilizing a processor 910 according to at least one embodiment. In at least one embodiment, the electronic device 900 may be, for example but not limited to, a notebook computer, a tower server, a rack server, a blade server, a laptop computer, a desktop computer, a tablet computer, a mobile device, a phone, an embedded computer, or any other suitable electronic device.

[0080] In at least one embodiment, the electronic device 900 may include, but is not limited to, a processor 910 communicatively coupled to any suitable number or kind of components, peripherals, modules, or devices. In at least one embodiment, the processor 910 is coupled using a bus or interface, such as an Ic bus, a system management bus ("SMBus"), a low pin count (LPC) bus, a serial peripheral interface ("SPI"), a high-definition audio ("HDA") bus, a serial advanced technology attachment ("SATA") bus, a universal serial bus ("USB") (versions 1, 2, 3), or a universal asynchronous receiver / transmitter ("UART") bus. In at least one embodiment, Fig. 9 A system is shown that includes interconnected hardware devices or "chips", while in other embodiments, Fig. 9 An exemplary system on chip (SoC) may be shown. In at least one embodiment, Fig. 9 The devices shown in can be interconnected with a proprietary interconnect, a standardized interconnect (e.g., PCIe), or some combination thereof. In at least one embodiment, Fig. 9 One or more components of the system are interconnected using Compute Express Link (CXL) interconnect lines.

[0081] In at least one embodiment, Fig. 9The display 924, the touch screen 925, the touch pad 930, the near field communication unit ("NFC") 945, the sensor hub 940, the thermal sensor 946, the fast chipset ("EC") 935, the trusted platform module ("TPM") 938, the BIOS / firmware / flash memory ("BIOS, FWFlash") 922, the DSP 960, the drive 920 (for example, a solid state disk ("SSD") or a hard disk drive ("HDD")), the wireless local area network unit ("WLAN") 950, the Bluetooth unit 952, the wireless wide area network unit ("WWAN") 956, the global positioning system (GPS) 955, the camera ("USB3.0 camera") 954 (for example, a USB3.0 camera), and / or the low power double data rate ("LPDDR") memory unit ("LPDDR3") 915 implemented in, for example, the LPDDR3 standard. Each of these components can be implemented in any suitable manner.

[0082] In at least one embodiment, other components may be communicatively coupled to the processor 910 through the components described above. In at least one embodiment, the accelerometer 941, ambient light sensor ("ALS") 942, compass 943, and gyroscope 944 may be communicatively coupled to the sensor hub 940. In at least one embodiment, the thermal sensor 939, fan 937, keyboard 936, and touchpad 930 may be communicatively coupled to the EC 935. In at least one embodiment, the speaker 963, earphone 964, and microphone ("mic") 965 may be communicatively coupled to the audio unit ("audio codec and class D amplifier") 962, which in turn may be communicatively coupled to the DSP 960. In at least one embodiment, the audio unit 962 may include, for example, but not limited to, an audio encoder / decoder ("codec") and a class D amplifier. In at least one embodiment, the SIM card ("SIM") 957 may be communicatively coupled to the WWAN unit 956. In at least one embodiment, components such as the WLAN unit 950 and the Bluetooth unit 952 and the WWAN unit 956 may be implemented as a next generation form factor (NGFF).

[0083] Reasoning and / or training logic 715 is used to perform reasoning and / or training operations related to one or more embodiments. In at least one embodiment, reasoning and / or training logic 715 can be used to Fig. 9 A system in which an inference or prediction operation is performed based at least in part on weight parameters computed using a neural network training operation, a neural network function and / or architecture described herein, or using a neural network use case.

[0084] Such components can be used for platform resiliency.

[0085] Fig.101000 is a block diagram of a processing system according to at least one embodiment. In at least one embodiment, system 1000 includes one or more processors 1002 and one or more graphics processors 1008, and can be a single-processor desktop system, a multi-processor workstation system, or a server system with a large number of (one or more) processors 1002 or (one or more) processor cores 1007. In at least one embodiment, system 1000 is a processing platform incorporated within a system-on-chip (SoC) integrated circuit for use in a mobile, handheld, or embedded device.

[0086] In at least one embodiment, the system 1000 may include or be incorporated into a server-based gaming platform, including a gaming console, a mobile gaming console, a handheld gaming console, or an online gaming console for gaming and media consoles. In at least one embodiment, the system 1000 is a mobile phone, a smart phone, a tablet computing device, or a mobile Internet device. In at least one embodiment, the processing system 1000 may also include a wearable device coupled to or integrated in a wearable device, such as a smart watch wearable device, a smart glasses device, an augmented reality device, or a virtual reality device. In at least one embodiment, the processing system 1000 is a television or set-top box device having one or more processors 1002 and a graphical interface generated by one or more graphics processors 1008.

[0087] In at least one embodiment, one or more processors 1002 each include one or more processor cores 1007 to process instructions that, when executed, perform operations for system and user software. In at least one embodiment, each of the one or more processor cores 1007 is configured to process a specific instruction set 1009. In at least one embodiment, the instruction set 1009 can facilitate complex instruction set computing (CISC), reduced instruction set computing (RISC), or computing through very long instruction words (VLIW). In at least one embodiment, (one or more) processor cores 1007 can each process a different instruction set 1009, which can include instructions that help emulate other instruction sets. In at least one embodiment, the processor core 1007 can also include other processing devices, such as a digital signal processor (DSP).

[0088] In at least one embodiment, the processor(s) 1002 include cache memory 1004. In at least one embodiment, the processor(s) 1002 may have a single internal cache or multiple levels of internal cache. In at least one embodiment, the cache memory is shared between various components of the processor(s) 1002. In at least one embodiment, the processor(s) 1002 also uses an external cache (e.g., a level 3 (L3) cache or a last level cache (LLC)) (not shown), which may be shared between the processor cores 1007 using known cache coherence techniques. In at least one embodiment, the processor(s) 1002 additionally includes a register file 1006, which may include different types of registers (e.g., integer registers, floating point registers, status registers, and instruction pointer registers) for storing different types of data. In at least one embodiment, the register file 1006 may include general registers or other registers.

[0089] In at least one embodiment, one or more processors 1002 are coupled to one or more interface buses 1010 to transmit communication signals, such as address, data, or control signals, between (one or more) processors 1002 and other components in the system 1000. In at least one embodiment, (one or more) interface buses 1010 may be a processor bus in one embodiment, such as a version of a direct media interface (DMI) bus. In at least one embodiment, (one or more) interface buses 1010 are not limited to DMI buses, and may include one or more peripheral component interconnect buses (e.g., PCI, PCI Express), memory buses, or other types of interface buses. In at least one embodiment, processor 1002 includes an integrated memory controller 1016 and a platform controller hub 1030. In at least one embodiment, memory controller 1016 facilitates communication between memory devices and other components of the processing system 1000, while platform controller hub (PCH) 1030 provides connections to I / O devices through local I / O buses.

[0090] In at least one embodiment, the memory device 1020 may be a dynamic random access memory (DRAM) device, a static random access memory (SRAM) device, a flash memory device, a phase change memory device, or have appropriate performance to be used as a processor memory. In at least one embodiment, the memory device 1020 may be used as a system memory of the processing system 1000 to store data 1022 and instructions 1021 for use when one or more processors 1002 execute applications or processes. In at least one embodiment, the memory controller 1016 is also coupled to an optional external graphics processor 1012, which may communicate with one or more graphics processors 1008 in (one or more) processors 1002 to perform graphics and media operations. In at least one embodiment, the display device 1011 may be connected to the processor 1002. In at least one embodiment, the display device 1011 may include one or more of the internal display devices, such as in a mobile electronic device or laptop device or an external display device connected via a display interface (e.g., DisplayPort, etc.). In at least one embodiment, the display device 1011 may include a head mounted display (HMD), such as a stereoscopic display device used in virtual reality (VR) applications or augmented reality (AR) applications.

[0091] In at least one embodiment, the platform controller hub 1030 enables peripheral devices to be connected to the storage device 1020 and (one or more) processors 1002 via a high-speed I / O bus. In at least one embodiment, the I / O peripherals include, but are not limited to, an audio controller 1046, a network controller 1034, a firmware interface 1028, a wireless transceiver 1026, a touch sensor 1025, a data storage device 1024 (e.g., a hard drive, flash memory, etc.). In at least one embodiment, the data storage device 1024 can be connected via a storage interface (e.g., SATA) or via a peripheral bus, such as a peripheral component interconnect bus (e.g., PCI, PCIe). In at least one embodiment, the touch sensor 1025 can include a touch screen sensor, a pressure sensor, or a fingerprint sensor. In at least one embodiment, the wireless transceiver 1026 can be a Wi-Fi transceiver, a Bluetooth transceiver, or a mobile network transceiver, such as a 3G, 4G, or long-term evolution (LTE) transceiver. In at least one embodiment, the firmware interface 1028 enables communication with the system firmware and can be, for example, a unified extensible firmware interface (UEFI). In at least one embodiment, the network controller 1034 can enable a network connection to a wired network. In at least one embodiment, a high-performance network controller (not shown) is coupled to the (one or more) interface bus 1010. In at least one embodiment, the audio controller 1046 is a multi-channel high-definition audio controller. In at least one embodiment, the processing system 1000 includes an optional legacy I / O controller 1040 for coupling legacy (e.g., Personal System 2 (PS / 2)) devices to the system 1000. In at least one embodiment, the platform controller hub 1030 can also be connected to one or more universal serial bus (USB) controllers 1042, which connect input devices such as a keyboard and mouse 1043 combination, a camera 1044, or other USB input devices.

[0092] In at least one embodiment, instances of memory controller 1016 and platform controller hub 1030 may be integrated into a discrete external graphics processor, such as external graphics processor 1012. In at least one embodiment, platform controller hub 1030 and / or memory controller 1016 may be external to one or more processors 1002. For example, in at least one embodiment, system 1000 may include external memory controller 1016 and platform controller hub 1030, which may be configured as a memory controller hub and a peripheral controller hub in a system chipset that communicates with processor 1002.

[0093] The reasoning and / or training logic 715 is used to perform reasoning and / or training operations related to one or more embodiments. In at least one embodiment, part or all of the reasoning and / or training logic 715 can be incorporated into (one or more) graphics processors 1008. For example, in at least one embodiment, the training and / or reasoning techniques described herein can use one or more ALUs included in the graphics processor. In at least one embodiment, the weight parameters can be stored in on-chip or off-chip memory and / or registers (shown or not shown), which configure the ALU of the graphics processor to perform one or more machine learning algorithms, neural network architectures, use cases, or training techniques described herein.

[0094] Such components can be used for platform resiliency.

[0095] Fig.11 is a block diagram of a processor 1100 having one or more processor cores 1102A-1102N, an integrated memory controller 1114, and an integrated graphics processor 1108 in accordance with at least one embodiment. In at least one embodiment, the processor 1100 may include additional cores, up to and including the additional core 1102N represented by the dashed box. In at least one embodiment, each of the (one or more) processor cores 1102A-1102N includes one or more internal cache units 1104A-1104N. In at least one embodiment, each processor core may also have access to one or more shared cache units 1106.

[0096] In at least one embodiment, the internal cache unit(s) 1104A-1104N and the shared cache unit(s) 1106 represent a cache memory hierarchy within the processor 1100. In at least one embodiment, the cache unit(s) 1104A-1104N may include at least one level of instruction and data cache within each processor core and one or more levels of cache in a shared mid-level cache, such as level 2 (L2), level 3 (L3), level 4 (L4), or other levels of cache, where the highest level of cache before external memory is categorized as LLC. In at least one embodiment, cache coherency logic maintains coherency between the various cache units 1106 and 1104A-1104N.

[0097] In at least one embodiment, the processor 1100 may also include a set of one or more bus controller units 1116 and a system agent core 1110. In at least one embodiment, the one or more bus controller units 1116 manage a set of peripheral buses, such as one or more PCI or PCIe buses. In at least one embodiment, the system agent core 1110 provides management functions for various processor components. In at least one embodiment, the system agent core 1110 includes one or more integrated memory controllers 1114 to manage access to various external memory devices (not shown).

[0098] In at least one embodiment, one or more processor cores 1102A-1102N include support for multiple threads simultaneously. In at least one embodiment, the system agent core 1110 includes components for coordinating and operating (one or more) processor cores 1102A-1102N during multithreaded processing. In at least one embodiment, the system agent core 1110 may additionally include a power control unit (PCU) that includes logic and components for regulating one or more power states of (one or more) processor cores 1102A-1102N and graphics processor 1108.

[0099] In at least one embodiment, the processor 1100 also includes a graphics processor 1108 for performing graphics processing operations. In at least one embodiment, the graphics processor 1108 is coupled with a shared cache unit (one or more) 1106 and a system agent core 1110 including one or more integrated memory controllers 1114. In at least one embodiment, the system agent core 1110 also includes a display controller 1111 for driving the graphics processor output to one or more coupled displays. In at least one embodiment, the display controller 1111 may also be a separate module coupled to the graphics processor 1108 via at least one interconnect, or may be integrated within the graphics processor 1108.

[0100] In at least one embodiment, a ring-based interconnect unit 1112 is used to couple the internal components of the processor 1100. In at least one embodiment, alternative interconnect units may be used, such as point-to-point interconnects, switched interconnects, or other technologies. In at least one embodiment, the graphics processor 1108 is coupled to the ring-based interconnect unit 1112 via an I / O link 1113.

[0101] In at least one embodiment, I / O link 1113 represents at least one of a variety of I / O interconnects, including packaged I / O interconnects that facilitate communication between various processor components and high-performance embedded memory modules 1118 (e.g., eDRAM modules). In at least one embodiment, each of the processor core(s) 1102A-1102N and graphics processor 1108 uses embedded memory module 1118 as a shared last level cache.

[0102] In at least one embodiment, (one or more) processor cores 1102A-1102N are homogeneous cores that execute a common instruction set architecture. In at least one embodiment, (one or more) processor cores 1102A-1102N are heterogeneous in terms of instruction set architecture (ISA), wherein one or more processor cores 1102A-1102N execute a common instruction set, while one or more other processor cores 1102A-1102N execute a subset or a different instruction set of the common instruction set. In at least one embodiment, in terms of microarchitecture, (one or more) processor cores 1102A-1102N are heterogeneous, wherein one or more cores with relatively high power consumption are coupled with one or more power cores with lower power consumption. In at least one embodiment, processor 1100 can be implemented on one or more chips or implemented as a SoC integrated circuit.

[0103] The reasoning and / or training logic 715 is used to perform reasoning and / or training operations related to one or more embodiments. In at least one embodiment, part or all of the reasoning and / or training logic 715 may be incorporated into the processor 1100. For example, in at least one embodiment, the training and / or reasoning techniques described herein may use one or more ALUs, (one or more) processor cores 1102A-1102N, or other processors included in the graphics processor 1108. Fig.11 In at least one embodiment, the weight parameters may be stored in on-chip or off-chip memory and / or registers (shown or not shown) that configure the ALU of the graphics processor 1100 / 1108 to execute one or more machine learning algorithms, neural network architectures, use cases, or training techniques described herein.

[0104] Such components can be used for platform resiliency.

[0105] Various embodiments may be described in the following terms:

[0106] 1. A processor, comprising:

[0107] One or more circuits for:

[0108] Identify components installed within the platform;

[0109] determining a capability classification for the component based on one or more component attributes;

[0110] generating an index entry for the component, the index entry comprising at least an identifier and the capability classification;

[0111] Determining that the described competency classification is not fully adequate;

[0112] populating one or more supplemental update entries for the component; and

[0113] The index entry and the one or more supplemental update entries for the component are stored.

[0114] 2. A processor as described in clause 1, wherein the capability classification includes at least one of partially sufficient, solicited, fully dependent, or virtual.

[0115] 3. A processor as described in clause 1, wherein one or more processing units are further configured to:

[0116] receiving a firmware update request for the component;

[0117] determining the capability classification using the index entry;

[0118] Based at least on the capability classification, determining that the firmware update will use the one or more supplemental update items; and

[0119] The firmware update is caused to be performed using the one or more supplemental update entries.

[0120] 4. The processor of clause 1, wherein the capability classification is associated with a capability on a component for performing at least one of a protection operation, a detection operation, or a recovery operation.

[0121] 5. The processor of clause 1, wherein the one or more circuits are further configured to:

[0122] receiving a firmware update request for the component;

[0123] determining that the capability classification corresponds to a partially sufficient component; and

[0124] Update information is retrieved from one or more external component storage locations.

[0125] 6. The processor of clause 1, wherein the one or more circuits are further configured to:

[0126] receiving a firmware update request for the component;

[0127] determining that the capability classification corresponds to a requesting component;

[0128] verifying the firmware update using one or more off-component services; and

[0129] Update information is retrieved from one or more external component storage locations.

[0130] 7. A processor as described in clause 1, wherein the one or more circuits are further configured to:

[0131] receiving updated parameters for the component from an authority associated with the platform;

[0132] authenticating the authority; and

[0133] The index entry is updated based on the update parameter for the component.

[0134] 8. The processor of clause 7, wherein the authority is at least one of a manufacturer of the platform or an owner of the platform.

[0135] 9. The processor of clause 1, wherein the processor is included in at least one of:

[0136] A system for performing simulation operations;

[0137] Systems for performing simulated operations to test or validate autonomous machine applications;

[0138] Systems for performing digital twin operations;

[0139] A system for performing light transport simulations;

[0140] Systems for rendering graphical output;

[0141] Systems for performing deep learning operations;

[0142] Systems implemented using edge devices;

[0143] Systems for generating or presenting virtual reality (VR) content;

[0144] Systems for generating or presenting augmented reality (AR) content;

[0145] Systems for generating or presenting mixed reality (MR) content;

[0146] A system comprising one or more virtual machines (VMs);

[0147] A system for performing operations of a conversational AI application;

[0148] A system for performing operations of a generative AI application;

[0149] A system for performing operations using a language model;

[0150] A system for performing one or more operations of generating content using a large language model (LLM);

[0151] A system implemented at least in part in a data center;

[0152] A system for performing hardware testing using simulation;

[0153] A system for performing one or more operations of generating content using a language model;

[0154] Systems for synthetic data generation;

[0155] A collaborative content creation platform for 3D assets; or

[0156] A system implemented at least in part using cloud computing resources.

[0157] 10. A computer-implemented method comprising:

[0158] receiving a firmware (FW) update request associated with a component forming at least part of a platform;

[0159] determining one or more capabilities associated with the component;

[0160] determining supplemental update information for the platform component based at least on the one or more capabilities;

[0161] obtaining the supplemental update information based at least on an identifier associated with the component; and

[0162] The FW update is caused to be installed for the component using at least the supplemental update information.

[0163] 11. The computer-implemented method of clause 10, further comprising:

[0164] receiving a second FW update request for a second component forming at least part of the platform;

[0165] determining one or more second capabilities associated with the second component; and

[0166] determining that the one or more second capabilities define the second component as a fully sufficient component; and

[0167] The FW update is caused to be installed for the component.

[0168] 12. The computer-implemented method of clause 10, wherein the one or more capabilities are associated with at least a protection operation, a detection operation, or a recovery operation.

[0169] 13. The computer-implemented method of clause 10, further comprising:

[0170] A capability level for the component is defined, the capability level comprising at least one of fully sufficient, partially sufficient, solicited, fully dependent, and virtual.

[0171] 14. The computer-implemented method of clause 10, further comprising:

[0172] receiving update parameters for components of the platform from an authority associated with the platform;

[0173] authenticating the authority; and

[0174] An index entry corresponding to the platform component is updated based on the update parameter for the component.

[0175] 15. The computer-implemented method of clause 10, further comprising:

[0176] identifying new components associated with the platform;

[0177] receiving authentication information associated with the new component; and

[0178] An index entry is generated for the new component, wherein the index entry at least includes an identifier and a new component capability classification.

[0179] 16. A system comprising:

[0180] One or more processing units are configured to determine a component capability level in response to receiving an update request for a component, and obtain supplemental update information for performing an update based at least on the component capability level and index information of the component.

[0181] 17. The system of clause 16, wherein the component capability level corresponds to an ability of the component to perform at least one of a protection operation, a detection operation, or a recovery operation using resources on the component.

[0182] 18. The system of clause 16, wherein the component capability level corresponds to one of fully sufficient, partially sufficient, requested, fully dependent, and virtual.

[0183] 19. The system of clause 16, wherein the index information is populated by a platform manufacturer and rooted in an elasticity engine of a platform including the component.

[0184] 20. The system of clause 16, wherein the supplemental update information comprises at least one of a verification key, a measurement operation, or an off-component storage location.

[0185] Other variations are within the spirit of the present disclosure. Thus, while the disclosed technology is susceptible to various modifications and alternative constructions, certain illustrated embodiments thereof are shown in the drawings and have been described in detail above. However, it should be understood that there is no intention to limit the disclosure to one or more specific forms disclosed, but on the contrary, it is intended to cover all modifications, alternative constructions, and equivalents that fall within the spirit and scope of the present disclosure as defined by the appended claims.

[0186] Unless otherwise noted or clearly contradictory to the context, in the context of describing the disclosed embodiments (particularly in the context of the appended claims), the use of the terms "one" and "an" and "the" and similar references should be interpreted as covering the singular and plural, rather than as definitions of terms. Unless otherwise noted, the terms "include", "have", "include" and "contain" should be interpreted as open terms (meaning "including but not limited to") unless otherwise noted. The term "connected" (which refers to a physical connection when unmodified) should be interpreted as partially or completely included, attached to or connected together, even if there are some interventions. Unless otherwise noted herein, references to numerical ranges herein are intended only to be used as a shorthand method of referring to each individual value falling within the range, respectively, and each individual value is incorporated into the specification as if it were individually described herein. Unless otherwise noted or contradictory to the context, the use of the term "set" (e.g., "item set") or "subset" should be interpreted as a non-empty set including one or more members. Furthermore, unless otherwise indicated or contradicted by context, the term "subset" of a corresponding set does not necessarily mean a proper subset of the corresponding set, but rather a subset and a corresponding set may be equivalent.

[0187] Unless expressly indicated otherwise or clearly contradicted by context, conjunctions such as phrases of the form "at least one of A, B, and C" or "at least one of A, B and C" are understood in context to be generally used to refer to an item, clause, or the like that may be A or B or C, or any non-empty subset of the set A and B and C. For example, in the illustrative example of a set having three members, the conjunction phrases "at least one of A, B, and C" and "at least one of A, B and C" refer to any of the following sets: {A}, {B}, {C}, {A, B}, {A, C}, {B, C}, {A, B, C}. Thus, such conjunction language is not generally intended to imply that certain embodiments require the presence of at least one of A, at least one of B, and at least one of C. In addition, unless expressly indicated otherwise or contradicted by context, the term "plurality" refers to a plural state (e.g., "plurality of items" means a plurality of items). The number of items in a plurality of items is at least two, but may be more if expressly indicated or indicated by context. Further, the phrase "based on" means "based at least in part on" rather than "based solely on" unless otherwise specified or clear from context.

[0188] Unless otherwise indicated herein or clearly contradictory to the context, the operations of the processes described herein may be performed in any suitable order. In at least one embodiment, processes such as those described herein (or variations and / or combinations thereof) are performed under the control of one or more computer systems configured with executable instructions and are implemented as code (e.g., executable instructions, one or more computer programs, or one or more applications) that are jointly executed on one or more processors by hardware or a combination thereof. In at least one embodiment, the code is stored on a computer-readable storage medium in the form of, for example, a computer program that includes a plurality of instructions that can be executed by one or more processors. In at least one embodiment, the computer-readable storage medium is a non-transitory computer-readable storage medium that excludes transient signals (e.g., propagated transient electrical or electromagnetic transmissions), but includes non-transitory data storage circuits (e.g., buffers, caches, and queues). In at least one embodiment, code (e.g., executable code or source code) is stored on a set of one or more non-transitory computer-readable storage media (or other memory for storing executable instructions) on which executable instructions are stored, which, when executed by one or more processors of a computer system (i.e., as a result of being executed), causes the computer system to perform the operations described herein. In at least one embodiment, a set of non-transitory computer-readable storage media includes a plurality of non-transitory computer-readable storage media, and one or more of the individual non-transitory storage media in the plurality of non-transitory computer-readable storage media lacks all the code, but the plurality of non-transitory computer-readable storage media stores all the code together. In at least one embodiment, the executable instructions are executed so that different instructions are executed by different processors, for example, a non-transitory computer-readable storage medium stores instructions, and a main central processing unit ("CPU") executes some instructions, while a graphics processing unit ("GPU") executes other instructions. In at least one embodiment, different components of the computer system have separate processors, and different processors execute different subsets of instructions.

[0189] Thus, in at least one embodiment, a computer system is configured to implement one or more services that individually or collectively perform the operations of the processes described herein, and such a computer system is configured with applicable hardware and / or software that enables the implementation of the operations. In addition, a computer system that implements at least one embodiment of the present disclosure is a single device, and in another embodiment is a distributed computer system that includes multiple devices that operate in different ways, so that the distributed computer system performs the operations described herein, and so that a single device does not perform all operations.

[0190] The use of any and all examples or exemplary language (e.g., "such as") provided herein is intended only to better illustrate embodiments of the present disclosure and does not limit the scope of the disclosure unless otherwise required. No language in the specification should be construed as indicating that any non-claimed element is essential to practicing the disclosure.

[0191] All references, including publications, patent applications, and patents, cited herein are hereby incorporated by reference to the same extent as if each reference were individually and specifically indicated to be incorporated by reference and were set forth in its entirety herein.

[0192] In the specification and claims, the terms "coupled" and "connected," as well as their derivatives, may be used. It should be understood that these terms may not be intended as synonyms for each other. On the contrary, in specific examples, "connected" or "coupled" may be used to indicate that two or more elements are in direct or indirect physical or electrical contact with each other. "Coupled" may also mean that two or more elements are not in direct contact with each other, but still cooperate or interact with each other.

[0193] Unless explicitly stated otherwise, it is understood that throughout the specification, terms such as "processing", "calculating", "calculating", "determining", etc. refer to the actions and / or processes of a computer or computing system or similar electronic computing device that processes and / or converts data represented as physical quantities (e.g., electronic) in the registers and / or memories of the computing system into other data similarly represented as physical quantities in the memories, registers or other such information storage, transmission or display devices of the computing system.

[0194] In a similar manner, the term "processor" may refer to any device or part of a memory that processes electronic data from registers and / or memory and converts the electronic data into other electronic data that can be stored in registers and / or memory. As a non-limiting example, a "processor" may be a CPU or a GPU. A "computing platform" may include one or more processors. As used herein, a "software" process may include, for example, software and / or hardware entities that perform work over time, such as tasks, threads, and intelligent agents. Similarly, each process may refer to multiple processes to execute instructions sequentially or in parallel, continuously or intermittently. The terms "system" and "method" may be used interchangeably herein, as long as a system may embody one or more methods, and a method may be considered a system.

[0195] In this document, reference may be made to obtaining, acquiring, receiving or inputting analog or digital data into a subsystem, a computer system or a computer-implemented machine. It is possible to obtain, acquire, receive or input analog and digital data in a variety of ways, such as by receiving data as a parameter of a function call or a call to an application programming interface. In some implementations, the process of obtaining, acquiring, receiving or inputting analog or digital data can be accomplished by transmitting data via a serial or parallel interface. In another implementation, the process of obtaining, acquiring, receiving or inputting analog or digital data can be accomplished by transmitting data from a providing entity to an acquiring entity via a computer network. It is also possible to reference to providing, outputting, transmitting, sending or presenting analog or digital data. In various examples, the process of providing, outputting, transmitting, sending or presenting analog or digital data can be accomplished by transmitting data as an input or output parameter of a function call, an application programming interface or an inter-process communication mechanism.

[0196] Although the above discussion sets forth example implementations of the described techniques, other architectures may be used to implement the described functionality and are intended to fall within the scope of the present disclosure. In addition, although specific responsibilities are defined above for discussion purposes, various functions and responsibilities may be allocated and divided in different ways, depending on the circumstances.

[0197] Furthermore, although the subject matter has been described in language specific to structural features and / or methodological acts, it should be understood that the subject matter claimed in the appended claims is not necessarily limited to the specific features or acts described. Rather, the specific features and acts are disclosed as exemplary forms of implementing the claims.

Claims

1. A processor, comprising: One or more circuits for: Identify components installed within the platform; determining a capability classification for the component based on one or more component attributes; generating an index entry for the component, the index entry comprising at least an identifier and the capability classification; Determining that the described competency classification is not fully adequate; populating one or more supplemental update entries for the component; as well as The index entry and the one or more supplemental update entries for the component are stored.

2. The processor of claim 1, wherein the capability classification comprises at least one of partially sufficient, solicited, fully dependent, or virtual.

3. The processor of claim 1 , wherein the one or more circuits are further configured to: receiving a firmware update request for the component; determining the capability classification using the index entry; Based at least on the capability classification, determining that the firmware update will use the one or more supplemental update items; and The firmware update is caused to be performed using the one or more supplemental update entries.

4. The processor of claim 1, wherein the capability classification is associated with a capability on a component for performing at least one of a protection operation, a detection operation, or a recovery operation.

5. The processor of claim 1 , wherein the one or more circuits are further configured to: receiving a firmware update request for the component; determining that the capability classification corresponds to a partially sufficient component; and Update information is retrieved from one or more external component storage locations.

6. The processor of claim 1 , wherein the one or more circuits are further configured to: receiving a firmware update request for the component; determining that the capability classification corresponds to a requesting component; verifying the firmware update using one or more off-component services; and Update information is retrieved from one or more external component storage locations.

7. The processor of claim 1 , wherein the one or more circuits are further configured to: receiving updated parameters for the component from an authority associated with the platform; authenticating the authority; and The index entry is updated based on the update parameter for the component.

8. The processor of claim 7, wherein the authority is at least one of a manufacturer of the platform or an owner of the platform.

9. The processor of claim 1, wherein the processor is included in at least one of: A system for performing simulation operations; Systems for performing simulated operations to test or validate autonomous machine applications; Systems for performing digital twin operations; A system for performing light transport simulations; Systems for rendering graphical output; Systems for performing deep learning operations; Systems implemented using edge devices; Systems for generating or presenting virtual reality (VR) content; Systems for generating or presenting augmented reality (AR) content; Systems for generating or presenting mixed reality (MR) content; A system comprising one or more virtual machines VM; A system for performing operations of a conversational AI application; A system for performing operations of a generative AI application; A system for performing operations using a language model; A system for performing one or more operations of generating content using a large language model (LLM); A system implemented at least in part in a data center; A system for performing hardware testing using simulation; A system for performing one or more operations of generating content using a language model; Systems for synthetic data generation; A collaborative content creation platform for 3D assets; or A system implemented at least in part using cloud computing resources.

10. A computer-implemented method comprising: receiving a firmware FW update request associated with a component forming at least part of a platform; determining one or more capabilities associated with the component; determining supplemental update information for the platform component based at least on the one or more capabilities; obtaining the supplemental update information based at least on an identifier associated with the component; as well as The FW update is caused to be installed for the component using at least the supplemental update information.

11. The computer-implemented method of claim 10, further comprising: receiving a second FW update request for a second component forming at least part of the platform; determining one or more second capabilities associated with the second component; as well as determining that the one or more second capabilities define the second component as a fully sufficient component; as well as The FW update is caused to be installed for the component.

12. The computer-implemented method of claim 10, wherein the one or more capabilities are associated with at least a protection operation, a detection operation, or a recovery operation.

13. The computer-implemented method of claim 10, further comprising: A capability level for the component is defined, the capability level comprising at least one of fully sufficient, partially sufficient, solicited, fully dependent, and virtual.

14. The computer-implemented method of claim 10, further comprising: receiving update parameters for components of the platform from an authority associated with the platform; Authenticating the said authority; as well as An index entry corresponding to the platform component is updated based on the update parameter for the component.

15. The computer-implemented method of claim 10, further comprising: identifying new components associated with the platform; receiving authentication information associated with the new component; as well as An index entry is generated for the new component, wherein the index entry at least includes an identifier and a new component capability classification.

16. A system comprising: One or more processing units are configured to determine a component capability level in response to receiving an update request for a component, and obtain supplemental update information for performing an update based at least on the component capability level and index information of the component.

17. The system of claim 16, wherein the component capability level corresponds to an ability of the component to perform at least one of a protection operation, a detection operation, or a recovery operation using resources on the component.

18. The system of claim 16, wherein the component capability level corresponds to one of fully sufficient, partially sufficient, requested, fully dependent, and virtual.

19. The system of claim 16, wherein the index information is populated by a platform manufacturer and rooted in an elastic engine of a platform including the component.

20. The system of claim 16, wherein the supplemental update information includes at least one of a verification key, a measurement operation, or an off-component storage location.

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