Protocol calculation method, engine, computer equipment, storage medium and program product

Abstract

The invention relates to the technical field of microprocessor structures, and discloses a protocol calculation method, an engine, computer equipment, a storage medium and a program product.The protocol calculation engine comprises an instruction receiving module used for receiving a protocol instruction sent by a core; the instruction splitting module is used for splitting the protocol instruction into a read request and a write request; the read request processing module is used for reading an operand corresponding to the read request from the draft book storage module; and the write request processing module is used for executing protocol calculation on the operand according to the protocol instruction to obtain a calculation result, and writing the calculation result into a draft book for storage. The protocol calculation engine specially used for protocol calculation is designed, and the protocol calculation instruction is executed asynchronously, so that compared with a traditional VPU form, the occupied chip area is small, the calculation efficiency is high, judgment is completed through answer words, and programming is convenient.

Description

Technical Field

[0001] The present invention relates to the technical field of microprocessor structure, and in particular to a protocol calculation method, an engine, a computer device, a storage medium and a program product. Background Art

[0002] Reduction is a type of parallel algorithm that uses a binary symbol associative operator to generate a result for N incoming data. Such operations include minimum, maximum, sum, logical AND / OR, etc. In order to improve the processing efficiency of the reduction algorithm, at present, the reduction algorithm is generally implemented through a vector processor (Vector Process Unit, VPU). Vector processors use vectors as the basic processing unit. Compared with scalar processors, vector processors have larger data processing bandwidth and can usually achieve dozens of times performance improvement.

[0003] VPU needs to support multiple vector calculation methods and occupies a huge area. In scenarios where only protocol calculations are required, most hardware resources are idle and have low utilization rates. Summary of the invention

[0004] In view of this, the present invention provides a reduction calculation method, engine, computer device, storage medium and program product to solve the problem that the current reduction algorithm implemented by vector processor occupies a large area and has low utilization efficiency.

[0005] In a first aspect, the present invention provides a protocol calculation engine, the protocol calculation engine comprising:

[0006] An instruction receiving module, used for receiving protocol instructions sent by the core;

[0007] An instruction disassembly module is used to split the protocol instruction into a read request and a write request;

[0008] A read request processing module, used for reading the operand corresponding to the read request from the draft book storage;

[0009] A write request processing module is used to perform a reduction calculation on the operand according to the reduction instruction to obtain a calculation result, and write the calculation result into the draft book.

[0010] The protocol computing engine provided in the embodiment of the present invention not only realizes the modularization of functions by dividing the protocol computing engine into an instruction receiving module, an instruction disassembly module, a read request processing module and a write request processing module, but also the protocol engine performs pipeline operations on the read and write operations of the draft book storage, and can realize high-bandwidth computing according to the data path bit width. Compared with the traditional VPU, this asynchronous execution of protocol instructions occupies a small chip area and has higher computing efficiency.

[0011] In an optional implementation, the write request processing module further includes:

[0012] Internal storage submodule, used to store operands.

[0013] The protocol computing engine provided by the embodiment of the present invention can make the operands accessed and processed by the write request processing module more quickly by storing the operands in the internal storage submodule, thereby improving the computing efficiency of the entire protocol computing engine. In addition, since the protocol engine's read and write operations on the draft book storage are pipeline operations, the internal storage submodule can serve as an intermediate storage layer to support such pipeline operations, thereby realizing high-bandwidth computing.

[0014] In a second aspect, the present invention provides an AI chip computing system, the AI ​​chip computing system comprising the protocol computing engine of the first aspect, and the AI ​​chip computing system further comprising:

[0015] A draft book storage module, used for receiving a read request sent by the protocol calculation engine, and returning an operand corresponding to the read request to the protocol calculation engine;

[0016] The core module is used to send the protocol instruction to the protocol computing engine and send the direct memory access instruction to the direct memory access engine module;

[0017] The direct memory access engine module moves the data for executing the protocol calculation from the external storage to the scratch book storage module, or moves the data of the scratch book storage module to the external storage according to the data transfer instruction initiated by the core module.

[0018] The AI ​​chip computing system provided by the embodiment of the present invention realizes efficient processing of protocol instructions by integrating a protocol computing engine. At the same time, the draft storage module, as an intermediate storage layer, can quickly store and return read requests and operands required by the protocol computing engine, thereby reducing data access delays. The introduction of the direct memory access engine module enables data to be efficiently transferred between the core module, external storage and the draft storage module, further improving data processing efficiency.

[0019] In an optional implementation, the draft book storage module is also used to store calculation results obtained by the specification calculation engine executing the specification calculation.

[0020] The AI ​​chip computing system provided by the embodiment of the present invention can significantly reduce the dependence on and access frequency of external storage when the draft book storage module simultaneously stores the operands and calculation results corresponding to the read request. That is, the operands and calculation result data can be directly stored and obtained in the draft book storage module without the need to immediately access the external storage each time, thereby saving time and resources for data transfer.

[0021] In a third aspect, the present invention provides a reduced computing method, which is applied to the AI ​​chip computing system of the second aspect, and the method is executed by a reduced computing engine, and the method includes:

[0022] Receive protocol instructions sent by the core module;

[0023] Decompose the protocol instructions into read requests and write requests;

[0024] Based on the read request, an operand corresponding to the read request is read from the scratch book storage;

[0025] Perform the specified calculation on the operands to obtain the calculation result.

[0026] The reduced calculation method provided by the embodiment of the present invention receives the reduced instruction sent by the core module through the reduced calculation engine, decomposes it into a read request and a write request, and sends the read request to the draft storage module for storage, and simultaneously reads the corresponding operand from the external storage to reduce the delay of data access, and finally performs reduced calculation on the operand to obtain the calculation result. When the reduced calculation engine is used to execute this algorithm, high-bandwidth calculation and pipeline operation are supported, so the execution efficiency is high and the chip area occupied is smaller.

[0027] In an optional implementation, decomposing the protocol instruction into a read request and a write request includes:

[0028] Identify the operation type, operand address, and result address in the specification instruction;

[0029] Based on the operation type, operand address and result address, the protocol instruction is divided into a read request and a write request; the read request contains the operand address; the write request contains the operation type and result address.

[0030] The reduced computing method provided by an embodiment of the present invention decomposes the reduced instruction into a read request and a write request, wherein the read request focuses on retrieving the required operand address from the storage, while the write request focuses on storing the calculation result at the specified result address. This decomposition allows each request to be processed independently, thereby improving the parallel processing capability and processing efficiency of the entire system.

[0031] In an optional implementation, the operands are subjected to a reduction calculation to obtain a calculation result, including:

[0032] Store operands;

[0033] Perform the specified calculation on the operands to obtain the calculation result.

[0034] The protocol calculation method provided in the embodiment of the present invention helps to reduce memory access latency by first storing the operands in a scratchpad storage module and reading them to an internal storage submodule before performing subsequent protocol calculations. The internal storage submodule can serve as an intermediate storage layer to support this pipeline operation, thereby achieving high-bandwidth calculations.

[0035] In an optional implementation, performing reduction calculation on the operands to obtain a calculation result further includes:

[0036] The calculation results are written into the scratchpad storage module for storage through the write request logic.

[0037] The reduced calculation method provided by the embodiment of the present invention can avoid frequent interaction with external storage by directly writing the calculation results into the scratchpad storage module, thereby reducing data access delay. During the calculation process, both the operands and the calculation results are stored in the scratchpad storage module, which can form a smoother data flow. This data flow helps to reduce the number of data movements and copies, thereby reducing the overhead in the calculation process.

[0038] In a fourth aspect, the present invention provides a computer device, comprising: a memory and a processor, the memory and the processor being communicatively connected to each other, the memory storing computer instructions, and the processor executing the reduction computing method of the third aspect or any corresponding embodiment thereof by executing the computer instructions.

[0039] In a fifth aspect, the present invention provides a computer-readable storage medium having computer instructions stored thereon, the computer instructions being used to enable a computer to execute the reduction calculation method of the third aspect or any corresponding embodiment thereof. BRIEF DESCRIPTION OF THE DRAWINGS

[0040] In order to more clearly illustrate the specific implementation methods of the present invention or the technical solutions in the prior art, the drawings required for use in the specific implementation methods or the description of the prior art will be briefly introduced below. Obviously, the drawings described below are some implementation methods of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying creative work.

[0041] Figure 1 is a schematic diagram of the structure of a protocol calculation engine according to an embodiment of the present invention;

[0042] Figure 2 is a schematic diagram of the architecture of an AI chip computing system according to an embodiment of the present invention;

[0043] Figure 3 is a flowchart of a reduction calculation method according to an embodiment of the present invention;

[0044] Figure 4 is an interactive schematic diagram of a reduced calculation method according to an embodiment of the present invention;

[0045] Figure 5 It is a schematic diagram of the hardware structure of a computer device according to an embodiment of the present invention. DETAILED DESCRIPTION

[0046] In order to make the purpose, technical solution and advantages of the embodiments of the present invention clearer, the technical solution in the embodiments of the present invention will be clearly and completely described below in conjunction with the drawings in the embodiments of the present invention. Obviously, the described embodiments are part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative work are within the scope of protection of the present invention.

[0047] A reduction is a type of parallel algorithm that uses a binary symbolic associative operator to generate a result for N data points. This type of operation includes minimum, maximum, sum, logical AND / OR, etc.

[0048] In order to improve the processing efficiency of the reduction algorithm, the reduction algorithm is generally implemented through a vector processor (VPU). Vector processors use vectors as basic processing units. Compared with scalar processors, vector processors have larger data processing bandwidth and can usually achieve dozens of times performance improvement.

[0049] VPU needs to support multiple vector calculation methods, so its internal hardware design is relatively complex and occupies a large physical area on the chip, which increases the cost and production difficulty of the chip. In scenarios where only reduction calculations are required, most of the VPU's hardware resources are idle and have low utilization. In addition, when performing reduction calculations with large amounts of data, in order to maximize the performance of the VPU, the VPU needs to rely on programmers to schedule instructions to ensure that the VPU pipeline can run efficiently. Taking addition as an example, the VPU keeps executing instructions such as vload\vadd\vstore, which is inefficient.

[0050] In this embodiment, a protocol calculation engine is provided, and the protocol calculation engine structure is as follows: Figure 1 As shown, the protocol engine includes:

[0051] An instruction receiving module, used for receiving protocol instructions sent by the core;

[0052] An instruction disassembly module is used to split the protocol instruction into a read request and a write request;

[0053] A read request processing module, used for reading the operand corresponding to the read request from the draft book storage;

[0054] A write request processing module is used to perform a reduction calculation on the operand according to the reduction instruction to obtain a calculation result, and write the calculation result into the draft book.

[0055] like Figure 1 As shown, the instruction receiving module is used to receive the protocol instruction sent by the core, and the instruction disassembly module is used to split the protocol instruction into a read request and a write request. When the protocol engine receives the protocol instruction sent by the core, it parses the protocol instruction according to the content of the received protocol instruction to obtain a series of read and write requests. The read request processing module will read the protocol operand corresponding to the read request from the draft book storage and carried by the external storage according to the read request; the write request processing module includes a control unit and an operation unit, and the write request is stored in the control unit. When operands A and B are read, the control unit activates the operation unit.

[0056] The types of reduction operations supported by the reduction calculation engine include summation, maximum value, and minimum value, as shown in Table 1:

[0057] Table 1: Operation types of the specification calculation engine

[0058] Supported operation types reduce_add reduce_max reduce_min

[0059] The data types supported by the protocol engine are shown in Table 2:

[0060] Table 2: Data types supported by the protocol engine

[0061]

[0062]

[0063] The operation unit calculates the data types and the specified operation types of data A and data B, performs calculations on data A and B, and obtains calculation results.

[0064] In some optional implementations, the write request processing module further includes:

[0065] Internal storage submodule, used to store operands.

[0066] When the read request operation module obtains the operand data A and B corresponding to the read request, it stores the operands A and B in the internal storage sub-module, and notifies the control unit to activate the operation unit. The operation unit reads data A and data B from the internal storage, and performs calculations on data A and B according to the data type and the protocol operation type to obtain the calculation results.

[0067] The embodiment of the present invention also provides an AI chip computing system including the above-mentioned protocol computing engine, and the architecture diagram of the system is as follows: Figure 2As shown, the AI ​​chip computing system also includes:

[0068] The draft book storage module is used to store the read request sent by the protocol calculation engine and return the operand corresponding to the read request to the protocol calculation engine;

[0069] The core module is used to send the protocol instruction to the protocol computing engine and send the direct memory access instruction to the direct memory access engine module;

[0070] The direct memory access engine module moves the data for executing the protocol calculation from the external storage to the scratch book storage module, or moves the data of the scratch book storage module to the external storage according to the data transfer instruction initiated by the core module.

[0071] The AI ​​chip computing system consists of a core, a protocol computing engine, a scratchpad storage module, and a direct memory access engine module. Specifically, the core is responsible for generating and sending direct memory access instructions to the external direct memory access engine module, instructing it to read data from external storage (such as DDR memory) to the scratchpad storage, or write data from the scratchpad storage to the external storage. The protocol computing engine load executes protocol asynchronous instructions, such as accumulation, maximum value, minimum value, etc. The scratchpad storage is an on-chip SRAM that provides fast data access for the core and the protocol computing engine, and is used to temporarily store data read from external storage; the direct memory access engine module reads data from external storage (such as DDR memory) to the scratchpad storage, or writes data in the scratchpad storage back to the external storage according to the core's instructions.

[0072] In some optional implementations, the draft book storage module is also used to store calculation results obtained by the specification calculation engine executing the specification calculation.

[0073] The write request processing module performs the reduction calculation on data A and data B to obtain the reduction result, and writes the calculation result into the draft storage module for storage according to the calculation data volume and calculation result address corresponding to the write request. The core module can update the status information of the draft storage module to reflect the new storage location and the used storage space.

[0074] According to an embodiment of the present invention, a reduction calculation method embodiment is also provided. It should be noted that the steps shown in the flowchart of the accompanying drawings can be executed in a computer system such as a set of computer executable instructions, and although the logical order is shown in the flowchart, in some cases, the steps shown or described can be executed in an order different from that shown here.

[0075] In this embodiment, a reduction calculation method is provided, which is applied to the above-mentioned AI chip computing system. The method is executed by a reduction calculation engine. Figure 3is a flow chart of a reduced calculation method according to an embodiment of the present invention. Figure 3 As shown, the process includes the following steps:

[0076] Step S301, receiving a protocol instruction sent by a core module.

[0077] Specifically, a reduction is a type of parallel algorithm that uses a binary symbolic associative operator to generate a result for N data inputs. Such operations include minimum, maximum, sum, logical AND / OR, etc.

[0078] Furthermore, the contents of the reduced calculation instructions are shown in Table 3 below:

[0079] Table 3: Contents of the calculation instructions

[0080]

[0081] Furthermore, the protocol computing engine has an instruction interface connected to the core module, which continuously monitors the communication bus or instruction queue from the core module and receives a number of protocol instructions sent from the core module.

[0082] Step S302, decomposing the protocol instruction into a read request and a write request.

[0083] Specifically, after receiving the protocol instruction from the core module, the protocol calculation engine parses the protocol instruction. The parsing process includes identifying the operation code (opcode) of the instruction, which is used to indicate the specific protocol operation corresponding to the protocol instruction, such as summation, maximum value, minimum value, etc.

[0084] Furthermore, based on the type of protocol instruction and the operation to be performed, the protocol calculation engine determines the type of read and write request that needs to be generated, that is, for operations that require reading operands, a read request is generated; for operations that require storing calculation results, a write request is generated.

[0085] In some optional implementations, the above step S302 includes:

[0086] Identify the operation type, operand address, and result address in the specification instruction;

[0087] Based on the operation type, operand address and result address, the protocol instruction is divided into a read request and a write request; the read request contains the operand address; the write request contains the operation type and result address.

[0088] Specifically, the protocol calculation engine identifies the address of the operand from the protocol instruction, and the address of the operand is used for the physical address of the corresponding operand stored in the standard scratchpad storage module or in the external storage.

[0089] Optionally, for each operand to be read, the specification calculation engine generates a read request, which includes the address of the operand, the amount of data expected to be read, and possible read priority.

[0090] Furthermore, the protocol calculation engine identifies the operation type and the result address from the protocol instruction, and generates a write request accordingly. Optionally, the write request also includes the data size and possible write priority.

[0091] Step S303, reading the operand corresponding to the read request from the draft book storage based on the read request.

[0092] Specifically, a read request is sent to the scratchpad storage module through an internal communication bus or interface, and the read request includes information such as the address and data size of the operation data to be read.

[0093] Further, the protocol calculation engine reads the operand corresponding to the read request from the scratchpad storage module.

[0094] Optionally, the draft book storage module needs to obtain data from the external storage based on the data address in advance.

[0095] Step S304, performing reduction calculation on the operands to obtain calculation results.

[0096] Specifically, first, operands are read from the scratchpad storage module, and reduction calculations are performed on the operands according to reduction instructions to obtain calculation results, such as summing, finding the maximum value, and finding the minimum value.

[0097] In some optional implementations, the above step S304 includes:

[0098] Store operands;

[0099] Perform the specified calculation on the operands to obtain the calculation result.

[0100] Before performing the reduction calculation, the operands are loaded from the scratchpad storage module storage or external storage into the internal cache or registers of the reduction calculation engine. Especially when the reduction calculation requires multiple accesses to the operands, or if the operands are large and cannot be loaded into the calculation unit at one time, storing them in the internal cache for subsequent use can improve the access efficiency of the operands.

[0101] In some optional implementations, the above step S304 includes:

[0102] The calculation results are written into the scratchpad storage module for storage through the write request logic.

[0103] The reduction operation is performed according to the operation type and data type, and the result is written back to the scratchpad storage. After the reduction instruction is executed, the answer word can be optionally written to the scratchpad storage according to the answer word type. After that, the core initiates the direct memory access operation again, and the direct memory access engine module moves the result of the reduction calculation from the scratchpad storage to the external storage.

[0104] In summary, the reduction computing method provided by the present invention realizes efficient data processing by designing a dedicated SIMD engine, that is, a reduction computing engine to specifically perform reduction computing, so as to realize asynchronous execution of reduction instructions. Compared with the traditional mode of performing reduction algorithms through vector processors, it reduces the chip area occupied and provides support for the development and application of AI chip computing systems.

[0105] For more information, see Figure 4 Interaction diagram, first, the direct memory access operation initiated by the core module, the direct memory access engine module will move the data to be executed by the protocol calculation from the external storage to the internal draft storage for preparation, after the data is ready. The core module sends the protocol instruction to the protocol calculation engine, and the protocol calculation engine decomposes several protocol instructions into a series of read requests and write requests by identifying the operation type, operand address and result address of the protocol instruction through the instruction disassembly module in the protocol calculation engine, where the read request includes the operand address and operand size, and the write instruction includes the operation type and result address.

[0106] Optionally, when the protocol calculation engine executes multiple protocol instructions at the same time, these instructions can be completed sequentially or in a preset order. When executed sequentially, by configuring whether to write a reply word, such as CMD0, CMD1, CMD2 and CMD3, when the reply word of CMD3 determines that the execution is completed, it indicates that CMD0-CMD2 are also executed;

[0107] The specification instructions can also be completed in a preset order, which can be maintained by the Barrier mechanism. Barrier is a synchronization mechanism that prevents all instructions before it from continuing to execute the next instruction before executing the Barrier, that is, the instruction after the Barrier. For example, in CMD0, CMD1, CMD2, BARRIER, CMD3 and CMD4, CMD0-2 are partially executed out of order, and CMD3-4 are partially completed out of order, but because of the barrier, CMD0-2 takes precedence over CMD3-4 to complete execution in the preset instruction execution order.

[0108] After the read request processing module sends the read request to the draft book storage module, it reads several groups of operands corresponding to the read request to efficiently access the required data, thereby reducing the delay in data access. When the operands are returned, the protocol calculation engine caches these data in its internal registers or cache, that is, the internal storage sub-module, to reduce the number of subsequent accesses to the draft book storage module.

[0109] The reduction calculation engine enters the calculation stage and performs reduction operations on the operands according to the operation type and data type in the write request, including summation, maximum value or minimum value. At the same time, since the reduction calculation engine's read and write operations on the draft book storage are all pipeline operations, the calculation bandwidth is further improved, allowing data to be processed and calculated faster.

[0110] After the calculation is completed, the protocol calculation engine will selectively write the calculation results back to the scratchpad storage module storage according to the answer word type. Finally, the core module initiates the direct memory access operation again, and the direct memory access engine module moves the result of the protocol calculation from the scratchpad storage module storage to the external storage.

[0111] The embodiment of the present invention also provides a computer device, see Figure 5 , Figure 5 is a schematic diagram of the structure of a computer device provided by an optional embodiment of the present invention, such as Figure 5 As shown, the computer device includes: one or more processors 10, a memory 20, and interfaces for connecting various components, including high-speed interfaces and low-speed interfaces. Various components are connected to each other using different buses for communication, and can be installed on a common mainboard or installed in other ways as needed. The processor can process the instructions executed in the computer device, including instructions stored in or on the memory to display the graphical information of the GUI on an external input / output device (such as, a display device coupled to the interface). In some optional embodiments, if necessary, multiple processors and / or multiple buses can be used together with multiple memories and multiple memories. Similarly, multiple computer devices can be connected, and each device provides some necessary operations (for example, as a server array, a group of blade servers, or a multi-processor system). Figure 5 A processor 10 is taken as an example.

[0112] Optionally, the processor 10 may also be the AI ​​chip involved in the present application. When the processor 10 is an AI chip, the computer device may include multiple AI chips with the same structure, wherein the address space of each of the AI ​​chips is continuous and unified, and any two of the AI ​​chips are connected through a communication link, thereby realizing the relevant functions involved in the embodiments of the present application.

[0113] Figure 5A processor 10 is taken as an example.

[0114] The processor 10 may be a central processing unit, a network processor or a combination thereof. The processor 10 may further include a hardware chip. The hardware chip may be a dedicated integrated circuit, a programmable logic device or a combination thereof. The programmable logic device may be a complex programmable logic device, a field programmable gate array, a general purpose array logic or any combination thereof.

[0115] The memory 20 stores instructions executable by at least one processor 10, so that the at least one processor 10 executes the method shown in the above embodiment.

[0116] The memory 20 may include a program storage area and a data storage area, wherein the program storage area may store an operating system, an application required for at least one function; the data storage area may store data created according to the use of the computer device, etc. In addition, the memory 20 may include a high-speed random access memory, and may also include a non-transient memory, such as at least one disk storage device, a flash memory device, or other non-transient solid-state storage device. In some optional embodiments, the memory 20 may optionally include a memory remotely arranged relative to the processor 10, and these remote memories may be connected to the computer device via a network. Examples of the above-mentioned network include, but are not limited to, the Internet, an intranet, a local area network, a mobile communication network, and combinations thereof.

[0117] The memory 20 may include a volatile memory, such as a random access memory; the memory may also include a non-volatile memory, such as a flash memory, a hard disk or a solid state drive; the memory 20 may also include a combination of the above types of memory.

[0118] The computer device also includes an input device 30 and an output device 40. The processor 10, the memory 20, the input device 30 and the output device 40 may be connected via a bus or other means. Figure 5 The example of connecting through bus is taken in the following.

[0119] The input device 30 can receive input digital or character information, and generate key signal input related to the user settings and function control of the computer device, such as a touch screen, a keypad, a mouse, a track pad, a touch pad, an indicator bar, one or more mouse buttons, a trackball, a joystick, etc. The output device 40 may include a display device, an auxiliary lighting device (e.g., an LED) and a tactile feedback device (e.g., a vibration motor), etc. The above-mentioned display device includes but is not limited to a liquid crystal display, a light emitting diode, a display and a plasma display. In some optional embodiments, the display device can be a touch screen.

[0120] The embodiment of the present invention also provides a computer-readable storage medium. The method according to the embodiment of the present invention can be implemented in hardware, firmware, or can be implemented as a computer code that can be recorded in a storage medium, or can be implemented as a computer code that is originally stored in a remote storage medium or a non-temporary machine-readable storage medium and will be stored in a local storage medium through a network download, so that the method described herein can be stored in such software processing on a storage medium using a general-purpose computer, a dedicated processor, or programmable or dedicated hardware. Among them, the storage medium can be a magnetic disk, an optical disk, a read-only storage memory, a random access memory, a flash memory, a hard disk or a solid-state hard disk, etc.; further, the storage medium can also include a combination of the above types of memories. It can be understood that a computer, a processor, a microprocessor controller, or programmable hardware includes a storage component that can store or receive software or computer code. When the software or computer code is accessed and executed by a computer, a processor, or hardware, the method shown in the above embodiment is implemented.

[0121] A part of the present invention may be applied as a computer program product, such as a computer program instruction, which, when executed by a computer, can call or provide the method and / or technical solution according to the present invention through the operation of the computer. Those skilled in the art should understand that the existence of the computer program instruction in a computer-readable medium includes, but is not limited to, a source file, an executable file, an installation package file, etc., and accordingly, the way in which the computer program instruction is executed by the computer includes, but is not limited to: the computer directly executes the instruction, or the computer compiles the instruction and then executes the corresponding compiled program, or the computer reads and executes the instruction, or the computer reads and installs the instruction and then executes the corresponding installed program. Here, the computer-readable medium may be any available computer-readable storage medium or communication medium accessible to the computer.

[0122] Although the embodiments of the present invention have been described in conjunction with the accompanying drawings, those skilled in the art may make various modifications and variations without departing from the spirit and scope of the present invention, and such modifications and variations are all within the scope defined by the appended claims.

Claims

1. A protocol computing engine, characterized in that: The protocol calculation engine includes: An instruction receiving module, used for receiving protocol instructions sent by the core; An instruction disassembly module, used for splitting the protocol instruction into a read request and a write request; A read request processing module, used for reading an operand corresponding to the read request from the draft book storage; A write request processing module is used to perform a reduction calculation on the operand according to the reduction instruction to obtain a calculation result, and write the calculation result into the draft book storage.

2. The engine according to claim 1, characterized in that The write request processing module also includes: The internal storage submodule is used to store the operands.

3. An AI chip computing system, characterized in that: The AI ​​chip computing system comprises the protocol computing engine according to claim 1 or 2, and the AI ​​chip computing system further comprises: A draft book storage module, used for receiving a read request sent by the protocol calculation engine, and returning an operand corresponding to the read request to the protocol calculation engine; A core module, used for sending protocol instructions to the protocol computing engine and sending direct memory access instructions to the direct memory access engine module; The direct memory access engine module moves the data for executing the protocol calculation from the external storage to the scratch book storage module, or moves the data of the scratch book storage module to the external storage according to the data transfer instruction initiated by the core module.

4. The system according to claim 3, characterized in that The draft book storage module is also used to store the calculation results obtained by the specification calculation engine executing the specification calculation.

5. A reduced calculation method, characterized in that: Applied to the AI ​​chip computing system of claim 3 or 4, the method is executed by a reduced computing engine, and the method includes: Receive protocol instructions sent by the core module; Decomposing the protocol instruction into a read request and a write request; Reading an operand corresponding to the read request from a scratch pad storage based on the read request; Perform a reduction calculation on the operands to obtain a calculation result.

6. The method according to claim 5, characterized in that The step of decomposing the protocol instruction into a read request and a write request includes: Identify the operation type, operand address and result address in the specification instruction; Based on the operation type, operand address and result address, the reduced instruction is split into a read request and a write request; the read request includes the operand address; the write request includes the operation type and the result address.

7. The method according to claim 5, characterized in that The performing of the reduction calculation on the operand to obtain the calculation result includes: storing the operand; Perform a reduction calculation on the operands to obtain a calculation result.

8. The method according to claim 7, characterized in that The performing of the reduction calculation on the operand to obtain the calculation result also includes: The calculation result is written into the draft book storage module for storage through write request logic.

9. A computer device, characterized in that: include: A memory and a processor, wherein the memory and the processor are communicatively connected to each other, the memory stores computer instructions, and the processor executes the reduction calculation method according to any one of claims 5 to 8 by executing the computer instructions.

10. A computer-readable storage medium, characterized in that: The computer-readable storage medium stores computer instructions, and the computer instructions are used to enable a computer to execute the reduction calculation method according to any one of claims 5 to 8.

Images