Method and system for sending NVMe command queue and finishing queue processing
By designing hardware modules to automatically process NVMe command queues and completion queues, the problem of high CPU usage in NVMe high-speed applications is solved, and efficient command queue sending and completion queue processing is realized to meet the needs of NVMe high-speed applications.
Patent Information
- Application Number
- CN202411770019.4
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2024-12-04
- Publication Date
- 2025-03-28
AI Technical Summary
In NVMe high-speed applications, the prior art sends commands through software and processes the completion queue, resulting in high CPU usage and unable to quickly process other transactions.
Design a hardware module for NVMe command queue sending and completing queue processing, including command queue processing module, command queue to AXI module, completion queue processing module and completion queue to AXI module. This module automatically fills in the NVMe command queue, reads the completion queue results, and notifies the software to process when the command is completed abnormally.
Processing NVMe command queues and completion queues through hardware modules reduces software overhead, improves the performance of command queue sending and completing queue processing, meets the needs of NVMe high-speed application, and reduces CPU usage.
Smart Images
Figure CN119718981A_ABST
Abstract
Description
Technical Field
[0001] The invention relates to the field of computer technology, and in particular to a method and system for NVMe command queue sending and completion queue processing. Background Art
[0002] Usually, the host sends the command to be executed to the NVMe command queue (Submission Queue, SQ) through software. When the command is executed, the NVMe controller will generate an interrupt to notify the host, and the host software reads the completion queue (Completion Queue, CQ) to obtain the status of command execution. Sending commands and processing the completion queue through software consumes a lot of time, and it will occupy the CPU so that it cannot quickly process other transactions. In high-speed applications of NVMe, such as RAID engines, it is necessary to send commands to the NVMe controller frequently, and the CPU also needs to perform other important tasks. In order to speed up the command sending and completion result processing process, it is necessary to design corresponding hardware modules to implement this function. Summary of the invention
[0003] In view of this, the present invention aims to propose a method and system for NVMe command queue sending and completion queue processing to meet the NVMe high-speed application requirements and reduce CPU occupancy.
[0004] To achieve the above object, the technical solution created by the present invention is implemented as follows:
[0005] A method for NVMe command queue sending and completion queue processing, comprising the following steps:
[0006] Receive the written command and store it in the FIFO, write the command in the FIFO into the command queue and record the relevant information of the command, and then notify the NVMe controller; the relevant information of the command includes the command identifier;
[0007] When receiving the interrupt signal sent by the NVMe controller, read the completion queue, clear the interrupt source, parse the content of the completion queue item, and then notify the NVMe controller; if the status of the completion queue item is unsuccessful, the content of the completion queue item is recorded in the register and an interrupt is generated; if the status of the completion queue item is successful, the relevant information of the recorded corresponding command is deleted.
[0008] Further, the method for NVMe command queue sending and completion queue processing also includes:
[0009] When a preset number of command queue entries are written, write the command queue tailgate bell register of the NVMe controller to notify the NVMe controller;
[0010] When all the completion queue entries are parsed, the completion queue head doorbell register of the NVMe controller is written to notify the NVMe controller.
[0011] A system for NVMe command queue sending and completion queue processing, comprising:
[0012] The command queue processing module is used to write the sent command into the FIFO, record the relevant information of the command, and send the command in the FIFO to the command queue to AXI module for reading; it is also used to clear the relevant information of the corresponding command that has been recorded after receiving the relevant information from the completion queue processing module;
[0013] The command queue to AXI module is used to write all commands in the FIFO into the command queue when the FIFO in the command queue processing module is not empty; and maintain the command queue tail pointer and write it into the command queue tail doorbell register;
[0014] The completion queue processing module is used to clear the NVMe interrupt after receiving the interrupt signal of the NVMe controller, read the completion queue item and detect its status; it is also used to maintain the completion queue head pointer and write it into the completion queue head doorbell register; it is also used to notify the register group module to generate an interrupt when it is detected that the completion queue item status is not a success state, and record the completion queue item information;
[0015] The completion queue to AXI module is used to generate a corresponding AXI read request according to the read completion queue request sent by the completion queue processing module, and arbitrate the update completion queue head doorbell request and the clear NVMe interrupt request sent by the completion queue processing module and then convert them into AXI write requests;
[0016] The AXI arbitration module is used to arbitrate the AXI write requests from the command queue to the AXI module and the completion queue to the AXI module, and finally generate an AXI write request, and distribute the response to the corresponding module according to the ID of the AXI write response.
[0017] Further, the command queue to AXI module includes a first state machine; the first state machine includes S0 state, S1 state, S2 state, S3 state, S4 state and S5 state, wherein:
[0018] The S0 state is the initial state of the module, which is used to wait for the configuration register, and enter the S1 state after the register configuration in the register group is completed and the START register is 1;
[0019] The S1 state is used to wait for the FIFO in the command queue processing module to be non-empty, and then enter the S2 state; if a soft reset signal is received, it enters the S0 state;
[0020] The S2 state is used to generate an AXI AW request to the corresponding address in the command queue, and enter the S3 state after receiving the handshake signal;
[0021] The S3 state is used to generate an AXI W request, write the data in the FIFO into the command queue, and maintain the tail pointer of the command queue; after writing, it enters the S4 state; if a soft reset signal is received, it enters the S0 state;
[0022] The S4 state is used to initiate an AXI AW request to the command queue tail doorbell register, and enter the S5 state after receiving the handshake signal;
[0023] The S5 state is used to initiate an AXI W request, write the command queue tail pointer to the register, and enter the S1 state after receiving the handshake signal.
[0024] Further, the completion queue processing module includes a second state machine, a third state machine and a fourth state machine; wherein:
[0025] The second state machine is used to receive an NVMe controller interrupt, clear the interrupt, start the third state machine and determine the status of the completion queue item;
[0026] The third state machine is used to send N full-beat burst read completion queue requests to the completion queue to AXI module after receiving the notification from the second state machine;
[0027] The fourth state machine is used to generate a request for updating the doorbell of the completion queue head to the completion queue transfer AXI module after receiving the last beat of the read completion queue response and completing the analysis of the completion queue list item;
[0028] When a soft reset request is received, the third state machine can be reset only after the second state machine is reset. The reset of the fourth state machine has no order requirement with the other two state machines.
[0029] The second state machine includes state S6, state S7, state S8, state S9, state S10, state S11 and state S12, wherein:
[0030] The S6 state is the initial state, which is used to wait for register configuration. When the registers in the register group are configured, the START register is 1 and then enters the S7 state;
[0031] The S7 state is used to wait for the NVMe controller interrupt. When the interrupt is received, it enters the S8 state. If a soft reset signal is received, it enters the S6 state.
[0032] The S8 state is used to clear the NVMe controller interrupt and then enter the S9 state; if a soft reset signal is received, it enters the S6 state;
[0033] The S9 state is used to start the third state machine to send a read CQ request, and then enter the S10 state;
[0034] The S10 state is used to send the AXI R channel ready signal. After receiving a read response, if the address is aligned, it enters the S11 state, if it is not aligned, it enters the S12 state, and if all read responses have been received, it enters the S7 state;
[0035] The S11 state is used to detect the first completion queue item; if there is a second completion queue item behind it, enter the S12 state; otherwise, if the read data has not been received, enter the S10 state. If it has been received and the completion queue item is valid, it means that there are still completion queue items to be read, then enter the S9 state to send a new read request. If it has been received and the completion queue item is invalid, enter the S7 state.
[0036] The S12 state is responsible for detecting the second completion queue item; if the read data has not been received, the S10 state is entered; if it has been received and the completion queue item is valid, it means that there are completion queue items that need to be read, and the S9 state is entered to send a new read request; if it has been received and the completion queue item is invalid, the S7 state is entered;
[0037] The third state machine includes state S13, state S14 and state S15, wherein:
[0038] The S13 state is the initial state, which is used to wait for the software to configure the registers. When the registers in the register group are configured, the START register is 1 and then enters the S14 state.
[0039] The S14 state is used to wait for the notification of the second state machine, and jump to the S15 state after receiving the notification; if a soft reset signal is received, it enters the S13 state;
[0040] The S15 state is used to send N full-beat burst read completion queue requests to the completion queue to AXI module, and enter the S14 state after the sending is completed;
[0041] The fourth state machine includes state S16, state S17 and state S18, wherein:
[0042] The S16 state is the initial state, which is used to wait for the software to configure the registers. When the registers in the register group are configured, the START register is 1 and then enters the S17 state.
[0043] The S17 state is responsible for waiting for the second state machine to receive the last beat of a read completion queue response and complete the analysis of the completion queue item, and then jump to the S18 state; if a soft reset signal is received, it enters the S16 state;
[0044] The S18 state is responsible for maintaining the CQH pointer, initiating an update completion queue head doorbell request to the completion queue to AXI module, and then jumping to the S17 state.
[0045] Further, the completion queue to AXI module includes a fifth state machine, and the fifth state machine includes S19 state, S20 state, S21 state, S22 state, S23 state, S24 state and S25 state, wherein:
[0046] The S19 state is the initial state, which is used to wait for the software to configure the registers. When the registers in the register group are configured, the START register is 1 and then enters the S20 state.
[0047] The S20 state is used to wait for the completion queue processing module to initiate a write request; when receiving the update completion queue head doorbell request, it jumps to the S21 state, and when receiving the clear interrupt request, it jumps to the S23 state; if a soft reset signal is received, it enters the S19 state;
[0048] The S21 state is used to send an AXI AW request to update the doorbell of the queue head, and then jump to the S22 state;
[0049] The S22 state is used to send an AXI W request to update the queue head doorbell; if there is a new update queue head doorbell request at this time, jump to the S21 state; if there is a clear interrupt request at this time, jump to the S23 state; if there is no request, jump to the S20 state;
[0050] The S23 state is used to send an AXI AW request to clear the interrupt, and then jump to the S24 state;
[0051] The S24 state is used to send an AXI W request to clear the interrupt, and then jump to the S25 state;
[0052] The S25 state is used to wait for the corresponding AXI B response; if there is an update completion queue head doorbell request at this time, it jumps to the S21 state; if there is no request, it jumps to the S20 state.
[0053] Further, the system for NVMe command queue sending and completion queue processing also includes a register group module, which includes a plurality of registers and is used to give an error interrupt signal when the completion queue item status is a non-successful state;
[0054] An AHB asynchronous bridge module is also included, which is used to convert the AHB clock domain to the AXI clock domain to configure the register group module.
[0055] An electronic device comprises a processor and a memory connected to the processor for storing instructions executable by the processor, wherein the processor is used to execute the above-mentioned method and system for NVMe command queue sending and completion queue processing.
[0056] A server comprises at least one processor and a memory connected to the processor in communication, wherein the memory stores instructions executable by the at least one processor, and the instructions are executed by the processor so that the at least one processor executes the above-mentioned method and system for NVMe command queue sending and completion queue processing.
[0057] A computer-readable storage medium stores a computer program, which, when executed by a processor, implements the above-mentioned method and system for NVMe command queue sending and completion queue processing.
[0058] Compared with the prior art, the method and system for NVMe command queue sending and completion queue processing created by the present invention have the following advantages:
[0059] The present invention creates the method and system for NVMe command queue sending and completion queue processing. The software writes commands to this module, and this module automatically fills in the NVMe command queue and reads the results of the completion queue. When the command is completed abnormally, the software is notified to process it, so as to meet the NVMe high-speed application requirements and reduce CPU occupancy. BRIEF DESCRIPTION OF THE DRAWINGS
[0060] The drawings constituting part of the present invention are used to provide a further understanding of the present invention. The exemplary embodiments and descriptions of the present invention are used to explain the present invention and do not constitute an improper limitation on the present invention. In the drawings:
[0061] Figure 1 A structural block diagram of a system for sending NVMe command queues and completing queue processing according to an embodiment of the present invention is shown;
[0062] Figure 2 A structural block diagram of a first state machine in a command queue to AXI module of a system for sending NVMe command queues and completing queue processing according to an embodiment of the present invention is shown;
[0063] Figure 3 A structural block diagram of a second state machine, a third state machine, and a fourth state machine in a completion queue processing module of a system for sending NVMe command queues and completing queue processing according to an embodiment of the present invention is shown;
[0064] Figure 4A structural block diagram of the fifth state machine in the completion queue to AXI module of the system for NVMe command queue sending and completion queue processing described in an embodiment of the present invention is shown. DETAILED DESCRIPTION
[0065] It should be noted that, in the absence of conflict, the embodiments of the present invention and the features in the embodiments may be combined with each other.
[0066] The present invention will be described in detail below with reference to the accompanying drawings and in combination with embodiments.
[0067] The present invention provides a hardware module for sending NVMe command queues and completing queue processing, which meets the operation process specified by the NVMe protocol. After the software writes a command to this hardware module, the command will be sent to the NVMe command queue by this hardware module, and then the hardware module automatically reads the NVMe completion queue to obtain the command completion status, sends an interrupt to the CPU when the command execution fails, and writes the corresponding failure status to the corresponding register. This module reduces software overhead and improves the performance of sending command queues and processing completion queues.
[0068] This hardware module mainly has the following registers:
[0069]
[0070]
[0071]
[0072] The structural diagram of this module is as follows Figure 1 Except for the AHB interface which uses the AHB clock domain, the rest of the module uses the AXI clock domain.
[0073] The main working process of the hardware module of this patent invention is as follows:
[0074] (1) The command queue processing module receives the command written by the software through the CPU, records the command identifier (cid) and other related information, and writes the command into the NVMe command queue through the command queue to AXI module;
[0075] (2) After writing a certain number of command queue items, the command queue processing module writes the command queue tail doorbell (SQT) register of the NVMe controller through the command queue to AXI module to notify the controller;
[0076] (3) When the completion queue processing module receives an interrupt from the NVMe controller, it reads the NVMe completion queue through the completion queue transfer AXI module and parses the completion queue item content. If it is not a success state, the corresponding completion queue item content is recorded in the register group and an interrupt is generated; if it is a success state, the command queue processing module is notified to delete the command information of the corresponding command identifier previously recorded;
[0077] (4) After parsing all completion queue items, the completion queue processing module writes the completion queue head doorbell (CQH) register of the NVMe controller through the completion queue to AXI module to notify the controller.
[0078] The specific introduction of each module is as follows:
[0079] The AHB asynchronous bridge module is an AHB to AHB asynchronous bridge that converts the AHB clock domain to the AXI clock domain for configuring registers.
[0080] The register group module is a register group module, which contains all the above registers and is responsible for giving an error interrupt signal when the completion queue item status is not a success status.
[0081] The command queue processing module is responsible for processing the AXI slave interface, writing the sent commands into the FIFO, and recording the command identifier of the command. After receiving the command identifier from the completion queue processing module, the corresponding command identifier record is cleared. The commands in the FIFO in the command queue processing module will be read by the command queue to AXI module.
[0082] The command queue to AXI module is responsible for writing all commands in the FIFO into the command queue when the FIFO in the command queue processing module is not empty, and then maintaining the command queue tail pointer and writing it into the command queue tail doorbell register.
[0083] The command queue is converted to the state machine in the AXI module as follows Figure 2 As shown, the red arrow indicates the soft reset jump path. Command queue to state machine in AXI module:
[0084] The S0 state is the initial state of the module, waiting for the software to configure the register. When the registers in the register group are configured, the START register is 1 and then enters the S1 state.
[0085] The S1 state is responsible for waiting for the FIFO in the command queue processing module to be non-empty, and then enters the S2 state. If a soft reset signal is received, it enters the S0 state.
[0086] The S2 state is responsible for generating an AXI AW request to the corresponding address in the command queue, and enters the S3 state after receiving the handshake signal.
[0087] The S3 state is responsible for generating AXI W requests, writing the data in the FIFO into the command queue, and maintaining the tail pointer of the command queue. After writing, it enters the S4 state. If a soft reset signal is received, it enters the S0 state.
[0088] The S4 state is responsible for initiating an AXI AW request to the command queue tail doorbell register, and enters the S5 state after receiving the handshake signal.
[0089] The S5 state is responsible for initiating an AXI W request, writing the command queue tail pointer into the register, and entering the S1 state after receiving the handshake signal.
[0090] The completion queue processing module is responsible for clearing the NVMe interrupt after receiving the interrupt request from the NVMe controller, reading the completion queue item and detecting its status, maintaining the completion queue head pointer, and writing it into the completion queue head doorbell register. When it is detected that the completion queue item status is not a success status, the register group is notified to generate an interrupt and record the completion queue item information.
[0091] This module contains 3 state machines, such as Figure 3 As shown in the figure, the red arrow indicates the soft reset jump path. The state machine in the completion queue processing module:
[0092] main_fsm is responsible for receiving NVMe controller interrupts, clearing interrupts, starting rd_cq_req fsm and determining the status of completion queue items.
[0093] The S6 state is the initial state, which is responsible for waiting for the software to configure the register. When the registers in the register group are configured, the START register is 1 and enters the S7 state.
[0094] The S7 state is responsible for waiting for the NVMe controller interrupt, and enters the S8 state when the interrupt is received. If a soft reset signal is received, it enters the S6 state.
[0095] The S8 state is responsible for clearing the NVMe controller interrupt and then entering the S9 state. If a soft reset signal is received, it enters the S6 state.
[0096] The S9 state is responsible for starting the rd_cq_req fsm state machine to send a read CQ request, and then enters the S10 state.
[0097] The S10 state is responsible for sending the AXI R channel ready signal. After receiving a read response, if the address is aligned, it enters the S11 state, if it is not aligned, it enters the S12 state, and if all read responses have been received, it enters the S7 state.
[0098] The S11 state is responsible for detecting the first completion queue item. If there is a second completion queue item, the S12 state is entered; otherwise, if the read data has not been received, the S10 state is entered. If it has been received and the completion queue item is valid, it means that there are still completion queue items to be read, and the S9 state is entered to send a new read request. If it has been received and the completion queue item is invalid, the S7 state is entered.
[0099] The S12 state is responsible for detecting the second completion queue item. If the read data has not been received, the S10 state is entered. If it has been received and the completion queue item is valid, it means that there are completion queue items that need to be read, and the S9 state is entered to send a new read request. If it has been received and the completion queue item is invalid, the S7 state is entered.
[0100] The rd_cq_req fsm is responsible for sending N full-beat burst read completion queue requests (N is configurable in the register group) to the completion queue to AXI module after receiving notification from main_fsm.
[0101] The S13 state is the initial state, which is responsible for waiting for the software to configure the register. When the registers in the register group are configured, the START register is 1 and enters the S14 state.
[0102] The S14 state is responsible for waiting for the notification from main_fsm, and jumps to the S15 state after receiving the notification. If a soft reset signal is received, it enters the S13 state.
[0103] The S15 state is responsible for sending N full-beat burst read completion queue requests to the completion queue to AXI module, and enters the S14 state after the sending is completed.
[0104] The upd_cqh fsm is responsible for generating a request to update the completion queue head doorbell to the completion queue AXI module after receiving the last beat of a read completion queue response and completing the analysis of the completion queue list item.
[0105] The S16 state is the initial state, which is responsible for waiting for the software to configure the register. When the registers in the register group are configured, the START register is 1 and enters the S17 state.
[0106] The S17 state is responsible for waiting for main_fsm to receive the last beat of a read completion queue response and complete the analysis of the completion queue item, and then jump to the S18 state. If a soft reset signal is received, it enters the S16 state.
[0107] The S18 state is responsible for maintaining the CQH pointer, initiating an update completion queue head doorbell request to the completion queue to AXI module, and then jumping to the S17 state.
[0108] When receiving a soft reset request, the rd_cq_req fsm can be reset only after the main fsm reset is completed. The reset of the upd_cqh fsm has no sequence requirement with the other two state machines.
[0109] The completion queue to AXI module is responsible for generating corresponding AXI read requests based on the read completion queue requests sent by the completion queue processing module, and arbitrating the update completion queue head doorbell requests and clear NVMe interrupt requests sent by the completion queue processing module and then converting them into AXI write requests.
[0110] The state machine in the completion queue to AXI module is as follows Figure 4 As shown, the red arrow indicates the soft reset jump path. The completion queue is converted to the state machine in the AXI module:
[0111] The S19 state is the initial state, which is responsible for waiting for the software to configure the register. When the registers in the register group are configured, the START register is 1 and enters the S20 state.
[0112] The S20 state is responsible for waiting for the completion queue processing module to initiate a write request. When receiving the update completion queue head doorbell request, it jumps to the S21 state, and when receiving the clear interrupt request, it jumps to the S23 state. If a soft reset signal is received, it enters the S19 state.
[0113] The S21 state is responsible for sending the AXI AW request to update the doorbell of the queue head, and then jumps to the S22 state.
[0114] The S22 state is responsible for sending the AXI W request to update the queue head doorbell. If there is a new update queue head doorbell request at this time, jump to the S21 state; if there is a clear interrupt request at this time, jump to the S23 state; if there is no request, jump to the S20 state.
[0115] The S23 state is responsible for sending the AXI AW request to clear the interrupt, and then jumps to the S24 state.
[0116] The S24 state is responsible for sending the AXI W request to clear the interrupt and then jumps to the S25 state.
[0117] The S25 state is responsible for waiting for the corresponding AXI B response. If there is an update completion queue head doorbell request at this time, it jumps to the S21 state; if there is no request, it jumps to the S20 state.
[0118] The AXI arbitration module uses round-robin mode to arbitrate the AXI write requests from the command queue to the AXI module and the completion queue to the AXI module, and finally generates an AXI write request. At the same time, the response is distributed to the corresponding module according to the AXI write response ID.
[0119] Those of ordinary skill in the art will appreciate that the units and method steps of each example described in conjunction with the embodiments disclosed herein can be implemented in electronic hardware, computer software, or a combination of the two. In order to clearly illustrate the interchangeability of hardware and software, the composition and steps of each example have been generally described in terms of function in the above description. Whether these functions are performed in hardware or software depends on the specific application and design constraints of the technical solution. Professional and technical personnel can use different methods to implement the described functions for each specific application, but such implementation should not be considered to be beyond the scope of the present invention.
[0120] In the several embodiments provided in the present application, it should be understood that the disclosed methods and systems can be implemented in other ways. For example, the division of the units described above is only a logical function division, and there may be other division methods in actual implementation, such as multiple units or components can be combined or integrated into another system, or some features can be ignored or not executed. The above-mentioned units may or may not be physically separated, and the components displayed as units may or may not be physical units, that is, they may be located in one place, or they may be distributed on multiple network units. Some or all of the units may be selected according to actual needs to achieve the purpose of the embodiments of the present invention.
[0121] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention, rather than to limit it. Although the present invention has been described in detail with reference to the aforementioned embodiments, those skilled in the art should understand that they can still modify the technical solutions described in the aforementioned embodiments, or replace some or all of the technical features therein by equivalents. These modifications or replacements do not make the essence of the corresponding technical solutions deviate from the scope of the technical solutions of the embodiments of the present invention, and they should all be included in the scope of the claims and specification of the present invention.
[0122] The above description is only a preferred embodiment of the present invention and is not intended to limit the present invention. Any modifications, equivalent substitutions, improvements, etc. made within the spirit and principle of the present invention should be included in the protection scope of the present invention.
Claims
1. A method for NVMe command queue sending and completion queue processing, characterized in that: The steps include: Receive the written command and store it in the FIFO, write the command in the FIFO into the command queue and record the relevant information of the command, and then notify the NVMe controller; the relevant information of the command includes the command identifier; When receiving the interrupt signal from the NVMe controller, read the completion queue, clear the interrupt source, parse the content of the completion queue item, and then notify the NVMe controller; If the status of the completion queue item is a non-successful status, the content of the completion queue item is recorded in a register and an interrupt is generated; if the status of the completion queue item is a successful status, the relevant information of the recorded corresponding command is deleted.
2. The method for NVMe command queue sending and completion queue processing according to claim 1, characterized in that: Also includes: When a preset number of command queue entries are written, write the command queue tailgate bell register of the NVMe controller to notify the NVMe controller; When all the completion queue entries are parsed, the completion queue head doorbell register of the NVMe controller is written to notify the NVMe controller.
3. A system for NVMe command queue sending and completion queue processing, characterized in that: include: The command queue processing module is used to write the sent command into the FIFO, record the relevant information of the command, and send the command in the FIFO to the command queue to AXI module for reading; it is also used to clear the relevant information of the corresponding command that has been recorded after receiving the relevant information from the completion queue processing module; The command queue to AXI module is used to write all commands in the FIFO into the command queue when the FIFO in the command queue processing module is not empty; and maintain the command queue tail pointer and write it into the command queue tail doorbell register; The completion queue processing module is used to clear the NVMe interrupt after receiving the interrupt signal of the NVMe controller, read the completion queue item and detect its status; it is also used to maintain the completion queue head pointer and write it into the completion queue head doorbell register; it is also used to notify the register group module to generate an interrupt when it is detected that the completion queue item status is not a success state, and record the completion queue item information; The completion queue to AXI module is used to generate a corresponding AXI read request according to the read completion queue request sent by the completion queue processing module, and arbitrate the update completion queue head doorbell request and the clear NVMe interrupt request sent by the completion queue processing module and then convert them into AXI write requests; The AXI arbitration module is used to arbitrate the AXI write requests from the command queue to the AXI module and the completion queue to the AXI module, and finally generate an AXI write request, and distribute the response to the corresponding module according to the ID of the AXI write response.
4. The system for NVMe command queue sending and completion queue processing according to claim 3, characterized in that: The command queue to AXI module includes a first state machine; the first state machine includes S0 state, S1 state, S2 state, S3 state, S4 state and S5 state, wherein: The S0 state is the initial state of the module, which is used to wait for the configuration register, and enter the S1 state after the register configuration in the register group is completed and the START register is 1; The S1 state is used to wait for the FIFO in the command queue processing module to be non-empty, and then enter the S2 state; if a soft reset signal is received, it enters the S0 state; The S2 state is used to generate an AXI AW request to the corresponding address in the command queue, and enter the S3 state after receiving the handshake signal; The S3 state is used to generate an AXI W request, write the data in the FIFO into the command queue, and maintain the tail pointer of the command queue; after writing, it enters the S4 state; if a soft reset signal is received, it enters the S0 state; The S4 state is used to initiate an AXI AW request to the command queue tail doorbell register, and enter the S5 state after receiving the handshake signal; The S5 state is used to initiate an AXI W request, write the command queue tail pointer to the register, and enter the S1 state after receiving the handshake signal.
5. The system for NVMe command queue sending and completion queue processing according to claim 1, characterized in that: The completion queue processing module includes a second state machine, a third state machine and a fourth state machine; wherein: The second state machine is used to receive an NVMe controller interrupt, clear the interrupt, start the third state machine and determine the status of the completion queue item; The third state machine is used to send N full-beat burst read completion queue requests to the completion queue to AXI module after receiving the notification from the second state machine; The fourth state machine is used to generate a request for updating the doorbell of the completion queue head to the completion queue transfer AXI module after receiving the last beat of the read completion queue response and completing the analysis of the completion queue list item; When a soft reset request is received, the third state machine can be reset only after the second state machine is reset. The reset of the fourth state machine has no order requirement with the other two state machines. The second state machine includes state S6, state S7, state S8, state S9, state S10, state S11 and state S12, wherein: The S6 state is the initial state, which is used to wait for register configuration. When the registers in the register group are configured, the START register is 1 and then enters the S7 state; The S7 state is used to wait for the NVMe controller interrupt. When the interrupt is received, it enters the S8 state. If a soft reset signal is received, it enters the S6 state. The S8 state is used to clear the NVMe controller interrupt and then enter the S9 state; if a soft reset signal is received, it enters the S6 state; The S9 state is used to start the third state machine to send a read CQ request, and then enter the S10 state; The S10 state is used to send the AXI R channel ready signal. After receiving a read response, if the address is aligned, it enters the S11 state, if it is not aligned, it enters the S12 state, and if all read responses have been received, it enters the S7 state; The S11 state is used to detect the first completion queue item; if there is a second completion queue item behind it, enter the S12 state; otherwise, if the read data has not been received, enter the S10 state. If it has been received and the completion queue item is valid, it means that there are still completion queue items to be read, then enter the S9 state to send a new read request. If it has been received and the completion queue item is invalid, enter the S7 state. The S12 state is responsible for detecting the second completion queue item; if the read data has not been received, the S10 state is entered; if it has been received and the completion queue item is valid, it means that there are completion queue items that need to be read, and the S9 state is entered to send a new read request; if it has been received and the completion queue item is invalid, the S7 state is entered; The third state machine includes state S13, state S14 and state S15, wherein: The S13 state is the initial state, which is used to wait for the software to configure the registers. When the registers in the register group are configured, the START register is 1 and then enters the S14 state. The S14 state is used to wait for the notification of the second state machine, and jump to the S15 state after receiving the notification; if a soft reset signal is received, it enters the S13 state; The S15 state is used to send N full-beat burst read completion queue requests to the completion queue to AXI module, and enter the S14 state after the sending is completed; The fourth state machine includes state S16, state S17 and state S18, wherein: The S16 state is the initial state, which is used to wait for the software to configure the registers. When the registers in the register group are configured, the START register is 1 and then enters the S17 state. The S17 state is responsible for waiting for the second state machine to receive the last beat of a read completion queue response and complete the analysis of the completion queue item, and then jump to the S18 state; if a soft reset signal is received, it enters the S16 state; The S18 state is responsible for maintaining the CQH pointer, initiating an update completion queue head doorbell request to the completion queue to AXI module, and then jumping to the S17 state.
6. The system for NVMe command queue sending and completion queue processing according to claim 1, characterized in that: The completion queue to AXI module includes a fifth state machine, and the fifth state machine includes S19 state, S20 state, S21 state, S22 state, S23 state, S24 state and S25 state, wherein: The S19 state is the initial state, which is used to wait for the software to configure the registers. When the registers in the register group are configured, the START register is 1 and then enters the S20 state. The S20 state is used to wait for the completion queue processing module to initiate a write request; when receiving the update completion queue head doorbell request, it jumps to the S21 state, and when receiving the clear interrupt request, it jumps to the S23 state; if a soft reset signal is received, it enters the S19 state; The S21 state is used to send an AXI AW request to update the doorbell of the queue head, and then jump to the S22 state; The S22 state is used to send an AXI W request to update the queue head doorbell; if there is a new update queue head doorbell request at this time, jump to the S21 state; if there is a clear interrupt request at this time, jump to the S23 state; if there is no request, jump to the S20 state; The S23 state is used to send an AXI AW request to clear the interrupt, and then jump to the S24 state; The S24 state is used to send an AXI W request to clear the interrupt, and then jump to the S25 state; The S25 state is used to wait for the corresponding AXI B response; if there is an update completion queue head doorbell request at this time, it jumps to the S21 state; if there is no request, it jumps to the S20 state.
7. The system for NVMe command queue sending and completion queue processing according to claim 1, characterized in that: Also included is a register group module, which includes a plurality of registers and is used to give an error interrupt signal when the completion queue entry status is a non-successful status; An AHB asynchronous bridge module is also included, which is used to convert the AHB clock domain to the AXI clock domain to configure the register group module.
8. An electronic device, comprising a processor and a memory connected to the processor for storing instructions executable by the processor, characterized in that: The processor is used to execute the method and system for NVMe command queue sending and completion queue processing described in any of claims 1-2 above.
9. A server, characterized in that: It includes at least one processor and a memory communicatively connected to the processor, wherein the memory stores instructions executable by the at least one processor, and the instructions are executed by the processor so that the at least one processor executes the method and system for NVMe command queue sending and completion queue processing as described in any one of claims 1-2.
10. A computer-readable storage medium storing a computer program, characterized in that: When the computer program is executed by a processor, the method and system for NVMe command queue sending and completion queue processing described in any one of claims 1-2 are implemented.