USB power supply circuit and electronic equipment

Abstract

The invention discloses a USB (Universal Serial Bus) power supply circuit and electronic equipment, and the USB power supply circuit comprises a USB interface, a change-over switch chip, a first logic chip, a second logic chip and a current limiting chip, the USB interface is respectively connected with the change-over switch chip, the first logic chip and the second logic chip; the first logic chip is also connected with the change-over switch chip and the second logic chip; the second logic chip is also connected with the current limiting chip; the first logic chip is used for identifying insertion information of the USB interface; the change-over switch chip is used for switching the uplink communication state and the downlink communication state of the USB interface according to the insertion information; the second logic chip is used for controlling the working state of the current limiting chip according to the insertion information; the working state comprises a current-limiting opening state and a current-limiting closing state. According to the technical scheme, the USB power supply circuit does not need to be controlled by an additional main controller, product requirements are met only through hardware building, product power consumption can be reduced, and meanwhile the service life of the product is prolonged.

Description

Technical Field

[0001] The present invention relates to the technical field of power supply circuits, and in particular to a USB power supply circuit and electronic equipment. Background Art

[0002] Universal Serial Bus (USB) is an interface that standardizes and unifies the connection of computer peripheral devices. In recent years, the USB Type-C interface has added the function of reversible pluggability based on the universality of the original USB interface and reduced the size of the interface.

[0003] The existing USB Type-C interface is used for display transmission, that is, when the DP Alt mode is used, a dedicated DPAUX control chip is generally used to solve the problem of the temperature of the forward and reverse plug-in function interface interchangeability. However, the DP AUX control chip is expensive, has a complex circuit structure, high power consumption, and a short lifespan. Summary of the invention

[0004] The present invention provides a USB power supply circuit and an electronic device to solve the problems existing in the prior art, so that no additional main controller is required to control the USB power supply circuit, and product requirements can be met simply by hardware construction, which is beneficial to reducing product power consumption and at the same time, improving product life.

[0005] In a first aspect, the present invention provides a USB power supply circuit, comprising: a USB interface, a switching chip, a first logic chip, a second logic chip and a current limiting chip;

[0006] The USB interface is connected to the switching chip, the first logic chip and the second logic chip respectively; the first logic chip is also connected to the switching chip and the second logic chip; the second logic chip is also connected to the current limiting chip;

[0007] The first logic chip is used to identify the insertion information of the USB interface; the switching switch chip is used to switch the upper communication state and the lower communication state of the USB interface according to the insertion information, and the upper communication state and the lower communication state each correspond to two pairs of data lines; the second logic chip is used to control the working state of the current limiting chip according to the insertion information; the working state includes a current limiting on state and a current limiting off state.

[0008] Optionally, the USB power supply circuit further includes: a transient voltage suppression module;

[0009] The switch chip is connected to the USB interface through the transient voltage suppression module.

[0010] Optionally, the transient voltage suppression module includes a first transient voltage suppression chip and a second transient voltage suppression chip;

[0011] The first transient voltage suppression chip is connected to the front data line of the USB interface; the second transient voltage suppression chip is connected to the back data line of the USB interface.

[0012] Optionally, the USB power supply circuit further includes: a noise suppression module;

[0013] The switch chip is connected to the USB interface through the noise suppression module.

[0014] Optionally, the noise suppression module includes a first common mode inductor, a second common mode inductor, a third common mode inductor and a fourth common mode inductor;

[0015] The first common-mode inductor is connected to the first data transmission line of the USB interface; the second common-mode inductor is connected to the first data reception line of the USB interface; the third common-mode inductor is connected to the second data reception line of the USB interface; and the fourth common-mode inductor is connected to the second data transmission line of the USB interface.

[0016] Optionally, the first logic chip includes a first insertion status acquisition pin and a second insertion status acquisition pin; the USB interface includes a first insertion status detection pin and a second insertion status detection pin; the first insertion status acquisition pin is connected to the first insertion status detection pin; and the second insertion status acquisition pin is connected to the second insertion status detection pin.

[0017] Optionally, the USB interface includes an upstream transmission data positive wiring, an upstream transmission data negative wiring, an upstream reception data positive wiring, a downstream reception data negative wiring, a downstream transmission data positive wiring, a downstream transmission data negative wiring, a downstream reception data positive wiring and a downstream reception data negative wiring;

[0018] The switching switch chip includes a switching selection pin, a first transmission data positive pin, a first transmission data negative pin, a first reception data positive pin, a first reception data negative pin, a second transmission data positive pin, a second transmission data negative pin, a second reception data positive pin, a second reception data negative pin, a third transmission data positive pin, a third transmission data negative pin, a third reception data positive pin and a third reception data negative pin;

[0019] The first logic chip includes a first insertion status output pin;

[0020] The first transmission data positive pin, the first transmission data negative pin, the first reception data positive pin, and the first reception data negative pin are used to be connected to the TXP lead, TXN lead, RXP lead, and RXN lead of an external inserted device in a one-to-one correspondence, respectively;

[0021] The second transmission data positive pin, the second transmission data negative pin, the second reception data positive pin, the second reception data negative pin, and the third transmission data positive pin are respectively connected to the upper transmission data positive wiring, the upper transmission data negative wiring, the upper reception data positive wiring, and the upper reception data negative wiring in one-to-one correspondence; the third transmission data positive pin, the third transmission data negative pin, the third reception data positive pin, and the third reception data negative pin are respectively connected to the lower transmission data positive wiring, the lower transmission data negative wiring, the lower reception data positive wiring, and the lower reception data negative wiring in one-to-one correspondence;

[0022] The switching selection pin of the switching switch chip is connected to the first insertion state output pin of the first logic chip.

[0023] Optionally, the first logic chip includes a second insertion state output pin and a third insertion state output pin; the second logic chip includes a first power supply control pin and a second power supply control pin;

[0024] The second insertion state output pin is connected to the first power supply control pin; and the third insertion state output pin is connected to the second power supply control pin.

[0025] Optionally, the second logic chip includes a power switch pin; the current limiting chip includes a power enable pin;

[0026] The power switch pin is connected to the power enable pin.

[0027] In a second aspect, the present invention provides an electronic device, comprising any one of the USB power supply circuits described above.

[0028] The technical solution of the present invention is to make the USB power supply circuit include a USB interface, a switching switch chip, a first logic chip, a second logic chip and a current limiting chip, the USB interface is respectively connected to the switching switch chip, the first logic chip and the second logic chip, and the first logic chip is also connected to the switching switch chip and the current limiting chip, and the first logic chip is used to identify the insertion information of the USB interface, the switching switch chip is used to switch the upper communication state and the lower communication state according to the insertion information, and the second logic chip is used to control the working state of the current limiting chip according to the insertion information, so that there is no need for an additional main controller to control the power supply circuit, and the reversible pluggable function of USB Type-C 3.0 is achieved by simply building hardware. At the same time, the current limiting chip is turned on and works only when an external plug-in device is inserted, which is beneficial to reduce product power consumption and improve product life.

[0029] It should be understood that the contents described in this section are not intended to identify the key or important features of the embodiments of the present invention, nor are they intended to limit the scope of the present invention. Other features of the present invention will become easily understood through the following description. BRIEF DESCRIPTION OF THE DRAWINGS

[0030] In order to more clearly illustrate the technical solutions in the embodiments of the present invention, the following briefly introduces the drawings required for use in the description of the embodiments. Obviously, the drawings described below are only some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without creative work.

[0031] Figure 1 A structural block diagram of a USB power supply circuit provided by an embodiment of the present invention. ;

[0032] Figure 2 A circuit schematic diagram of a USB interface provided by an embodiment of the present invention;

[0033] Figure 3 A circuit schematic diagram of a first logic chip provided in an embodiment of the present invention;

[0034] Figure 4 A circuit schematic diagram of a first transient suppression unit provided in an embodiment of the present invention;

[0035] Figure 5 A circuit schematic diagram of a first transient voltage suppression chip provided by an embodiment of the present invention;

[0036] Figure 6 A circuit schematic diagram of a second transient voltage suppression chip provided by an embodiment of the present invention;

[0037] Figure 7 A circuit schematic diagram of a switching switch chip provided in an embodiment of the present invention;

[0038] Figure 8 A circuit schematic diagram of a second logic chip provided by an embodiment of the present invention;

[0039] Fig. 9 A circuit schematic diagram of a current limiting chip provided in an embodiment of the present invention;

[0040] Fig.10 A partial circuit schematic diagram of a USB power supply circuit provided by an embodiment of the present invention. DETAILED DESCRIPTION

[0041] In order to enable those skilled in the art to better understand the scheme of the present invention, the technical scheme in the embodiments of the present invention will be clearly and completely described below in conjunction with the drawings in the embodiments of the present invention. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work should fall within the scope of protection of the present invention.

[0042] It should be noted that the terms "first", "second", etc. in the specification and claims of the present invention and the above-mentioned drawings are used to distinguish similar objects, and are not necessarily used to describe a specific order or sequence. It should be understood that the numbers used in this way can be interchanged where appropriate, so that the embodiments of the present invention described herein can be implemented in an order other than those illustrated or described herein.

[0043] Figure 1 This is a structural block diagram of a USB power supply circuit provided by an embodiment of the present invention. This embodiment provides a USB power supply circuit, referring to Figure 1 As shown, the USB power supply circuit includes: a USB interface CN1, a switching switch chip U1, a first logic chip U2, a second logic chip U4 and a current limiting chip U3; the USB interface CN1 is connected to the switching switch chip U1, the first logic chip U2 and the second logic chip U4 respectively; the first logic chip U2 is also connected to the switching switch chip U1 and the second logic chip U4; the second logic chip U4 is also connected to the current limiting chip U3; the first logic chip U2 is used to identify the insertion information of the USB interface CN1; the switching switch chip U1 is used to switch the upper communication state and the lower communication state of the USB interface CN1 according to the insertion information, and the upper communication state and the lower communication state each correspond to two pairs of data routings; the second logic chip U4 is used to control the working state of the current limiting chip U3 according to the insertion information.

[0044] The working state of the current limiting chip U3 includes a current limiting on state and a current limiting off state. When the current limiting chip U3 is in the current limiting on state, the USB power supply circuit has a voltage output, and when the current limiting chip U3 is in the current limiting off state, the USB power supply circuit has no voltage output.

[0045] In this embodiment, the USB interface CN1 is a Type-C interface. The USB interface CN1 is connected to the first logic chip U2, and the first logic chip U2 is used to identify the insertion information of the USB interface CN1, wherein the insertion information of the USB interface CN1 includes whether an external device is inserted and whether no external device is inserted, etc., wherein whether an external device is inserted includes whether the external device is inserted from the front and whether the external device is inserted from the back.

[0046] The switch chip U1 is connected to the USB interface CN1 and the first logic chip U2. The switch chip U1 is used to switch the uplink communication state and the downlink communication state of the USB interface CN1 according to the insertion information of the USB interface CN1 identified by the first logic chip U2.

[0047] Specifically, the USB interface CN1 has four pairs of data lines, of which two pairs of high-speed lines are on the front of the USB interface CN1, which are front data lines, and the other two pairs of high-speed lines are on the back of the USB interface CN1, which are back data lines. When the upper communication of the USB interface is turned on, data is transmitted through the front data lines, and when the lower communication of the USB interface is turned on, data is transmitted through the back data lines, so that the USB interface CN1 can realize the forward and reverse insertion function. Since the main chip only supports one bus, four inputs and two outputs are realized by switching the switch chip U1, which can solve the problem that the main chip has no redundant interfaces. The first logic chip U2 is used to identify the insertion information such as whether the external device of the USB interface CN1 is inserted from the front or the back, so that the switching switch chip U1 can determine when its output switches to the front and when it switches to the back according to the insertion information of the USB interface CN1, so that the forward and reverse pluggable function of the USB interface CN1 can be realized without the need for a main control chip.

[0048] The second logic chip U4 is connected to the USB interface CN1, the current limiting chip U3 and the first logic chip U2. The second logic chip U4 is used to control the current limiting chip U3 to be in a working state such as current limiting on or current limiting off according to insertion information such as whether an external device is inserted into the USB interface CN1 identified by the first logic chip U2.

[0049] In this embodiment, the USB power supply circuit includes a USB interface, a switching switch chip, a first logic chip, a second logic chip and a current limiting chip. The USB interface is connected to the switching switch chip, the first logic chip and the second logic chip respectively, and the first logic chip is also connected to the switching switch chip and the current limiting chip. The first logic chip is used to identify the insertion information of the USB interface, the switching switch chip is used to switch the upper communication state and the lower communication state of the USB interface according to the insertion information, and the second logic chip is used to control the working state of the current limiting chip according to the insertion information. Therefore, there is no need for an additional main controller to control the power supply circuit, and the reversible pluggable function of USB Type-C 3.0 is achieved simply by hardware construction. At the same time, the current limiting chip is turned on only when an external plug-in device is inserted, which is beneficial to reduce product power consumption and improve product life.

[0050] Optional, Figure 2 A circuit diagram of a USB interface provided by an embodiment of the present invention, Figure 3 The circuit schematic diagram of the first logic chip provided by the embodiment of the present invention is combined with reference to Figure 1-Figure 3 As shown, the first insertion status acquisition pin of the first logic chip U2 is connected to the first insertion status detection pin of the USB interface CN1; the second insertion status acquisition pin of the first logic chip U2 is connected to the second insertion status detection pin of the USB interface CN1.

[0051] Among them, reference Figure 2 As shown, the USB interface CN1 is a Type-C 3.0 interface. The USB interface CN1 includes four pairs of data traces, namely, SSTXP1 trace, SSTXN1 trace, SSRXP1 trace, SSRXN1 trace, SSTXP2 trace, SSTXN2 trace, SSRXP2 trace and SSRXN2 trace, among which, SSTXP1 trace, SSTXN1 trace, SSRXP2 trace and SSRXN2 trace are front data traces, and SSRXP1 trace, SSRXN1 trace, SSTXP2 trace and SSTXN2 trace are back data traces.

[0052] The USB interface CN1 further includes a first insertion status detection pin and a second insertion status detection pin, which are used to identify the insertion direction of the external device of the USB interface CN1.

[0053] The USB interface CN1 further includes a DP1 pin, a DN1 pin, a DP2 pin, and a DN2 pin, wherein the DP1 pin and the DP2 pin are connected to USB_DP, and the DN1 pin and the DN2 pin are connected to USB_DM; the DP2 pin is connected to USB_DP through a resistor R6, and the DN2 pin is connected to USB_DM through a resistor R7, and USB_DP and USB_DM are standard USB2.0 interfaces. In an exemplary embodiment, R6 and R7 are 0R / 1% / 1 / 16W / 0402.

[0054] In an alternative embodiment, Figure 4 The circuit schematic diagram of the first transient suppression unit provided by the embodiment of the present invention is shown in FIG. Figure 1-Figure 4 As shown, the USB power supply circuit also includes a first transient suppression unit TVS2, which is connected between the DP and DM wirings to implement electrostatic protection for the USB2.0 interface.

[0055] In an exemplary embodiment, the first transient suppression unit TVS2 includes JEU05UCR.

[0056] The USB interface CN1 also includes a VBUS pin, an SBU1 pin, an SBUS pin, an SBU2 pin, and a GND pin. The SBU1 pin and the SBU2 pin are left empty. The VBUS pin and the SBUS pin are connected to USB_5V_1, and the GND pin is grounded. USB_5V_1 is also grounded through TVS1. TVS1 includes an electrostatic protector and a capacitor C1 in parallel. In an exemplary embodiment, the electrostatic protector is JEU05D3U, and the capacitor C1 is 100nF / 10% / 16V / X7R / 0402.

[0057] Figure 5 A circuit schematic diagram of a first transient voltage suppression chip provided by an embodiment of the present invention, Figure 6 The circuit schematic diagram of the second transient voltage suppression chip provided by the embodiment of the present invention. Figure 1-Figure 6 As shown, the USB power supply circuit further includes: a transient voltage suppression module; the switching switch chip U1 is connected to the USB interface CN1 through the transient voltage suppression module.

[0058] The transient voltage suppression module is used to implement electrostatic protection for the USB interface CN1. Since the USB interface CN1 is exposed, static electricity and other energy interference may come in. By setting a transient voltage suppression module on the bus of the USB interface CN1, the interference caused by static electricity can be eliminated.

[0059] In an optional embodiment, the transient voltage suppression module includes a first transient voltage suppression chip TVS3 and a second transient voltage suppression chip TVS4; the first transient voltage suppression chip TVS3 is connected to the front data line of the USB interface CN1; the second transient voltage suppression chip TVS4 is connected to the back data line of the USB interface CN1, so as to eliminate the electrostatic interference of the front data line and the back data line of the USB interface CN1 respectively. It should be noted that the junction capacitance of the first transient voltage suppression chip TVS3 and the second transient voltage suppression chip TVS4 is less than 0.3pF to prevent the first transient voltage suppression chip TVS3 and the second transient voltage suppression chip TVS4 from affecting the signal of the USB interface CN1 and causing the USB power supply circuit to fail to work.

[0060] In an exemplary embodiment, the first transient voltage suppression chip TVS3 and the second transient voltage suppression chip TVS4 are both TVS / 3.3V / DFN2510-10L / WS4423EC chips. The IO1 pin and NC4 pin of the first transient voltage suppression chip TVS3 are connected to the SSTXP1 trace of the USB interface CN1, the IO2 pin and NC3 trace are connected to the SSTXN1 trace of the USB interface CN1, the IO3 pin and NC2 pin are connected to the SSRXN2 trace of the USB interface CN1, and the IO4 pin and NC1 pin are connected to the SSRXN2 trace of the USB interface CN1. The IO1 pin and NC4 pin of the second transient voltage suppression chip TVS4 are connected to the SSRXP1 trace of the USB interface CN1, the IO2 pin and NC3 trace are connected to the SSRXN1 trace of the USB interface CN1, the IO3 pin and NC2 pin are connected to the SSTXN2 trace of the USB interface CN1, and the IO4 pin and NC1 pin are connected to the SSTXN2 trace of the USB interface CN1. The GND1 pin and the GND2 pin of the first transient voltage suppression chip TVS3 and the second transient voltage suppression chip TVS4 are both grounded.

[0061] Optionally, the USB power supply circuit further includes: a noise suppression module; the switch chip U1 is connected to the USB interface CN1 through the noise suppression module. The noise suppression module is used to eliminate the interference noise generated by the USB interface CN1 during operation, thereby preventing the USB power supply circuit from affecting the WIFI signal.

[0062] Continue to refer Figure 2As shown, in an optional embodiment, the noise suppression module includes a first common-mode inductor L1, a second common-mode inductor L2, a third common-mode inductor L3 and a fourth common-mode inductor L4; the first common-mode inductor L1 is connected to the SSTXP1 routing and the SSTXN1 routing of the USB interface CN1; the second common-mode inductor L2 is connected to the SSRXP1 routing and the SSRXN1 routing of the USB interface CN1; the third common-mode inductor L3 is connected to the SSRXP2 routing and the SSRXN2 routing of the USB interface CN1; and the fourth common-mode inductor L4 is connected to the SSTXP2 routing and the SSTXN2 routing of the USB interface CN1.

[0063] In an optional embodiment, the first common-mode inductor L1 is connected in parallel with the resistors R1 and R2, the second common-mode inductor L2 is connected in parallel with the resistors R3 and R5, the third common-mode inductor L3 is connected in parallel with the resistors R8 and R12, and the fourth common-mode inductor L4 is connected in parallel with the resistors R9 and R13, wherein the resistors R1, R2, R3, R5, R8, R12, R9 and R13 are all selected from NI / 0R / 1% / 1 / 20W / 0201, thereby reducing the common-mode interference signal.

[0064] The first logic chip U2 may include, but is not limited to, a CC logic chip.

[0065] In an exemplary embodiment, reference Figure 3 As shown, the first logic chip U2 is a modified PTN5150AHXMP chip. The first logic chip U2 includes a VDD pin, a ROLE pin, a VBUS pin, an INTB pin, a GND pin, an SDA pin, and an SDL pin. Among them, the VDD pin is connected to the power supply voltage 3V3_USB_ID, and the power supply voltage 3V3_USB_ID is grounded through a capacitor C6. The ROLE pin is connected to USB_ROLE. The VBUS pin is connected to the power supply voltage USB_5V_1 through a resistor R27, and the VBUS pin is grounded through a capacitor C7. The GND pin is grounded, and the SDA pin and the SDL pin are left empty. In an exemplary embodiment, the capacitor C6 is 100nF / 10% / 16V / X7R / 0402, and the resistor R27 is 0R / 1% / 1 / 16W / 0402.

[0066] In addition, the first logic chip U2 also includes a first insertion status acquisition pin and a second insertion status acquisition pin, namely, a CC1 pin and a CC2 pin. The first insertion status acquisition pin is connected to the first insertion status detection pin of the USB interface CN1, namely, the CC1 pin, and the second insertion status acquisition pin is connected to the second insertion status detection pin of the USB interface CN1, namely, the CC2 pin, so that the first logic chip U2 can identify whether the external device of the USB interface CN1 is inserted from the front or the back. In an exemplary embodiment, when the CCI pin or the CC2 pin is 1, that is, the CC1 pin or the CC2 pin has a high level, the first logic chip U2 recognizes that an external device is inserted into the USB interface CN1; when the CC1 pin is 1, that is, a high level, and the CC2 pin is 0, that is, a low level, the first logic chip U2 recognizes that the external device of the USB interface CN1 is inserted from the front; on the contrary, when the CCI pin is 0 and the CC2 pin is 1, the first logic chip U2 recognizes that the external device of the USB interface CN1 is inserted from the back; in addition, if the CC1 pin and the CC2 pin are both 0, the first logic chip U2 recognizes that no external device is inserted into the USB interface CN1.

[0067] Optional, Figure 7 The circuit schematic diagram of the switching switch chip U1 provided in the embodiment of the present invention is shown in FIG. Figure 1-Figure 7As shown, the USB interface CN1 includes an upper transmission data positive wiring (i.e., SSTXP1 wiring), an upper transmission data negative wiring (i.e., SSTXN1 wiring), an upper receiving data positive wiring (i.e., SSRXP1 wiring), a lower receiving data negative wiring (i.e., SSRXN1 wiring), a lower transmission data positive wiring (i.e., SSTXP2 wiring), a lower transmission data negative wiring (i.e., SSTXN2 wiring), a lower receiving data positive wiring (i.e., SSRXP2 wiring), and a lower receiving data negative wiring (i.e., SSRXN2 wiring); the switching switch chip U1 includes a switching selection pin (i.e., SEL pin), a first transmission data positive wiring (i.e., A0P pin), a first Transmitting data negative pin (i.e., A0N pin), first receiving data positive pin (i.e., A1P pin), first receiving data negative pin (i.e., A1N pin), second transmitting data positive pin (i.e., B0P pin), second transmitting data negative pin (i.e., B0N pin), second receiving data positive pin (i.e., B1P pin), second receiving data negative pin (i.e., B1N pin), third transmitting data positive pin (i.e., C0P pin), third transmitting data negative pin (i.e., C0N pin), third receiving data positive pin (i.e., C1P pin) and third receiving data negative pin (i.e., C1N pin); the first logic chip U2 includes a first insertion status output pin (i.e., ENB pin).The first data transmission positive pin, the first data transmission negative pin, the first data reception positive pin, and the first data reception negative pin are used to be connected to the SSUSB_TXP lead, SSUSB_TXN lead, SSUSB_RXP lead, and SSUSB_RXN lead of the external inserted device in a one-to-one correspondence, respectively, so that the external inserted device can realize data transmission and reception between the switching switch chip U1; the second data transmission positive pin, the second data transmission negative pin, the second data reception positive pin, and the second data reception negative pin are connected to the upper transmission data positive wiring, the upper transmission data negative wiring, the upper reception data positive wiring, and the upper reception data negative wiring in a one-to-one correspondence; the third data transmission positive pin, the third data transmission negative pin, and the third reception data positive pin are connected to the upper transmission data positive wiring, the upper transmission data negative wiring, the upper reception data positive wiring, and the upper reception data negative wiring in a one-to-one correspondence. and the third receiving data negative pin are respectively connected one-to-one with the lower transmission data positive wiring, the lower transmission data negative wiring, the lower receiving data positive wiring and the lower receiving data negative wiring; the switching selection pin of the switching switch chip is connected with the first insertion state output pin of the first logic chip, so that the switching switch chip U1 can selectively turn on the second transmission data positive pin, the second transmission data negative pin, the second receiving data positive pin and the second receiving data negative pin, or the third transmission data positive pin, the third transmission data negative pin, the third receiving data positive pin and the third receiving data negative pin according to the insertion state of the external insertion device received by the switching selection pin, so as to realize switching the upper communication state and the lower communication state of the USB interface according to the insertion information of the external insertion device.

[0068] The switching chip U1 may include but is not limited to an analog switch.

[0069] In an exemplary embodiment, the switch chip U1 is an AW35710QNR chip. The first transmission data positive pin is connected to the SSUSB_TXP lead of the external plug-in device through a resistor R10, the first transmission data negative pin is connected to the SSUSB_TXN lead through a resistor R11, the first reception data positive pin is connected to the SSUSB_RXP lead through a resistor R14, and the first reception data negative pin is connected to the SSUSB_RXN lead through a resistor R15. In an exemplary embodiment, the resistor R10, the resistor R11, the resistor R14 and the resistor R15 are all 0R / 1% / 1 / 16W / 0402.

[0070] The switch chip U1 further includes a 0EN pin, which is connected to USB_ID through a resistor R17 and is also connected to 3V3_USB_ID through a resistor R16. In an exemplary embodiment, the resistor R16 and the resistor R17 are both 10K / 1% / 1 / 20W / 0201.

[0071] The switching switch chip U1 also includes a switching selection pin (i.e., SEL pin). The first logic chip U2 also includes a first insertion state output pin (i.e., ENB pin). The switching selection pin of the switching switch chip U1 is connected to the first insertion state output pin of the first logic chip U2, so that the insertion information of the USB interface CN1 identified by the first logic chip U2 can be transmitted to the switching selection pin of the switching switch chip U1 through the first insertion state output pin, so that the switching switch chip U1 can control the conduction of its second transmission data positive pin, the second transmission data negative pin, the second reception data positive pin, the second reception data negative pin, the third transmission data positive pin, the third transmission data negative pin, the third reception data positive pin, and the third reception data negative pin through the switching selection pin, thereby switching the upper communication state and the lower communication state of the USB interface.

[0072] The switch chip U1 also includes a VCC pin and a GND pin. Among them, the GND pin is grounded. The VCC pin is connected to 3V3_USB_ID and is connected to the power supply 3V3 through a resistor R4. The resistor R4 and 3V3_USB_3V are grounded through parallel capacitors C2, C3 and C4. In an exemplary embodiment, the resistor R4 is 0R / 1% / 1 / 10W / 0603, the capacitor C2 is 10uF / 20% / 6.3V / X5R / 0402, the capacitor C3 is 100nF / 10% / 6.3V / X5R / 0201, and the capacitor C4 is 10nF / 10% / 6.3V / X7R / 0201.

[0073] Optional, Figure 8 A circuit schematic diagram of a second logic chip provided in an embodiment of the present invention, Fig. 9 The circuit schematic diagram of the current limiting chip provided by the embodiment of the present invention is shown in FIG. Figure 1-Figure 9 As shown, the first logic chip U2 includes a second insertion status output pin (i.e., CTRL pin) and a third insertion status output pin (i.e., ID pin); the second logic chip U4 includes a first power supply control pin (i.e., C pin) and a second power supply control pin (i.e., B pin); the second insertion status output pin is connected to the first power supply control pin; and the third insertion status output pin is connected to the second power supply control pin.

[0074] Optional, combined with reference Figure 1-Figure 9 As shown, the second logic chip also includes a power switch pin (ie, Y pin); the current limiting chip U3 also includes a power enable pin (ie, EN pin); and the power switch pin is connected to the power enable pin.

[0075] The second logic chip U4 may include, but is not limited to, a configurable logic circuit.

[0076] In an exemplary embodiment, reference Figure 8 As shown, the second logic chip U4 includes a NI / 74LVC1G97GW chip. The second logic chip U4 includes a B pin, a GND pin, an A pin, a Y pin, a VCC pin) and a C pin). The GND pin is grounded, and the VCC pin is connected to 3V3_USB_ID.

[0077] The current limiting chip U3 may include, but is not limited to, a power switch. In an exemplary embodiment, reference Fig. 9 As shown, the current limiting chip U3 is a U / TSOT23-5 / 1A / RT9742GGJ5F chip. The current limiting chip U3 includes an OUT pin, a GND pin, a FAULT pin, an EN pin, and an IN pin. The GND pin is grounded, the IN pin is connected to the power supply USB_5V, and the power supply USB_5V is connected to the ground through a capacitor C11. The EN pin is connected to the power supply USB_5V through a resistor R32, and the EN pin is also connected to USB_Power_EN through a resistor R35. The resistor R35 and the EN pin are also connected to VDD_EXT through a resistor R33. In an exemplary embodiment, the capacitor C11 is 10uF / 20% / 16V / X5R / 0603, the resistor R32 is NI / 10K / 1% / 1 / 20W / 0201, the resistor R33 is 10K / 1% / 1 / 20W / 0201, and the resistor R35 is 0R / 1% / 1 / 20W / 0201.

[0078] The power enable pin (EN pin) of the current limiting chip U3 is connected to the power switch pin (Y pin) of the second logic chip U4, so that the level of the power switch pin of the second logic chip U4 controls the output of the power switch pin.

[0079] Specifically, when the first logic chip U2 recognizes that the insertion information of the USB interface CN1 is that an external device has been inserted, the second insertion status output pin of the first logic chip U2 outputs a low level, and the third insertion status output pin outputs a high level. Since the second insertion status output pin and the third insertion status output pin of the first logic chip U2 are respectively connected to the first power supply control pin and the second power supply control pin of the second logic chip U4, the first power supply control pin of the second logic chip U4 is a low level, and the second power supply control pin is a high level. At this time, the power supply switch pin of the second logic chip U4 outputs a high level, so that the power supply enable pin of the current limiting chip U3 is a high level, and the current limiting chip U3 is in the current limiting open state, so that the USB power supply circuit has a voltage output. On the contrary, when the first logic chip U2 recognizes that the insertion information of the USB interface CN1 is that no external device is inserted, the second insertion state output pin of the first logic chip U2 outputs a high level, and the third insertion state output pin outputs a low level, so that the first power supply control pin of the second logic chip U4 is a high level, and the second power supply control pin is a low level. At this time, the power supply switch pin of the second logic chip U4 outputs a low level, so that the power supply enable pin of the current limiting chip U3 is a low level, and the current limiting chip U3 is in a closed state, so that the USB power supply circuit has no voltage output. In this way, the USB interface CN1 can be protected and energy saving can be achieved at the same time.

[0080] The FAULT pin of the current limiting chip U3 is connected to USB_FAULT through a resistor R36, and the resistors R36 and USB_FAULT are connected to VDD_EXT through a resistor R34, so that when there is an overcurrent in the power supply circuit, the FAULT pin outputs a high level (i.e., an overcurrent signal) to the system end, thereby achieving overcurrent protection.

[0081] Fig.10 A partial circuit schematic diagram of a USB power supply circuit provided by an embodiment of the present invention. In an optional embodiment, refer to Fig.10 As shown, the ground line of the USB power supply circuit is connected to the ground line of the system end through a resistor R20 and a capacitor C5 connected in parallel, so that the energy coupled to the system ground line when the USB is static electricity can be absorbed and isolated. In an exemplary embodiment, the resistor R20 is 0R / 1% / 1 / 8W / 0805, and the capacitor C5 is NI / 1nF / 5% / 100V / NP0 / 0805.

[0082] An embodiment of the present invention further provides an electronic device, which includes the USB power supply circuit provided by any embodiment of the present invention. Since the electronic device provided by the embodiment of the present invention includes the USB power supply circuit provided by the embodiment of the present invention, it can have the corresponding structure and features of the USB power supply circuit provided by the embodiment of the present invention, and can achieve the beneficial effects of the USB power supply circuit provided by the embodiment of the present invention. The same points can be referred to the above description.

[0083] In an optional embodiment, the electronic device provided in this embodiment is a complex network communication product, such as an indoor 5G fusion switch or an outdoor 5G fusion switch.

[0084] The above specific implementations do not constitute a limitation on the protection scope of the present invention. It should be understood by those skilled in the art that various modifications, combinations, sub-combinations and substitutions can be made according to design requirements and other factors. Any modification, equivalent substitution and improvement made within the spirit and principle of the present invention should be included in the protection scope of the present invention.

Claims

1. A USB power supply circuit, characterized in that: include: USB interface, switch chip, first logic chip, second logic chip and current limiting chip; The USB interface is connected to the switching chip, the first logic chip and the second logic chip respectively; the first logic chip is also connected to the switching chip and the second logic chip; the second logic chip is also connected to the current limiting chip; The first logic chip is used to identify the insertion information of the USB interface; the switching switch chip is used to switch the upper communication state and the lower communication state of the USB interface according to the insertion information, and the upper communication state and the lower communication state each correspond to two pairs of data lines; the second logic chip is used to control the working state of the current limiting chip according to the insertion information; the working state includes a current limiting on state and a current limiting off state.

2. The USB power supply circuit according to claim 1, characterized in that: Also includes: Transient voltage suppression module; The switch chip is connected to the USB interface through the transient voltage suppression module.

3. The USB power supply circuit according to claim 2, characterized in that: The transient voltage suppression module includes a first transient voltage suppression chip and a second transient voltage suppression chip; The first transient voltage suppression chip is connected to the front data line of the USB interface; the second transient voltage suppression chip is connected to the back data line of the USB interface.

4. The USB power supply circuit according to claim 1, characterized in that: Also includes: Noise suppression module; The switch chip is connected to the USB interface through the noise suppression module.

5. The USB power supply circuit according to claim 4, characterized in that: The noise suppression module includes a first common mode inductor, a second common mode inductor, a third common mode inductor and a fourth common mode inductor; The first common-mode inductor is connected to the first data transmission line of the USB interface; the second common-mode inductor is connected to the first data reception line of the USB interface; the third common-mode inductor is connected to the second data reception line of the USB interface; and the fourth common-mode inductor is connected to the second data transmission line of the USB interface.

6. The USB power supply circuit according to claim 1, characterized in that: The first logic chip includes a first insertion status acquisition pin and a second insertion status acquisition pin; the USB interface includes a first insertion status detection pin and a second insertion status detection pin; The first insertion status acquisition pin is connected to the first insertion status detection pin; and the second insertion status acquisition pin is connected to the second insertion status detection pin.

7. The USB power supply circuit according to claim 6, characterized in that: The USB interface includes an upper transmission data positive wiring, an upper transmission data negative wiring, an upper reception data positive wiring, a lower reception data negative wiring, a lower transmission data positive wiring, a lower transmission data negative wiring, a lower reception data positive wiring and a lower reception data negative wiring; The switching switch chip includes a switching selection pin, a first transmission data positive pin, a first transmission data negative pin, a first reception data positive pin, a first reception data negative pin, a second transmission data positive pin, a second transmission data negative pin, a second reception data positive pin, a second reception data negative pin, a third transmission data positive pin, a third transmission data negative pin, a third reception data positive pin and a third reception data negative pin; The first logic chip includes a first insertion status output pin; The first transmission data positive pin, the first transmission data negative pin, the first reception data positive pin, and the first reception data negative pin are used to be connected to the SSUSB_TXP lead, SSUSB_TXN lead, SSUSB_RXP lead, and SSUSB_RXN lead of an external plug-in device, respectively, one by one; The second transmission data positive pin, the second transmission data negative pin, the second reception data positive pin, the second reception data negative pin, and the third transmission data positive pin are respectively connected to the upper transmission data positive wiring, the upper transmission data negative wiring, the upper reception data positive wiring, and the upper reception data negative wiring in one-to-one correspondence; the third transmission data positive pin, the third transmission data negative pin, the third reception data positive pin, and the third reception data negative pin are respectively connected to the lower transmission data positive wiring, the lower transmission data negative wiring, the lower reception data positive wiring, and the lower reception data negative wiring in one-to-one correspondence; The switching selection pin of the switching switch chip is connected to the first insertion state output pin of the first logic chip.

8. The USB power supply circuit according to claim 6, characterized in that: The first logic chip includes a second insertion state output pin and a third insertion state output pin; the second logic chip includes a first power supply control pin and a second power supply control pin; The second insertion state output pin is connected to the first power supply control pin; and the third insertion state output pin is connected to the second power supply control pin.

9. The USB power supply circuit according to claim 7, characterized in that: The second logic chip includes a power switch pin; the current limiting chip includes a power enable pin; The power switch pin is connected to the power enable pin.

10. An electronic device, characterized in that: The USB power supply circuit comprises the USB power supply circuit as claimed in any one of claims 1 to 9.

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