AHB Bus Bridge with ECC Bus Function and Its Control Method

Abstract

The present invention discloses an AHB bus bridge with ECC bus function and its control method, including: an AHB bus module, which is used to generate data operation instructions, obtain data operation instructions, determine the type of data operation instructions, and transmit the transmission data corresponding to the data operation instructions according to the type of data operation instructions; an error correction and detection module, which is used to generate corresponding 8-bit ECC data according to the type of data operation instructions or perform ECC verification on the transmission data; a transmission conversion module, which is used to convert the data operation instructions into corresponding read commands of the SRAM interface protocol according to the type of data operation instructions, or merge the transmission data and the corresponding 8-bit ECC data of the transmission data and then convert them into corresponding SRAM interface protocol data. The AHB bus bridge with ECC bus function and its control method of the present application optimize the matching of the ECC bit width and the data bit width, reduce the waste of the memory area, and improve the use efficiency of the memory while ensuring the data correctness.

Description

Technical Field

[0001] The present invention relates to the technical field of digital electronic technology, and particularly to an AHB bus bridge with ECC bus function and its control method. Background Art

[0002] In digital system design, a bus bridge is used to connect buses with different protocols, enabling communication between master devices and slave devices on different buses. The AHB bus protocol introduced by ARM Corporation is widely used in high-performance systems and supports data read and write operations of different widths. To ensure the correctness of data during transmission and storage, an ECC function is usually integrated in the bus bridge. However, traditional ECC implementation methods may lead to waste of memory (such as SRAM) area because the ECC bit width does not match the data bit width. Summary of the Invention

[0003] To solve the technical problems in the background art, the present invention proposes an AHB bus bridge with ECC bus function and its control method.

[0004] The AHB bus bridge with ECC bus function proposed by the present invention includes:

[0005] An AHB bus module for generating data operation instructions, obtaining data operation instructions, determining the type of data operation instructions, and transmitting the transmission data corresponding to the data operation instructions according to the type of data operation instructions; the data operation instructions include Word 32bit write data action, byte 8bit / halfword 16bit write data action, read data action; the transmission data includes Word 32bit write data, byte 8bit / halfword 16bit write data, read data;

[0006] An error correction and detection module for generating corresponding 8bit ECC data according to the type of data operation instructions or performing ECC verification on the transmission data;

[0007] A transmission conversion module for converting the data operation instructions into corresponding read commands of the SRAM interface protocol according to the type of data operation instructions or merging the transmission data and the corresponding 8bit ECC data of the transmission data and converting them into corresponding SRAM interface protocol data;

[0008] An output module for obtaining the Mbist control status and writing the SRAM interface protocol data into the data storage module based on the Mbist control status, and the Mbist control status includes control enable and control disable;

[0009] A data storage module, configured to store the written transmission data and read out the written transmission data according to a read command of the SRAM interface protocol.

[0010] Preferably, the transmission of the transmission data corresponding to the data operation instruction according to the type of the data operation instruction specifically includes:

[0011] When the data operation instruction is specifically a Word 32-bit write data operation, the transmission path is specifically to transmit the data operation instruction and the transmission data to the error correction and detection module;

[0012] When the data operation instruction is specifically a byte 8-bit / halfword 16-bit write data operation, the transmission path is specifically to transmit the data operation instruction and the transmission data to the error correction and detection module;

[0013] When the data operation instruction is specifically a read data operation, the transmission path is specifically to transmit the data operation instruction to the transmission conversion module.

[0014] Preferably, the error correction and detection module specifically includes:

[0015] The ENC unit is configured to generate corresponding 8-bit ECC data when the received data operation instruction is specifically a Word 32-bit write data operation, and merge the Word 32-bit write data and the 8-bit ECC data and transmit them to the transmission conversion module;

[0016] The DEC unit is configured to receive the read data transmitted by the data storage module when the data operation instruction is specifically a read data operation, and perform ECC verification on the transmission data. When an ECC verification error occurs, an ECC error flag is generated; when the ECC verification data is correct, the correct read data is returned to the AHB bus module;

[0017] The FSM unit is configured to perform a read operation on the data storage module when the data operation instruction is specifically a byte 8-bit / halfword 16-bit write data operation to obtain a group of 32-bit data, and perform data replacement on the group of 32-bit data according to the position of the byte 8-bit write data or the position of the halfword 16-bit write data to generate corresponding first-type 32-bit data, and transmit the first-type 32-bit data to the ENC unit;

[0018] The ENC unit is further configured to generate corresponding 8-bit ECC data according to the first-type 32-bit data, and merge the first-type 32-bit data and the corresponding 8-bit ECC data and transmit them to the transmission conversion module.

[0019] Preferably, the transmission conversion module specifically includes:

[0020] An instruction conversion unit, which is used to convert a data operation instruction into a read command of the corresponding SRAM interface protocol when the data operation instruction is specifically a read data operation;

[0021] A data conversion unit, which is used to convert the merged transmission data and the corresponding 8-bit ECC data of the transmission data into corresponding SRAM interface protocol data when the data operation instruction is specifically a Word 32-bit write data operation;

[0022] The data conversion unit is also used to convert the merged first type of data and the corresponding 8-bit ECC data of the first type of data into corresponding SRAM interface protocol data when the data operation instruction is specifically a byte 8-bit / halfword 16-bit write data operation.

[0023] Preferably, writing the SRAM interface protocol data into the data storage module based on the Mbist control state specifically includes:

[0024] When the Mbist control state is specifically control enabled, writing the SRAM interface protocol data into the data storage module after passing the SRAM DFT correctness test;

[0025] When the Mbist control state is specifically control not enabled, directly writing the SRAM interface protocol data into the data storage module.

[0026] The AHB bus bridge control method with ECC bus function proposed by the present invention, this control method is applied to the AHB bus bridge with ECC bus function described in any one of the above, and this control method includes the following steps:

[0027] S1. Obtain a data operation instruction, determine the type of the data operation instruction, and transmit the transmission data corresponding to the data operation instruction according to the type of the data operation instruction. The data operation instruction includes a Word 32-bit write data operation, a byte 8-bit / halfword 16-bit write data operation, and a read data operation;

[0028] S2. Generate corresponding 8-bit ECC data according to the type of the data operation instruction or perform ECC verification on the transmission data;

[0029] S3. Convert the data operation instruction into a corresponding read command of the SRAM interface protocol according to the type of the data operation instruction or convert the result of merging the transmission data and the corresponding 8-bit ECC data of the transmission data into corresponding SRAM interface protocol data;

[0030] S4. Obtain the Mbist control status, and write the SRAM interface protocol data into the data storage module based on the Mbist control status. The Mbist control status includes control enable and control disable.

[0031] Preferably, when the data operation instruction is specifically a Word 32bit write data operation, step S2 specifically includes:

[0032] Generate 8bit ECC data corresponding to the Word 32bit write data, and merge the Word 32bit write data with the corresponding 8bit ECC data;

[0033] When the data operation instruction is specifically a byte 8bit / halfword 16bit write data operation, step S2 specifically includes: perform a read operation on the data storage module to obtain a set of 32bit data, perform data replacement on the set of 32bit data according to the position of the byte 8bit write data or the position of the halfword 16bit write data to generate corresponding first-type 32bit data, generate corresponding 8bit ECC data according to the first-type 32bit data, and merge the first-type 32bit data with the corresponding 8bit ECC data;

[0034] When the data operation instruction is specifically a read data operation, step S2 specifically includes: perform ECC verification on the transmitted data, generate an ECC error flag when the ECC verification fails; when the ECC verification data is correct, execute step S3.

[0035] Preferably, when the data operation instruction is specifically a Word 32bit write data operation, step S3 specifically includes:

[0036] Convert the result of merging the Word 32bit write data with the corresponding 8bit ECC data into corresponding SRAM interface protocol data;

[0037] When the data operation instruction is specifically a byte 8bit / halfword 16bit write data operation, step S3 specifically includes: convert the result of merging the first-type 32bit data with the corresponding 8bit ECC data into corresponding SRAM interface protocol data;

[0038] When the data operation instruction is specifically a read data operation, step S3 specifically includes: convert the read data operation into a read command corresponding to the SRAM interface protocol.

[0039] Preferably, when the data operation instruction is specifically a Word 32bit write data operation or a byte 8bit / halfword16bit write data operation, step S4 specifically includes:

[0040] When the Mbist control state is specifically control enabled, the SRAM interface protocol data is written into the data storage module after passing the SRAM DFT correctness test.

[0041] When the Mbist control state is specifically control disabled, the SRAM interface protocol data is directly written into the data storage module.

[0042] In the present invention, the proposed AHB bus bridge with ECC bus function and its control method obtain data operation instructions, determine the types of data operation instructions, and transmit the transmission data corresponding to the data operation instructions according to the types of data operation instructions. The data operation instructions include Word 32bit write data action, byte 8bit / halfword 16bit write data action, and read data action; according to the types of data operation instructions, corresponding 8bit ECC data is generated or ECC verification is performed on the transmission data; according to the types of data operation instructions, the data operation instructions are converted into corresponding read commands of the SRAM interface protocol, or the result of merging the transmission data and the corresponding 8bit ECC data of the transmission data is converted into corresponding SRAM interface protocol data; the Mbist control state is obtained, and the SRAM interface protocol data is written into the data storage module based on the Mbist control state. The Mbist control state includes control enabled and control disabled. By optimizing the matching of the ECC bit width and the data bit width, the waste of the memory area is reduced, while the correctness of the data is ensured, and the use efficiency of the memory is improved. Description of the Drawings

[0043] Figure 1 It is a schematic diagram of the system architecture of the AHB bus bridge with ECC bus function proposed by the present invention;

[0044] Figure 2 It is a schematic diagram of the working process structure of the control method of the AHB bus bridge with ECC bus function proposed by the present invention. Detailed Embodiment

[0045] Referring to Figure 1 and Figure 2 The AHB bus bridge with ECC bus function proposed by the present invention includes:

[0046] The AHB bus module is used to generate data operation instructions, obtain data operation instructions, determine the types of data operation instructions, and transmit the transmission data corresponding to the data operation instructions according to the types of data operation instructions; the data operation instructions include Word 32-bit write data actions, byte 8-bit / halfword 16-bit write data actions, and read data actions; the transmission data includes Word 32-bit write data, byte 8-bit / halfword 16-bit write data, and read data.

[0047] In this embodiment, transmitting the transmission data corresponding to the data operation instruction according to the type of the data operation instruction specifically includes:

[0048] When the data operation instruction is specifically a Word 32-bit write data action, the transmission path is specifically to transmit the data operation instruction and the transmission data to the error correction and detection module;

[0049] When the data operation instruction is specifically a byte 8-bit / halfword 16-bit write data action, the transmission path is specifically to transmit the data operation instruction and the transmission data to the error correction and detection module;

[0050] When the data operation instruction is specifically a read data action, the transmission path is specifically to transmit the data operation instruction to the transmission conversion module.

[0051] The error correction and detection module is used to generate corresponding 8-bit ECC data or perform ECC verification on the transmission data according to the type of the data operation instruction. Among them, ECC (Error Checking and Correcting) represents error checking and correction.

[0052] In this embodiment, the error correction and detection module specifically includes:

[0053] The ENC unit is used to generate corresponding 8-bit ECC data when the received data operation instruction is specifically a Word 32-bit write data action, and merge and transmit the Word 32-bit write data and the 8-bit ECC data to the transmission conversion module. Among them, the ENC unit represents the encoding unit.

[0054] The DEC unit is used to receive the read data transmitted by the data storage module and perform ECC verification on the transmission data when the data operation instruction is specifically a read data action. When an ECC verification error occurs, an ECC error flag is generated; when the ECC verification data is correct, the correct read data is returned to the AHB bus module. Among them, the DEC unit represents the decoding unit.

[0055] The FSM unit is used to perform a read operation on the data storage module when the data operation instruction is specifically a byte 8-bit / halfword 16-bit write data action, so as to obtain a set of 32-bit data. According to the position of the byte 8-bit write data or the position of the halfword 16-bit write data, data replacement is performed on the set of 32-bit data to generate corresponding first-type 32-bit data, and the first-type 32-bit data is transmitted to the ENC unit. Herein, the FSM unit represents a finite state machine unit.

[0056] The ENC unit is further used to generate corresponding 8-bit ECC data according to the first-type 32-bit data, and transmit the first-type 32-bit data and the corresponding 8-bit ECC data to the transmission conversion module in a combined manner.

[0057] The transmission conversion module is used to convert the data operation instruction into a corresponding read command of the SRAM interface protocol according to the type of the data operation instruction, or convert the transmitted data and the corresponding 8-bit ECC data of the transmitted data into corresponding SRAM interface protocol data after combination.

[0058] In this embodiment, the transmission conversion module specifically includes:

[0059] The instruction conversion unit is used to convert the data operation instruction into a corresponding read command of the SRAM interface protocol when the data operation instruction is specifically a read data action.

[0060] The data conversion unit is used to convert the combined transmitted data and the corresponding 8-bit ECC data of the transmitted data into corresponding SRAM interface protocol data when the data operation instruction is specifically a Word 32-bit write data action.

[0061] The data conversion unit is further used to convert the combined first-type data and the corresponding 8-bit ECC data of the first-type data into corresponding SRAM interface protocol data when the data operation instruction is specifically a byte 8-bit / halfword 16-bit write data action.

[0062] The output module is used to obtain the Mbist control status, and write the SRAM interface protocol data into the data storage module based on the Mbist control status. The Mbist control status includes control enable and control disable.

[0063] In this embodiment, the SRAM interface protocol data is written into the data storage module based on the Mbist control state, which specifically includes: when the Mbist control state is specifically control enabled, the SRAM interface protocol data is written into the data storage module after passing the SRAM DFT correctness test. When the Mbist control state is specifically control disabled, the SRAM interface protocol data is directly written into the data storage module.

[0064] In this embodiment, the SRAM DFT correctness test is performed through the Mbist (Memory Bulk-in Self-Test) control module. In addition to the DFT machine test, this module also supports users to perform the correctness test on the SRAM in a software manner. The enabling of this module cannot complete the data transmission of normal functions, and this module is only used to separately test whether there are defects in the SRAM production process.

[0065] The data storage module is used to store the written transmission data and read out the written transmission data according to the read command of the SRAM interface protocol.

[0066] The write data processing flow is as follows:

[0067] 1) If a Word 32bit write data operation occurs on the AHB bus, first the data will enter the ENC unit to generate 8bit ECC data. The Word 32bit and the 8bit ECC result are merged together and then enter the transmission conversion module, which converts the data of the AHB interface protocol into the SRAM interface protocol data. If the Mbist control module is not enabled, it is directly output to the inside of the data storage module through the transmission conversion module. At this time, the operation of writing to the SRAM through the AHB interface and adding ECC is completed. If the Mbist control module is enabled, the data in the data storage module comes from the Mbist control module, and the data can be random numbers, all 0s, or all 1s. The bus bridge we designed also supports passing the SRAM Mbist test.

[0068] 2) If a byte 8bit / halfword 16bit write data operation occurs on the AHB bus, first a read operation needs to be performed on the SRAM to read out 32bit data. According to the position of the byte 8bit (4 byte positions in the 32bit data) or halfword 16bit (2 halfword positions in the 32bit data) to be written, a new 32bit data is generated, and a new 8bit ECC result is generated using the new 32bit data. The subsequent writing process is the same as the 32bit write data process.

[0069] The read data processing flow is as follows:

[0070] If a read data operation occurs on the AHB bus, the read command, read address, and other information of the AHB bus will be converted into a read command of the SRAM interface protocol through the transmission conversion module. At this time, the SRAM will return 40-bit data (32-bit valid data + 8-bit ECC data). The 40-bit data is subjected to ECC verification by the DEC unit. If an error occurs, an ECC Error flag will be generated. Otherwise, if the data is correct, the correct read data will be returned to the AHB bus.

[0071] In this embodiment, when the AHB bus bridge performs a Byte / halfword write operation, it needs to perform a read-before-write operation, which takes 3 cycles, 1 cycle more than the ordinary byte write operation (2 cycles). If it is a Memory write Byte / halfword operation, it needs to take 4 cycles, 2 cycles more than the ordinary byte write operation (2 cycles). This saves the Memory area, and at the same time, the ECC function ensures the correctness of the data.

[0072] Referring to Figure 1 and Figure 2 , the AHB bus bridge control method with ECC bus function proposed by the present invention is applied to the AHB bus bridge with ECC bus function in any of the above items. The control method includes the following steps:

[0073] S1. Obtain a data operation instruction, determine the type of the data operation instruction, and transmit the transmission data corresponding to the data operation instruction according to the type of the data operation instruction. The data operation instruction includes a Word 32-bit write data operation, a byte 8-bit / halfword 16-bit write data operation, and a read data operation.

[0074] S2. Generate corresponding 8-bit ECC data according to the type of the data operation instruction or perform ECC verification on the transmission data.

[0075] In this embodiment, when the data operation instruction is specifically a Word 32-bit write data operation, step S2 specifically includes:

[0076] Generate 8-bit ECC data corresponding to the Word 32-bit write data, and merge the Word 32-bit write data with the corresponding 8-bit ECC data;

[0077] When the data operation instruction is specifically a byte 8-bit / halfword 16-bit write data operation, step S2 specifically includes: performing a read operation on the data storage module to obtain a set of 32-bit data, replacing the data in the set of 32-bit data according to the position of the byte 8-bit write data or the position of the halfword 16-bit write data to generate corresponding first-type 32-bit data, generating corresponding 8-bit ECC data based on the first-type 32-bit data, and merging the first-type 32-bit data with the corresponding 8-bit ECC data.

[0078] When the data operation instruction is specifically a read data operation, step S2 specifically includes: performing an ECC check on the transmitted data, generating an ECC error flag when the ECC check fails; when the ECC check data is correct, executing step S3.

[0079] S3. Convert the data operation instruction into a read command of the corresponding SRAM interface protocol according to the type of the data operation instruction, or convert the result of merging the transmitted data and the corresponding 8-bit ECC data of the transmitted data into the corresponding SRAM interface protocol data.

[0080] In this embodiment, when the data operation instruction is specifically a Word 32-bit write data operation, step S3 specifically includes:

[0081] Converting the result of merging the Word 32-bit write data and the corresponding 8-bit ECC data into the corresponding SRAM interface protocol data;

[0082] When the data operation instruction is specifically a byte 8-bit / halfword 16-bit write data operation, step S3 specifically includes: converting the result of merging the first-type 32-bit data and the corresponding 8-bit ECC data into the corresponding SRAM interface protocol data;

[0083] When the data operation instruction is specifically a read data operation, step S3 specifically includes: converting the read data operation into a read command of the corresponding SRAM interface protocol.

[0084] S4. Obtain the Mbist control status, and write the SRAM interface protocol data into the data storage module based on the Mbist control status. The Mbist control status includes control enabled and control disabled.

[0085] In this embodiment, when the data operation instruction is specifically a Word 32-bit data write operation or a byte 8-bit / halfword 16-bit data write operation, step S4 specifically includes: when the Mbist control state is specifically control enabled, writing the SRAM interface protocol data into the data storage module after passing the SRAM DFT correctness test; when the Mbist control state is specifically control disabled, directly writing the SRAM interface protocol data into the data storage module.

[0086] The above is only a preferred specific embodiment of the present invention, but the protection scope of the present invention is not limited thereto. Any person skilled in the art within the technical scope disclosed by the present invention, according to the technical solution and inventive concept of the present invention, making equivalent substitutions or changes, shall be covered by the protection scope of the present invention.

Claims

1. AHB bus bridge with ECC bus function, characterized in that: include: AHB bus module, used for generating data operation instructions, obtaining data operation instructions, determining the type of data operation instructions, and transmitting the transmission data corresponding to the data operation instructions according to the type of data operation instructions; data operation instructions include Word 32bit write data action, byte 8bit / halfword 16bit write data action, and read data action; transmission data includes Word 32bit write data, byte 8bit / halfword 16bit write data, and read data; The error correction and detection module is used to generate corresponding 8-bit ECC data or perform ECC check on the transmitted data according to the type of data operation instruction; A transmission conversion module, used to convert the data operation instruction into a corresponding SRAM interface protocol read command according to the type of the data operation instruction or to merge the transmission data and the 8-bit ECC data corresponding to the transmission data and convert them into corresponding SRAM interface protocol data; The output module is used to obtain the Mbist control state and write the SRAM interface protocol data into the data storage module based on the Mbist control state. The Mbist control state includes control enable and control disable. A data storage module, used for storing written transmission data and reading out the written transmission data according to a read command of the SRAM interface protocol; The output module is used to configure the SRAM interface protocol data to be all 0, all 1 or random number mode and write it into the data storage module when the Mbist control state is enabled.

2. The AHB bus bridge with ECC bus function according to claim 1, characterized in that: The transmitting of the transmission data corresponding to the data operation instruction according to the type of the data operation instruction specifically includes: When the data operation instruction is specifically a Word 32bit write data action, the transmission path is specifically to transmit the data operation instruction and the transmission data to the error correction and detection module; When the data operation instruction is specifically a byte 8bit / halfword 16bit write data action, the transmission path is specifically to transmit the data operation instruction and the transmission data to the error correction and detection module; When the data operation instruction is specifically a data read operation, the transmission path is specifically to transmit the data operation instruction to the transmission conversion module.

3. The AHB bus bridge with ECC bus function according to claim 1, characterized in that: The error correction and detection module specifically includes: The ENC unit is used for generating corresponding 8-bit ECC data when the received data operation instruction is specifically a Word 32-bit write data action, and combining the Word 32-bit write data with the 8-bit ECC data and transmitting them to the transmission conversion module; The DEC unit is used to receive the read data transmitted by the data storage module when the data operation instruction is specifically a read data action, and perform ECC check on the transmitted data. When an error occurs in the ECC check, an ECC error flag is generated; when the ECC check data is correct, the correct read data is returned to the AHB bus module; The FSM unit is used for, when the data operation instruction is specifically a byte 8-bit / halfword 16-bit write data action, performing a read operation on the data storage module to obtain a group of 32-bit data, performing data replacement on the group of 32-bit data according to a position of the byte 8-bit write data or a position of the halfword 16-bit write data to generate corresponding first-type 32-bit data, and transmitting the first-type 32-bit data to the ENC unit; The ENC unit is further used to generate corresponding 8-bit ECC data according to the first type 32-bit data, and combine the first type 32-bit data and the corresponding 8-bit ECC data and transmit them to the transmission conversion module.

4. The AHB bus bridge with ECC bus function according to claim 3, characterized in that: The transmission conversion module specifically includes: An instruction conversion unit, used for converting the data operation instruction into a read command of a corresponding SRAM interface protocol when the data operation instruction is specifically a data read action; A data conversion unit, used for converting the combined transmission data and the 8-bit ECC data corresponding to the transmission data into corresponding SRAM interface protocol data when the data operation instruction is specifically a Word 32-bit write data action; The data conversion unit is also used to convert the merged first type data and the 8-bit ECC data corresponding to the first type data into corresponding SRAM interface protocol data when the data operation instruction is specifically a byte 8-bit / halfword 16-bit data write action.

5. The AHB bus bridge with ECC bus function according to claim 1, characterized in that: The step of writing the SRAM interface protocol data into the data storage module based on the Mbist control state specifically includes: When the Mbist control state is specifically control enabled, the SRAM interface protocol data is written into the data storage module after being tested for correctness by the SRAM DFT; When the Mbist control state is specifically control disabled, the SRAM interface protocol data is directly written into the data storage module.

6. AHB bus bridge control method with ECC bus function, characterized in that: The control method is applied to the AHB bus bridge with ECC bus function as claimed in any one of claims 1 to 5, and the control method comprises the following steps: S1. Obtain a data operation instruction, determine the type of the data operation instruction, and transmit the transmission data corresponding to the data operation instruction according to the type of the data operation instruction. The data operation instruction includes a word 32-bit write data action, a byte 8-bit / halfword 16-bit write data action, and a read data action; S2. Generate corresponding 8-bit ECC data or perform ECC check on the transmitted data according to the type of data operation instruction; S3, converting the data operation instruction into a corresponding SRAM interface protocol read command according to the type of the data operation instruction or converting the result of merging the transmission data and the 8-bit ECC data corresponding to the transmission data into corresponding SRAM interface protocol data; S4, obtaining the Mbist control state, and writing the SRAM interface protocol data into the data storage module based on the Mbist control state, the Mbist control state including control enabled and control disabled; When the Mbist control state is enabled, the SRAM interface protocol data is configured as all 0s, all 1s, or random number mode and written into the data storage module.

7. The AHB bus bridge control method with ECC bus function according to claim 6, characterized in that: When the data operation instruction is specifically a Word 32bit write data action, step S2 specifically includes: Generate 8-bit ECC data corresponding to the Word 32-bit write data, and merge the Word 32-bit write data with the corresponding 8-bit ECC data; When the data operation instruction is specifically a byte 8-bit / halfword 16-bit write data action, step S2 specifically includes: performing a read operation on the data storage module to obtain a group of 32-bit data, performing data replacement on the group of 32-bit data according to the position of the byte 8-bit write data or the position of the halfword 16-bit write data to generate corresponding first-type 32-bit data, generating corresponding 8-bit ECC data according to the first-type 32-bit data, and merging the first-type 32-bit data with the corresponding 8-bit ECC data; When the data operation instruction is specifically a data read action, step S2 specifically includes: performing ECC check on the transmitted data, and when an ECC check error occurs, generating an ECC error flag; when the ECC check data is correct, executing step S3.

8. The AHB bus bridge control method with ECC bus function according to claim 7, characterized in that: When the data operation instruction is specifically a Word 32bit write data action, step S3 specifically includes: The result of merging Word 32-bit write data and corresponding 8-bit ECC data is converted into corresponding SRAM interface protocol data; When the data operation instruction is specifically a byte 8bit / halfword 16bit write data action, step S3 specifically includes: converting the result of combining the first type 32bit data and the corresponding 8bitECC data into corresponding SRAM interface protocol data; When the data operation instruction is specifically a data read action, step S3 specifically includes: converting the data read action into a corresponding read command of the SRAM interface protocol.

9. The AHB bus bridge control method with ECC bus function according to claim 8, characterized in that: When the data operation instruction is specifically a Word 32-bit write data action or a byte 8-bit / halfword 16-bit write data action, step S4 specifically includes: When the Mbist control state is specifically control enabled, the SRAM interface protocol data is written into the data storage module after being tested for correctness by the SRAM DFT; When the Mbist control state is specifically control disabled, the SRAM interface protocol data is directly written into the data storage module.

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