Discrete cosine transform processing device and discrete cosine transform processing method
By disassembling the discrete cosine transformation matrix into an operation matrix and a permutation matrix, using low-dimensional matrix multiplication operation, the problems of high hardware cost and low resource utilization efficiency in the prior art are solved, and efficient discrete cosine transformation processing is achieved.
Patent Information
- Application Number
- CN202411885438.2
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2024-12-19
- Publication Date
- 2025-03-28
AI Technical Summary
When performing discrete cosine transformations, the prior art requires a large number of multipliers, resulting in high hardware costs and high computational costs. When the input data dimensions change, the hardware structure cannot be flexibly adjusted, resulting in low resource utilization efficiency.
By disassembling the discrete cosine transformation matrix into an operation matrix and a permutation matrix, low-dimensional matrix multiplication operation is used, combined with an adder and multiplication and accumulation operation circuit, discrete cosine transformation processing is realized.
It reduces hardware costs, improves computing efficiency and resource utilization efficiency, and can flexibly adjust the hardware structure to adapt to changes in different input data dimensions.
Smart Images
Figure CN119719592A_ABST
Abstract
Description
Technical Field
[0001] The present application relates to the field of image processing technology, and in particular to a discrete cosine transform processing device and a discrete cosine transform processing method. Background Art
[0002] Discrete cosine transform is often used in the field of image processing or video encoding and decoding. In the prior art, a large number of multipliers are used to perform matrix multiplication operations in discrete cosine transform, which requires a lot of cost in hardware implementation, and multiple multiplication operations need to be performed, resulting in an excessively high overall amount of calculation. On the other hand, in the prior art, another architecture is to first use the parity symmetry characteristics in the discrete cosine transform matrix to simplify the amount of calculation, but this architecture requires pre-setting multiple multipliers that can perform matrix multiplication operations of different dimensions. If the application requirements change (for example, the number of dimensions of the input data increases, etc.), the hardware structure under this architecture cannot be flexibly adjusted, resulting in a decrease in the overall resource utilization efficiency. Summary of the invention
[0003] One of the purposes of the present application is to provide a discrete cosine transform processing device and a discrete cosine transform processing method that can use low-dimensional matrix multiplication operations to perform discrete cosine transforms, so as to improve the deficiencies of the prior art.
[0004] In some embodiments, a discrete cosine transform processing device includes an adder, a register, a plurality of multiplication-accumulation operation circuits, an accumulator, an operation control circuit, and an output circuit. The adder processes a first input data according to a first permutation matrix to generate a second input data. The register stores an operation matrix. The operation control circuit configures the plurality of multiplication-accumulation operation circuits and the accumulator according to a matrix multiplication operation corresponding to a unit dimension, so as to multiply the operation matrix and the second input data through the plurality of multiplication-accumulation operation circuits and the accumulator, thereby generating a first operation result. The output circuit processes the first operation result according to a second permutation matrix to generate a second operation result, wherein the first permutation matrix, the operation matrix, and the second permutation matrix are decomposed from a discrete cosine transform matrix.
[0005] In some embodiments, a discrete cosine transform processing method performed by a processing device includes the following operations: processing a first input data according to a first permutation matrix to generate a second input data; configuring a plurality of multiplication-accumulation operation circuits and an accumulator in the processing device according to a matrix multiplication operation corresponding to a unit dimension, so as to multiply an operation matrix with the second input data through the plurality of multiplication-accumulation operation circuits and the accumulator to generate a first operation result; and processing the first operation result according to a second permutation matrix to generate a second operation result, wherein the first permutation matrix, the operation matrix and the second permutation matrix are decomposed from a discrete cosine transform matrix.
[0006] The features, implementation and effects of the present application are described in detail below with reference to the accompanying drawings. BRIEF DESCRIPTION OF THE DRAWINGS
[0007] Figure 1 A schematic diagram of a discrete cosine transform processing device 100 is drawn according to some embodiments of the present application;
[0008] Figure 2 According to some embodiments of the present application, Figure 1 A flowchart of related operations of a discrete cosine transform processing device;
[0009] Figure 3 According to some embodiments of the present application, Figure 2 Flowchart of the two operations in ;
[0010] Figure 4 According to some embodiments of the present application, Figure 1 Schematic diagram of the multiplication and accumulation circuit;
[0011] Figure 5 According to some embodiments of the present application, Figure 2 A flowchart of the two operations in ; and
[0012] Figure 6 A flowchart of a discrete cosine transform processing method is drawn according to some embodiments of the present application.
[0013] Reference numerals:
[0014] 100: discrete cosine transform processing device;
[0015] 110: adder;
[0016] 120: Select circuit;
[0017] 125: register;
[0018] 130: multiplication and accumulation circuit;
[0019] 140: accumulator;
[0020] 150: operation control circuit;
[0021] 160: output circuit;
[0022] 401-408: multiplier;
[0023] 411~414: adder;
[0024] 600: Discrete cosine transform processing method;
[0025] A: operation matrix;
[0026] DIN, S: input data;
[0027] P l , P r : permutation matrix;
[0028] R1, R2: operation results;
[0029] s11, s12, s13, s14, d11, d31, d32, t11, t12, t21, t22: elements;
[0030] S210, S220, S230, S240, S250, S260: operation;
[0031] S301, S302, S303, S501, S502, S503, S504: steps;
[0032] S610, S620, S630: operation. DETAILED DESCRIPTION
[0033] All words used herein have their ordinary meanings. The definitions of the above words in commonly used dictionaries, including any use examples of the words discussed herein in the content of this application are only examples and should not limit the scope and meaning of this application. Similarly, this application is not limited to the various embodiments shown in this specification.
[0034] As used herein, "coupled" or "connected" may refer to two or more elements making direct physical or electrical contact with each other, or making indirect physical or electrical contact with each other, or may refer to two or more elements operating or acting on each other. As used herein, the term "circuit" may refer to a device composed of at least one transistor and / or at least one active and passive element connected in a certain manner to process signals.
[0035] Some embodiments of the present application are about processing devices and methods based on discrete cosine transform (DCT). Discrete cosine transform is commonly used in applications such as image processing and video encoding and decoding. For example, discrete cosine transform can be used to compress images or videos, reduce noise, extract features, reconstruct images, etc. Therefore, the processing devices and methods provided in some embodiments of the present application can also be used in the above-mentioned application fields, but the present application is not limited thereto.
[0036] In order to better understand the embodiments of the present application, the mathematical concept of discrete cosine transform will be briefly described below, and the relevant operations and settings of the embodiments of the present application will be illustrated later.
[0037] If expressed in matrix form, the mathematical formula of discrete cosine transform can be expressed as the following formula (1):
[0038]
[0039] Where Y is the output after discrete cosine transform processing, X is the input data, and D is the discrete cosine transform matrix. Based on the mathematical formula (1) of the discrete cosine transform matrix, the discrete cosine transform matrix D can be further derived as follows:
[0040]
[0041] In some embodiments, the discrete cosine transform processing device and method proposed in the present application can perform discrete cosine transform by disassembling the discrete cosine transform matrix D in the above formula, thereby improving the hardware processing efficiency and resource utilization efficiency of the overall system under the same computing power, so as to bring clear improvements to technical fields such as image processing, video encoding and decoding.
[0042] Figure 1 A schematic diagram of a discrete cosine transform processing device 100 is drawn according to some embodiments of the present application. In some embodiments, the discrete cosine transform processing device 100 may be implemented by hardware, for example, the discrete cosine transform processing device 100 may be implemented as an integrated circuit.
[0043] The DCT processing apparatus 100 includes an adder 110 , a selection circuit 120 , a register 125 , a multiply accumulate (MAC) circuit 130 , an accumulator 140 , an operation control circuit 150 , and an output circuit 160 .
[0044] Adder 110 is based on the permutation matrix P r The input data DIN is processed to generate input data S. In some embodiments, the permutation matrix P rAll elements in can only take the value of 0, 1 or -1. In this way, operations such as addition and subtraction can be used to implement the permutation matrix P r The operation of processing the input data DIN does not require the use of circuits such as multipliers to perform the permutation matrix P r The operation when processing the input data DIN can reduce the hardware cost.
[0045] The selection circuit 120 selects a corresponding operation matrix A from a plurality of preset operation matrices A according to the current processing requirements, and stores the correlation coefficient of the operation matrix A in the register 125. For example, the selection circuit 120 may select the operation matrix A according to the dimension number of the input data DIN.
[0046] The operation control circuit 150 configures a plurality of multiplication-accumulation operation circuits 130 and an accumulator 140 according to the matrix multiplication operation corresponding to the unit dimension, so as to multiply the operation matrix A and the input data S through the plurality of multiplication-accumulation operation circuits 130 and the accumulator 140, thereby generating an operation result R1. In some embodiments, the matrix multiplication operation corresponding to the unit dimension is based on the basic circuit unit corresponding to the multiplication-accumulation operation circuit 130.
[0047] The output circuit 160 is based on the permutation matrix P l The operation result R1 is processed to generate the operation result R2. In some embodiments, the operation result R2 may be the output of the input data DIN after the discrete cosine transform is performed. For example, the input data DIN is equivalent to the input data X in formula (1), and the operation result R2 is equivalent to the output Y in formula (1). In some embodiments, the permutation matrix P l All elements in can only take the value of 0 or 1. In this way, operations such as addition and subtraction can be used to implement the permutation matrix P l The operation does not require a multiplier or other circuit to perform the permutation matrix P l In some embodiments, the output circuit 160 may be an adder, which can equivalently multiply the permutation matrix P by addition and subtraction operations. l The output circuit 160 includes a buffer that can generate an operation result R2 according to the permutation matrix P. l The output order of the related elements in the operation result R1 is adjusted according to the corresponding elements in the operation result R1, and the operation result R1 is output as the operation result R2 according to the output order.
[0048] In some embodiments, the permutation matrix P r , permutation matrix P l In some embodiments, the operation matrix A, the permutation matrix P r and the permutation matrix Pl The permutation matrix P can be decomposed from the discrete cosine transform matrix D of formula (1). For example, the permutation matrix P can be predetermined by mathematical simulation software (such as, but not limited to, MATLAB) executed on a computer. r , permutation matrix P l Related data information such as multiple operation matrices A, etc., so that these data information are stored in the discrete cosine transform processing device 100 in advance.
[0049] The following will explain the offline generation of the permutation matrix P r , permutation matrix P l An embodiment of data information related to a plurality of operation matrices A, etc. As previously described, the operation matrix A, the permutation matrix P r and the permutation matrix P l It can be decomposed from the discrete cosine transform matrix D of formula (1). Specifically, the operation matrix A and the permutation matrix P r and the permutation matrix P l The product of is the discrete cosine transform matrix D, which can be expressed as the following formula (2):
[0050] D=P l ×A×P r (2);
[0051] Please refer to the attachment at the end of the article, which shows a method for determining the operation matrix A and the permutation matrix P according to an embodiment of the present application. r and the permutation matrix P l The algorithm can be executed by, but not limited to, the aforementioned mathematical simulation software. This algorithm mainly includes several steps. The first step is initialization: the permutation matrix P r and the permutation matrix P l are set to zero matrices of dimension N×N, where N is the dimension of the input data DIN; the second step is the first layer loop, from the value i to L-1, where L is the unit dimension mentioned above, and the permutation matrix P is set by this value. r and the permutation matrix P l The third step is the second layer of loop, which is m from log2(L) to log2(N)-1, then i from 0 to n-1, and finally j from 0 to n-1 to fill the permutation matrix P r and the permutation matrix P l The remaining elements in; and the fourth step is based on the permutation matrix P r The inverse matrix and permutation matrix P l The inverse matrix of and the discrete cosine matrix D set the operation matrix A.
[0052] In some embodiments, the discrete cosine transform processing device 100 may use formula (2) to complete the discrete cosine transform operation of formula (1), and the operation flow may be derived in sequence as shown in the following formula (3):
[0053] Y=D×X=P l ×A×P r ×X=P l ×A×S=P l ×T(3);
[0054] Among them, Y is equivalent to the operation result R2, X is equivalent to the input data DIN, S is the input data S (which is the product of the permutation matrix and the input data DIN), and T is the product of the operation matrix A and the input data S (which is equivalent to the operation result R1). The detailed operation and setting method will be described later with reference to other figures.
[0055] Figure 2 According to some embodiments of the present application, Figure 1 Flow chart of the related operations performed by the discrete cosine transform processing device 100. In operation S210, the adder 110 performs the operation according to the permutation matrix P r Process the input data DIN to generate input data S. In operation S220, the selection circuit 120 selects the corresponding operation matrix A according to the number of dimensions of the input data DIN, and stores the operation matrix A in the register 125. In operation S230, the operation control circuit 150 determines the matrix multiplication operation corresponding to the unit dimension according to the operation matrix A, and configures multiple multiplication and accumulation operation circuits 130 and the accumulator 140 according to the matrix multiplication operation. In operation S240, the multiple multiplication and accumulation operation circuits 130 and the accumulator 140 multiply the operation matrix A with the input data S to generate the operation result R1. In operation S250, the operation control circuit 150 confirms whether the operations of the multiple multiplication and accumulation operation circuits 130 and the accumulator 140 have been completed. If so, operation S260 is executed. If not, operation S240 is continued. In operation S260, the output circuit 160 determines the matrix multiplication operation corresponding to the unit dimension according to the operation matrix A, and configures multiple multiplication and accumulation operation circuits 130 and the accumulator 140 according to the matrix multiplication operation. l The operation result R1 is processed to generate an operation result R2.
[0056] In some embodiments, the aforementioned unit dimension is determined by a multiply-accumulate operation circuit that can perform matrix multiplication of the smallest dimension among the plurality of multiply-accumulate operation circuits 130. For example, if each of the plurality of multiply-accumulate operation circuits 130 is implemented by a multiply-accumulate operation circuit that can perform 2×2 matrix multiplication, then the matrix multiplication operation corresponding to the unit dimension L (or the smallest dimension) is 2×2 matrix multiplication, and the unit dimension is 2.
[0057] For example, if the dimension number N of the input data DIN is 4 and the unit dimension L is 2, each of the plurality of multiply-accumulate operation circuits 130 is a multiply-accumulate operation circuit that performs 2×2 matrix multiplication as a basic circuit unit. Under this condition, the input data DIN can be expressed as the following formula:
[0058]
[0059] Accordingly, the discrete cosine transform matrix D can be expressed as the following formula:
[0060]
[0061] Furthermore, according to the symmetric property of the discrete cosine transform matrix D, the discrete cosine transform matrix D in the above formula can be further re-expressed as the following formula:
[0062]
[0063] Through the operation of the attachment, we can deduce the operation matrix A and the permutation matrix P r And the permutation matrix P l Satisfies the following formula:
[0064]
[0065] Accordingly, in operation S210, the permutation matrix P r The input data DIN is processed to generate input data S, which can be expressed as the following formula:
[0066]
[0067] It can be seen from the calculation results of the above formula that the mathematical operation in operation S210 only involves addition and subtraction operations, and thus can be performed by the adder 110 .
[0068] Then, the operation matrix A may be further multiplied by the input data S to generate an operation result R1, which may be expressed as the following formula (4):
[0069]
[0070] Figure 3 According to some embodiments of the present application, Figure 2Flowchart of operation S230 and operation S240. Operation S230 includes step S301 and step S302, and operation S240 includes step S303. In step S301, the operation control circuit 150 disassembles the operation matrix A into multiple first sub-matrices. In step S302, the operation control circuit 150 disassembles the input data S into multiple second sub-matrices. In step S303, the operation control circuit 150 controls the multiple multiplication and accumulation operation circuits 130 to multiply the multiple first sub-matrices with the multiple sub-matrices to generate an operation result R1.
[0071] Continuing with the previous example, in this example, the dimension of the operation matrix A is relatively low and can be completely decomposed into a diagonal 2×2 matrix multiplication. Therefore, the operation control circuit 150 can further decompose the operation matrix A of formula (4) into the following formula:
[0072]
[0073] Among them, the multiple elements d in the operation matrix A 11 d 31 d 32 d 21 d 22 d 41 and 42 The four sub-matrices formed are the first sub-matrices mentioned above, and the multiple elements s in the input data S 11 、s 12 、s 13 、s 14 、s 21 、s 22 、s 23 、s 24 、s 31 、s 32 、s 33 、s 34 、s 41 、s 42 、s 43 and 44 The four sub-matrices respectively formed are the aforementioned second sub-matrices.
[0074] As can be seen from the above formula, if there is only one idle multiplication-accumulation operation circuit 130 in the discrete cosine transform processing device 100, the operation control circuit 150 can continuously call the multiplication-accumulation operation circuit 130 four times to perform the operation of the above formula to generate the operation result R1 (equivalent to finding T in formula (4)). If there are four or more idle multiplication-accumulation operation circuits 130 in the discrete cosine transform processing device 100, the operation control circuit 150 can simultaneously call the four multiplication-accumulation operation circuits 130 to perform the operation of the above formula to directly generate the operation result R1. Similarly, if there are two idle multiplication-accumulation operation circuits 130 in the discrete cosine transform processing device 100, the operation control circuit 150 can continuously call the two multiplication-accumulation operation circuits 130 twice to perform the operation of the above formula to generate the operation result R1.
[0075] Finally, in operation S260, the output circuit 160 may perform the remaining operations in formula (3), that is, according to the permutation matrix P l The operation result R1 is processed to generate the operation result R2 (which is equivalent to Y in formula (3)), which can be expressed as follows:
[0076]
[0077] As mentioned above, in some embodiments, the output circuit 160 may be a buffer, and its controller may replace multiple elements of the matrix T in the above formula according to the permutation matrix P l The output circuit 160 is written into the buffer in the order of the first row, the second row, the third row and the fourth row of , and outputs them in the same order as the matrix Y (equivalent to the operation result R2). Alternatively, in some other embodiments, the output circuit 160 may be an adder (or a multiplier) that can convert the permutation matrix P l Multiply by matrix T to get matrix Y.
[0078] Based on the attached operation matrix A and the above examples, the general formula for decomposing the operation matrix A based on formula (4) can be deduced as follows:
[0079]
[0080] High-dimensional matrix operations can be further decomposed into matrix multiplication operations corresponding to unit dimensions.
[0081] For example, a matrix multiplication of dimension 2L can be decomposed into 4 matrix multiplications of dimension L and 2 matrix accumulation operations:
[0082]
[0083] Similarly, a matrix multiplication of dimension 4L can be first decomposed into a matrix multiplication operation of dimension 2L, and finally decomposed into multiple matrix multiplications and matrix accumulation operations of dimension L:
[0084]
[0085] In this way, the operation control circuit 150 can decompose the operation matrix A in the above manner, and call the multiplication and accumulation operation circuit 130 corresponding to the unit dimension to perform the operation of formula (4), so as to obtain the operation result R1.
[0086] Figure 4 According to some embodiments of the present application, Figure 1 Schematic diagram of the multiplication and accumulation circuit 130. Taking the multiplication and accumulation circuit 130 for executing the multiple first and second sub-matrices decomposed based on formula (4) as an example, the multiplication and accumulation circuit 130 may include multiple multipliers 401-408 and multiple adders 411-414. The multiplier 401 is used to multiply the element d 11 With element s 11 , the multiplier 402 is used to multiply the element d 11 With element s 21 , and the adder 411 is used to add the output of the multiplier 401 and the output of the multiplier 402 to generate the element t 11 The multiplier 403 is used to multiply the element d 11 With element s 12 , the multiplier 404 is used to multiply the element d 11 With element s 22 , and the adder 412 is used to add the output of the multiplier 403 and the output of the multiplier 404 to generate the element t 12 The multiplier 405 is used to multiply the element d 31 With element s 11 , the multiplier 406 is used to multiply the element d 32 With element s 21 , and the adder 413 is used to add the output of the multiplier 405 and the output of the multiplier 406 to generate the element t 21 The multiplier 407 is used to multiply the element d 31 With element s 12 , the multiplier 408 is used to multiply the element d 32 With element s 22 , and the adder 414 is used to add the output of the multiplier 406 and the output of the multiplier 407 to generate the element t 22 It should be understood that Figure 4 The multiply-accumulate operation circuit 130 is a basic circuit unit configured to perform 2×2 matrix multiplication, but the present application is not limited thereto.
[0087] Figure 5 According to some embodiments of the present application, Figure 2 Flowchart of operation S230 and operation S240. Operation S230 includes step S501 and step S502, and operation S240 includes step S503 and S504. In step S501, the operation control circuit 150 disassembles the operation matrix A into multiple first sub-matrices. In step S502, the operation control circuit 150 disassembles the input data S into multiple second sub-matrices. In step S503, the operation control circuit 150 controls multiple multiplication and addition operation circuits 130 to multiply multiple first sub-matrices with multiple first sub-matrices to generate multiple operator results. In step S504, the operation control circuit 150 controls the accumulator 140 to add corresponding two of the multiple operator results to generate an operation result R1.
[0088] Different from Figure 3 For example, in this case, the dimension of the operation matrix A is high and cannot be completely decomposed into a diagonal 2×2 matrix multiplication. For example, formula (4) in this case can be rewritten as follows:
[0089]
[0090] In this case, the operation control circuit 150 can decompose the above equation as follows:
[0091]
[0092] In this way, the operation control circuit 150 can control multiple multiplication and accumulation operation circuits 130 to sequentially perform multiple matrix multiplication operations in the above formula to generate multiple operator results, and control the accumulator 140 to add corresponding two of the multiple operator results to generate an operation result R1 (equivalent to finding multiple elements in the matrix T).
[0093] Figure 6 A flowchart of a discrete cosine transform processing method 600 is drawn according to some embodiments of the present application. In some embodiments, the discrete cosine transform processing method 600 may be performed by a processing device (which may be, but is not limited to, Figure 1 The discrete cosine transform processing device 100 is executed.
[0094] In operation S610, a first input data is processed according to a first permutation matrix to generate a second input data. In operation S620, a plurality of multiplication-accumulation operation circuits and the accumulator in the processing device are configured according to a matrix multiplication operation corresponding to a unit dimension, so as to multiply an operation matrix and the second input data by the plurality of multiplication-accumulation operation circuits and an accumulator, thereby generating a first operation result. In operation S630, the first operation result is processed according to a second permutation matrix to generate a second operation result, wherein the first permutation matrix, the operation matrix and the second permutation matrix are decomposed from a discrete cosine transform matrix.
[0095] The description of the discrete cosine transform processing method 600 can refer to the aforementioned multiple embodiments, so it is not repeated here. The above multiple operations are only examples and are not limited to being performed in the order in this example. Without violating the operation mode and scope of each embodiment of the present application, these operations can be appropriately increased, replaced, omitted, performed in a different order, or can be performed simultaneously or partially simultaneously.
[0096] In summary, the discrete cosine transform processing device and the discrete cosine transform processing method provided in some embodiments of the present application can decompose the discrete cosine transform matrix into an operation matrix and a plurality of permutation matrices, wherein a simple circuit such as an adder can be used to implement the multiplication operation of the aforementioned permutation matrix, thereby reducing the overall circuit cost and improving the utilization efficiency of the multiplier in the hardware, thereby improving the processing efficiency of the discrete cosine transform.
[0097] Although the embodiments of the present application are described above, these embodiments are not intended to limit the present application. Technicians in this technical field may change the technical features of the present application based on the explicit or implicit contents of the present application. All these changes may fall within the scope of patent protection sought by the present application. The scope of patent protection of the present application shall be based on the scope of the patent application of this specification.
[0098] Appendix: A determination matrix A, a permutation matrix P r and the permutation matrix P l The calculation process of the algorithm is as follows.
[0099]
[0100]
[0101]
[0102] Among them, 0 m×n is an m×n dimensional zero matrix (i.e., all its elements are 0), A m×n is a submatrix of m×n dimensions, A m×n(i,j) is the element in the i-th row and j-th column of the matrix, and A -1 Represents the inverse matrix of matrix A.
Claims
1. A discrete cosine transform processing device, characterized in that: include: an adder, processing a first input data according to a first permutation matrix to generate a second input data; a register storing an operation matrix; A plurality of multiply-accumulate operation circuits; an accumulator; an operation control circuit, configuring the plurality of multiplication-accumulation operation circuits and the accumulator according to a matrix multiplication operation corresponding to a unit dimension, so as to multiply and accumulate the operation matrix and the second input data through the plurality of multiplication-accumulation operation circuits and the accumulator, thereby generating a first operation result; and an output circuit, processing the first operation result according to a second permutation matrix to generate a second operation result, The first permutation matrix, the operation matrix and the second permutation matrix are decomposed from a discrete cosine transform matrix.
2. The discrete cosine transform processing device according to claim 1, characterized in that: Also includes: A selection circuit selects the operation matrix according to the one-dimensional number of the first input data.
3. The discrete cosine transform processing device according to claim 1, characterized in that: A product of the first permutation matrix, the operation matrix and the second permutation matrix is the discrete cosine transform matrix.
4. The discrete cosine transform processing device according to claim 1, wherein: The operation control circuit decomposes the operation matrix into a plurality of first sub-matrices, decomposes the second input data into a plurality of second sub-matrices, and controls the plurality of multiplication-accumulation operation circuits to multiply the plurality of first sub-matrices with the plurality of sub-matrices to generate the first operation result.
5. The discrete cosine transform processing device according to claim 1, wherein: The operation control circuit decomposes the operation matrix into multiple first sub-matrices, decomposes the second input data into multiple second sub-matrices, controls the multiple multiplication and addition operation circuits to multiply the multiple first sub-matrices with the multiple sub-matrices to generate multiple operator results, and controls the accumulator to add corresponding two of the multiple operator results to generate the first operation result.
6. The discrete cosine transform processing device according to claim 1, characterized in that: All elements in the first permutation matrix can only take the value of 0, 1 or -1.
7. The discrete cosine transform processing device according to claim 1, characterized in that: All elements in the second permutation matrix can only take the value of 0 or 1.
8. A discrete cosine transform processing method, characterized in that: Executed by a processing device, the discrete cosine transform processing method includes: Processing a first input data according to a first permutation matrix to generate a second input data; configuring a plurality of multiplication-accumulation operation circuits and an accumulator in the processing device according to a matrix multiplication operation corresponding to a unit dimension, so as to multiply an operation matrix and the second input data by the plurality of multiplication-accumulation operation circuits and the accumulator, thereby generating a first operation result; and Processing the first operation result according to a second permutation matrix to generate a second operation result, The first permutation matrix, the operation matrix and the second permutation matrix are decomposed from a discrete cosine transform matrix.
9. The discrete cosine transform processing method according to claim 8, characterized in that: Also includes: The operation matrix is selected according to the number of one-dimensional dimensions of the first input data.
10. The discrete cosine transform processing method according to claim 8, characterized in that: A product of the first permutation matrix, the operation matrix and the second permutation matrix is the discrete cosine transform matrix.