Method and device for storing time sequence delay and calculating accurate time sequence report

Abstract

According to the method and device for storing the time sequence delay and calculating the accurate time sequence report, the method and device are effective and accurate, different delays are used in different stages, the high-temperature and low-temperature time sequence is stable, when a user opens the time sequence report, after voltage and temperature are selected, the delays corresponding to devices and signals can be automatically selected, and the time sequence report is presented to the user. The method comprises the following steps: (1) an initialization stage; (2) a layout and wiring stage: using default input conversion, output load and worst time delay; (3) a time sequence repairing stage: repairing the time sequence violation through a wiring result; (4) generating a time sequence report which comprises normal temperature time sequence analysis and serialization of wiring delay of all voltages and temperatures; and (5) selecting a time sequence report by a user: storing the voltage and the temperature selected by the user into a time sequence report configuration file by an interface, selecting corresponding time sequence delay after a bottom layer tool reads the related voltage and the temperature, assigning the time delay to a time sequence diagram, performing full-path analysis, and generating the time sequence report.

Description

Technical Field

[0001] The present invention relates to the technical field of integrated circuits, and in particular to a method for storing timing delays and calculating accurate timing reports, and a device for storing timing delays and calculating accurate timing reports. Background Art

[0002] FPGA (Field Programmable Gate Array) circuit is an integrated chip mainly based on digital circuits. It was invented by Ross Freeman, one of the founders of Xilinx in 1985. It is a type of programmable logic device PLD (Programmable Log Logic Device Dev Logic Device).

[0003] Timing performance is a very important indicator of FPGA circuits. When timing violations occur, it is difficult for FPGA circuits to work properly. Timing performance not only depends on excellent algorithms but also accurate timing models. The performance during layout and routing can cover all temperatures under the current voltage, and the timing report can view the timing results under different voltages and temperatures.

[0004] The existing timing delay design scheme only uses a secondary timing model delay when creating the timing diagram, and uses the default delay of the channel during routing, which is pessimistic. This leads to unstable high and low temperature timing. All internal connections and channels of the device use the default load, and the accuracy of the timing report is further reduced. Routing obtains the channel type and delay through the structure. In this scheme, the channel delay is saved in two copies, one in the timing module and the other in the structure module, resulting in data redundancy. Summary of the invention

[0005] In order to overcome the defects of the prior art, the technical problem to be solved by the present invention is to provide a method for saving timing delays and calculating accurate timing reports, which is effective and accurate, uses different delays in different stages, and has stable timing at high and low temperatures. When the user opens the timing report, after selecting the voltage and temperature, it can automatically select the delay corresponding to the device and signal, and present the timing report to the user.

[0006] The technical solution of the present invention is: the method for saving timing delay and calculating accurate timing report comprises the following steps: (1) Initialization phase: Set the default voltage, obtain the maximum delay information of the devices and channels in the timing model, and obtain the default delay based on the current delay information; (2) Layout and routing stage: use default input conversion, output load, and worst-case delay; (3) Timing repair phase: repair timing violations through routing results, including setup and hold; (4) Generate timing reports: including normal temperature timing analysis and serializing routing delays for all voltages and temperatures; (5) User selection of timing report stage: The interface saves the voltage and temperature selected by the user to the timing report configuration file. After the underlying tool reads the relevant voltage and temperature, it selects the corresponding timing delay and assigns the delay to the timing diagram, performs full path analysis, and generates a timing report.

[0007] The method of the present invention for preserving timing delay and calculating accurate timing report is effective and accurate, different delays are used in different stages, and high and low temperature timing is stable. When the user opens the timing report, after selecting the voltage and temperature, the delay corresponding to the device and signal can be automatically selected, and the timing report is presented to the user.

[0008] A device for storing timing delays and calculating accurate timing reports is also provided, comprising: Initialization module, which is configured to set the default voltage, obtain the maximum delay information of the device and channel in the timing model, and obtain the default delay according to the current delay information; Place and route modules, which are configured to use default input transitions, output loads, and worst-case delays; A timing repair module configured to repair timing violations through routing results, including setup and hold; Generate timing report module, which is configured to include room temperature timing analysis and sequence routing delays for all voltages and temperatures; The user selects the timing report module, which is configured as an interface that saves the voltage and temperature selected by the user into the timing report configuration file. After the underlying tool reads the relevant voltage and temperature, it selects the corresponding timing delay and assigns the delay to the timing diagram, performs full-path analysis, and generates a timing report. BRIEF DESCRIPTION OF THE DRAWINGS

[0009] Figure 1 The overall flow chart of the method for saving timing delay and calculating accurate timing report according to the present invention is shown.

[0010] Figure 2 A flowchart showing step (1) of the method for storing timing delays and calculating accurate timing reports according to the present invention is shown.

[0011] Figure 3 A flowchart showing step (2) of the method for storing timing delays and calculating accurate timing reports according to the present invention is shown.

[0012] Figure 4 A flowchart showing the repair establishment of step (3) of the method for saving timing delay and calculating accurate timing report according to the present invention is shown.

[0013] Figure 5A flowchart showing the repair and maintenance of step (3) of the method for preserving timing delay and calculating accurate timing report according to the present invention is shown.

[0014] Figure 6 A flowchart showing step (4) of the method for storing timing delays and calculating accurate timing reports according to the present invention is shown.

[0015] Figure 7 A flow chart of the delay fitting method of step (5) of the method for saving timing delay and calculating accurate timing report according to the present invention is shown.

[0016] Figure 8 A flowchart showing the interaction between the user interface and the underlying layer of step (5) of the method for saving timing delays and calculating accurate timing reports according to the present invention. DETAILED DESCRIPTION

[0017] like Figure 1 As shown, the method for saving timing delay and calculating accurate timing report includes the following steps: (1) Initialization phase: Set the default voltage, obtain the maximum delay information of the devices and channels in the timing model, and obtain the default delay based on the current delay information; (2) Layout and routing stage: use default input conversion, output load, and worst-case delay; (3) Timing repair phase: repair timing violations through routing results, including setup and hold; (4) Generate timing reports: including normal temperature timing analysis and serializing routing delays for all voltages and temperatures; (5) User selection of timing report stage: The interface saves the voltage and temperature selected by the user to the timing report configuration file. After the underlying tool reads the relevant voltage and temperature, it selects the corresponding timing delay and assigns the delay to the timing diagram, performs full path analysis, and generates a timing report.

[0018] The method of the present invention for preserving timing delay and calculating accurate timing report is effective and accurate, different delays are used in different stages, and high and low temperature timing is stable. When the user opens the timing report, after selecting the voltage and temperature, the delay corresponding to the device and signal can be automatically selected, and the timing report is presented to the user.

[0019] like Figure 2 As shown, preferably, in step (1), the timing model includes delay information of devices and channels, the input conversion is the conversion of the device or channel of the previous level, and there are delay and conversion data tables corresponding to input conversion and output load for different voltages and temperatures, and each device and channel has a voltage and temperature corresponding to the maximum delay, minimum delay and default delay; There are two types of delays in the timing diagram: device internal delay and signal connection delay. The device delay is determined by the circuit itself after the voltage and temperature are selected. After the netlist is generated, the internal connection of the device has been confirmed, and the delay is obtained in the timing model through the fan-out number of the device output port.

[0020] like Figure 3 As shown, preferably, in the step (2), the layout and routing modify the connection delay of the signal, wherein the signal delay of the layout is calculated through two device coordinates, and the routing is related to the channel of the routing path; after the timing diagram is created, the worst voltage and temperature are set as the current delay information; the routing process directly obtains the default delay through the channel type; the routing module transmits the channel coordinates to the timing interface, the timing obtains the channel type through the structure, and then obtains the default delay according to the channel type, and returns it to the routing module.

[0021] Preferably, in step (3), the timing model uses the most pessimistic data, the maximum delay is used for repairing the establishment, and the minimum delay is used for repairing the retention; after the routing is completed, if there is a timing violation, the establishment or retention is repaired through routing, and the timing violation is modified in accordance with the following rules: the default is to open, repair the establishment and repair the retention switches, and the default repair time is 1200 seconds. When the delay is less than or equal to 0, there is no repair time limit; like Figure 4 As shown, the repair establishment calls the timing interface after each repair is completed to obtain the relaxation value until the relaxation value is greater than 0, the running time or the number of repair signals exceeds the set value, and the repair is stopped; After the overall routing is completed, check whether the modification establishment switch is turned on, obtain the establishment relaxation value from the timing interface, and check whether the establishment timing is violated; if there is a timing violation, read the maximum number of repair violations and start repairing the timing path of the establishment timing violation; during the repair process, determine whether it has timed out and the modification is completed; like Figure 5 As shown, the hold timing violation includes: detecting whether there is a hold timing violation before routing is completed; using the minimum delay timing model information before repairing; and adding a repair cross-clock switch during the hold repair process, which is not turned on by default.

[0022] Preferably, in step (4), after the timing violation is repaired, a normal temperature timing model is used to perform timing analysis to calculate the clock operating frequency, establish and maintain relaxation values ​​for the same clock, establish and maintain relaxation values ​​across clocks, remove relaxation values, and restore relaxation values.

[0023] like Figure 6As shown, preferably, in the step (4), the wiring delay is serialized: the channel delay at this stage no longer uses the default delay, but searches for the delay in the lookup table according to the input conversion and output load; the wiring module obtains all voltages and temperatures, traverses these voltages and temperatures to calculate the signal delay respectively, and serializes them into a file to prepare for the user to select a timing report; the wiring transmits the coordinates, input conversion and output load of the current channel to the timing module, obtains the type of channel from the structure module, and then obtains the two-dimensional table of conversion and delay from the timing model; since the input conversion and output load in the two-dimensional table are difference values, it is not necessarily possible to find the same value, and the specific value needs to be calculated in the form of fitting here; Generate normal temperature timing report: To generate a normal temperature timing report, the routing module only needs to calculate all signal delays under normal temperature delay and pass them to the timing module. The timing module resets the delays of the connections on the timing diagram, performs full timing path analysis, and generates a normal temperature timing report.

[0024] Preferably, in step (5), all voltage and temperature delays are calculated to prepare for the user to select timing information; in the timing model, each voltage and temperature forms a two-dimensional delay table with input conversion as columns and output load as rows; the delay is calculated, and the delay value is fitted according to the input conversion and output load.

[0025] In the timing model, different voltages and temperatures have corresponding two-dimensional tables with input conversion as columns and output load as rows (see Table 1). To calculate the delay, the delay value is fitted according to the input conversion and output load.

[0026] Table 1

[0027] According to the table, we can see that the input conversion and output load have several representative values, which may be different from the actual quantity. In order to avoid extreme values, the return values ​​are all within the format. The specific rules are as follows: 1. If there is only one value in the table, return that value directly.

[0028] 2. Can be found in the table, return the subscript value.

[0029] 3. If the value is not found in the table and is less than the minimum subscript value, the minimum value is returned.

[0030] 4. If the value is not found in the table and is greater than the maximum subscript value, the maximum value is returned.

[0031] Not found in the table, greater than the minimum value and less than the maximum value, fits between the first large value and the last small value.

[0032] According to the linear formula: (x-x1) / (x2-x1) = (y-y1) / (y2-y1) we get y = (y2 - y1) × (x - x1) / (x2 - x1) + y1. The meaning of each parameter is shown in Table 2.

[0033] Table 2

[0034] like Figure 7 As shown, preferably, in the step (5), when fitting the delay value, all signal trees are traversed, one signal tree is traversed for all voltages and temperatures, the delay is calculated for a certain voltage and temperature, and the values ​​of other voltages and temperatures are also fitted at the same time and saved in the relevant structure. When obtaining other voltages and temperatures, they are directly obtained from the cache; in order to save memory resources, the cache is cleared before calculating the delay of the next signal tree.

[0035] Preferably, in step (5), after the user selects the information for generating the timing report through the interface, it is saved in the configuration file; the bottom layer reads the timing parameters, obtains the device delay from the timing model according to the voltage and temperature set by the user, obtains the corresponding voltage and temperature signal delay from the serialized wiring delay, performs full path analysis, generates the timing report data, and sends a completion message to the interface; after the interface receives the completion message, it displays the specific timing report. The interaction process between the user interface and the bottom layer is as follows: Figure 8 shown.

[0036] A person skilled in the art can understand that all or part of the steps in the above-mentioned embodiment method can be completed by instructing the relevant hardware through a program, and the program can be stored in a computer-readable storage medium. When the program is executed, it includes the steps of the above-mentioned embodiment method, and the storage medium can be: ROM / RAM, disk, CD, memory card, etc. Therefore, corresponding to the method of the present invention, the present invention also includes a device for saving timing delay and calculating accurate timing report, which is usually represented in the form of functional modules corresponding to the steps of the method. The device includes: Initialization module, which is configured to set the default voltage, obtain the maximum delay information of the device and channel in the timing model, and obtain the default delay according to the current delay information; Place and route modules, which are configured to use default input transitions, output loads, and worst-case delays; A timing repair module configured to repair timing violations through routing results, including setup and hold; Generate timing report module, which is configured to include room temperature timing analysis and sequence routing delays for all voltages and temperatures; The user selects the timing report module, which is configured as an interface that saves the voltage and temperature selected by the user into the timing report configuration file. After the underlying tool reads the relevant voltage and temperature, it selects the corresponding timing delay and assigns the delay to the timing diagram, performs full-path analysis, and generates a timing report.

[0037] The present invention provides a timing model that can be searched through a lookup table. The timing model includes parameters such as voltage, temperature, input conversion (input conversion) and output load (output load), which affect the timing delay. The worst delay is used during wiring, the maximum delay is used during establishment, and the minimum delay is used during maintenance. After wiring is completed, the timing violation repair, repair establishment and repair maintenance must be performed. The timing violation is minimized at any temperature. After wiring, the normal temperature delay under the current voltage is used, and the operating frequency is displayed relatively normally. After wiring, the delays corresponding to all voltages and temperatures are calculated according to the wiring results, and all results are saved. When the user opens the timing report, the voltage and temperature are selected. The method can automatically select the delay corresponding to the device and signal, and present the timing report to the user.

[0038] The above description is only a preferred embodiment of the present invention and does not limit the present invention in any form. Any simple modification, equivalent changes and modifications made to the above embodiments based on the technical essence of the present invention are still within the protection scope of the technical solution of the present invention.

Claims

1. A method for storing timing delays and calculating accurate timing reports, characterized in that: It includes the following steps: (1) Initialization phase: Set the default voltage, obtain the maximum delay information of the devices and channels in the timing model, and obtain the default delay based on the current delay information; (2) Layout and routing stage: use default input conversion, output load, and worst-case delay; (3) Timing repair phase: repair timing violations through routing results, including setup and hold; (4) Generate timing reports: including normal temperature timing analysis and serializing routing delays for all voltages and temperatures; (5) User selection of timing report stage: The interface saves the voltage and temperature selected by the user to the timing report configuration file. After the underlying tool reads the relevant voltage and temperature, it selects the corresponding timing delay and assigns the delay to the timing diagram, performs full path analysis, and generates a timing report.

2. The method for storing timing delay and calculating accurate timing report according to claim 1, characterized in that: In step (1), the timing model includes delay information of devices and channels. The input conversion is the conversion of the device or channel of the previous level. There are delay and conversion data tables corresponding to input conversion and output load for different voltages and temperatures. Each device and channel has a voltage and temperature corresponding to the maximum delay, minimum delay and default delay. There are two types of delays in the timing diagram: device internal delay and signal connection delay. The device delay is determined by the circuit itself after the voltage and temperature are selected. After the netlist is generated, the internal connection of the device has been confirmed, and the delay is obtained in the timing model through the fan-out number of the device output port.

3. The method for storing timing delay and calculating accurate timing report according to claim 2, characterized in that: In the step (2), the layout and routing modify the connection delay of the signal, wherein the signal delay of the layout is calculated by two device coordinates, and the routing is related to the channel of the routing path; after the timing diagram is created, the worst voltage and temperature are set as the current delay information; The routing process directly obtains the default delay through the channel type; the routing module passes the channel coordinates to the timing interface, the timing obtains the channel type through the structure, and then obtains the default delay based on the channel type and returns it to the routing module.

4. The method for storing timing delay and calculating accurate timing report according to claim 3, characterized in that: In the step (3), the timing model uses the most pessimistic data, the maximum delay is used for repairing the establishment, and the minimum delay is used for repairing the hold; after the routing is completed, if there is a timing violation, the establishment or hold is repaired through routing, and the timing violation is modified according to the following rules: the default is to open, repair the establishment and repair the hold switches, and the default repair time is 1200 seconds. When the delay is less than or equal to 0, there is no repair time limit; Repair establishment calls the timing interface after each repair is completed to obtain the relaxation value. Repair is stopped until the relaxation value is greater than 0, the running time or the number of repair signals exceeds the set value. After the overall routing is completed, check whether the modification establishment switch is turned on, obtain the establishment relaxation value from the timing interface, and check whether the establishment timing is violated; if there is a timing violation, read the maximum number of repair violations and start repairing the timing path of the establishment timing violation; During the repair process, determine whether the timeout has occurred and whether the modification has been completed; Hold timing violations include: detecting whether there are hold timing violations before routing is completed; using minimum delay timing model information before repairing; and adding a repair cross-clock switch during the hold repair process, which is not turned on by default.

5. The method for storing timing delay and calculating accurate timing report according to claim 4, characterized in that: In the step (4), after the timing violation is repaired, a normal temperature timing model is used to perform timing analysis, calculate the clock operating frequency, establish a relaxation value for the same clock, maintain the relaxation value, establish a relaxation value across clocks, maintain the relaxation value, remove the relaxation value, and restore the relaxation value.

6. The method for storing timing delay and calculating accurate timing report according to claim 5, characterized in that: In the step (4), the wiring delay is serialized: the channel delay at this stage no longer uses the default delay, but searches for the delay in the lookup table according to the input conversion and output load; the wiring module obtains all voltages and temperatures, traverses these voltages and temperatures to calculate the signal delay respectively, and serializes them into a file to prepare for the user to select a timing report; the wiring transmits the coordinates, input conversion and output load of the current channel to the timing module, obtains the type of channel from the structure module, and then obtains the two-dimensional table of conversion and delay from the timing model, and calculates the specific value in a fitting form; Generate normal temperature timing report: To generate a normal temperature timing report, the routing module only needs to calculate all signal delays under normal temperature delay and pass them to the timing module; the timing module resets the delay of the connection on the timing diagram, performs full timing path analysis, and generates a normal temperature timing report.

7. The method for storing timing delay and calculating accurate timing report according to claim 6, characterized in that: In the step (5), all voltage and temperature delays are calculated to prepare for the user to select timing information; in the timing model, each voltage and temperature forms a two-dimensional delay table with input conversion as columns and output load as rows; Calculate the delay and fit the delay value based on the input transition and output load.

8. The method for storing timing delay and calculating accurate timing report according to claim 7, characterized in that: In the step (5), when fitting the delay value, all signal trees are traversed, one signal tree is traversed for all voltages and temperatures, the delay is calculated for a certain voltage and temperature, and the values ​​of other voltages and temperatures are also fitted at the same time and saved in the relevant structure. When obtaining other voltages and temperatures, they are directly obtained from the cache; in order to save memory resources, the cache is cleared before calculating the delay of the next signal tree.

9. The method for storing timing delay and calculating accurate timing report according to claim 8, characterized in that: In the step (5), after the user selects information for generating a timing report through the interface, it is saved in a configuration file; the bottom layer reads the timing parameters, obtains the device delay from the timing model according to the voltage and temperature set by the user, obtains the signal delay of the corresponding voltage and temperature from the serialized wiring delay, performs full path analysis, generates timing report data, and sends a completion message to the interface; after the interface receives the completion message, it displays a specific timing report.

10. The device for storing timing delay and calculating accurate timing report according to claim 1, characterized in that: It includes: Initialization module, which is configured to set the default voltage, obtain the maximum delay information of the device and channel in the timing model, and obtain the default delay according to the current delay information; Place and route modules, which are configured to use default input transitions, output loads, and worst-case delays; A timing repair module configured to repair timing violations through routing results, including setup and hold; Generate timing report module, which is configured to include room temperature timing analysis and sequence routing delays for all voltages and temperatures; The user selects the timing report module, which is configured as an interface that saves the voltage and temperature selected by the user into the timing report configuration file. After the underlying tool reads the relevant voltage and temperature, it selects the corresponding timing delay and assigns the delay to the timing diagram, performs full-path analysis, and generates a timing report.

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