Global routing method and device based on dynamic tree, electronic equipment and storage medium

Abstract

The application discloses a dynamic tree-based global routing method and device, electronic equipment and storage medium, relates to the technical field of integrated circuits, and the method comprises the following steps: generating a tree topology with the shortest wire length and a tree topology determined by the shortest wire length and congestion reduction weighting for each wire net; constructing the two tree topologies of each wire net into a tree forest respectively; selecting a candidate tree from each tree forest according to a target function and selecting a candidate template path of the candidate tree; determining a global routing scheme of the corresponding wire net according to each candidate tree and candidate template path; generating a tree topology for reducing congestion for the wire net with congestion in the global routing scheme, and replacing the tree topology not selected in the tree forest of the wire net with congestion; deleting the tree forest corresponding to the wire net without congestion in the global routing scheme; and then repeating the steps of global routing. The application updates the tree topology of the congested wire net, reduces the congestion, deletes the tree forest of the wire net without congestion, reduces the calculation amount, and improves the efficiency.

Description

Technical Field

[0001] This application relates to the field of integrated circuit technology, and in particular to a global routing method, apparatus, electronic device and storage medium based on dynamic tree. Background Technology

[0002] Global routing is a crucial early step in the automated routing process for integrated circuits (ICs) layouts and an important research area in electronic design automation (EDA). After layout is complete, global routing can, within a limited time, coarsely identify the metal connections and layer allocations of all nets in the layout, providing key guidance for subsequent detailed routing. However, existing global routing solutions still suffer from low efficiency and insufficient congestion handling capabilities. Summary of the Invention

[0003] The main objective of this application is to propose a global routing method, apparatus, electronic device, and storage medium based on dynamic trees, so as to improve the efficiency of global routing of integrated circuits and reduce congestion.

[0004] To achieve the above objectives, one aspect of this application proposes a global routing method based on a dynamic tree, the method comprising the following steps:

[0005] For each circuit network, generate a first tree topology with the shortest line length and a second tree topology determined by the shortest line length and congestion reduction weighting.

[0006] The first tree topology and the second tree topology of each of the circuit nets are respectively constructed into corresponding tree forests;

[0007] Based on the objective function of global routing, one tree topology is selected from the two tree topologies of each of the tree forests as a candidate tree for each of the circuit nets, and a candidate template path is selected for the candidate tree;

[0008] A global routing scheme for the corresponding circuit net is determined based on each of the candidate trees and each of the candidate template paths;

[0009] For the congested circuit nets in the global routing scheme, a third tree topology to reduce congestion is generated, and the unselected tree topologies in the tree forest of the congested circuit nets are replaced with the third tree topology.

[0010] Delete the forest of trees corresponding to the circuit nets without congestion in the global cabling scheme;

[0011] Returning to the objective function of global routing, select one tree topology from the two tree topologies of each tree forest as a candidate tree for each circuit net and select the candidate template path of the candidate tree until a preset termination condition is reached, and take the current global routing scheme as the target global routing scheme for each circuit net.

[0012] In some embodiments, generating a first tree topology with the shortest line length and a second tree topology determined by the shortest line length and congestion reduction weighting for each circuit net includes the following steps:

[0013] Generate the shortest right-angle Steiner minimum tree for each of the circuit nets as the first tree topology;

[0014] Template routing is performed on the corresponding circuit nets based on each of the right-angle Steiner minimum trees to obtain the congestion distribution map of each of the circuit nets;

[0015] The undo and rewind algorithm is used to generate the winding tree corresponding to each of the circuit nets based on each of the congestion distribution maps, which serves as the second tree topology.

[0016] In some embodiments, generating a third-tree topology to reduce congestion in the congested circuit nets of the global routing scheme includes the following steps:

[0017] The undo and rewind algorithm is used to generate a winding tree for the congested circuit nets in the global routing scheme, which serves as the third tree topology.

[0018] In some embodiments, generating the shortest right-angle Steiner minimum tree for each of the circuit nets as the first tree topology includes the following steps:

[0019] The FLUTE algorithm is used to generate the shortest right-angle Steiner minimum tree for each of the circuit nets, which is then used as the first tree topology.

[0020] In some embodiments, generating the winding tree for each of the circuit nets using the unwinding and rewinding algorithm includes the following steps:

[0021] The undo and rewind algorithm of CUGR2 is used to generate the winding tree of each of the circuit nets.

[0022] In some embodiments, the step of selecting one tree topology from the two tree topologies of each of the tree forests as a candidate tree for each of the circuit nets according to the objective function of global routing, and selecting the candidate template path of the candidate tree, includes the following steps:

[0023] Initialize the first candidate probability of two tree topologies and the second candidate probability of two 2-pin nets of the two tree topologies in each of the tree forests;

[0024] Significance calculations are performed on each of the first candidate probabilities and each of the second candidate probabilities;

[0025] The minimum value of the objective function is obtained based on the result of the significance calculation and the gradient descent method, and then each of the first candidate probabilities and each of the second candidate probabilities are updated.

[0026] If the updated first candidate probability and second candidate probability meet the selection criteria, then the tree topology corresponding to the largest first candidate probability in each of the tree forests is selected as the candidate tree, and the 2-pin net corresponding to the largest second candidate probability in the candidate tree is selected as the candidate template path.

[0027] If the updated first candidate probability and second candidate probability do not meet the selection criteria, then return to the method of updating each first candidate probability and each second candidate probability according to the result of the significance calculation and the gradient descent method until the updated first candidate probability and second candidate probability meet the selection criteria.

[0028] In some embodiments, the method further includes the following steps:

[0029] Determine whether the updated probabilities of the first and second candidates reach 90%;

[0030] The candidate is determined to meet the selection criteria if the updated first candidate probability and the second candidate probability reach 90%.

[0031] If the updated first candidate probability and second candidate probability do not reach 90%, it is determined that the selection condition is not met.

[0032] To achieve the above objectives, another aspect of the embodiments of this application proposes a global routing apparatus based on a dynamic tree, the apparatus comprising:

[0033] The tree topology generation unit is used to generate the first tree topology with the shortest line length and the second tree topology determined by the shortest line length and congestion reduction weighting for each circuit net.

[0034] A tree forest construction unit is used to construct the first tree topology and the second tree topology of each of the circuit nets into corresponding tree forests;

[0035] The tree and path selection unit is used to select one of the tree topologies from the two tree topologies of each of the tree forests as a candidate tree for each of the circuit nets according to the objective function of global routing, and to select the candidate template path of the candidate tree.

[0036] A global routing unit is used to determine a global routing scheme for the corresponding circuit net based on each of the candidate trees and each of the candidate template paths.

[0037] The tree forest update unit is used to generate a third tree topology to reduce congestion for the congested circuit network in the global cabling scheme, and to replace the tree topology that was not selected in the tree forest of the congested circuit network with the third tree topology.

[0038] The tree forest deletion unit is used to delete the tree forest corresponding to the circuit network without congestion in the global wiring scheme.

[0039] The repeated selection unit is used to return the selection of one tree topology from the two tree topologies of each tree forest as a candidate tree for each circuit net according to the objective function of global routing, and to select the candidate template path of the candidate tree until the preset termination condition is reached, and to take the current global routing scheme as the target global routing scheme for each circuit net.

[0040] To achieve the above objectives, another aspect of this application provides an electronic device, which includes a memory and a processor. The memory stores a computer program, and the processor executes the computer program to implement the above-described method.

[0041] To achieve the above objectives, another aspect of the embodiments of this application proposes a computer-readable storage medium storing a computer program that, when executed by a processor, implements the above-described method.

[0042] The embodiments of this application include at least the following beneficial effects:

[0043] This application can generate a first tree topology with the shortest line length and a second tree topology determined by weighting the shortest line length and congestion reduction for each circuit net; construct the first tree topology and the second tree topology of each circuit net into corresponding tree forests; select one tree topology from the two tree topologies of each tree forest as a candidate tree for each circuit net according to the objective function of global routing, and select candidate template paths for the candidate trees; determine the global routing scheme for the corresponding circuit nets based on each candidate tree and each candidate template path; generate a third tree topology to reduce congestion for the circuit nets with congestion in the global routing scheme, and replace the unselected tree topologies in the tree forest of the congested circuit nets with the third tree topology; delete the tree forests corresponding to the circuit nets without congestion in the global routing scheme; return to selecting one tree topology from the two tree topologies of each tree forest as a candidate tree for each circuit net according to the objective function of global routing, and select candidate template paths for the candidate trees, until a preset termination condition is reached, and use the current global routing scheme as the target global routing scheme for each circuit net. In addition to generating the first tree topology with the shortest line length, this application also generates a second tree topology that balances the shortest line length with reducing congestion. Then, a tree forest is constructed based on the two tree topologies, and global routing is performed based on the tree forest. For circuit nets with congestion, their tree topology is updated to obtain a tree topology with less congestion, thereby reducing congestion. For circuit nets without congestion, their tree forest is deleted, thereby reducing the amount of computation in the global routing process and improving efficiency. Attached Figure Description

[0044] To more clearly illustrate the technical solutions in the embodiments of this application, the accompanying drawings used in the description of the embodiments will be briefly introduced below. Obviously, the accompanying drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0045] Figure 1 Example diagrams of tree topologies and template paths for various nets provided in embodiments of this application;

[0046] Figure 2 An example flowchart of a global routing method provided in an embodiment of this application;

[0047] Figure 3 A training flowchart for the tree forest perspective provided in this application embodiment;

[0048] Figure 4 A flowchart illustrating the global routing method based on a dynamic tree provided in this application embodiment;

[0049] Figure 5 Example flowchart of dynamically updating tree forest provided in the embodiments of this application;

[0050] Figure 6 An example flowchart of a global routing method based on a dynamic tree provided in an embodiment of this application;

[0051] Figure 7 Example flowchart for dynamically reducing the size of a tree forest as provided in this application embodiment;

[0052] Figure 8 A schematic diagram of the structure of a global routing device based on a dynamic tree provided in an embodiment of this application;

[0053] Figure 9 This is a schematic diagram of the hardware structure of an electronic device provided in an embodiment of this application. Detailed Implementation

[0054] To make the objectives, technical solutions, and advantages of this application clearer, the following detailed description is provided in conjunction with the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely illustrative of this application and are not intended to limit it. In the following description, when referring to the accompanying drawings, unless otherwise indicated, the same numbers in different drawings represent the same or similar elements. The embodiments described in the following exemplary embodiments do not represent all embodiments consistent with those of this application; they are merely examples of apparatuses and methods consistent with some aspects of the embodiments of this application as detailed in the appended claims.

[0055] It is understood that the terms “first,” “second,” etc., used in this application may be used herein to describe various concepts, but unless otherwise stated, these concepts are not limited by these terms. These terms are only used to distinguish one concept from another. For example, without departing from the scope of the embodiments of this application, first information may also be referred to as second information, and similarly, second information may also be referred to as first information. Depending on the context, the words “if,” “when,” or “in response to a determination” as used herein may be interpreted as “when…” or “when…” or “in response to a determination.”

[0056] As used in this application, the terms "at least one", "multiple", "each", "any", etc., "at least one" includes one, two or more, "multiple" includes two or more, "each" refers to each of the corresponding multiples, and "any" refers to any one of the multiples.

[0057] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this application belongs. The terminology used herein is for the purpose of describing embodiments of this application only and is not intended to limit this application.

[0058] Before providing a detailed description of the embodiments of this application, some terms and related technologies involved in the embodiments of this application will be explained first. The terms and related technologies involved in the embodiments of this application are subject to the following interpretations:

[0059] Global routing typically aims to reduce wire length, via count, and congestion. Wire length refers to the total length of wires or signal lines connecting circuit components across all metal layers in the layout. Vias are electrical connections between different metal layers; the number of vias is the sum of all via counts on the layout. Congestion occurs when the number of traces in a routing unit exceeds the maximum allowed number, violating design rules; congestion is the sum of the excess in all routing units on the layout. With increasing chip design complexity and scale, traditional global routing algorithms still lack sufficient global consideration of overall layout routing resources and net distribution. This makes it difficult to effectively address congestion issues in the early stages of routing, significantly impacting the speed of subsequent EDA algorithms and the quality of the final layout.

[0060] Generally speaking, the global routing process involves the following steps:

[0061] 1. Spanning Tree Topology: Utilizing algorithms such as FLUTE to quickly generate a Rectilinear Steiner Minimal Tree (RSMT). FLUTE is a Rectilinear Steiner Minimal Tree construction algorithm that uses a lookup table method. This algorithm is fast and can achieve optimal results on low-degree (i.e., low-pin-count) networks. A Rectilinear Steiner Minimal Tree is the shortest path connecting a group of pins in a two-dimensional plane. A Rectilinear Steiner Minimal Tree can quickly provide an initial routing reference for a network.

[0062] 2. Pattern Routing: For the right-angle Steiner minimum tree generated in the first step, the Depth-First Search (DFS) algorithm is used to decompose the right-angle Steiner minimum tree into two-pin nets. A two-pin net is a net formed by two points in the tree that share an edge. Since the right-angle Steiner minimum tree is only two-dimensional, algorithms such as Dynamic Programming are needed to determine the specific routing of the two-pin nets and the layer assignment of the metal lines. That is, each two-pin net of the right-angle Steiner minimum tree is replaced with a routing pattern that conforms to certain templates (such as L-shaped or Z-shaped) while layer assignment is performed to quickly complete the 3D routing.

[0063] 3. Maze Routing: After the above algorithm process, there may still be nets that are difficult to route. The maze routing algorithm can better complete the routing of these nets.

[0064] Most commonly used global routing algorithms are CPU (Central Processing Unit) based algorithms, such as CUGR2. While they perform well in small-scale circuits, computation time and memory consumption increase exponentially in large-scale integrated circuit design, limiting the efficiency and scalability of automated design as modern integrated circuits continue to grow in scale. To address this challenge, GPU (Graphics Processing Unit) based acceleration algorithms have gained increasing attention in recent years. The parallel computing capabilities of GPUs can significantly accelerate certain computationally intensive tasks, especially in the automation of routing at very large scales, where their high parallelism and large data throughput advantages are fully utilized. Compared to algorithms running solely on a CPU that can only call one or a few threads, GPU-based algorithms have achieved considerable advantages in terms of runtime and other aspects during the global routing process of large-scale circuit design.

[0065] Next, the relevant technologies involved in this application will be described. It should be noted that the relevant technologies in this application are only used to describe this application more clearly, and the relevant technologies do not necessarily constitute prior art to this application.

[0066] The related technology (DGR) has proposed a global routing method that can utilize GPU computing resources. DGR first models a tree forest, which corresponds to two levels of selection probability matrices. The first level of selection probability matrix represents the selection probability of different tree topologies in each net (in this application, circuit nets can be simply referred to as nets, while 2-pin nets are a part of the structure of circuit nets). The second level of selection probability matrix represents the selection probability of different routing templates in each 2-pin net derived from all tree topologies. Then, the authors model the weights of wire length, via, and overflow. Finally, the overhead caused by each routing choice in each net is multiplied by the selection probability corresponding to that specific routing choice in parallel to obtain an objective function expression.

[0067] The relationship between the two-level selection probability matrices and specific wiring patterns comes from the tree forest. The structure of the tree forest is as follows: Figure 1 As shown in (a) above, the various tree topologies and their corresponding candidate paths are as follows: Figure 1 As shown in (b), the tree forest contains an indefinite number of net structures. Each net contains two tree topologies, each with a certain selection probability during optimization, and the sum of the selection probabilities of the two tree topologies is 1. Each tree topology can be further subdivided into a series of 2-pin nets. If the horizontal and vertical coordinates of the two pins of a 2-pin net are not the same (i.e., the line connecting the two points is diagonal), then for this 2-pin net, if routing is performed from one pin to another according to an L-shaped template, there will be two routing possibilities: horizontal routing first and then vertical routing, or vertical routing first and then horizontal routing. Both routing methods have a probability of being selected, and the sum of the selection probabilities of all routing templates under the same 2-pin net is 1.

[0068] After completing the above modeling work, the optimizer is used to optimize the minimum value of the objective function. The weight parameters with smaller objective function values ​​correspond to better global routing choices. Figure 2 The workflow of the DGR (Device Growing Regression) technology was demonstrated. After reading in the nets, layout, and other information required for routing, the tree forest was first initialized, giving each net two tree topologies. After the tree forest modeling was completed, the training process began. During training, gradient descent and other methods were used to continuously try to find the minimum value of the objective function until the candidate conditions were met. At this point, it can be considered that a better tree topology and candidate paths for 2-pin nets that meet expectations have been obtained, and training can stop. To explain the training process in detail, Figure 3The training process from a tree forest perspective is demonstrated. First, the unknown probabilities of each choice are initialized. Then, gradient descent is used to find the minimum of the objective function. After several iterations, the option with the highest probability within the same group is selected as the final choice. This algorithm achieves parallel computation by utilizing the parallel computing resources of the GPU. This mechanism of using probability to continuously represent the objective function reduces routing time and improves routing quality. After training, based on the selected candidate tree topology and candidate 2-pin net paths, the dynamic programming algorithm in CUGR2 is used for layer allocation to obtain the 3D routing results for the template routing stage. Next, common routing algorithms such as maze routing are used to perform the finest and final adjustments to areas where congestion is difficult to alleviate.

[0069] However, through analysis of the DGR routing process, the inventors of this application believe that DGR still has room for optimization. First, the DGR spanning tree topology is not generated from a global perspective; it only calls the FLUTE algorithm during generation. This algorithm generates the shortest spanning tree, but it cannot guarantee that congestion will be avoided as much as possible under this topology. Second, the DGR spanning tree remains static throughout the subsequent process. Even if the optimizer performs tree topology selection and template selection from a global perspective, the inherent topology of the spanning tree limits the optimizer's optimization potential.

[0070] Based on this, embodiments of this application provide a global routing method, apparatus, electronic device, and storage medium based on a dynamic tree. The technical solution of this application includes: generating a first tree topology with the shortest line length and a second tree topology determined by weighting the shortest line length and congestion reduction for each circuit net; constructing the first tree topology and the second tree topology of each circuit net into corresponding tree forests; selecting one tree topology from the two tree topologies of each tree forest as a candidate tree for each circuit net according to the objective function of global routing, and selecting candidate template paths for the candidate trees; determining the global routing scheme for the corresponding circuit nets based on each candidate tree and each candidate template path; generating a third tree topology to reduce congestion for the circuit nets with congestion in the global routing scheme, and replacing the unselected tree topologies in the tree forest of the congested circuit nets with the third tree topology; deleting the tree forests corresponding to the circuit nets without congestion in the global routing scheme; returning to selecting one tree topology from the two tree topologies of each tree forest as a candidate tree for each circuit net according to the objective function of global routing, and selecting candidate template paths for the candidate trees, until a preset termination condition is reached, and using the current global routing scheme as the target global routing scheme for each circuit net. In addition to generating the first tree topology with the shortest line length, this application also generates a second tree topology that balances the shortest line length with reducing congestion. Then, a tree forest is constructed based on the two tree topologies, and global routing is performed based on the tree forest. For circuit nets with congestion, their tree topology is updated to obtain a tree topology with less congestion, thereby reducing congestion. For circuit nets without congestion, their tree forest is deleted, thereby reducing the amount of computation in the global routing process and improving efficiency.

[0071] This application provides a global routing method based on dynamic trees, relating to the field of integrated circuit technology. The global routing method based on dynamic trees provided in this application can be applied to terminals, servers, or software running on either terminal or server. In some embodiments, the terminal can be a smartphone, tablet, laptop, desktop computer, smart speaker, smartwatch, or in-vehicle terminal, but is not limited to these. The server can be configured as an independent physical server, a server cluster composed of multiple physical servers, or a distributed system. It can also be configured as a cloud server providing basic cloud computing services such as cloud services, cloud databases, cloud computing, cloud functions, cloud storage, network services, cloud communication, middleware services, domain name services, security services, CDN, and big data and artificial intelligence platforms. The server can also be a node server in a blockchain network. The software can be an application implementing the global routing method based on dynamic trees, but is not limited to the above forms.

[0072] This application can be used in a wide variety of general-purpose or special-purpose computer system environments or configurations. Examples include: personal computers, server computers, handheld or portable devices, tablet devices, multiprocessor systems, microprocessor-based systems, set-top boxes, programmable consumer electronics, network PCs, minicomputers, mainframe computers, and distributed computing environments including any of the above systems or devices. This application can be described in the general context of computer-executable instructions executed by a computer, such as program modules. Generally, program modules include routines, programs, objects, components, data structures, etc., that perform specific tasks or implement specific abstract data types. This application can also be practiced in distributed computing environments where tasks are performed by remote processing devices connected via a communication network. In distributed computing environments, program modules can reside in local and remote computer storage media, including storage devices.

[0073] Reference Figure 4 This application provides a global routing method based on a dynamic tree, which may include, but is not limited to, steps S400 to S460, as follows:

[0074] S400: Generate the first tree topology with the shortest line length and the second tree topology determined by the shortest line length and congestion reduction weighting for each circuit net.

[0075] Specifically, each net generates two tree topologies: one is the first tree topology with the shortest line length, and the other is the second tree topology that balances the shortest line length with reducing congestion.

[0076] Furthermore, S400 may include S401 to S403:

[0077] S401: Generate the shortest right-angle Steiner minimum tree for each of the circuit nets as the first tree topology;

[0078] S402: Perform template routing on the corresponding circuit nets according to each of the right-angle Steiner minimum trees, and then obtain the congestion distribution map of each of the circuit nets;

[0079] S403: Using the undo and rewind algorithm, generate the winding tree corresponding to each of the circuit nets based on each of the congestion distribution maps as the second tree topology.

[0080] Specifically, in order to create more possibilities for globally optimal routing for the optimizer in the initial stage, a good tree topology needs to be generated as early as possible during the tree generation stage. The quality of a tree topology is reflected in two aspects: first, whether it can have the shortest possible line length, and second, whether it can effectively avoid congestion. Obtaining a tree that is conducive to globally optimal routing requires a trade-off between these two aspects.

[0081] Considering the actual situation in cabling, the difficulty of cabling varies in different areas. Some areas may have a high probability of congestion due to high network density or complex routing methods. Similarly, networks passing through these areas also have a higher probability of congestion. However, it is difficult to predict the distribution of congestion and the probability of network congestion in advance with fast and high accuracy. Traditional tree generation algorithms such as FLUTE only consider the shortest line length and do not simultaneously optimize for both reducing line length and avoiding congestion. Even if the congestion distribution is obtained in advance with coarse granularity using algorithms such as RUDY, the difference in congestion levels between different areas necessitates dynamically balancing the optimization weights of line length and congestion based on the congestion level when generating the tree, which remains very complex and difficult.

[0082] To alleviate the above problems, considering that the DGR algorithm can comprehensively weigh the topological merits of a tree from a global perspective, DGR prioritizes congestion in congested regions and vice versa. Therefore, this embodiment introduces two trees with completely different topological characteristics into the forest: one with the shortest line length and the other with the ability to avoid congestion to some extent. Combined with DGR's ability to measure the merits of trees from a global perspective, this indirectly achieves a dynamic trade-off between line length and congestion optimization weights, selecting the superior tree topology from a global perspective.

[0083] Reference Figure 5 In the process of traversing each net, this embodiment adopts the following method to complete the first construction of the tree forest:

[0084] 1) Use the FLUTE algorithm to quickly generate a right-angle Steiner minimum tree with the shortest or near-shortest line length; therefore, S401 can be further specified as: using the FLUTE algorithm to generate a right-angle Steiner minimum tree with the shortest line length for each of the circuit nets as the first tree topology.

[0085] 2) Using CUGR2 in conjunction with this right-angle Steiner minimum tree for template routing, a more accurate congestion distribution map can be obtained;

[0086] 3) The undo and rewind algorithm is used to generate a tree that can bypass the current congestion while still maintaining a short line length. Therefore, S403 can be further specified as: using the undo and rewind algorithm of CUGR2 to generate the winding tree of each of the circuit nets.

[0087] Therefore, two trees can be obtained for each net, and in subsequent optimization processes, both the shortest line length and congestion avoidance can be considered as much as possible. Finally, both obtained trees are added to the forest.

[0088] Still refer to Figure 1 (b) in the middle Figure 1 (b) in this example illustrates the construction of a tree forest using the method described in this embodiment. Each wire network structure contains two tree topologies: the first is a right-angle Steiner minimum tree structure generated using the FLUTE algorithm, and the second is a wire-wrap tree structure generated using the undo and rewind algorithm. This example demonstrates that the right-angle Steiner minimum tree has a shorter wire length, while the wire-wrap tree can sacrifice some wire length to bypass congested areas.

[0089] The beneficial effects of this embodiment:

[0090] Because of the use of a dynamic tree generation method, the generation of wiring trees is more flexible and can generate wiring trees in real time according to the congestion situation, which significantly reduces the occurrence of congestion.

[0091] S410: Construct the first tree topology and the second tree topology of each of the circuit nets into corresponding tree forests.

[0092] It is understandable that the two tree topologies corresponding to each net form a tree forest, that is, each net corresponds to a tree forest.

[0093] S420: Based on the objective function of global routing, select one tree topology from the two tree topologies of each tree forest as a candidate tree for each circuit net and select the candidate template path of the candidate tree.

[0094] Specifically, the objective function in this embodiment can be aimed at minimizing the length of the global wiring.

[0095] Select a tree topology from each tree forest, and select candidate template paths from multiple template paths in the selected tree topology.

[0096] Furthermore, S420 may include S421 to S425:

[0097] S421: Initialize the first candidate probability of the two tree topologies and the second candidate probability of the two tree topologies' 2-pin nets in each of the tree forests;

[0098] S422: Perform significance calculation on each of the first candidate probabilities and each of the second candidate probabilities;

[0099] S423: Obtain the minimum value of the objective function based on the result of the significance calculation and the gradient descent method, and then update each of the first candidate probabilities and each of the second candidate probabilities;

[0100] S424: If the updated first candidate probability and second candidate probability meet the selection conditions, then in each of the tree forests, the tree topology corresponding to the largest first candidate probability is selected as the candidate tree, and the 2-pin net corresponding to the largest second candidate probability in the candidate tree is selected as the candidate template path.

[0101] S425: If the updated first candidate probability and second candidate probability do not meet the selection criteria, then return to the result calculated based on the significance and the gradient descent method to update each of the first candidate probability and each of the second candidate probabilities until the updated first candidate probability and second candidate probability meet the selection criteria.

[0102] S430: Determine the global routing scheme for the corresponding circuit net based on each of the candidate trees and each of the candidate template paths.

[0103] For example, this embodiment can perform global routing based on the candidate tree and candidate template path using the CUGR2 algorithm.

[0104] S440: Generate a third tree topology to reduce congestion for the congested circuit nets in the global routing scheme, and replace the unselected tree topologies in the tree forest of the congested circuit nets with the third tree topology.

[0105] Specifically, for wired networks that are still congested, a new tree topology is generated to reduce congestion. The newly generated tree topology is then added to the corresponding tree forest, and any unselected tree topologies in the tree forest are deleted.

[0106] Furthermore, the step in S440 of generating a third-tree topology to reduce congestion for the congested circuit nets in the global routing scheme may include:

[0107] The undo and rewind algorithm is used to generate a winding tree for the congested circuit nets in the global routing scheme, which serves as the third tree topology.

[0108] Furthermore, the above steps can be specifically defined as: using the undo and rewind algorithm of CUGR2 to generate the winding tree of each of the circuit nets.

[0109] Specifically, the reason why DGR has an advantage in routing quality over traditional routing algorithms is that it can select the tree topology and the routing template of the 2-pin net from a more global perspective. However, the tree topology generated by DGR is not generated from a global perspective. Therefore, the optimization space of DGR is limited by the non-globally optimal tree forest. This means that the global optimization achieved by DGR does not take into account the global optimization of the entire process. Its global environment consideration scope only includes the template routing process and does not include the tree generation stage before the template routing process.

[0110] To alleviate this problem, this embodiment aims to expand the global environment consideration to the tree generation and template routing stages. This means generating tree topologies that maintain short trace lengths while effectively avoiding congestion, achieving a better routing effect than DGR with a more global perspective. Based on a thorough consideration of the global layout environment, specifically in the tree generation scheme, a highly accurate global congestion prediction algorithm can generate a highly effective tree structure that avoids congestion in the early stages. Alternatively, the tree structure can be iterated using real-time congestion results during the routing process. However, the former is a long-standing challenge in the routing field of electronic design automation. Firstly, before the tree generation stage, a high-precision prediction of all potential congestion scenarios for all nets is required. Then, for the predicted congestion areas, a tree topology that bypasses congestion is generated for all nets while fully considering the global context. Since it is difficult to obtain an accurate congestion distribution map during the tree generation stage, the latter approach takes a gradual approach, using feedback iterations to progressively approximate the global optimum. During cabling, the congestion distribution map is obtained in real time. For the still congested networks, the topology is regenerated while the already cabled results are canceled, and the DGR process is restarted. This allows the congestion to be bypassed while still continuing to optimize from a global perspective.

[0111] The steps involved in dynamically updating a tree forest may include:

[0112] 1) After the objective function optimization curve of DGR becomes flat, the optimal routing scheme has been obtained by the optimizer in the current state.

[0113] 2) Then, for the still congested network, the CUGR2 undo and rewind algorithm is used to regenerate its tree topology. The generated tree topology is added to the candidate forest of tree topology for the network, while the tree topology that was not selected in the previous step is removed.

[0114] 3) After traversing the still congested network and dynamically updating the tree topology, re-perform the DGR training and optimization process. Repeat the above process several times until there is no more room for optimization.

[0115] The reason for pruning tree topologies is that tree topologies that were not selected in the previous iteration have been proven by the DGR selection mechanism to be inferior to selected tree topologies from a global perspective. Therefore, they will not be selected by the optimizer again in subsequent stages, and there is no need to retain them. At the same time, pruning redundant tree topologies can control the size of the forest, save computing resources, and thus reduce runtime overhead.

[0116] By dynamically updating the tree, more possibilities for global optima can be created, providing more optimization space for DGR and allowing for further optimization of the objective function.

[0117] The beneficial effects of this embodiment:

[0118] By making local adjustments only to congested networks, unnecessary redundant calculations are reduced, thus improving the overall performance of the cabling algorithm.

[0119] S450: Delete the forest of trees corresponding to the uncongested circuit nets in the global cabling scheme.

[0120] Specifically, during each dynamic tree update, since the number of congested nets only accounts for a small portion of the total, to conserve computing resources, there is no need to further optimize the routing of most nets that are no longer congested. Therefore, in this embodiment, when performing a dynamic tree update, these nets that are no longer congested can be removed from the list of nets that need further optimization, while only those nets that are still congested are retained for further optimization.

[0121] Reference Figure 6 This embodiment provides an example flowchart of a global wiring method based on dynamic trees. In this embodiment, an algorithm for dynamically reducing the size of the forest needs to be executed before each training session. Meanwhile... Figure 7 This paper presents a specific implementation method for dynamically reducing the size of the forest network from a forest perspective. First, all nets are traversed to check for congestion: if there are congested cabling units along the routing path, the net is considered congested; otherwise, it is considered uncongested. If there is no congestion, the net is removed from the forest and does not participate in the next training iteration. With this method, the size of the forest participating in training in each workflow loop decreases rapidly with the number of loops. Since the proportion of congested nets is relatively low, even with multiple dynamic tree updates and retraining, the computational resource consumption does not increase linearly compared to the single training iteration of DGR. This embodiment achieves a better trade-off between computational resource consumption and routing efficiency.

[0122] The beneficial effects of this embodiment:

[0123] By introducing a method to dynamically reduce the size of forest trees, recalculation is avoided, thus improving the computational efficiency of global routing.

[0124] S460: Return to the step of selecting one tree topology from the two tree topologies of each tree forest as a candidate tree for each circuit net according to the objective function of global routing, and selecting the candidate template path of the candidate tree until the preset termination condition is reached, and take the current global routing scheme as the target global routing scheme for each circuit net.

[0125] It is understandable that after replacing the tree topology and deleting the tree forest with no congestion wires, the tree forest in this embodiment undergoes dynamic updates, and then repeats S410 and subsequent steps with the current tree forest to achieve iterative selection of tree topology and template path, which can further reduce congestion.

[0126] The following section will provide a detailed introduction and explanation of the solutions in the embodiments of this application, using specific application examples.

[0127] The purpose of this embodiment is to overcome the shortcomings of traditional global routing algorithms in terms of low efficiency and insufficient congestion handling capability when processing large-scale circuits. At the same time, it improves the flexibility of the algorithm based on DGR and provides a GPU-accelerated global routing dynamic congestion optimization method. By introducing dynamic tree generation, local update and congestion tree processing mechanisms, the congestion problem generated during global routing is optimized.

[0128] The objective of this embodiment is achieved through the following technical solution:

[0129] This embodiment includes three key steps: Step 1) First, in the pre-training preparation stage, the tree forest construction method is clarified using the congestion prediction tree generation method to obtain a tree forest that takes into account both line length and congestion awareness; Step 2) Second, after each training is completed, for the still congested network, the tree topology in its tree forest is dynamically updated to expand the possibility of global optimization; Step 3) Third, to address the problem of wasted computing resources caused by repeated training in Step 2), a method for dynamically reducing the size of the candidate tree forest is proposed. By removing those networks without congestion from the tree forest before training, the size of the tree forest is dynamically reduced, thereby saving computing resources and achieving faster wiring speed.

[0130] This embodiment constructs a new and complete routing process based on DGR through the above three steps: still referring to Figure 6After inputting the required data such as nets and layout for the routing problem, for each net, the FLUTE algorithm is first used to obtain the right-angle Steiner minimum tree, and then the CUGR2 algorithm is used to obtain the winding tree, thus completing the initialization of the tree forest construction. Compared with DGR, this embodiment obtains a clear method for initializing and constructing the tree forest. Then, the training process begins, using gradient descent to obtain the minimum value of the objective function. Finally, the optimal tree topology and candidate paths for 2-pin nets are obtained by judging whether the selection probability is greater than 90%, thus completing the selection of the tree forest. After the tree forest selection is completed, for nets that are still congested, a new congestion-aware winding tree is generated based on the current congestion situation, and then the tree topology of the corresponding nets in the tree forest that will no longer be selected is replaced, thereby dynamically updating the composition of the tree forest and obtaining more potential optimization space for the next round of retraining. Before starting the next round of training, nets without congestion are removed from the tree forest to reduce the size of the tree forest. After completing the work of dynamically updating the trees and reducing the size of the tree forest, the next round of training can begin. Figure 5 As can be seen, the complete routing process constitutes a loop, and the number of loops can be arbitrarily controlled based on the routing effect and time consumption. In contrast, DGR does not perform loops, and its coarse-grained forest processing method limits its routing effect.

[0131] pass Figure 2 and Figure 6 The comparison reveals the changes in this embodiment before and after introducing the above three steps on top of DGR. In the three steps, the congestion prediction tree generation method plays a role in the initial tree forest construction, providing a tree forest structure that balances line length and congestion avoidance to a certain extent in the initial stage. The dynamic tree update method and the dynamic candidate tree forest size reduction method play a role between the two training rounds. These two methods respectively process the congested and non-congested networks from the previous round's results, and together cover all networks in the tree forest. They employ improvement methods in both wiring efficiency and time consumption, achieving a good balance between these two conflicting aspects.

[0132] Next, we will describe a more specific implementation method.

[0133] This embodiment utilizes benchmark tests provided by the International Symposium on Physical Design (ISPD) ISPD18 and ISPD19 competitions, and the International Conference on Computer-Aided Design (ICCAD) ICCAD19 competition. The benchmark tests are input into this patent to obtain global routing results, and then detailed routing results from the benchmark tests are obtained through relevant technical means. The platform configuration for running the global routing program is shown in Table 1.

[0134] Table 1

[0135]

[0136] The test results of this embodiment are shown in Table 2. The ICCAD19 weighting standard was adopted, and the routing results are divided into three items: line length, via, and overflow.

[0137] Table 2

[0138]

[0139]

[0140] In addition to the implementation methods mentioned in this embodiment, the following modifications can be made: the number of tree updates can be controlled independently; and it is fully compatible with other tree generation algorithms.

[0141] Reference Figure 8 This application also provides a global routing apparatus based on a dynamic tree, which can implement the above-described global routing method based on a dynamic tree. The apparatus includes:

[0142] The tree topology generation unit is used to generate the first tree topology with the shortest line length and the second tree topology determined by the shortest line length and congestion reduction weighting for each circuit net.

[0143] A tree forest construction unit is used to construct the first tree topology and the second tree topology of each of the circuit nets into corresponding tree forests;

[0144] The tree and path selection unit is used to select one of the tree topologies from the two tree topologies of each of the tree forests as a candidate tree for each of the circuit nets according to the objective function of global routing, and to select the candidate template path of the candidate tree.

[0145] A global routing unit is used to determine a global routing scheme for the corresponding circuit net based on each of the candidate trees and each of the candidate template paths.

[0146] The tree forest update unit is used to generate a third tree topology to reduce congestion for the congested circuit network in the global cabling scheme, and to replace the tree topology that was not selected in the tree forest of the congested circuit network with the third tree topology.

[0147] The tree forest deletion unit is used to delete the tree forest corresponding to the circuit network without congestion in the global wiring scheme.

[0148] The repeated selection unit is used to return the selection of one tree topology from the two tree topologies of each tree forest as a candidate tree for each circuit net according to the objective function of global routing, and to select the candidate template path of the candidate tree until the preset termination condition is reached, and to take the current global routing scheme as the target global routing scheme for each circuit net.

[0149] It is understood that the content of the above method embodiments is applicable to the present device embodiments. The specific functions implemented by the present device embodiments are the same as those of the above method embodiments, and the beneficial effects achieved are also the same as those achieved by the above method embodiments.

[0150] This application also provides an electronic device, which includes a memory and a processor. The memory stores a computer program, and the processor executes the computer program to implement the aforementioned global routing method based on a dynamic tree. This electronic device can be any smart terminal, including tablet computers, in-vehicle computers, etc.

[0151] It is understood that the content of the above method embodiments is applicable to this device embodiment. The specific functions implemented by this device embodiment are the same as those of the above method embodiments, and the beneficial effects achieved are also the same as those achieved by the above method embodiments.

[0152] Please see Figure 9 , Figure 9 The hardware structure of an electronic device according to another embodiment is illustrated. The electronic device includes:

[0153] The processor 901 can be implemented using a general-purpose CPU (Central Processing Unit), microprocessor, application-specific integrated circuit (ASIC), or one or more integrated circuits, and is used to execute relevant programs to implement the technical solutions provided in the embodiments of this application.

[0154] The memory 902 can be implemented as a read-only memory (ROM), static storage device, dynamic storage device, or random access memory (RAM). The memory 902 can store the operating system and other application programs. When the technical solutions provided in the embodiments of this specification are implemented through software or firmware, the relevant program code is stored in the memory 902 and is called and executed by the processor 901 using the global routing method based on dynamic trees according to the embodiments of this application.

[0155] The input / output interface 903 is used to implement information input and output;

[0156] The communication interface 904 is used to enable communication and interaction between this device and other devices. Communication can be achieved through wired means (such as USB, Ethernet cable, etc.) or wireless means (such as mobile network, WIFI, Bluetooth, etc.).

[0157] Bus 905 transmits information between various components of the device (e.g., processor 901, memory 902, input / output interface 903, and communication interface 904);

[0158] The processor 901, memory 902, input / output interface 903, and communication interface 904 are connected to each other within the device via bus 905.

[0159] This application also provides a computer-readable storage medium storing a computer program that, when executed by a processor, implements the above-described global routing method based on a dynamic tree.

[0160] It is understood that the content of the above method embodiments is applicable to this storage medium embodiment. The specific functions implemented in this storage medium embodiment are the same as those in the above method embodiments, and the beneficial effects achieved are also the same as those achieved in the above method embodiments.

[0161] Memory, as a non-transitory computer-readable storage medium, can be used to store non-transitory software programs and non-transitory computer-executable programs. Furthermore, memory may include high-speed random access memory, and may also include non-transitory memory, such as at least one disk storage device, flash memory device, or other non-transitory solid-state storage device. In some embodiments, memory may optionally include memory remotely located relative to the processor, and these remote memories can be connected to the processor via a network. Examples of such networks include, but are not limited to, the Internet, intranets, local area networks, mobile communication networks, and combinations thereof.

[0162] The embodiments described in this application are for the purpose of more clearly illustrating the technical solutions of the embodiments of this application, and do not constitute a limitation on the technical solutions provided by the embodiments of this application. As those skilled in the art will know, with the evolution of technology and the emergence of new application scenarios, the technical solutions provided by the embodiments of this application are also applicable to similar technical problems.

[0163] Those skilled in the art will understand that the technical solutions shown in the figures do not constitute a limitation on the embodiments of this application, and may include more or fewer steps than shown, or combine certain steps, or different steps.

[0164] The device embodiments described above are merely illustrative. The units described as separate components may or may not be physically separate; that is, they may be located in one place or distributed across multiple network units. Some or all of the modules can be selected to achieve the purpose of this embodiment according to actual needs.

[0165] Those skilled in the art will understand that all or some of the steps in the methods disclosed above, as well as the functional modules / units in the systems and devices, can be implemented as software, firmware, hardware, or suitable combinations thereof.

[0166] The terms “first,” “second,” “third,” “fourth,” etc. (if present) in the specification and accompanying drawings of this application are used to distinguish similar objects and are not necessarily used to describe a specific order or sequence. It should be understood that such data can be interchanged where appropriate so that the embodiments of this application described herein can be implemented in orders other than those illustrated or described herein. Furthermore, the terms “comprising” and “having,” and any variations thereof, are intended to cover non-exclusive inclusion; for example, a process, method, system, product, or apparatus that comprises a series of steps or units is not necessarily limited to those steps or units explicitly listed, but may include other steps or units not explicitly listed or inherent to such processes, methods, products, or apparatus.

[0167] It should be understood that in this application, "at least one (item)" means one or more, and "more than" means two or more. "And / or" is used to describe the relationship between related objects, indicating that three relationships can exist. For example, "A and / or B" can represent three cases: only A exists, only B exists, and both A and B exist simultaneously, where A and B can be singular or plural. The character " / " generally indicates that the preceding and following related objects are in an "or" relationship. "At least one (item) of the following" or similar expressions refer to any combination of these items, including any combination of single or plural items. For example, at least one (item) of a, b, or c can represent: a, b, c, "a and b", "a and c", "b and c", or "a and b and c", where a, b, and c can be single or multiple.

[0168] In the several embodiments provided in this application, it should be understood that the disclosed apparatus and methods can be implemented in other ways. For example, the apparatus embodiments described above are merely illustrative; for instance, the division of the units described above is only a logical functional division, and in actual implementation, there may be other division methods. For example, multiple units or components may be combined or integrated into another system, or some features may be ignored or not executed. Furthermore, the coupling or direct coupling or communication connection shown or discussed may be through some interfaces; the indirect coupling or communication connection between apparatuses or units may be electrical, mechanical, or other forms.

[0169] The units described above as separate components may or may not be physically separate. The components shown as units may or may not be physical units; that is, they may be located in one place or distributed across multiple network units. Some or all of the units can be selected to achieve the purpose of this embodiment according to actual needs.

[0170] Furthermore, the functional units in the various embodiments of this application can be integrated into one processing unit, or each unit can exist physically separately, or two or more units can be integrated into one unit. The integrated unit can be implemented in hardware or as a software functional unit.

[0171] If the integrated unit is implemented as a software functional unit and sold or used as an independent product, it can be stored in a computer-readable storage medium. Based on this understanding, the technical solution of this application, in essence, or the part that contributes to the prior art, or all or part of the technical solution, can be embodied in the form of a software product. This computer software product is stored in a storage medium and includes multiple instructions to cause a computer device (which may be a personal computer, server, or network device, etc.) to execute all or part of the steps of the methods of the various embodiments of this application. The aforementioned storage medium includes various media capable of storing programs, such as USB flash drives, portable hard drives, read-only memory (ROM), random access memory (RAM), magnetic disks, or optical disks.

[0172] The preferred embodiments of the present application have been described above with reference to the accompanying drawings, but this does not limit the scope of the claims of the present application. Any modifications, equivalent substitutions, and improvements made by those skilled in the art without departing from the scope and substance of the embodiments of the present application shall be within the scope of the claims of the present application.

Claims

1. A global routing method based on dynamic trees, characterized in that, The method includes the following steps: For each circuit network, generate a first tree topology with the shortest line length and a second tree topology determined by the shortest line length and congestion reduction weighting. The first tree topology and the second tree topology of each of the circuit nets are respectively constructed into corresponding tree forests; Based on the objective function of global routing, one tree topology is selected from the two tree topologies of each of the tree forests as a candidate tree for each of the circuit nets, and a candidate template path is selected for the candidate tree; A global routing scheme for the corresponding circuit net is determined based on each of the candidate trees and each of the candidate template paths; For the congested circuit nets in the global routing scheme, a third tree topology to reduce congestion is generated, and the unselected tree topologies in the tree forest of the congested circuit nets are replaced with the third tree topology. Delete the forest of trees corresponding to the circuit nets without congestion in the global cabling scheme; Returning to the objective function of global routing, select one tree topology from the two tree topologies of each tree forest as a candidate tree for each circuit net and select the candidate template path of the candidate tree until a preset termination condition is reached, and take the current global routing scheme as the target global routing scheme for each circuit net.

2. The dynamic tree based global routing method of claim 1, wherein, The process of generating a first tree topology with the shortest line length and a second tree topology determined by the shortest line length and congestion reduction weighting for each circuit net includes the following steps: Generate the shortest right-angle Steiner minimum tree for each of the circuit nets as the first tree topology; Template routing is performed on the corresponding circuit nets based on each of the right-angle Steiner minimum trees to obtain the congestion distribution map of each of the circuit nets; The undo and rewind algorithm is used to generate the winding tree corresponding to each of the circuit nets based on each of the congestion distribution maps, which serves as the second tree topology.

3. The global routing method based on dynamic tree according to claim 1, characterized in that, The process of generating a third-tree topology to reduce congestion in the congested circuit nets of the global routing scheme includes the following steps: The undo and rewind algorithm is used to generate a winding tree for the congested circuit nets in the global routing scheme, which serves as the third tree topology.

4. The global routing method based on dynamic tree according to claim 2, characterized in that, The process of generating the shortest right-angle Steiner minimum tree for each of the circuit nets as the first tree topology includes the following steps: The FLUTE algorithm is used to generate the shortest right-angle Steiner minimum tree for each of the circuit nets, which is then used as the first tree topology.

5. The global routing method based on a dynamic tree according to any one of claims 2 or 3, characterized in that, Generating the winding tree for each of the circuit nets using the aforementioned undo / rewind algorithm includes the following steps: The undo and rewind algorithm of CUGR2 is used to generate the winding tree of each of the circuit nets.

6. The global routing method based on dynamic tree according to claim 1, characterized in that, The step of selecting one tree topology from the two tree topologies of each of the tree forests as a candidate tree for each of the circuit nets based on the objective function of global routing, and selecting the candidate template path of the candidate tree, includes the following steps: Initialize the first candidate probability of two tree topologies in each of the tree forests and the second candidate probability of the 2-pin net of the two tree topologies; Significance calculations are performed on each of the first candidate probabilities and each of the second candidate probabilities; The minimum value of the objective function is obtained based on the result of the significance calculation and the gradient descent method, and then each of the first candidate probabilities and each of the second candidate probabilities are updated. If the updated first candidate probability and second candidate probability meet the selection criteria, then the tree topology corresponding to the largest first candidate probability in each of the tree forests is selected as the candidate tree, and the 2-pin net corresponding to the largest second candidate probability in the candidate tree is selected as the candidate template path. If the updated first candidate probability and second candidate probability do not meet the selection criteria, then return to the method of updating each first candidate probability and each second candidate probability according to the result of the significance calculation and the gradient descent method until the updated first candidate probability and second candidate probability meet the selection criteria.

7. The global routing method based on a dynamic tree according to claim 6, characterized in that, The method further includes the following steps: Determine whether the updated probabilities of the first and second candidates reach 90%. The candidate probability and the second candidate probability, after being updated, are determined to meet the selection criteria if they both reach 90%. If the updated first candidate probability and second candidate probability do not reach 90%, it is determined that the selection condition is not met.

8. A global routing device based on a dynamic tree, characterized in that, The device includes: The tree topology generation unit is used to generate the first tree topology with the shortest line length and the second tree topology determined by the shortest line length and congestion reduction weighting for each circuit net. A tree forest construction unit is used to construct the first tree topology and the second tree topology of each of the circuit nets into corresponding tree forests; The tree and path selection unit is used to select one of the tree topologies from the two tree topologies of each of the tree forests as a candidate tree for each of the circuit nets according to the objective function of global routing, and to select the candidate template path of the candidate tree. A global routing unit is used to determine a global routing scheme for the corresponding circuit net based on each of the candidate trees and each of the candidate template paths. The tree forest update unit is used to generate a third tree topology to reduce congestion for the congested circuit network in the global cabling scheme, and to replace the tree topology that was not selected in the tree forest of the congested circuit network with the third tree topology. The tree forest deletion unit is used to delete the tree forest corresponding to the circuit network without congestion in the global wiring scheme. The repeated selection unit is used to return the selection of one tree topology from the two tree topologies of each tree forest as a candidate tree for each circuit net according to the objective function of global routing, and to select the candidate template path of the candidate tree until the preset termination condition is reached, and to take the current global routing scheme as the target global routing scheme for each circuit net.

9. An electronic device, characterized in that, The electronic device includes a memory and a processor, the memory storing a computer program, and the processor executing the computer program to implement the method as described in any one of claims 1 to 7.

10. A computer-readable storage medium storing a computer program, characterized in that, When the computer program is executed by a processor, it implements the method as described in any one of claims 1 to 7.

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