Test system, color filter and test method of array substrate
By designing a simplified test system and summarizing the test lines to the bus, the problem of low detection efficiency of color filters for diagonal arrangement pixel units in the prior art is solved, and efficient power-on testing and detection effects are achieved.
Patent Information
- Application Number
- CN202311259527.1
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2023-09-27
- Publication Date
- 2025-03-28
AI Technical Summary
The prior art is difficult to efficiently detect color filters using diagonally arranged pixel units, especially when the test lines are complex, it is impossible to take into account the efficiency of the test and the rationality of the trace.
A test system is designed, by summarizing the source line and gate line to the bus, the line arrangement of the test line and system is simplified, and efficient power-on testing of any sub-pixel is achieved.
This method simplifies the test circuit, improves detection efficiency, and can efficiently detect the display of pixels, and is suitable for color filters of diagonally arranged pixel units.
Smart Images
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Abstract
Description
Technical Field
[0001] The present invention relates to the field of display technology, and in particular to a testing system, a color filter and a testing method for an array substrate. Background Art
[0002] The display screen filters the incident light through a color filter (CF), selects a small range of light waves to pass through, and then realizes color imaging through a combination of different colors. The color filter usually includes multiple pixel units, each pixel unit includes multiple sub-pixels, usually including four types of sub-pixels: R (red) red sub-pixel, G (green) green sub-pixel, B (blue) blue sub-pixel and W (white) color sub-pixel.
[0003] like Figure 1 As shown in the figure, in the traditional color filter, RGB or RGBW sub-pixels are mainly arranged in Strip. At this time, RGB in the same column has exactly the same arrangement rule. This traditional sub-pixel arrangement cannot provide a higher resolution. In order to meet the high resolution requirements of display products, such as Figure 2 As shown, the same sub-pixels in different columns can be arranged diagonally to achieve higher resolution. In order to detect defects in display modules in advance, electrical testing equipment is usually used to perform display inspection on color filters before display module molding, thereby reducing the loss of module materials and production in the later process. Current electrical testing usually performs red, green, blue, white and black monochrome image inspections, such as Figure 1 For the sub-pixel arrangement shown in the figure, when conducting electrical testing, directly connect the corresponding RGB drive lines separately and give electrical test signals to each for testing, so as to achieve the test effect of different colors. Figure 2 As shown in the sub-pixel arrangement, the conventional test method mentioned above cannot take into account both the test efficiency and the rationality of the routing due to problems such as complex routing.
[0004] Therefore, a method for detecting a color filter using diagonally arranged pixel units is needed. Summary of the invention
[0005] The present invention aims to solve at least one of the problems in the background technology. To this end, the present invention provides a test system, a color filter and a test method for an array substrate, wherein the test system simplifies the test circuit and the circuit arrangement of the test system, and can efficiently detect the display status of pixels.
[0006] A test system according to an embodiment of a first aspect of the present invention includes a pixel layer and a test circuit, wherein the pixel layer includes a plurality of pixel units, each pixel unit includes at least three sub-pixels, wherein the sub-pixels are arranged in a Mosaic manner, and each of the sub-pixels is provided with a TFT switch, wherein the TFT switch includes a source electrode, a gate electrode, and a drain electrode; the test circuit includes a source line group and a gate line group, wherein the source line group includes a first source line, a second source line, and a third source line which are sequentially connected to the source electrode of one of the sub-pixels, and the first source line, the second source line, and the third source line are sequentially arranged repeatedly along the first direction, and the gate ... The gate of the pixel is connected to a first gate line, a second gate line and a third gate line, and the first gate line, the second gate line and the third gate line are repeatedly arranged in sequence along the second direction; wherein the source line group includes a first source bus, a second source bus and a third source bus, and a plurality of the first source lines, the second source lines and the third source lines are respectively summarized in the first source bus, the second source bus and the third source bus, and at the same time, the gate line group includes a first gate bus, a second gate bus and a third gate bus, and a plurality of the first gate lines, the second gate lines and the third gate lines are respectively summarized in the first gate bus, the second gate bus and the third gate bus.
[0007] It can be seen that this solution aggregates all source lines into a source bus and all gate lines into a gate bus, and any sub-pixel can be powered on for testing by energizing the corresponding gate bus and source bus, thereby simplifying the arrangement of the test circuits and the test system, and achieving efficient detection of the display condition.
[0008] According to another embodiment of the present invention, the sub-pixels include a red sub-pixel, a blue sub-pixel and a green sub-pixel.
[0009] According to another embodiment of the present invention, the sub-pixels include a red sub-pixel, a blue sub-pixel, a green sub-pixel and a white sub-pixel.
[0010] According to another embodiment of the present invention, the source line group includes a fourth source bus and multiple fourth source lines, the multiple fourth source lines are respectively connected to the sources of multiple white sub-pixels, and the multiple first source lines, the second source lines, the third source lines and the fourth source lines are repeatedly arranged in sequence along the first direction.
[0011] According to another embodiment of the present invention, the gate line group includes a fourth gate bus and a plurality of fourth gate lines, the plurality of fourth gate lines are respectively connected to the gates of a plurality of white sub-pixels, and a plurality of the first gate lines, the second gate lines, the third gate lines and the fourth gate lines are repeatedly arranged in sequence along the second direction.
[0012] According to another embodiment of the present invention, it also includes a test power supply, which is electrically connected to the first gate bus, the second gate bus, the third gate bus, the first source bus, the second source bus and the third source bus, and the test parameters provided by the test power supply are one or more of resistance value, current value or voltage value.
[0013] According to a method for detecting a color filter according to an embodiment of a second aspect of the present invention, the color filter includes a pixel layer, and the pixel layer includes at least three sub-pixels arranged in a mosaic manner. The method includes:
[0014] Mark the gate line and source line of the sub-pixel at each position;
[0015] Based on the flag, a gate line and a source line of at least one of the sub-pixels are powered on and tested.
[0016] According to another embodiment of the present invention, marking the gate line and the source line of the sub-pixel at each position specifically includes:
[0017] Divide the gate lines into three groups, labeled G1, G2, and G3;
[0018] The source lines are divided into three groups, labeled S1, S2 and S3 respectively.
[0019] According to a method for detecting an array substrate in an embodiment of a third aspect of the present invention, the array substrate includes a pixel layer, and the pixel layer includes at least three sub-pixels arranged in a mosaic manner. The method includes:
[0020] Mark the gate line and source line of the sub-pixel at each position;
[0021] Based on the flag, a gate line and a source line of at least one of the sub-pixels are powered on and tested.
[0022] According to another embodiment of the present invention, marking the gate line and the source line of the sub-pixel at each position specifically includes:
[0023] Divide the gate lines into three groups, labeled G1, G2, and G3;
[0024] The source lines are divided into three groups, marked as S1, S2 and S3 respectively.
[0025] Compared with the prior art, the present invention has the following beneficial effects:
[0026] The present invention discloses a test system, comprising a pixel layer and a test circuit, wherein the pixel layer comprises a plurality of pixel units, each pixel unit comprises at least three sub-pixels, wherein the sub-pixels are arranged in a Mosaic manner, and each sub-pixel is provided with a TFT switch, and the TFT switch comprises a source electrode, a gate electrode and a drain electrode; the test circuit comprises a source electrode line group and a gate electrode line group, the source electrode line group comprises a first source electrode line, a second source electrode line and a third source electrode line which are sequentially connected to a source electrode of a sub-pixel, and the first source electrode line, the second source electrode line and the third source electrode line are sequentially arranged repeatedly along a first direction, and the gate ... The gates of the sub-pixels are connected to the first gate line, the second gate line and the third gate line, and the first gate line, the second gate line and the third gate line are arranged repeatedly in sequence along the second direction; wherein the source line group includes the first source bus, the second source bus and the third source bus, and the plurality of first source lines, the second source lines and the third source lines are respectively summarized in the first source bus, the second source bus and the third source bus, and at the same time, the gate line group includes the first gate bus, the second gate bus and the third gate bus, and the plurality of first gate lines, the second gate line and the third gate line are respectively summarized in the first gate bus, the second gate bus and the third gate bus. It can be seen that by summarizing all the source lines to the source bus and summarizing all the gate lines to the gate bus, any sub-pixel can be powered on by energizing the corresponding gate bus and source bus, which simplifies the arrangement of the test circuit and the test system, and can efficiently detect the display of the pixel.
[0027] Additional aspects and advantages of the present invention will be given in part in the following description and in part will be obvious from the following description, or will be learned through practice of the present invention. BRIEF DESCRIPTION OF THE DRAWINGS
[0028] The accompanying drawings are only used to illustrate the embodiments and are not to be considered as limiting the present invention. In addition, the same reference symbols are used to represent the same components throughout the accompanying drawings. In the accompanying drawings:
[0029] Figure 1 is a schematic diagram of a pixel layer in the prior art;
[0030] Figure 2 A schematic diagram of an embodiment of a pixel unit of a test system provided by the present application;
[0031] Figure 3 A schematic diagram of another embodiment of a pixel unit of a test system provided by the present application;
[0032] Figure 4 A schematic diagram of an embodiment of a test system provided by the present application;
[0033] Figure 5 A schematic diagram of a flow chart of an embodiment of a method for testing a color filter provided in the present application;
[0034] Figure 6 A schematic flow chart of another embodiment of a method for testing a color filter provided in the present application;
[0035] Figure 7 A schematic diagram of a process flow of an embodiment of a method for testing an array substrate provided in the present application;
[0036] Figure 8 This is a flow chart of another embodiment of the array substrate testing method provided in the present application; the meanings of the marks in the figure are:
[0037] 10. Test system;
[0038] 100, pixel layer; 110, pixel unit; 111, sub-pixel; 1111, red sub-pixel;
[0039] 1112, blue sub-pixel; 1113, green sub-pixel; 1114, white sub-pixel;
[0040] 112. TFT switch;
[0041] 210, source line group; 211, first source bus line; 2111, first source line;
[0042] 212, a second source bus line; 2121, a second source line; 213, a third source bus line;
[0043] 2131, third source line;
[0044] 220, gate line group; 221, first gate bus line; 2211, first gate line;
[0045] 222, a second gate bus line; 2221, a second gate line; 223, a third gate bus line;
[0046] 2231. The third gate line. DETAILED DESCRIPTION
[0047] Embodiments of the present invention are described in detail below, examples of which are shown in the accompanying drawings, wherein the same or similar reference numerals throughout represent the same or similar elements or elements having the same or similar functions. The embodiments described below with reference to the accompanying drawings are exemplary and are only used to explain the present invention, and cannot be understood as limiting the present invention.
[0048] In the description of the present invention, it is to be understood that a feature defined as "first" or "second" may explicitly or implicitly include one or more of the features. In the description of the present invention, unless otherwise specified, "plurality" means two or more.
[0049] In the description of the present invention, it should be noted that, unless otherwise clearly specified and limited, the terms "installed", "connected", and "connected" should be understood in a broad sense, for example, it can be a fixed connection, a detachable connection, or an integral connection; it can be a mechanical connection or an electrical connection; it can be a direct connection, or it can be indirectly connected through an intermediate medium, or it can be the internal communication of two components. For ordinary technicians in this field, the specific meanings of the above terms in the present invention can be understood according to specific circumstances.
[0050] In order to illustrate the testing system, color filter and array substrate testing method provided in the present application, a detailed description is given below in conjunction with the accompanying drawings and the textual description of the embodiments.
[0051] Reference below Figure 2-Figure 4 A test system 10 according to an embodiment of the first aspect of the present invention is described. Figure 2-Figure 4As shown, the test system 10 includes a pixel layer 100 and a test circuit. Specifically, the pixel layer 100 includes a plurality of identical pixel units 110, each pixel unit 110 includes at least three sub-pixels 111, wherein the plurality of sub-pixels 111 are arranged in a Mosaic manner, that is, a diagonal arrangement is adopted, and a TFT switch 112 is provided in each sub-pixel 111, each TFT switch 112 includes a source electrode (not shown in the figure), a gate electrode (not shown in the figure) and a drain electrode (not shown in the figure), and further, the test circuit includes a source line group 210 and a gate electrode group 211. The gate line group 220 includes a first source line 2111, a second source line 2121 and a third source line 2131, and the first source line 2111, the second source line 2121 and the third source line 2131 are respectively connected to the source of a sub-pixel 111, and the first source line 2111, the second source line 2121 and the third source line 2131 are repeatedly arranged in sequence along the first direction. Further, the gate line group 220 includes a first gate line 2211, a second gate line 2221 and a third gate line 2231, and the first gate line 2211, the second gate line 2221 and The third gate line 2231 is connected to the gate of a sub-pixel 111 respectively. At the same time, the first gate line 2211, the second gate line 2221 and the third gate line 2231 are repeatedly arranged in sequence along the second direction, and the first direction and the second direction are perpendicular to each other. Further, the source line group 210 includes a first source bus 211, a second source bus 212 and a third source bus 213. The plurality of first source lines 2111, the second source lines 2121 and the third source lines 2131 are respectively aggregated in the first source bus 211, the second source bus 212 and the third source bus 213. At the same time, the gate line group 220 It includes a first gate bus 221, a second gate bus 222 and a third gate bus 223. A plurality of first gate lines 2211, a second gate line 2221 and a third gate line 2231 are respectively aggregated in the first gate bus 221, the second gate bus 222 and the third gate bus 223. In this solution, all source lines are aggregated into the source bus, and all gate lines are aggregated into the gate bus. Then, any sub-pixel 111 can be powered on for testing by energizing the corresponding gate bus and source bus, thereby simplifying the test circuit and the circuit arrangement of the test system 10, and being able to efficiently detect the display status of the pixel.
[0052] It should be noted that each pixel unit 110 may include sub-pixels 111 of three different colors, or each pixel unit 110 may include sub-pixels 111 of four different colors, or each pixel unit 110 may include sub-pixels 111 of more than four different colors. It should be noted that according to the number of sub-pixels 111 of different colors, a corresponding number of gate buses and source buses need to be set. For example, when each pixel unit 110 includes sub-pixels 111 of three different colors, three different gate buses and source buses need to be set, or when each pixel unit 110 includes sub-pixels 111 of four different colors, four different gate buses and source buses need to be set, or when each pixel unit 110 includes sub-pixels 111 of more than four different colors, more than four different gate buses and source buses need to be set.
[0053] It should be noted that during testing, at least one gate bus and source bus need to be powered on at the same time. If the display conditions of all sub-pixels 111 need to be tested, all gate bus and source bus need to be powered on at the same time.
[0054] It should be noted that the first direction may be an X-axis direction, and the second direction may be a Y-axis direction perpendicular to the X-axis direction.
[0055] According to one embodiment of the present invention, Figure 2 and Figure 4 As shown, the sub-pixel 111 includes a red sub-pixel 1111, a blue sub-pixel 1112 and a green sub-pixel 1113. At this time, each pixel unit 110 includes 3 red sub-pixels 1111, 3 blue sub-pixels 1112 and 3 green sub-pixels 1113, respectively, and the red sub-pixels 1111 of each row are located on different columns, the green sub-pixels 1113 of each row are located on different columns, and the blue sub-pixels 1112 of each row are located on different columns.
[0056] According to one embodiment of the present invention, Figure 3 As shown, the sub-pixel 111 includes a red sub-pixel 1111, a blue sub-pixel 1112, a green sub-pixel 1113 and a white sub-pixel 1114. At this time, each pixel unit 110 includes 3 red sub-pixels 1111, 3 blue sub-pixels 1112, 3 green sub-pixels 1113 and 3 white sub-pixels 1114, respectively, and the red sub-pixels 1111 of each row are located on different columns, the green sub-pixels 1113 of each row are located on different columns, the blue sub-pixels 1112 of each row are located on different columns, and the white sub-pixels 1114 of each row are located on different columns.
[0057] It should be noted that, in some other embodiments, each pixel unit 110 includes 3 red sub-pixels 1111, 3 blue sub-pixels 1112, 3 green sub-pixels 1113 and 7 white sub-pixels 1114. In this case, the white sub-pixel 1114 is arranged on the outside of the red sub-pixel 1111, the blue sub-pixel 1112 and the green sub-pixel 1113, and the white sub-pixel 1114 is located in the same row or the same column.
[0058] According to one embodiment of the present invention, Figure 3 As shown, the source line group 210 includes a fourth source bus (not shown in the figure) and multiple fourth source lines (not shown in the figure), the multiple fourth source lines are respectively connected to the sources of multiple white sub-pixels 1114, and the multiple first source lines 2111, the second source lines 2121, the third source lines 2131 and the fourth source lines are repeatedly arranged in sequence along the first direction. It can be understood that by setting multiple fourth source lines connected to the sub-pixels 111 and a fourth source bus that aggregates the multiple fourth source lines, the power-on test of the sub-pixels of the fourth color can be achieved.
[0059] It should be noted that multiple source bus lines and source lines can correspond to any one of the red sub-pixel 1111, the blue sub-pixel 1112, the green sub-pixel 1113 or the white sub-pixel 1114. For example, the first source line 2111 is connected to the red sub-pixel 1111, the first source line 2111 is connected to the blue sub-pixel 1112, the first source line 2111 is connected to the green sub-pixel 1113, and the first source line 2111 is connected to the white sub-pixel 1114. It can be understood that different source bus lines and source lines can also correspond to sub-pixels 111 of other colors, and no specific limitation is made here.
[0060] According to one embodiment of the present invention, the gate line group 220 includes a fourth gate bus (not shown in the figure) and multiple fourth gate lines (not shown in the figure), the multiple fourth gate lines are respectively connected to the gates of multiple white sub-pixels 1114, and the multiple first gate lines 2211, the second gate lines 2221, the third gate lines 2231 and the fourth gate lines are repeatedly arranged in sequence along the second direction. It can be understood that by setting multiple fourth gate lines connected to the sub-pixels 111 and a fourth gate bus that aggregates the multiple fourth gate lines, the power-on test of the sub-pixels of the fourth color can be achieved.
[0061] It should be noted that the gate bus and the multiple gate lines can correspond to any one of the red sub-pixel 1111, the blue sub-pixel 1112, the green sub-pixel 1113 or the white sub-pixel 1114. For example, the first gate line 2211 is connected to the red sub-pixel 1111, the first gate line 2211 is connected to the blue sub-pixel 1112, the first gate line 2211 is connected to the green sub-pixel 1113, and the first gate line 2211 is connected to the white sub-pixel 1114. It can be understood that different gate bus lines and multiple gate lines can also correspond to sub-pixels 111 of other colors, which is not specifically limited here.
[0062] According to one embodiment of the present invention, a test power supply (not shown in the figure) is also included, and the test power supply is electrically connected to the first gate bus 221, the second gate bus 222, the third gate bus 223, the first source bus 211, the second source bus 212 and the third source bus 213, and the test parameters provided by the test power supply are one or more of resistance value, current value or voltage value.
[0063] It should be noted that in some embodiments, more than three gate bus lines and source bus lines are included, for example, a fourth gate bus line and a fourth source bus line are included. In this case, the test power supply is electrically connected to the fourth gate bus line and the fourth source bus line.
[0064] Reference below Figure 5 and Figure 6 A method for detecting a color filter according to an embodiment of the second aspect of the present invention is described as follows: Figure 5 As shown, the color filter includes a pixel layer, and the pixel layer includes at least three sub-pixels arranged in a Mosaic manner. The detection method specifically includes the steps of:
[0065] Step S100: marking the gate line and source line of the sub-pixel at each position;
[0066] Specifically, the gate lines and source lines of sub-pixels of different colors are marked, so that the sub-pixels of different colors can be distinguished.
[0067] Step S200: Based on the mark, a gate line and a source line of at least one sub-pixel are subjected to a power-on test.
[0068] Specifically, by energizing the marked gate line and source line, the display status of at least one pixel can be detected.
[0069] It should be noted that the color filter includes a pixel layer. Specifically, the pixel layer may include at least three sub-pixels of different colors, for example, red sub-pixels, green sub-pixels, blue sub-pixels or white sub-pixels. At the same time, a gate bus can be set to aggregate all gate lines into the gate bus, and a source bus can be set to aggregate all source lines into the source bus. During detection, it is only necessary to energize the corresponding gate bus and source bus to achieve detection.
[0070] According to one embodiment of the present invention, Figure 6 As shown, the pixel layer includes three sub-pixels of different colors. Step S100: marking the gate line and source line of the sub-pixel at each position, specifically including the steps of:
[0071] Step S110: Divide the gate lines into three groups, marked as G1, G2 and G3 in sequence;
[0072] Specifically, the gate line of the first color is marked as G1, the gate line of the second color is marked as G2, and the gate line of the third color is marked as G3, and the three different gate lines are sequentially arranged along one direction.
[0073] Step S120: Divide the source lines into three groups, marked as S1, S2 and S3 respectively.
[0074] Specifically, the source line of the first color is marked as S1, the source line of the second color is marked as S2, and the source line of the third color is marked as S3, and the three different source lines are arranged in sequence along another direction.
[0075] It can be seen that by dividing and marking all the gate lines and source lines on the color filter, it is possible to detect sub-pixels of different colors by energizing the corresponding gate lines and source lines in combination.
[0076] Reference below Figure 7 and Figure 8 A method for detecting an array substrate according to an embodiment of the third aspect of the present invention is described. Figure 7 As shown, the array substrate includes a pixel layer constituting a color filter, and the pixel layer includes at least three sub-pixels arranged in a Mosaic manner. The detection method specifically includes the steps of:
[0077] Step S300: marking the gate line and source line of the sub-pixel at each position;
[0078] Specifically, the gate lines and source lines of sub-pixels of different colors are marked, so that the sub-pixels of different colors can be distinguished.
[0079] Step S400: Based on the mark, a power-on test is performed on a gate line and a source line of at least one sub-pixel.
[0080] Specifically, by energizing the marked gate line and source line, the display status of at least one pixel can be detected.
[0081] It should be noted that the array substrate includes a pixel layer. Specifically, the pixel layer can include at least three sub-pixels of different colors, for example, red sub-pixels, green sub-pixels, blue sub-pixels or white sub-pixels. At the same time, a gate bus can be set to aggregate all gate lines into the gate bus, and a source bus can be set to aggregate all source lines into the source bus. During detection, it is only necessary to energize the corresponding gate bus and source bus to achieve detection.
[0082] According to one embodiment of the present invention, Figure 8 As shown, the pixel layer includes three sub-pixels of different colors. Step S300: marking the gate line and source line of the sub-pixel at each position, specifically including the steps of:
[0083] Step S310: Divide the gate lines into three groups, marked as G1, G2 and G3 in sequence;
[0084] Specifically, the gate line of the first color is marked as G1, the gate line of the second color is marked as G2, and the gate line of the third color is marked as G3, and the three different gate lines are sequentially arranged along one direction.
[0085] Step S320: Divide the source lines into three groups, marked as S1, S2 and S3 respectively.
[0086] Specifically, the source line of the first color is marked as S1, the source line of the second color is marked as S2, and the source line of the third color is marked as S3, and the three different source lines are arranged in sequence along another direction.
[0087] It can be seen that by dividing and marking all the gate lines and source lines on the pixel layer of the array substrate, it is possible to detect sub-pixels of different colors by energizing the corresponding gate lines and source lines in combination.
[0088] The test system, color filter and array substrate test method provided above are preferred embodiments and should not be construed as limiting the scope of protection of the present application. Those skilled in the art should be aware that various improvements or substitutions may be made without departing from the concept of the present application, and all improvements or substitutions should be within the scope of protection of the present application, that is, the scope of protection of the present application should be based on the claims.
[0089] In the absence of conflict, the above embodiments and features in the embodiments may be combined with each other.
Claims
1. A testing system, characterized in that: Included are: A pixel layer, wherein the pixel layer includes a plurality of pixel units, each pixel unit includes at least three sub-pixels, wherein the sub-pixels are arranged in a Mosaic manner, and each sub-pixel is provided with a TFT switch, and the TFT switch includes a source electrode, a gate electrode, and a drain electrode; A test circuit, wherein the test circuit includes a source line group and a gate line group, the source line group includes a first source line, a second source line, and a third source line sequentially connected to the source of one of the sub-pixels, and the first source line, the second source line, and the third source line are sequentially arranged repeatedly along the first direction, and the gate line group includes a first gate line, a second gate line, and a third gate line sequentially connected to the gate of one of the sub-pixels, and the first gate line, the second gate line, and the third gate line are sequentially arranged repeatedly along the second direction; Among them, the source line group includes a first source bus, a second source bus and a third source bus, and multiple first source lines, the second source lines and the third source lines are respectively summarized in the first source bus, the second source bus and the third source bus, and at the same time, the gate line group includes a first gate bus, a second gate bus and a third gate bus, and multiple first gate lines, the second gate lines and the third gate lines are respectively summarized in the first gate bus, the second gate bus and the third gate bus.
2. The test system according to claim 1, characterized in that: The sub-pixels include a red sub-pixel, a blue sub-pixel and a green sub-pixel.
3. The test system according to claim 1, characterized in that: The sub-pixels include a red sub-pixel, a blue sub-pixel, a green sub-pixel and a white sub-pixel.
4. The test system according to claim 3, characterized in that: The source line group includes a fourth source bus and multiple fourth source lines, the multiple fourth source lines are respectively connected to the sources of multiple white sub-pixels, and the multiple first source lines, the second source lines, the third source lines and the fourth source lines are repeatedly arranged in sequence along the first direction.
5. The test system according to claim 4, characterized in that: The gate line group includes a fourth gate bus and a plurality of fourth gate lines, the plurality of fourth gate lines are respectively connected to the gates of a plurality of white sub-pixels, and the plurality of first gate lines, the second gate lines, the third gate lines and the fourth gate lines are repeatedly arranged in sequence along the second direction.
6. The test system according to claim 1, characterized in that: It also includes a test power supply, which is electrically connected to the first gate bus, the second gate bus, the third gate bus, the first source bus, the second source bus and the third source bus, and the test parameters provided by the test power supply are one or more of resistance value, current value or voltage value.
7. A method for detecting a color filter, wherein the color filter comprises a pixel layer, wherein the pixel layer comprises at least three sub-pixels arranged in a mosaic manner, wherein: The method comprises: Mark the gate line and source line of the sub-pixel at each position; Based on the flag, a gate line and a source line of at least one of the sub-pixels are powered on and tested.
8. The detection method according to claim 7, characterized in that The marking of the gate line and the source line of the sub-pixel at each position specifically includes: Divide the gate lines into three groups, labeled G1, G2, and G3; The source lines are divided into three groups, labeled S1, S2 and S3 respectively.
9. A method for detecting an array substrate, characterized in that: The array substrate includes a pixel layer, and the pixel layer includes at least three sub-pixels arranged in a mosaic manner. The method includes: Mark the gate line and source line of the sub-pixel at each position; Based on the flag, a gate line and a source line of at least one of the sub-pixels are powered on and tested.
10. The detection method according to claim 9, characterized in that: The marking of the gate line and the source line of the sub-pixel at each position specifically includes: Divide the gate lines into three groups, labeled G1, G2, and G3; The source lines are divided into three groups, labeled S1, S2 and S3 respectively.