Pixel circuit, display panel, and display device

Abstract

The present application relates to a pixel circuit, a display panel, and a display device. The pixel circuit includes a driving transistor, a first switching tube, a second switching tube, a third switching tube, a fourth switching tube, a first capacitor, a second capacitor, and a light-emitting element; the first switching tube is connected between a data line and the first end of the second capacitor; the first capacitor is connected between a first power supply and the first end of the second capacitor; the second end of the second capacitor is connected to the gate of the driving transistor; the first electrode of the driving transistor is connected to the first power supply; the second switching tube is connected between the second electrode of the driving transistor and the gate, the third switching tube is connected between the second electrode of the driving transistor and the first electrode of the light-emitting element, and the fourth switching tube is connected between an initialization signal source and the first electrode of the light-emitting element; wherein the first switching tube and the second switching tube are N-type transistors, and / or the fourth switching tube is a dual-gate transistor. The use of this pixel circuit can improve the screen flickering phenomenon of high PPI display screens.

Description

Technical Field

[0001] The present application relates to the field of display technology, and in particular to a pixel circuit, a display panel, and a display device. Background Art

[0002] As the PPI (pixels per inch) of display screens increases, the smaller the area of ​​a single sub-pixel, the fewer transistors it can accommodate. Therefore, on high-PPI displays, the number of transistors in the pixel circuit is typically smaller than that in current driver circuits. This reduction in the number of transistors in the pixel circuit can result in a loss of some functionality, leading to issues such as flicker. Therefore, there is an urgent need to address the problem of improving screen flicker in pixel circuits suitable for high-PPI displays. Summary of the Invention

[0003] Based on this, it is necessary to provide a pixel circuit, display panel and display device that can be applied to high PPI display screens to improve screen flickering in order to address the above technical problems.

[0004] In a first aspect, the present application provides a pixel circuit. The pixel circuit includes a driving transistor, a first switching tube, a second switching tube, a third switching tube, a fourth switching tube, a first capacitor, a second capacitor, and a light-emitting element; the first switching tube is connected between a data line and a first end of a second capacitor; the first capacitor is connected between a first power supply and a first end of the second capacitor; the second end of the second capacitor is connected to the gate of the driving transistor; the first electrode of the driving transistor is connected to the first power supply; the second switching tube is connected between the second electrode of the driving transistor and the gate; the third switching tube is connected between the second electrode of the driving transistor and the first electrode of the light-emitting element; and the fourth switching tube is connected between an initialization signal source and the first electrode of the light-emitting element; wherein the first switching tube and the second switching tube are N-type transistors, and / or the fourth switching tube is a dual-gate transistor.

[0005] In one embodiment, the gate of the first switching tube is connected to the second scanning signal, the first electrode of the first switching tube is connected to the data line, and the second electrode of the first switching tube is connected to the first end of the second capacitor; the first end of the first capacitor is connected to the first power supply, and the second end of the first capacitor is connected to the first end of the second capacitor; the gate of the second switching tube is connected to the first scanning signal, the first electrode of the second switching tube is connected to the gate of the driving transistor, and the second electrode of the second switching tube is connected to the second electrode of the driving transistor; the gate of the third switching tube is connected to the light-emitting signal, the first electrode of the third switching tube is connected to the second electrode of the driving transistor, and the second electrode of the third switching tube is connected to the first electrode of the light-emitting element; the gate of the fourth switching tube is connected to the third scanning signal, the first electrode of the fourth switching tube is connected to the initialization signal source, and the second electrode of the fourth switching tube is connected to the first electrode of the light-emitting element; the second electrode of the light-emitting element is connected to the second power supply.

[0006] In one embodiment,

[0007] The pixel circuit further includes a third capacitor;

[0008] A first end of the third capacitor is connected to the gate of the driving transistor, and a second end of the third capacitor is connected to a variable voltage;

[0009] Optionally, in the bias phase, the second end of the third capacitor is connected to a bias voltage; in the data voltage writing phase, the second end of the third capacitor is connected to a preset voltage, and the preset voltage is different from the bias voltage;

[0010] Optionally, the preset voltage is higher than the bias voltage;

[0011] Optionally, in the bias phase, the first switch tube, the second switch tube, and the third switch tube are turned off, and the fourth switch tube is turned on;

[0012] Optionally, in the data voltage writing phase, the first switch tube is turned on, and the data line transmits the data voltage;

[0013] Optionally, in the first initialization stage, the first switch tube is turned on, and the data line transmits the second initialization voltage;

[0014] Optionally, in the first initialization stage, the second switch tube, the third switch tube and the fourth switch tube are turned on;

[0015] Optionally, in the threshold compensation stage, the first switch tube is turned on, and the data line transmits the second initialization voltage; the second switch tube is turned on, and the third switch tube is turned off;

[0016] Optionally, in the threshold compensation stage, the fourth switch tube is turned off;

[0017] Optionally, in the first initialization stage, the threshold compensation stage, and the light-emitting stage, the second end of the third capacitor is connected to a preset voltage;

[0018] Optionally, the write frame of the pixel circuit includes one or more bias phases;

[0019] Optionally, the biasing stage is in a non-light emitting stage of the pixel circuit;

[0020] Optionally, the writing frame of the pixel circuit includes one or more light emitting phases;

[0021] Optionally, in the same writing frame, the bias phase and the light emitting phase are alternately arranged;

[0022] Optionally, in the same writing frame, the data voltage writing phase precedes the biasing phase;

[0023] Optionally, in the same writing frame, the first initialization phase, the threshold compensation phase, the data voltage writing phase, and the bias phase are arranged in sequence.

[0024] In one embodiment, in the same write frame, the number of pulses corresponding to the bias voltage connected to the second end of the third capacitor is equal to the number of off-pulses of the light-emitting signal connected to the gate of the third switching tube divided by N, and / or the number of on-pulses of the third scanning signal connected to the gate of the fourth switching tube minus 1 is equal to the number of off-pulses of the light-emitting signal connected to the gate of the third switching tube divided by N, where N is an integer greater than or equal to 1;

[0025] Optionally, N is 1, 2 or 3;

[0026] Optionally, the hold frame of the pixel circuit includes one or more bias phases;

[0027] Optionally, the holding frame of the pixel circuit includes one or more light emitting phases;

[0028] Optionally, in the same holding frame, the bias phase and the light emitting phase are alternately arranged;

[0029] Optionally, in the same holding frame, the number of pulses corresponding to the bias voltage connected to the second end of the third capacitor is equal to the number of off-pulses of the light-emitting signal connected to the gate of the third switching tube divided by M, and / or the number of on-pulses of the third scanning signal connected to the gate of the fourth switching tube is equal to the number of off-pulses of the light-emitting signal connected to the gate of the third switching tube divided by M, where M is an integer greater than or equal to 1;

[0030] Optionally, M is 1, 2 or 3;

[0031] Optionally, in the light-emitting stage, the third switch tube is turned on, and the first switch tube, the second switch tube and the fourth switch tube are turned off.

[0032] Optionally, the start time of the transition edge of the second scanning signal connected to the gate of the first switching tube from the on-level to the off-level is after the end time of the transition edge of the voltage on the data line from the second initialization voltage to the data voltage; or the start time of the transition edge of the second scanning signal connected to the gate of the first switching tube from the on-level to the off-level is the end time of the transition edge of the voltage on the data line from the second initialization voltage to the data voltage;

[0033] Optionally, the end time of the transition edge of the second scanning signal connected to the gate of the first switching tube from the on-level to the off-level is before the start time of the transition edge of the voltage on the data line from the data voltage to the second initialization voltage; or the end time of the transition edge of the second scanning signal connected to the gate of the first switching tube from the on-level to the off-level is the start time of the transition edge of the voltage on the data line from the data voltage to the second initialization voltage;

[0034] Optionally, in the bias phase, the start time of the on-level of the third scanning signal connected to the gate of the fourth switching tube is after the second scanning signal connected to the gate of the first switching tube jumps from the on-level to the off-level, and before the light-emitting signal connected to the gate of the third switching tube jumps from the off-level to the on-level;

[0035] Optionally, the dual-gate transistor includes at least two transistors connected in series.

[0036] In the second aspect, the present application also provides a pixel circuit, which includes a driving transistor, a first switching tube, a second switching tube, a second capacitor and a third capacitor; the first switching tube is connected between the data line and the first end of the second capacitor; the second end of the second capacitor is connected to the gate of the driving transistor; the first electrode of the driving transistor is connected to the first power supply; the second switching tube is connected between the second electrode and the gate of the driving transistor; the first end of the third capacitor is connected to the gate of the driving transistor, and the second end of the third capacitor is connected to a variable voltage.

[0037] In one embodiment, during the bias phase, the second end of the third capacitor is connected to a bias voltage; during the data voltage writing phase, the second end of the third capacitor is connected to a preset voltage, which is different from the bias voltage.

[0038] Optionally, the preset voltage is higher than the bias voltage;

[0039] Optionally, in the data voltage writing phase, the first switch tube is turned on, and the data line transmits the data voltage;

[0040] Optionally, in the first initialization stage, the first switch tube is turned on, and the data line transmits the second initialization voltage;

[0041] Optionally, the pixel circuit further includes a light-emitting element, and a third switching tube and / or a fourth switching tube;

[0042] The third switch tube is connected between the second electrode of the driving transistor and the first electrode of the light emitting element, and the fourth switch tube is connected between the initialization signal source and the first electrode of the light emitting element;

[0043] Optionally, in the bias phase, the first switch tube, the second switch tube, and the third switch tube are turned off, and the fourth switch tube is turned on;

[0044] Optionally, in the first initialization stage, the second switch tube, the third switch tube and the fourth switch tube are turned on;

[0045] Optionally, in the threshold compensation stage, the first switch tube is turned on, and the data line transmits the second initialization voltage; the second switch tube is turned on, and the third switch tube is turned off;

[0046] Optionally, in the threshold compensation stage, the fourth switch tube is turned off;

[0047] Optionally, in the first initialization stage, the threshold compensation stage, and the light-emitting stage, the second end of the third capacitor is connected to a preset voltage;

[0048] Optionally, in the light-emitting stage, the third switch tube is turned on, and the first switch tube, the second switch tube and the fourth switch tube are turned off;

[0049] Optionally, the write frame of the pixel circuit includes one or more bias phases;

[0050] Optionally, the biasing stage is in a non-light emitting stage of the pixel circuit;

[0051] Optionally, the writing frame of the pixel circuit includes one or more light emitting phases;

[0052] Optionally, in the same writing frame, the bias phase and the light emitting phase are alternately arranged;

[0053] Optionally, in the same writing frame, the data voltage writing phase precedes the biasing phase;

[0054] Optionally, in the same writing frame, the first initialization phase, the threshold compensation phase, the data voltage writing phase, and the bias phase are arranged in sequence;

[0055] Optionally, the pixel circuit further includes a first capacitor connected between the first power supply and a first end of the second capacitor.

[0056] In a third aspect, the present application further provides a method for driving a pixel circuit, the pixel circuit comprising a driving transistor, a first switching transistor, a second switching transistor, a second capacitor, and a third capacitor; the first switching transistor is connected between a data line and a first end of the second capacitor; the second end of the second capacitor is connected to a gate of the driving transistor; the first electrode of the driving transistor is connected to a first power supply; the second switching transistor is connected between the second electrode and the gate of the driving transistor; the first end of the third capacitor is connected to the gate of the driving transistor, and the second end of the third capacitor is connected to a variable voltage;

[0057] The driving method includes:

[0058] In the bias phase, the second end of the third capacitor is connected to the bias voltage;

[0059] During the data voltage writing phase, the second end of the third capacitor is connected to a preset voltage, which is different from the bias voltage.

[0060] In one embodiment, during the data voltage writing phase, the second scanning signal connected to the gate of the first switch is at an on-level, and the data line transmits the data voltage;

[0061] Optionally, in the first initialization stage, the second scanning signal connected to the gate of the first switch tube is at a conduction level, and the data line transmits a second initialization voltage;

[0062] Optionally, the pixel circuit further includes a third switch tube, a fourth switch tube and a light-emitting element, the third switch tube is connected between the second electrode of the driving transistor and the first electrode of the light-emitting element, and the fourth switch tube is connected between the initialization signal source and the first electrode of the light-emitting element;

[0063] In the first initialization stage, the first scanning signal connected to the gate of the second switch tube is at the on-level, the light emitting signal connected to the gate of the third switch tube is at the on-level, and the third scanning signal connected to the gate of the fourth switch tube is at the on-level;

[0064] Optionally, in the threshold compensation stage, the second scanning signal connected to the gate of the first switch tube is at an on-level, and the data line transmits a second initialization voltage; the first scanning signal connected to the gate of the second switch tube is at an on-level, and the light-emitting signal connected to the gate of the third switch tube is at an off-level;

[0065] Optionally, in the threshold compensation stage, the third scanning signal connected to the gate of the fourth switch tube is at an off level;

[0066] Optionally, in the first initialization stage, the threshold compensation stage, and the light-emitting stage, the second end of the third capacitor is connected to a preset voltage;

[0067] Optionally, the write frame of the pixel circuit includes one or more bias phases;

[0068] Optionally, the biasing stage is in a non-light emitting stage of the pixel circuit;

[0069] Optionally, the writing frame of the pixel circuit includes one or more light emitting phases;

[0070] Optionally, in the same writing frame, the bias phase and the light emitting phase are alternately arranged;

[0071] Optionally, in the same writing frame, the data voltage writing phase precedes the biasing phase;

[0072] Optionally, in the same writing frame, the first initialization phase, the threshold compensation phase, the data voltage writing phase, and the bias phase are arranged in sequence;

[0073] Optionally, in the same write frame, the number of pulses corresponding to the bias voltage connected to the second end of the third capacitor is equal to the number of off-pulses of the light-emitting signal connected to the gate of the third switching tube divided by N, and / or the number of on-pulses of the third scanning signal connected to the gate of the fourth switching tube minus 1 is equal to the number of off-pulses of the light-emitting signal connected to the gate of the third switching tube divided by N, where N is an integer greater than or equal to 1;

[0074] Optionally, N is 1, 2 or 3;

[0075] Optionally, the hold frame of the pixel circuit includes one or more bias phases;

[0076] Optionally, the holding frame of the pixel circuit includes one or more light emitting phases;

[0077] Optionally, in the same holding frame, the bias phase and the light emitting phase are alternately arranged;

[0078] Optionally, in the same holding frame, the number of pulses corresponding to the bias voltage connected to the second end of the third capacitor is equal to the number of off-pulses of the light-emitting signal connected to the gate of the third switching tube divided by M, and / or the number of on-pulses of the third scanning signal connected to the gate of the fourth switching tube is equal to the number of off-pulses of the light-emitting signal connected to the gate of the third switching tube divided by M, where M is an integer greater than or equal to 1;

[0079] Optionally, M is 1, 2 or 3;

[0080] Optionally, in the light-emitting stage, the light-emitting signal connected to the gate of the third switch tube is at a conduction level;

[0081] Optionally, in the light-emitting stage, the second scanning signal connected to the gate of the first switching tube is at an off-level, the first scanning signal connected to the gate of the second switching tube is at an off-level, and the third scanning signal connected to the gate of the fourth switching tube is at an off-level;

[0082] Optionally, the start time of the transition edge of the second scanning signal connected to the gate of the first switching tube from the on-level to the off-level is after the end time of the transition edge of the voltage on the data line from the second initialization voltage to the data voltage; or the start time of the transition edge of the second scanning signal connected to the gate of the first switching tube from the on-level to the off-level is the end time of the transition edge of the voltage on the data line from the second initialization voltage to the data voltage;

[0083] Optionally, the end time of the transition edge of the second scanning signal connected to the gate of the first switching tube, which jumps from the on-level to the off-level, is before the start time of the transition edge of the voltage on the data line, which jumps from the data voltage to the second initialization voltage; or the end time of the transition edge of the second scanning signal connected to the gate of the first switching tube, which jumps from the on-level to the off-level, is the start time of the transition edge of the voltage on the data line, which jumps from the data voltage to the second initialization voltage;

[0084] Optionally, in the bias phase, the start time of the on-level of the third scanning signal connected to the gate of the fourth switching tube is after the second scanning signal connected to the gate of the first switching tube jumps from the on-level to the off-level, and before the light-emitting signal connected to the gate of the third switching tube jumps from the off-level to the on-level;

[0085] Optionally, the pixel circuit further includes a first capacitor connected between the first power supply and a first end of the second capacitor.

[0086] In a fourth aspect, the present application further provides a display panel, which includes the pixel circuit as described in any one of the first and second aspects above.

[0087] In a fifth aspect, the present application further provides a display device, which includes the display panel as described in the fourth aspect above.

[0088] In the above-mentioned pixel circuit, display panel, and display device, the pixel circuit includes a driving transistor, a first switching transistor, a second switching transistor, a third switching transistor, a fourth switching transistor, a first capacitor, a second capacitor, and a light-emitting element; the first switching transistor is connected between a data line and the first end of the second capacitor; the first capacitor is connected between a first power supply and the first end of the second capacitor; the second end of the second capacitor is connected to the gate of the driving transistor; the first electrode of the driving transistor is connected to the first power supply; the second switching transistor is connected between the second electrode of the driving transistor and the gate; the third switching transistor is connected between the second electrode of the driving transistor and the first electrode of the light-emitting element; and the fourth switching transistor is connected between an initialization signal source and the first electrode of the light-emitting element; wherein the first switching transistor and the second switching transistor are N-type transistors, and / or the fourth switching transistor is a dual-gate transistor. That is, the first switching transistor, the second switching transistor, and the fourth switching transistor are low-leakage current transistors. Thus, during the light-emitting phase, the first switching transistor, the second switching transistor, and the fourth switching transistor are off as switches. Since they are all low-leakage current transistors, their leakage current has little effect on the driving current driving the light-emitting element, thereby avoiding flickering during screen light-emitting. BRIEF DESCRIPTION OF THE DRAWINGS

[0089] In order to more clearly illustrate the embodiments of the present application or the technical solutions in the prior art, the following briefly introduces the drawings required for use in the embodiments or the description of the prior art. Obviously, the drawings described below are only some embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without any creative work.

[0090] Figure 1 is a schematic structural diagram of a pixel circuit in one embodiment;

[0091] Figure 2is a connection diagram of a pixel circuit in one embodiment;

[0092] Figure 3 A schematic diagram of a signal timing sequence in one embodiment;

[0093] Figure 4 is a schematic structural diagram of another pixel circuit in one embodiment;

[0094] Figure 5 is a connection diagram of another pixel circuit in one embodiment;

[0095] Figure 6 A schematic diagram of a signal timing sequence in one embodiment;

[0096] Figure 7 A schematic diagram of switching time points in one embodiment;

[0097] Figure 8 A schematic diagram of another switching time point in one embodiment;

[0098] Figure 9 A schematic diagram of another switching time point in one embodiment;

[0099] Figure 10 A schematic diagram of another switching time point in one embodiment;

[0100] Figure 11 A pulse comparison diagram in one embodiment;

[0101] Figure 12 A schematic diagram of a timing simulation of signals in one embodiment;

[0102] Figure 13 Schematic diagram of data voltage comparison in one embodiment;

[0103] Figure 14 Schematic diagram of the effect of threshold voltage fluctuation on brightness change in one embodiment;

[0104] Figure 15 FIG. 1 is a schematic diagram illustrating the effect of power supply voltage fluctuation on brightness change in one embodiment. DETAILED DESCRIPTION

[0105] In order to make the above-mentioned purposes, features and advantages of the present application more clearly understood, the specific embodiments of the present application are described in detail below with reference to the accompanying drawings. It should be understood that many specific details are set forth in the following description to facilitate a full understanding of the present application, but the present application can be implemented in many other ways than those described herein, and those skilled in the art can make similar improvements without violating the connotation of the present application. Therefore, the present application is not limited to the specific embodiments disclosed below.

[0106] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as those commonly understood by those skilled in the art to which this application pertains. The terms used herein in the specification of this application are for the purpose of describing specific embodiments only and are not intended to limit this application.

[0107] It will be understood that the terms "first," "second," "third," "fourth," "fifth," etc., used herein may be used to describe various elements, but these elements are not limited by these terms. These terms are only used to distinguish a first element from another element. For example, a first resistor may be referred to as a second resistor, and similarly, a second resistor may be referred to as a first resistor without departing from the scope of this application. The first resistor and the second resistor are both resistors, but they are not the same resistor.

[0108] It can be understood that the “connection” in the following embodiments should be understood as “electrical connection”, “communication connection”, etc. if there is transmission of electrical signals or data between the connected circuits, modules, units, etc.

[0109] It is understood that “at least one” refers to one or more, “a plurality” refers to two or more, and “at least a portion of an element” refers to a portion or all of an element.

[0110] As used herein, the singular forms "a," "an," and "the" may also include the plural forms, unless the context clearly indicates otherwise. It should also be understood that the terms "include," "comprising," "having," and the like specify the presence of stated features, integers, steps, operations, components, parts, or combinations thereof, but do not preclude the presence or addition of one or more other features, integers, steps, operations, components, parts, or combinations thereof. Furthermore, the term "and / or" as used in this specification includes any and all combinations of the relevant listed items.

[0111] As the PPI (Pixels Per Inch) of display screens gradually increases, the area reserved for individual pixel circuits becomes smaller and smaller, and the number of transistors that can be accommodated in a single pixel circuit also decreases. Therefore, on high-PPI displays, the number of transistors in the pixel circuit is usually less than that of common pixel circuits today. Common pixel circuits are 7T1C or 8T1C, while pixel circuits of high-PPI displays are 2T1C, 3T1C, or 4T2C. Among them, 7T means that the pixel circuit has 7 transistors, and 1C means that the pixel circuit has 1 capacitor.

[0112] Reducing the number of transistors in a pixel circuit can result in the loss of some pixel circuit functions, such as row-by-row lighting, PWM dimming, and anode initialization. The pixel circuits in many high-PPI screens cannot operate in a row-by-row manner, requiring all pixels to light up and turn off simultaneously. This results in prolonged periods of screen blackout, resulting in noticeable flicker. Furthermore, the reduced number of transistors makes it difficult for high-PPI screens to achieve low-frequency operation. This is primarily because, to mitigate low-frequency flicker and frequency-cutting flicker, dynamic refresh rate drivers require resetting the driver transistors (DTFTs) in the pixel circuit, which increases the number of TFTs. Furthermore, the current demand for higher brightness leads to greater current demands, which in turn exacerbates ELVDDIR Drop (the voltage drop in the display's positive supply voltage wiring caused by resistance and current). Existing conventional pixel circuits are very sensitive to ELVDDIR Drop, resulting in severe brightness unevenness, which is more pronounced at higher brightness levels.

[0113] In view of this, the embodiments of the present application propose a pixel circuit that, compared to conventional pixel circuits, has fewer transistors and a smaller layout space. This makes it more suitable for high-PPI screens than conventional pixel circuits. By reducing leakage paths, it is more suitable for screens with dynamic refresh rates, improving the flicker problem caused by the ELVDDIR Drop phenomenon. Furthermore, the pixel circuit adds a bias adjustment function for the drive transistor to improve the low-frequency and frequency-cutting flicker problems of the screen.

[0114] In one embodiment, Figure 1 and Figure 2 As shown, a pixel circuit is provided, which includes a driving transistor T1, a first switching transistor T2, a second switching transistor T3, a third switching transistor T5, a fourth switching transistor T4, a first capacitor C2, a second capacitor C1, and part or all of a light-emitting element. The first switching transistor T2 is connected between a data line and the first end of the second capacitor C1; the first capacitor C2 is connected between a first power source and the first end of the second capacitor C1; the second end of the second capacitor C1 is connected to the gate of the driving transistor T1; the first electrode of the driving transistor T1 is connected to the first power source; the second switching transistor T3 is connected between the second electrode and the gate of the driving transistor T1; the third switching transistor T5 is connected between the second electrode of the driving transistor T1 and the first electrode of the light-emitting element; and the fourth switching transistor T4 is connected between an initialization signal source and the first electrode of the light-emitting element.

[0115] The first switch transistor T2 is an N-type transistor, and / or the second switch transistor T3 is an N-type transistor, and / or the fourth switch transistor T4 is a dual-gate transistor. For example, the first switch transistor T2 is a metal oxide transistor. The second switch transistor T3 is a metal oxide transistor. For example, the fourth switch transistor T4 is a P-type transistor.

[0116] In an optional embodiment of the present application, Figure 1 As shown in the example, the second electrode of the light-emitting element can be connected to a second power source. For example, one of the first and second electrodes of the light-emitting element can be an anode, and the other can be a cathode. For example, one of the first and second power sources can be a high voltage, and the other can be a low voltage. For example, the first electrode of the light-emitting element can be an anode. For example, the first power source ELVDD is a positive power source that provides a constant positive power supply voltage, and the second power source ELVSS is a negative power source that provides a constant negative power supply voltage.

[0117] Combine Figures 1 to 3 As shown, the working phase of the pixel circuit may include part or all of a first initialization phase P1, a threshold compensation phase P2, a data voltage writing phase P3, a second initialization phase P4 and a light emitting phase P5.

[0118] Illustratively, in the first initialization stage P1, T2, T3, T5 and T4 are turned on, and the first pole (e.g., anode) voltage of the light-emitting element and the gate voltage of the driving transistor T1 are initialized to the first initialization voltage Vref1 using the first initialization voltage Vref1 output by the initialization signal source; and the voltage of the node n5 connected to the second pole of T2 is initialized using the second initialization voltage Vini output by the data line.

[0119] During threshold compensation phase P2, T2 and T3 are turned on, T5 and T4 are turned off, and the gate-source voltage Vgs of driving transistor T1 equals Vref1 - VDD. Since T2 shorts the gate and drain of T1, the voltage VDD of the first power supply continuously raises nodes n1 and n3 until the gate-source voltage Vgs of driving transistor T1 equals Vth_T1. At this point, the voltage Vn1 of node n1 equals VDD + Vth_T1, and the voltage Vn5 of node n5 equals Vini. Under the control of the first power supply, the gate-source voltage of driving transistor T1 equals the threshold voltage Vth_T1 of driving transistor T1.

[0120] In the data voltage writing phase P3, T2 is turned on, and T3, T5, and T4 are turned off. The data voltage (e.g., data voltage) output by the data line acts on the gate of the driving transistor T1 through T2 and C1 to change the gate voltage of the driving transistor T1 to the target driving voltage. In this way, the driving transistor T1 can generate a target driving current when the gate voltage is the target driving voltage, so that the target driving current passes through the third switching tube T5 when the third switching tube is turned on to drive the light-emitting element to emit light.

[0121] In the second initialization phase P4, T4 is turned on to control the first electrode voltage of the light emitting element to be the first initialization voltage. T3, T5 and T2 are turned off.

[0122] In the light emitting stage P5, T5 is turned on, T2, T3 and T4 are in the off state, the driving transistor T1 generates a driving current, and the driving current is transmitted to the light emitting element through T5 to drive the light emitting element to emit light.

[0123] Among them, in the light-emitting stage, if the leakage current of other turned-off switching tubes is large, the voltage of the circuit node n5 where the second pole of T2 is located and the circuit node n1 where the gate of T1 is located cannot be maintained, thereby affecting the size of the driving current output by the driving transistor T1, thereby affecting the change in the luminous brightness of the light-emitting element and causing flicker.

[0124] In the embodiment of the present application, since the first switch tube T2 and the second switch tube T3 are N-type transistors with low leakage current, and the fourth switch tube T4 is a dual-gate transistor with low leakage current, the voltages at the circuit node n5 where the second electrode of T2 is located and the circuit node n1 where the gate of T1 is located can maintain target values, thereby ensuring that the driving current does not fluctuate, and further ensuring that the light-emitting element emits light normally without flickering problems.

[0125] In the related art, the first switch tube T2 and the second switch tube T3 are P-type TFTs (for example, low-temperature polycrystalline silicon P-type thin-film transistors). The control end of the driving transistor T1 is easily affected by the leakage current of this type of transistor TFT and cannot maintain the target voltage, causing flickering; and the third switch tube T5 is a single-gate LTPS (low-temperature polycrystalline silicon) TFT. The pixel circuit design used in conventional high-PPI screens mostly uses short-channel TFT devices to reduce the layout space required for the pixel circuit. However, single-gate short-channel TFT devices often have the problem of excessively large off-state current, causing the initialization voltage Vref of the initialization signal source to lower the potential of the first electrode of the light-emitting element, resulting in dark spots.

[0126] In the above-mentioned 5T2C pixel circuit provided in an embodiment of the present application, the first switch tube T2 is connected between the data line and the first end of the second capacitor C1; the first capacitor C2 is connected between the first power supply and the first end of the second capacitor C1; the second end of the second capacitor C1 is connected to the gate of the driving transistor T1; the first electrode of the driving transistor T1 is connected to the first power supply; the second switch tube T3 is connected between the second electrode and the gate of the driving transistor T1, the third switch tube T5 is connected between the second electrode of the driving transistor T1 and the first electrode of the light-emitting element, and the fourth switch tube T4 is connected between the initialization signal source and the first electrode of the light-emitting element; wherein the first switch tube T2 and the second switch tube T3 are N-type transistors, and / or the fourth switch tube T4 is a dual-gate transistor, that is, the first switch tube T2, the second switch tube T3 and the fourth switch tube T4 are low-leakage current transistors. In this way, in the light-emitting stage, the first switch tube T2, the second switch tube T3 and the fourth switch tube T4 are turned off. Since they are all transistors with low leakage current, their leakage current has little effect on the driving current that drives the light-emitting element to emit light, thereby avoiding the flicker problem during the screen lighting process and will not affect the potential of the first electrode of the light-emitting element. It is suitable for high PPI screens.

[0127] In one embodiment, the gate of the first switch transistor T2 is connected to the second scan signal Scan2, the first electrode of the first switch transistor T2 is connected to the data line SRC, and the second electrode of the first switch transistor T2 is connected to the first end of the second capacitor; the first end of the first capacitor C2 is connected to the first power supply ELVDD, and the second end of the first capacitor is connected to the first end of the second capacitor C1; the gate of the second switch transistor is connected to the first scan signal Scan1, the first electrode of the second switch transistor T3 is connected to the gate of the driving transistor, and the second electrode of the second switch transistor T3 is connected to the second electrode of the driving transistor T1; the gate of the third switch transistor T5 is connected to the emission signal EM, the first electrode of the third switch transistor T5 is connected to the second electrode of the driving transistor T1, and the second electrode of the third switch transistor T5 is connected to the first electrode of the light-emitting element; the gate of the fourth switch transistor T4 is connected to the third scan signal Scan3, the first electrode of the fourth switch transistor T4 is connected to the initialization signal source Vref, and the second electrode of the fourth switch transistor T4 is connected to the first electrode of the light-emitting element; the second electrode of the light-emitting element is connected to the second power supply ELVSS.

[0128] In a possible implementation, the driving transistor T1 is a P-type transistor, the fourth switch transistor T4 is a P-type dual-gate transistor, the third switch transistor T5 is a P-type transistor, and the first switch transistor T2 and the second switch transistor T3 are N-type transistors.

[0129] In one possible implementation, the dual-gate transistor includes at least two transistors connected in series.

[0130] Take this as an example, Figure 2The figure shows a connection diagram of a pixel circuit, where OLED represents a light-emitting element.

[0131] Among them, the gate of the first switch tube T2 is controlled by the second scan signal Scan2, the drain of the first switch tube T2 is connected to the data line SRC, the source of the first switch tube T2 is connected to the first end of the second capacitor C1, and the connection point between the two is the n5 node in the circuit; the first end of the first capacitor C2 is connected to the first power supply, and the second end of the first capacitor C2 is connected to the first end of the second capacitor C1; the second end of the second capacitor C1 is connected to the gate of the driving transistor T1, and the connection point between the two is the n1 node in the circuit; the source of the driving transistor T1 is connected to the first power supply, and the drain of the driving transistor T1 is connected to the source of T3; the second The gate of the switch tube T3 is controlled by the first scan signal Scan1, and the drain of the second switch tube T3 is connected to the gate of T1; the gate of the third switch tube T5 is controlled by the light-emitting signal EM, the drain of the third switch tube T5 is connected to the drain of T1, and the source of the third switch tube T5 is connected to the anode of the light-emitting element, and the connection point between the two is the n4 node in the circuit; the gate of the fourth switch tube T4 is controlled by the third scan signal Scan3, the drain of the fourth switch tube T4 is connected to the initialization signal source Vref, and the source of the fourth switch tube T4 is connected to the anode of the light-emitting element; the cathode of the light-emitting element is connected to the second power supply ELVSS.

[0132] Please refer to Figure 3 The timing diagram of each signal in each stage of the pixel circuit is shown. Figure 2 The operation of the pixel circuit shown in FIG. The initialization signal source Vref can output a constant first initialization voltage Vref1. The data line SRC can transmit the second initialization voltage Vini and the data voltage (i.e., the data voltage) in a time-sharing manner, outputting either Vini or the data voltage at different stages. Scan1, Scan2, Scan3, and EM are all alternating signals. Furthermore, P1 represents the first initialization stage (reset), P2 represents the threshold compensation stage (Vth compensation), P3 represents the data voltage writing stage (datawriting), P4 represents the second initialization stage, and P5 represents the emission stage (emission).

[0133] First initialization stage P1: EM is set low, that is, EM is at the on-level, and transistor T5 is turned on; Scan1 and Scan2 are set high, that is, Scan1 and Scan2 are at the on-level, and transistors T2 and transistor T3 are turned on; the second initialization voltage Vini transmitted by the data line SRC initializes the node n5; Scan3 is set low, transistor T4 is turned on, and the initialization signal source Vref→node n4→node n3→node n1 forms a path, and Vref initializes the first electrode of the light-emitting element and the gate of the driving transistor T1. At this time, Vn5=Vini, Vn1=Vref.

[0134] Threshold Compensation Phase P2: EM is set high, meaning it is at the off-level, and transistor T5 is off. Scan3 is set high, meaning it is at the off-level, and transistor T4 is off. Scan1 and Scan2 remain high, meaning they are at the on-level, and transistors T2 and T3 remain on. At the beginning of P2, the gate-source voltage Vgs of transistor T1 is equal to Vref1 - VDD. At this point, because transistor T3 shorts the gate and drain of transistor T1, the positive voltage VDD output by ELVDD continuously raises the node voltages at nodes n1 and n3 until the gate-source voltage Vgs of transistor T1 equals the threshold voltage Vth_T1 of transistor T1. At this point, the voltage at node n1, Vn1, equals VDD + Vth_T1, and the voltage at node n5, Vn5, equals Vini.

[0135] Data voltage writing phase P3: Scan1 is set low, that is, Scan1 is at the off-level, and transistor T3 is turned off; Scan2 remains high, that is, Scan2 is at the on-level, and transistor T2 continues to be on; the data line SRC switches from outputting Vini to outputting the data voltage, and the data voltage is written to the n5 node. Due to capacitive coupling, the voltage Vn1_p3 of the n1 node connected to the gate of transistor T1 will synchronously change to: Vn1_p3 = (data-Vini)*(C1 / (C1+Cgs_t1))+VDD+Vth_T1.

[0136] Second initialization stage P4: Scan3 is set low, that is, Scan3 is at the on-level, and T4 is turned on; the voltage Vref1 is written into the first electrode of the light-emitting element to initialize the first electrode.

[0137] Light-emitting stage P5: Scan2 is set low, that is, Scan2 is at the off level, T2 is turned off; C2 maintains the potential of node n5; EM is set low, that is, EM is at the on level, T5 is turned on; T5 is a P-type TFT, according to the saturation region current formula of P-type TFT: It can be learned that:

[0138]

[0139] Among them, I OLED is the luminous current of the light-emitting element, Cox is the dielectric constant of the oxide layer of the driving transistor T1; μ is the effective mobility of the driving transistor T1; is the width-to-length ratio of the channel of the driving transistor T1; C1 is the capacitance value of the capacitor C1, C2 is the capacitance value of the capacitor C2, and Cgs_t1 is the capacitance value of the gate-source parasitic capacitance of T1.

[0140] From this we can see that I OLED It has nothing to do with the voltage VDD of the first power supply and the threshold voltage Vth_T1 of T1. The fluctuation of the voltage VDD of the first power supply will not affect the light-emitting current, and the fluctuation of the threshold voltage of the driving transistor T1 will not affect the light-emitting current, that is, the compensation for ELVDDIR Drop and the compensation for the threshold voltage fluctuation of T1 are achieved, that is, the ELVDDIR Drop phenomenon and the impact of the threshold voltage fluctuation of T1 on I OLED The effect of this is reduced, thus ensuring that flickering is avoided during the lighting phase.

[0141] As mentioned above, the embodiment of the present application further provides a 5T3C pixel circuit, which adds an OBS (On-bias) function to the driving transistor T1 to improve the low-frequency and frequency-cutting flicker problems of the screen. The 5T3C pixel circuit is described below.

[0142] Here, in the second initialization phase P4 of the pixel circuit, an OBS function is added.

[0143] In one embodiment, Figure 1 Based on this, we provide Figure 4 Another pixel circuit shown in FIG. 1 further includes a third capacitor C3 , wherein a first terminal of the third capacitor C3 is connected to the gate of the driving transistor T1 , and a second terminal of the third capacitor C3 is connected to a variable voltage.

[0144] By connecting a variable voltage, the third capacitor C3 controls the voltage of the gate of the driving transistor T1 to change under the action of the variable voltage, thereby resetting the driving transistor T1 from a negative bias state to an original state, thereby avoiding problems such as screen flickering caused by the bias of the driving transistor T1.

[0145] Based on this, in the embodiment of the present application, in addition to the above-mentioned stages, a bias stage is added to the working stage of the pixel circuit, in which a variable voltage is controlled to be connected.

[0146] Optionally, the bias phase P4 precedes the light-emitting phase P5. That is, the drive transistor T1 is reset to its original state based on the variable voltage before the pixel circuit enters the light-emitting phase P5. Optionally, the bias phase P4 follows the data voltage writing phase P3. Exemplarily, the OBS function can be implemented using the third capacitor C3 during the second initialization phase of the pixel circuit, while initializing the first electrode of the light-emitting element, before the pixel circuit enters the light-emitting phase P5.

[0147] In an optional embodiment, during the bias phase P4, the second end of the third capacitor C3 is connected to the bias voltage OBS; during the data voltage writing phase P3, the second end of the third capacitor C3 is connected to the preset voltage VGH. The preset voltage VGH is different from the bias voltage OBS.

[0148] That is, the variable voltage can be divided into the bias voltage OBS and the preset voltage VGH in a time-division manner, wherein in the bias phase P4 , the variable voltage is the bias voltage OBS.

[0149] In an optional embodiment of the present application, in the first initialization stage P1, the threshold compensation stage P2, and the light-emitting stage P5, the second end of the third capacitor C3 is connected to the preset voltage VGH.

[0150] For example, the preset voltage VGH may be higher than the bias voltage OBS. For example, the preset voltage VGH is a high level, and the bias voltage OBS is a low level.

[0151] Optionally, the value of the bias voltage OBS may be predetermined. In an optional implementation of the present application, the value of the bias voltage OBS acting on the third capacitor C3 of the pixel circuit in different types of display devices may be different and may be predetermined through experimental testing or the like.

[0152] In this way, the third capacitor C3 can be used to control the voltage of the gate of the driving transistor T1 to be the reset voltage during the process in which the voltage connected to its second end changes from the preset voltage VGH to the bias voltage OBS (for example, during the falling edge of the preset voltage VGH switching to the bias voltage OBS), and the driving transistor T1 is reset from the negative bias state to the original state when the gate is at the reset voltage.

[0153] Furthermore, when the pixel circuit is in the light-emitting stage, the voltage connected to the second end of the third capacitor C3 changes back to the preset voltage. Correspondingly, the voltage of the gate of the driving transistor T1 is the required driving voltage. When the gate voltage is the driving voltage, the driving transistor T1 generates a target driving current, so that the target driving current passes through the third switching tube T5 when the third switching tube T5 is turned on, thereby driving the light-emitting element to emit light.

[0154] For ease of understanding, Figure 2 On the basis of Figure 5 shows a connection diagram of another pixel circuit. Figure 6 The timing diagram of each signal in each stage of the pixel circuit is shown. Figure 5 GB represents the variable voltage connected to the second terminal of the third capacitor C3.

[0155] In an optional embodiment of the present application, in the first initialization phase P1, the first switch T2 is turned on, and the data line SRC transmits the second initialization voltage Vini, so that the second initialization voltage Vini is transmitted to the first end of the second capacitor C1 via the turned-on first switch T2.

[0156] In an optional embodiment of the present application, during the first initialization phase P1, the second switch T3, the third switch T5, and the fourth switch T4 are turned on. In this way, the first initialization voltage Vref1 from the initialization signal source is transmitted to the first terminal of the light-emitting element via the turned-on fourth switch T4, thereby initializing the first terminal of the light-emitting element. In this way, the first initialization voltage Vref1 from the initialization signal source is transmitted to the gate of the driving transistor T1 via the turned-on second switch T3, the third switch T5, and the fourth switch T4, thereby initializing the gate of the driving transistor T1. During the first initialization phase P1, the first switch T2 is turned on, and the data line SRC transmits the second initialization voltage Vini. In this way, the second initialization voltage Vini is transmitted to the first end of the second capacitor C1 via the turned-on first switch T2.

[0157] Based on this, for example:

[0158] P1: the light-emitting signal EM is set low, that is, the light-emitting signal EM is at the on-level, and T5 is turned on; the first scan signal Scan1 and the second scan signal Scan2 are set high, that is, the first scan signal Scan1 and the second scan signal Scan2 are at the on-level, and T2 and T3 are turned on; the second initialization voltage Vini transmitted by the data line SRC initializes the node n5; the third scan signal Scan3 is set low, that is, the third scan signal Scan3 is at the on-level, T4 is turned on, and the initialization signal source Vref→node n4→node n3→node n1 forms a path, and Vref1 initializes the first electrode of the light-emitting element and the gate of the driving transistor T1. At this time, Vn5=Vini, Vn1=Vref.

[0159] In an optional embodiment of the present application, during the threshold compensation phase P2, the first switch T2 is turned on, and the data line SRC transmits the second initialization voltage Vini. The second switch T3 is turned on, and the third switch T5 is turned off. In this manner, the second initialization voltage Vini is transmitted to the first terminal of the second capacitor C1 via the turned-on first switch T2. In this manner, a voltage related to the voltage of the first power supply ELVDD and the threshold voltage of the driving transistor T1 is transmitted to the gate of the driving transistor T1.

[0160] In an optional embodiment of the present application, in the threshold compensation stage P2 , the fourth switch tube T4 is turned off.

[0161] Based on this, for example:

[0162] P2: The luminescence signal EM is set high, that is, EM is at the off-level, and T5 is turned off. The third scan signal Scan3 is set high, that is, the third scan signal Scan3 is at the off-level, and T4 is turned off. The first scan signal Scan1 and the second scan signal Scan2 are still set high, that is, the first scan signal Scan1 and the second scan signal Scan2 are at the on-level, and T2 and T3 remain on. In the initial stage of P2, the gate-source voltage Vgs of T1 is equal to Vref-VDD. At this time, because T3 shorts the gate and drain of T1, the positive voltage VDD output by ELVDD continuously raises the node voltages of nodes n1 and n3 until the gate-source voltage Vgs of T1 equals the threshold voltage Vth_T1 of T1. At this time, the voltage Vn1 of node n1 = VDD + Vth_T1, and the voltage Vn5 of node n5 = Vini.

[0163] In an optional embodiment of the present application, during the data voltage writing phase P3, the first switch T2 is turned on, and the SRC data line transmits the data voltage. In this way, the data voltage is transmitted to the first end of the second capacitor C1 via the turned-on first switch T2. For example:

[0164] P3: The first scan signal Scan1 is set to low, that is, the first scan signal Scan1 is at the off level, and T3 is closed; the second scan signal Scan2 remains high, that is, the second scan signal Scan2 is at the on level, and T2 continues to be turned on; the data line SRC switches from outputting Vini to outputting the data voltage, and the data voltage is written to the node n5. Due to capacitive coupling, the voltage of the n1 node connected to the gate of T1 will change synchronously to the driving voltage: the voltage of the node n1 in the P3 stage V n1_p3 =(data-Vini)*(C1 / (C1+C3+Cgs,t1))+VDD+Vth_T1.

[0165] also, Figure 6 In the P3 phase, the second scanning signal Scan2 is turned on by the on level ( Figure 6 The high level in the Figure 6 The low level in the transition edge ( Figure 6 The falling edge in the t1 is located within the period when the data line SRC outputs the data voltage, wherein t1 is the start time of the transition edge of the second scan signal Scan2 switching from the on level to the off level, and t3 is the end time of the transition edge of the second scan signal Scan2 switching from the on level to the off level; t2 is the start time of the data line SRC outputting the data voltage, that is, the end time of the transition edge required for the data line SRC to switch from the Vini voltage to the data voltage; t4 is the end time of the data line SRC outputting the data voltage, that is, the start time of the transition edge required for the data line SRC to switch from the data voltage to the Vini voltage. For other possible implementations of the relationship between t1, t2, t3 and t4, please refer to the description below. In the bias phase P4, t5 is the on level of the third scan signal Scan3 ( Figure 6 t6 is the time when the second scanning signal Scan2 changes from the on level to the off level; t7 is the time when the luminous signal EM changes from the off level to the on level. It can be understood that the transition from one level to another is completed in a relatively short period of time. Figure 6 The level changes of each signal during the transition process are not shown in the figure. Figure 6 In the figure, t1, t3 and t6 indicate the same position. For other definitions of the contextual relationship between t5, t6 and t7, please refer to the following description.

[0166] Optionally, in the data voltage writing phase P3 , the second switch tube T3 , the fourth switch tube T4 , and the third switch tube T5 are turned off.

[0167] In an optional embodiment of the present application, during the bias phase P4, the first switch T2, the second switch T3, and the third switch T5 are turned off, and the fourth switch T4 is turned on. In this way, the first initialization voltage Vref1 from the initialization signal source is transmitted to the first electrode of the light-emitting element via the turned-on fourth switch T4, thereby initializing the first electrode of the light-emitting element.

[0168] In an optional embodiment of the present application, the bias phase P4 is in a non-luminous phase of the pixel circuit. For example, the bias phase P4 is in a second-stage initialization phase. For example, the bias phase and the second-stage initialization phase are synchronized or overlapped. For example:

[0169] P4: The first end of C3 is connected to the variable voltage GB, and the second end of C3 is connected to the node n1. When the variable voltage GB switches from the preset voltage (VGH voltage) to the bias voltage (OBS voltage), the change amplitude is △OBS. This voltage change is coupled through the capacitor C3, thereby lowering the potential of the n1 node to the reset voltage: the voltage of the node n1 Vn1_p4 = [C3 / (C3+Cgs_t1+(C1*C2) / (C1+C2))]*△OBS+Vn1_p3; in the P4 stage, the voltage of the n1 node is maintained at this potential, so that the driving transistor T1 in the negative bias state is reset, thereby improving the low-frequency flicker and frequency-cutting flicker.

[0170] In addition, after OBS is completed, in the light-emitting stage, the variable voltage GB is switched back to VGH. This change is coupled through the capacitor C3, so that the potential of the n1 node is pulled back to the driving voltage Vn1_p3. Figure 6 The values ​​of the GB voltage and the OBS voltage shown can be adjusted to achieve reset of the driving transistors with different bias levels.

[0171] Meanwhile, in the P4 phase, the third scan signal Scan3 is set to low, that is, the third scan signal Scan3 is at the on-level, T4 is turned on, and Vref1 is written into the first electrode of the light emitting element to initialize the first electrode of the light emitting element.

[0172] In an optional embodiment of the present application, in the light-emitting phase P5, the third switch tube T5 is turned on, and the first switch tube T2, the second switch tube T3 and the fourth switch tube T4 are turned off.

[0173] P5: Scan2 is set low, that is, Scan2 is at the off level, T2 is turned off; C2 maintains the potential of the n5 node; EM is set low, that is, EM is at the on level, T5 is turned on; taking T5 as a P-type TFT as an example, according to the saturation current formula of the P-type TFT: It can be learned that:

[0174]

[0175] It can also be seen from this that in this 5T3C circuit, I OLED It has nothing to do with VDD and the threshold voltage Vth_T1 of T1, and realizes the compensation of ELVDDIR Drop and the threshold voltage fluctuation of T1, that is, it avoids the ELVDDIR Drop phenomenon and the threshold voltage fluctuation of T1 on I OLED The effect of this is reduced, thus ensuring that flickering is avoided during the lighting phase.

[0176] In the 5T3C circuit provided in the embodiments of the present application, the TFTs connected to the n1 and n5 nodes are both low-leakage N-type TFTs, thereby reducing the leakage path of the gate of the driving transistor T1 and preventing the gate potential of the driving transistor T1 from varying too much within a frame, causing flicker. This also reduces the pixel circuit's demand for capacitor size and the required pixel layout space, making it more suitable for high-PPI screens. Secondly, T4, which connects to the first electrode of the light-emitting element, is a dual-gate TFT. High-PPI products typically use short-channel devices to reduce pixel layout space. Using a dual-gate TFT in T4 here avoids the problem of dark spots caused by the initialization power supply Vref during the light-emitting phase pulling down the pixel anode potential due to the high off-state current of the short-channel device, thereby reducing yield loss. Furthermore, the extraction process of the threshold voltage Vth_T1 is separated from the data writing process. Using the first power supply ELVDD to extract the threshold voltage Vth_T1 of the driver transistor T1 maximizes the time required for threshold voltage extraction, making the extracted Vth_T1 value as close as possible to the actual value and improving the pixel circuit's ability to compensate for threshold voltage non-uniformity. The first power supply ELVDD voltage is also extracted during the Vth_T1 extraction process, enabling ELVDDIR Drop compensation. Furthermore, the data voltage is written to the gate of the driver transistor DTFT via capacitor coupling C1, increasing the data voltage write speed. This makes the pixel circuit suitable for screens with short line cycles, such as those with multiple lines and high refresh rates. Even with short line cycles, the data voltage can be properly written to the gate of the driver transistor DTFT. In addition, the gate of the driving transistor DTFT is connected to the variable voltage GB through the capacitor C3. The variable voltage lowers the gate potential of the driving transistor DTFT through the capacitor C3 capacitive coupling, thereby realizing the OBS function of the driving transistor DTFT, improving the low-frequency flicker and frequency-cutting flicker of the screen, and reducing the space required for the pixel circuit layout without adding TFTs. At the same time, the capacitor C3 can also be used as a storage capacitor to maintain the gate potential of the driving transistor DTFT during the light-emitting stage.

[0177] In one embodiment, as mentioned above, before the light-emitting stage, the working stage of the pixel circuit also includes a data voltage writing stage P3, and in the data voltage writing stage P3, the first switch tube T2 is turned on under the control of the second scan signal Scan2, the second switch tube T3 is turned off under the control of the first scan signal Scan1, the third switch tube T5 is turned off under the control of the light-emitting signal EM, and the fourth switch tube T4 is turned off under the control of the third scan signal Scan3; the data voltage (data voltage) transmitted by the data line acts on the gate of the driving transistor through the first switch tube T2 and the second capacitor C1, so that the gate voltage of the driving transistor is the driving voltage.

[0178] Wherein, when the second scanning signal Scan2 is at the on-level, the first switch tube T2 is turned on. Referring to the above discussion, it can be seen that the on-level of the second scanning signal Scan2 can be a high level, and the off-level of the second scanning signal Scan2 can be a low level. Optionally, as Figure 6 As shown, in the data voltage writing phase P3, the second scan signal Scan2 is switched from the off level to the on level.

[0179] In an optional embodiment of the present application, the starting time t1 of the transition edge of the second scan signal Scan2 connected to the gate of the first switch transistor T2, which transitions from the on-level V1 to the off-level V2, occurs after the ending time t2 of the transition edge of the voltage on the data line transitioning from the second initialization voltage Vini to the data voltage data. Alternatively, the starting time t1 of the transition edge of the second scan signal Scan2 connected to the gate of the first switch transistor T2, which transitions from the on-level V1 to the off-level V2, occurs at the ending time t2 of the transition edge of the voltage on the data line transitioning from the second initialization voltage Vini to the data voltage data.

[0180] That is, the earliest switching time point of the second scanning signal Scan2 of the K-th row pixel circuit from the on-level V1 (for example, a high level) to the off-level V2 (for example, a low level) is: the moment when the data line SRC switches from Vini to the transition edge required for the data voltage of the K-th row pixel circuit (for example, a rising edge or a falling edge, for example, when the voltage Vini is greater than the data voltage, it is a falling edge, for example, when the voltage Vini is less than the data voltage, it is a rising or falling edge).

[0181] For example, Figure 7 As shown, t1 is after t2; Figure 8 As shown, t1 is the same as t2.

[0182] In an optional embodiment of the present application, the end time t3 of the transition edge of the second scan signal Scan2 connected to the gate of the first switch tube T2, which transitions from the on-level V1 to the off-level V2, occurs before the start time t4 of the transition edge of the voltage on the data line transitioning from the data voltage data to the second initialization voltage Vini. Alternatively, the end time t3 of the transition edge of the second scan signal Scan2 connected to the gate of the first switch tube T2, which transitions from the on-level V1 to the off-level V2, occurs before the start time t4 of the transition edge of the voltage on the data line transitioning from the data voltage data to the second initialization voltage Vini.

[0183] That is, before the data line SRC starts switching from the data voltage of the K-th row pixel circuit to the transition edge (for example, a rising edge or a falling edge, for example, when the voltage Vini is greater than the data voltage, it is a rising edge, for example, when the voltage Vini is less than the data voltage, it is a falling edge), the second scanning signal Scan2 of the K-th row pixel circuit needs to be completely switched from the on-level V1 (for example, a high level) to the off-level V2 (for example, a low level).

[0184] For example, Figure 9 As shown, t3 is before t4; Figure 10 As shown, t3 is the same as t4.

[0185] In summary, the entire switching period of the second scan signal Scan2 from the on level V1 (eg, high level) to the off level V2 (eg, low level) must be within the period of the data line SRC outputting the data voltage, thereby preventing erroneous writing of the data voltage data.

[0186] In an optional embodiment of the present application, in the bias phase P4, the start time t5 of the on-level of the third scan signal Scan3 connected to the gate of the fourth switch tube T4 is after the second scan signal Scan2 connected to the gate of the first switch tube T2 jumps from the on-level to the off-level (i.e., time t6), and before the light-emitting signal EM connected to the gate of the third switch tube T5 jumps from the off-level to the on-level (i.e., time t7).

[0187] In an optional embodiment of the present application, in the bias phase P4, the end time t8 of the on-level of the third scan signal Scan3 connected to the gate of the fourth switch tube T4 is after the second scan signal Scan2 connected to the gate of the first switch tube T2 jumps from the on-level to the off-level (i.e., time t6), and before the light-emitting signal EM connected to the gate of the third switch tube T5 jumps from the off-level to the on-level (i.e., time t7).

[0188] For example, the on-level of the third scan signal Scan3 may be a low level, and the off-level of the third scan signal Scan3 may be a high level.

[0189] That is, after the falling edge of the second scan signal Scan2 in phase P3, the third scan signal Scan3 switches to the on level; or before the falling edge of the luminescence signal EM begins, the third scan signal Scan3 switches to the on level. This allows the first electrode (e.g., anode) of the light-emitting element to be initialized in phase P4.

[0190] In an optional embodiment of the present application, the writing frame of the pixel circuit includes one or more bias phases P4.

[0191] In an optional embodiment of the present application, the writing frame of the pixel circuit includes one or more light-emitting phases P5.

[0192] In an optional embodiment of the present application, the holding frame of the pixel circuit includes one or more bias phases P4.

[0193] In an optional embodiment of the present application, the holding frame of the pixel circuit includes one or more light-emitting phases P5.

[0194] During screen display, a display cycle includes a write frame, or a write frame and a hold frame. A write frame refers to a subframe in which the pixel grayscale data voltage is written, and a hold frame refers to a subframe in which no image data voltage is written to the pixel circuit, but the driver chip DDIC still drives the internal circuit of the panel to work normally to prevent flicker. For example, when the base frequency is 60Hz, at a 30Hz refresh rate, one display cycle consists of 1 write frame plus 1 hold frame; at a 1Hz refresh rate, one display cycle consists of 1 write frame plus 59 hold frames. The refresh rate is defined as: refresh frequency / frame frequency; base refresh frequency / base frame frequency.

[0195] In an optional embodiment of the present application, Figure 11 As shown, in the same write frame, the bias stage P4 (for example, corresponding to the on-level period of the third scan signal Scan3 and / or the bias voltage or low-level period in the GB voltage) and the light-emitting stage P5 (for example, corresponding to the on-level or high-level period of the light-emitting signal EM) are alternately set.

[0196] In an optional embodiment of the present application, in the same writing frame, the data voltage writing phase P3 is before the biasing phase P4.

[0197] In an optional embodiment of the present application, in the same writing frame, the first initialization phase P1, the threshold compensation phase P2, the data voltage writing phase P3, and the bias phase P4 are arranged in sequence. The writing frame may include the first initialization phase P1, the threshold compensation phase P2, the data voltage writing phase P3, the bias phase P4, and the light emitting phase P5.

[0198] In an optional embodiment of the present application, in the same writing frame, the pulse corresponding to the bias voltage connected to the second end of the third capacitor C3 (eg Figure 11 The number of low-level pulses in the GB voltage is equal to the turn-off pulse of the light-emitting signal EM connected to the gate of the third switch tube (such as Figure 11 The number of high-level pulses in the PWM pulse generator is divided by N.

[0199] In an optional embodiment of the present application, in the same writing frame, the gate of the fourth switch tube T4 is connected to the on-pulse of the third scan signal Scan3 (eg Figure 11The number of low-level pulses in the gate of the third switch tube T5 minus 1 is equal to the turn-off pulse of the light-emitting signal EM connected to the gate of the third switch tube T5 (such as Figure 11 The number of high-level pulses in the output is divided by N, where N is an integer greater than or equal to 1.

[0200] In an optional embodiment of the present application, N is 1, 2, or 3. That is, the frequency of the third scan signal Scan3 and the pulse of the output bias voltage can be the same as the frequency of the luminescence signal EM, or 1 / 2 or 1 / 3 of the frequency of the luminescence signal EM. In this way, it can be ensured that when the luminescence signal EM is at a high level in each stage, the third scan signal Scan3 and the bias voltage can complete the anode initialization and the OBS processing of the driving transistor T1.

[0201] In an optional embodiment of the present application, Figure 11 As shown, in the same holding frame, the bias stage P4 (for example, corresponding to the on-level period of the third scanning signal Scan3 and / or the bias voltage or low-level period in the GB voltage) and the light-emitting stage P5 (for example, corresponding to the on-level or high-level period of the light-emitting signal EM) are alternately set.

[0202] For example, the holding frame may include a biasing phase P4 and a light emitting phase P5. For example, the holding frame may not include a first initialization phase P1, a threshold compensation phase P2, and a data voltage writing phase P3.

[0203] In an optional embodiment of the present application, in the same holding frame, the pulse corresponding to the bias voltage connected to the second end of the third capacitor C3 (eg Figure 11 The number of low-level pulses in the GB voltage is equal to the turn-off pulse of the light-emitting signal EM connected to the gate of the third switch tube T5 (such as Figure 11 The number of high-level pulses in ) is divided by M.

[0204] In an optional embodiment of the present application, in the same holding frame, the gate of the fourth switch tube T4 is connected to the on-pulse of the third scan signal Scan3 (eg Figure 11 The number of low-level pulses in the gate of the third switch tube T5 is equal to the turn-off pulse of the light-emitting signal EM connected to the gate of the third switch tube T5 (such as Figure 11 The number of high-level pulses in the PWM pulse generator is divided by M, where M is an integer greater than or equal to 1.

[0205] In an optional embodiment of the present application, M is 1, 2 or 3.

[0206] For example, taking N and M as 1, Figure 11The figure shows a comparison of the number of pulses for different signals. Here, when the base frequency is 60 Hz and the frame duration is 16.6 ms, multiple EM pulses (luminous pulses) of the luminous signal EM are set within a base frame. With four EM pulses within a frame, the EM frequency is 4 * base frequency = 240 Hz. Other frequencies can be implemented similarly to the above method, for example, 30 Hz = 1 write frame + 1 hold frame, which will not be further described here.

[0207] Based on the above description, for example, Figure 5 The pixel circuit shown in FIG. Figure 12 Provides a timing simulation diagram of each signal.

[0208] In addition, for Figure 5 The pixel circuit shown in FIG. 1 simulates the brightness control of the data voltage pair, as shown in FIG. Figure 13 As shown in the figure, we can see that changing the data voltage can normally control the pixel brightness. Figure 14 As shown, in the grayscale simulation of the driving transistor of the G255 grayscale and the driving transistor of the G64 grayscale, when the threshold voltage Vth of the driving transistor fluctuates within ±0.5V, the brightness of the light-emitting element changes; it can be seen that under the G255 grayscale brightness, when the Vth of the driving transistor fluctuates within ±0.5V, the brightness change is within 6%, indicating that the pixel circuit has the function of compensating for the fluctuation of the Vth of the driving transistor, thereby avoiding the flickering of the light-emitting element.

[0209] like Figure 15 As shown, for Figure 5 In the pixel circuit shown, when the brightness is 600 nit, the data voltage is kept unchanged and the brightness offset when ELVDD fluctuates at ±0.5 V is simulated. It can be seen that the offset of ELVDD has little effect on the brightness, while the light emission of the light-emitting element in the traditional existing pixel circuit is very sensitive to the offset of ELVDD, indicating that the pixel circuit provided in the present application has a good ELVDDIR Drop compensation effect.

[0210] In one embodiment, the present application also provides a pixel circuit, which includes a driving transistor, a first switching tube, a second switching tube, a second capacitor and a third capacitor; the first switching tube is connected between the data line and the first end of the second capacitor; the second end of the second capacitor is connected to the gate of the driving transistor; the first electrode of the driving transistor is connected to the first power supply; the second switching tube is connected between the second electrode and the gate of the driving transistor; the first end of the third capacitor is connected to the gate of the driving transistor, and the second end of the third capacitor is connected to a variable voltage.

[0211] The above-mentioned pixel circuit is connected to a variable voltage, so that the third capacitor controls the voltage of the gate of the driving transistor to change under the action of the variable voltage, thereby resetting the driving transistor from a negative bias state to an original state, thereby avoiding the driving transistor bias affecting the low frequency and frequency switching flicker of the screen.

[0212] Optionally, in the bias phase, the second end of the third capacitor is connected to a bias voltage; in the data voltage writing phase, the second end of the third capacitor is connected to a preset voltage, and the preset voltage is different from the bias voltage;

[0213] Optionally, the preset voltage is higher than the bias voltage;

[0214] Optionally, in the data voltage writing phase, the first switch tube is turned on, and the data line transmits the data voltage;

[0215] Optionally, in the first initialization stage, the first switch tube is turned on, and the data line transmits the second initialization voltage;

[0216] Optionally, the pixel circuit further includes a light-emitting element, and a third switching tube and / or a fourth switching tube;

[0217] The third switch tube is connected between the second electrode of the driving transistor and the first electrode of the light emitting element, and the fourth switch tube is connected between the initialization signal source and the first electrode of the light emitting element;

[0218] Optionally, in the bias phase, the first switch tube, the second switch tube, and the third switch tube are turned off, and the fourth switch tube is turned on;

[0219] Optionally, in the first initialization stage, the second switch tube, the third switch tube and the fourth switch tube are turned on;

[0220] Optionally, in the threshold compensation stage, the first switch tube is turned on, and the data line transmits the second initialization voltage; the second switch tube is turned on, and the third switch tube is turned off;

[0221] Optionally, in the threshold compensation stage, the fourth switch tube is turned off;

[0222] Optionally, in the first initialization stage, the threshold compensation stage, and the light-emitting stage, the second end of the third capacitor is connected to a preset voltage;

[0223] Optionally, in the light-emitting stage, the third switch tube is turned on, and the first switch tube, the second switch tube and the fourth switch tube are turned off;

[0224] Optionally, the write frame of the pixel circuit includes one or more bias phases;

[0225] Optionally, the biasing stage is in a non-light emitting stage of the pixel circuit;

[0226] Optionally, the writing frame of the pixel circuit includes one or more light emitting phases;

[0227] Optionally, in the same writing frame, the bias phase and the light emitting phase are alternately arranged;

[0228] Optionally, in the same writing frame, the data voltage writing phase precedes the biasing phase;

[0229] Optionally, in the same writing frame, the first initialization phase, the threshold compensation phase, the data voltage writing phase, and the bias phase are arranged in sequence;

[0230] Optionally, the pixel circuit further includes a first capacitor connected between the first power supply and a first end of the second capacitor.

[0231] This embodiment can be combined with some or all of the features of the above embodiments, which will not be described in detail here.

[0232] The connection relationship and functional implementation of the pixel circuit are consistent with the pixel circuits described in the above embodiments. Please refer to the above description for details and will not be repeated here.

[0233] In one embodiment, based on the same inventive concept, the present application further provides a method for driving a pixel circuit, the pixel circuit comprising a driving transistor T1, a first switching transistor T2, a second switching transistor T3, a second capacitor C1, and a third capacitor C3; the first switching transistor is connected between a data line and a first end of the second capacitor; the second end of the second capacitor is connected to a gate of the driving transistor; the first electrode of the driving transistor is connected to a first power source; the second switching transistor is connected between the second electrode and the gate of the driving transistor; the first end of the third capacitor is connected to the gate of the driving transistor; and the second end of the third capacitor is connected to a variable voltage.

[0234] The driving method includes: in the bias phase P4, the second end of the third capacitor is connected to the bias voltage OBS; in the data voltage writing phase P3, the second end of the third capacitor is connected to the preset voltage VGH, and the preset voltage VGH is different from the bias voltage OBS.

[0235] In one embodiment, in the data voltage writing phase P3, the second scanning signal connected to the gate of the first switch tube is at the on-level, and the data line transmits the data voltage.

[0236] Optionally, in the first initialization phase P1, the second scanning signal connected to the gate of the first switch tube is at a conduction level, and the data line transmits a second initialization voltage.

[0237] Optionally, the pixel circuit further includes a third switch tube, a fourth switch tube and a light-emitting element, the third switch tube is connected between the second electrode of the driving transistor and the first electrode of the light-emitting element, and the fourth switch tube is connected between the initialization signal source and the first electrode of the light-emitting element.

[0238] In the first initialization stage, the first scanning signal connected to the gate of the second switch tube is at the on-level, the light emitting signal connected to the gate of the third switch tube is at the on-level, and the third scanning signal connected to the gate of the fourth switch tube is at the on-level.

[0239] Optionally, during the threshold compensation phase, the second scanning signal connected to the gate of the first switch is at an on-level, and the data line transmits a second initialization voltage. The first scanning signal connected to the gate of the second switch is at an on-level, and the light-emitting signal connected to the gate of the third switch is at an off-level.

[0240] Optionally, in the threshold compensation stage, the third scanning signal connected to the gate of the fourth switch tube is at a turn-off level.

[0241] Optionally, in the first initialization stage, the threshold compensation stage, and the light-emitting stage, the second end of the third capacitor is connected to a preset voltage.

[0242] Optionally, a write frame for the pixel circuit includes one or more bias phases.

[0243] Optionally, the bias phase is in a non-light emitting phase of the pixel circuit.

[0244] Optionally, a writing frame of the pixel circuit includes one or more light emitting phases.

[0245] Optionally, in the same writing frame, the bias phase and the light emitting phase are alternately arranged.

[0246] Optionally, in the same writing frame, the data voltage writing phase precedes the biasing phase.

[0247] Optionally, in the same writing frame, the first initialization phase, the threshold compensation phase, the data voltage writing phase, and the bias phase are arranged in sequence.

[0248] Optionally, in the same write frame, the number of pulses corresponding to the bias voltage connected to the second end of the third capacitor is equal to the number of turn-off pulses of the luminous signal connected to the gate of the third switching tube divided by N, and / or the number of turn-on pulses of the third scanning signal connected to the gate of the fourth switching tube minus 1 is equal to the number of turn-off pulses of the luminous signal connected to the gate of the third switching tube divided by N, where N is an integer greater than or equal to 1.

[0249] Optionally, N is 1, 2 or 3.

[0250] Optionally, the hold frame of the pixel circuit includes one or more bias phases.

[0251] Optionally, the holding frame of the pixel circuit includes one or more light emitting phases.

[0252] Optionally, in the same holding frame, the bias phase and the light emitting phase are alternately arranged.

[0253] Optionally, in the same holding frame, the number of pulses corresponding to the bias voltage connected to the second end of the third capacitor is equal to the number of turn-off pulses of the luminous signal connected to the gate of the third switching tube divided by M, and / or, in the same holding frame, the number of turn-on pulses of the third scanning signal connected to the gate of the fourth switching tube is equal to the number of turn-off pulses of the luminous signal connected to the gate of the third switching tube divided by M, where M is an integer greater than or equal to 1.

[0254] Optionally, M is 1, 2 or 3.

[0255] Optionally, in the light-emitting stage, the light-emitting signal connected to the gate of the third switch tube is at a conduction level.

[0256] Optionally, in the light-emitting stage, the second scanning signal connected to the gate of the first switching tube is at an off level, the first scanning signal connected to the gate of the second switching tube is at an off level, and the third scanning signal connected to the gate of the fourth switching tube is at an off level.

[0257] Optionally, the start time of the transition edge of the second scanning signal connected to the gate of the first switching tube, in which the second scanning signal transitions from the on-level to the off-level, is after the end time of the transition edge of the voltage on the data line transitioning from the second initialization voltage to the data voltage. Alternatively, the start time of the transition edge of the second scanning signal connected to the gate of the first switching tube, in which the second scanning signal transitions from the on-level to the off-level, is the end time of the transition edge of the voltage on the data line transitioning from the second initialization voltage to the data voltage.

[0258] Optionally, the end time of the transition edge of the second scanning signal connected to the gate of the first switching tube, in which the second scanning signal transitions from the on-level to the off-level, is before the start time of the transition edge of the voltage on the data line transitioning from the data voltage to the second initialization voltage. Alternatively, the end time of the transition edge of the second scanning signal connected to the gate of the first switching tube, in which the second scanning signal transitions from the on-level to the off-level, is the start time of the transition edge of the voltage on the data line transitioning from the data voltage to the second initialization voltage.

[0259] Optionally, in the bias stage, the start time of the on-level of the third scanning signal connected to the gate of the fourth switching tube is after the second scanning signal connected to the gate of the first switching tube jumps from the on-level to the off-level, and before the luminous signal connected to the gate of the third switching tube jumps from the off-level to the on-level.

[0260] Optionally, the pixel circuit further includes a first capacitor connected between the first power supply and the first end of the second capacitor.

[0261] This embodiment can be combined with some or all of the features of the above embodiments, which will not be described in detail here.

[0262] For other limitations of this method, please refer to the above description of the pixel circuit embodiment, which will not be repeated here.

[0263] In one embodiment, the present application further provides a display panel, which includes a pixel circuit as described in any one of the above embodiments.

[0264] In one embodiment, a display device is further provided, comprising a display panel as described in any of the above embodiments. The display device may include a mobile phone, a tablet computer, a laptop computer, a wearable device, an in-vehicle display device, etc.

[0265] The technical features of the above embodiments can be combined arbitrarily. To make the description concise, not all possible combinations of the technical features in the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

[0266] The above-described embodiments merely represent several implementation methods of the present application. While the descriptions are relatively specific and detailed, they should not be construed as limiting the scope of the present application. It should be noted that a person of ordinary skill in the art may make various modifications and improvements without departing from the spirit of the present application, and these modifications and improvements fall within the scope of protection of the present application. Therefore, the scope of protection of the present application shall be determined by the appended claims.

Claims

1. A pixel circuit, characterized in that: The pixel circuit includes a driving transistor, a first switching tube, a second switching tube, a third switching tube, a fourth switching tube, a first capacitor, a second capacitor and a light-emitting element; The first switch is connected between the data line and the first end of the second capacitor; the first capacitor is connected between the first power supply and the first end of the second capacitor; the second end of the second capacitor is connected to the gate of the driving transistor; and the first electrode of the driving transistor is connected to the first power supply. The second switch tube is connected between the second electrode and the gate of the driving transistor, the third switch tube is connected between the second electrode of the driving transistor and the first electrode of the light-emitting element, and the fourth switch tube is connected between the initialization signal source and the first electrode of the light-emitting element; wherein the first switch tube and the second switch tube are N-type transistors, and / or the fourth switch tube is a dual-gate transistor; The pixel circuit also includes a third capacitor; the first end of the third capacitor is connected to the gate of the driving transistor, and the second end of the third capacitor is connected to a variable voltage; in the bias stage, the second end of the third capacitor is connected to the bias voltage; in the data voltage writing stage, the second end of the third capacitor is connected to a preset voltage, and the preset voltage is different from the bias voltage.

2. The pixel circuit according to claim 1, wherein: The gate of the first switch tube receives the second scan signal, the first electrode of the first switch tube is connected to the data line, and the second electrode of the first switch tube is connected to the first end of the second capacitor; A first end of the first capacitor is connected to the first power supply, and a second end of the first capacitor is connected to a first end of the second capacitor; The gate of the second switch tube is connected to the first scanning signal, the first electrode of the second switch tube is connected to the gate of the driving transistor, and the second electrode of the second switch tube is connected to the second electrode of the driving transistor; The gate of the third switch tube is connected to the light emitting signal, the first electrode of the third switch tube is connected to the second electrode of the driving transistor, and the second electrode of the third switch tube is connected to the first electrode of the light emitting element; The gate of the fourth switch tube is connected to the third scan signal, the first electrode of the fourth switch tube is connected to the initialization signal source, and the second electrode of the fourth switch tube is connected to the first electrode of the light-emitting element; The second electrode of the light emitting element is connected to a second power source.

3. The pixel circuit according to claim 1, wherein: The preset voltage is higher than the bias voltage.

4. The pixel circuit according to claim 1, wherein: In the bias phase, the first switch tube, the second switch tube, and the third switch tube are turned off, and the fourth switch tube is turned on.

5. The pixel circuit according to claim 1, wherein: During the data voltage writing phase, the first switch is turned on and the data line transmits the data voltage.

6. The pixel circuit according to claim 5, wherein: In the first initialization stage, the first switch tube is turned on, and the data line transmits a second initialization voltage.

7. The pixel circuit according to claim 6, wherein: In the first initialization stage, the second switch tube, the third switch tube, and the fourth switch tube are turned on.

8. The pixel circuit according to claim 1, wherein: In the threshold compensation stage, the first switch tube is turned on, and the data line transmits a second initialization voltage; the second switch tube is turned on, and the third switch tube is turned off.

9. The pixel circuit according to claim 1, wherein: During the threshold compensation stage, the fourth switch tube is turned off.

10. The pixel circuit according to claim 5 or 6, characterized in that: In the first initialization stage, the threshold compensation stage, and the light-emitting stage, the second end of the third capacitor is connected to a preset voltage.

11. The pixel circuit according to claim 1, wherein: In the light-emitting stage, the third switch tube is turned on, and the first switch tube, the second switch tube and the fourth switch tube are turned off.

12. The pixel circuit according to claim 11, wherein: A write frame of the pixel circuit includes one or more of the bias phases.

13. The pixel circuit according to claim 12, wherein: The bias phase is a non-light emitting phase of the pixel circuit.

14. The pixel circuit according to claim 13, wherein: The writing frame of the pixel circuit includes one or more of the light emitting phases.

15. The pixel circuit according to claim 14, wherein: In the same writing frame, the biasing phase and the light emitting phase are alternately arranged.

16. The pixel circuit according to claim 14, wherein: In the same writing frame, the data voltage writing phase precedes the biasing phase.

17. The pixel circuit according to claim 14, wherein: In the same writing frame, the first initialization phase, the threshold compensation phase, the data voltage writing phase, and the bias phase are arranged in sequence.

18. The pixel circuit according to claim 14, wherein: In the same write frame, the number of pulses corresponding to the bias voltage connected to the second end of the third capacitor is equal to the number of turn-off pulses of the luminous signal connected to the gate of the third switching tube divided by N, and / or the number of turn-on pulses of the third scanning signal connected to the gate of the fourth switching tube minus 1 is equal to the number of turn-off pulses of the luminous signal connected to the gate of the third switching tube divided by N, where N is an integer greater than or equal to 1.

19. The pixel circuit according to claim 18, wherein: N is 1, 2 or 3.

20. The pixel circuit according to claim 11, wherein: The holding frame of the pixel circuit includes one or more of the bias phases.

21. The pixel circuit according to claim 20, wherein: The holding frame of the pixel circuit includes one or more of the light emitting phases.

22. The pixel circuit according to claim 21, wherein: In the same holding frame, the biasing phase and the light emitting phase are alternately arranged.

23. The pixel circuit according to claim 22, wherein: In the same holding frame, the number of pulses corresponding to the bias voltage connected to the second end of the third capacitor is equal to the number of turn-off pulses of the luminous signal connected to the gate of the third switching tube divided by M, and / or the number of turn-on pulses of the third scanning signal connected to the gate of the fourth switching tube is equal to the number of turn-off pulses of the luminous signal connected to the gate of the third switching tube divided by M, where M is an integer greater than or equal to 1.

24. The pixel circuit according to claim 23, wherein: M is 1, 2 or 3.

25. The pixel circuit according to claim 10, wherein: In the light-emitting stage, the third switch tube is turned on, and the first switch tube, the second switch tube and the fourth switch tube are turned off.

26. The pixel circuit according to claim 23, wherein: The starting time of the transition edge of the second scanning signal connected to the gate of the first switching tube from the on level to the off level is after the ending time of the transition edge of the voltage on the data line from the second initialization voltage to the data voltage; or, the starting time of the transition edge of the second scanning signal connected to the gate of the first switching tube from the on level to the off level is the ending time of the transition edge of the voltage on the data line from the second initialization voltage to the data voltage.

27. The pixel circuit according to claim 26, wherein: The end time of the transition edge of the second scanning signal connected to the gate of the first switching tube from the on-level to the off-level is before the start time of the transition edge of the voltage on the data line from the data voltage to the second initialization voltage; or, the end time of the transition edge of the second scanning signal connected to the gate of the first switching tube from the on-level to the off-level is the start time of the transition edge of the voltage on the data line from the data voltage to the second initialization voltage.

28. The pixel circuit according to claim 27, wherein: In the bias stage, the start time of the on-level of the third scanning signal connected to the gate of the fourth switching tube is after the second scanning signal connected to the gate of the first switching tube jumps from the on-level to the off-level, and before the light-emitting signal connected to the gate of the third switching tube jumps from the off-level to the on-level.

29. The pixel circuit according to claim 28, wherein: A dual-gate transistor includes at least two transistors connected in series.

30. A pixel circuit, characterized in that: The pixel circuit includes a driving transistor, a first switching transistor, a second switching transistor, a second capacitor and a third capacitor; The first switch is connected between the data line and the first end of the second capacitor; the second end of the second capacitor is connected to the gate of the driving transistor; the first electrode of the driving transistor is connected to the first power supply; The second switch tube is connected between the second electrode and the gate of the driving transistor; A first end of the third capacitor is connected to the gate of the driving transistor, and a second end of the third capacitor is connected to a variable voltage; In the bias phase, the second end of the third capacitor is connected to a bias voltage; in the data voltage writing phase, the second end of the third capacitor is connected to a preset voltage, which is different from the bias voltage.

31. The pixel circuit according to claim 30, wherein: The preset voltage is higher than the bias voltage.

32. The pixel circuit according to claim 30, wherein: During the data voltage writing phase, the first switch is turned on and the data line transmits the data voltage.

33. The pixel circuit according to claim 30, wherein: In the first initialization stage, the first switch tube is turned on, and the data line transmits a second initialization voltage.

34. The pixel circuit according to claim 30, wherein: The pixel circuit further includes a light-emitting element, and a third switching tube and / or a fourth switching tube.

35. The pixel circuit according to claim 34, wherein: The third switch tube is connected between the second electrode of the driving transistor and the first electrode of the light emitting element, and the fourth switch tube is connected between the initialization signal source and the first electrode of the light emitting element.

36. The pixel circuit according to claim 35, wherein: In the bias phase, the first switch tube, the second switch tube, and the third switch tube are turned off, and the fourth switch tube is turned on.

37. The pixel circuit according to claim 35, wherein: In the first initialization stage, the second switch tube, the third switch tube, and the fourth switch tube are turned on.

38. The pixel circuit according to claim 35, wherein: In the threshold compensation stage, the first switch tube is turned on, and the data line transmits a second initialization voltage; the second switch tube is turned on, and the third switch tube is turned off.

39. The pixel circuit according to claim 35, wherein: During the threshold compensation stage, the fourth switch tube is turned off.

40. The pixel circuit according to claim 37, wherein: In the first initialization stage, the threshold compensation stage, and the light-emitting stage, the second end of the third capacitor is connected to a preset voltage.

41. The pixel circuit according to claim 34, wherein: In the light-emitting stage, the third switch tube is turned on, and the first switch tube, the second switch tube and the fourth switch tube are turned off.

42. The pixel circuit according to claim 41, wherein: A write frame of the pixel circuit includes one or more of the bias phases.

43. The pixel circuit according to claim 42, wherein: The bias phase is a non-light emitting phase of the pixel circuit.

44. The pixel circuit according to claim 43, wherein: The writing frame of the pixel circuit includes one or more of the light emitting phases.

45. The pixel circuit according to claim 44, wherein: In the same writing frame, the biasing phase and the light emitting phase are alternately arranged.

46. ​​The pixel circuit according to claim 44, wherein: In the same writing frame, the data voltage writing phase precedes the biasing phase.

47. The pixel circuit according to claim 44, wherein: In the same writing frame, the first initialization phase, the threshold compensation phase, the data voltage writing phase, and the bias phase are arranged in sequence.

48. The pixel circuit according to claim 30, wherein: The pixel circuit further includes a first capacitor connected between a first power source and a first end of the second capacitor.

49. A method for driving a pixel circuit, characterized in that: The pixel circuit includes a driving transistor, a first switching transistor, a second switching transistor, a second capacitor and a third capacitor; The first switch is connected between the data line and the first end of the second capacitor; the second end of the second capacitor is connected to the gate of the driving transistor; the first electrode of the driving transistor is connected to the first power supply; The second switch tube is connected between the second electrode and the gate of the driving transistor. A first end of the third capacitor is connected to the gate of the driving transistor, and a second end of the third capacitor is connected to a variable voltage; The driving method includes: In the bias phase, the second end of the third capacitor is connected to the bias voltage; During the data voltage writing phase, the second end of the third capacitor is connected to a preset voltage, and the preset voltage is different from the bias voltage.

50. The driving method according to claim 49, wherein: In the data voltage writing phase, the second scanning signal connected to the gate of the first switch tube is at an on-level, and the data line transmits the data voltage; In the first initialization stage, the second scanning signal connected to the gate of the first switch tube is at a conduction level, and the data line transmits a second initialization voltage.

51. The driving method according to claim 49, wherein: The pixel circuit also includes a third switch tube, a fourth switch tube and a light-emitting element. The third switch tube is connected between the second electrode of the driving transistor and the first electrode of the light-emitting element. The fourth switch tube is connected between the initialization signal source and the first electrode of the light-emitting element.

52. The driving method according to claim 51, characterized in that: In the first initialization stage, the first scanning signal connected to the gate of the second switch tube is at the on-level, the light emitting signal connected to the gate of the third switch tube is at the on-level, and the third scanning signal connected to the gate of the fourth switch tube is at the on-level; In the threshold compensation stage, the second scanning signal connected to the gate of the first switch tube is at an on-level, and the data line transmits a second initialization voltage; the first scanning signal connected to the gate of the second switch tube is at an on-level, and the light-emitting signal connected to the gate of the third switch tube is at an off-level; In the threshold compensation stage, the third scanning signal connected to the gate of the fourth switch tube is at an off level; During the first initialization phase, the threshold compensation phase, and the light-emitting phase, the second end of the third capacitor is connected to a preset voltage.

53. The driving method according to claim 52, characterized in that: A write frame of the pixel circuit includes one or more of the bias phases.

54. The driving method according to claim 53, characterized in that: The bias phase is in a non-light emitting phase of the pixel circuit; The writing frame of the pixel circuit includes one or more of the light emitting phases.

55. The driving method according to claim 54, characterized in that: In the same writing frame, the biasing phase and the light emitting phase are alternately arranged.

56. The driving method according to claim 55, characterized in that: In the same writing frame, the data voltage writing phase is before the biasing phase; In the same writing frame, the first initialization phase, the threshold compensation phase, the data voltage writing phase, and the bias phase are arranged in sequence; In the same write frame, the number of pulses corresponding to the bias voltage connected to the second end of the third capacitor is equal to the number of turn-off pulses of the luminous signal connected to the gate of the third switching tube divided by N, and / or the number of turn-on pulses of the third scanning signal connected to the gate of the fourth switching tube minus 1 is equal to the number of turn-off pulses of the luminous signal connected to the gate of the third switching tube divided by N, where N is an integer greater than or equal to 1.

57. The driving method according to claim 56, characterized in that: N is 1, 2 or 3.

58. The driving method according to claim 51, wherein: A holding frame of the pixel circuit includes one or more of the bias phases; The holding frame of the pixel circuit includes one or more light emission phases.

59. The driving method according to claim 58, characterized in that: In the same holding frame, the biasing phase and the light emitting phase are alternately arranged; In the same holding frame, the number of pulses corresponding to the bias voltage connected to the second end of the third capacitor is equal to the number of turn-off pulses of the luminous signal connected to the gate of the third switching tube divided by M, and / or the number of turn-on pulses of the third scanning signal connected to the gate of the fourth switching tube is equal to the number of turn-off pulses of the luminous signal connected to the gate of the third switching tube divided by M, where M is an integer greater than or equal to 1.

60. The driving method according to claim 59, wherein: M is 1, 2 or 3.

61. The driving method according to claim 59, wherein: In the light-emitting stage, the light-emitting signal connected to the gate of the third switch tube is at the on-level; In the light-emitting stage, the second scanning signal connected to the gate of the first switching tube is at an off level, the first scanning signal connected to the gate of the second switching tube is at an off level, and the third scanning signal connected to the gate of the fourth switching tube is at an off level.

62. The driving method according to claim 49, wherein: The starting time of the transition edge of the second scanning signal connected to the gate of the first switching tube from the on-level to the off-level is after the ending time of the transition edge of the voltage on the data line from the second initialization voltage to the data voltage; or the starting time of the transition edge of the second scanning signal connected to the gate of the first switching tube from the on-level to the off-level is the ending time of the transition edge of the voltage on the data line from the second initialization voltage to the data voltage; The end moment of the transition edge of the second scanning signal connected to the gate of the first switching tube from the on-level to the off-level is before the start moment of the transition edge of the voltage on the data line from the data voltage to the second initialization voltage; or, the end moment of the transition edge of the second scanning signal connected to the gate of the first switching tube from the on-level to the off-level is the start moment of the transition edge of the voltage on the data line from the data voltage to the second initialization voltage.

63. The driving method according to claim 51, wherein: In the bias stage, the start time of the on-level of the third scanning signal connected to the gate of the fourth switching tube is after the second scanning signal connected to the gate of the first switching tube jumps from the on-level to the off-level, and before the light-emitting signal connected to the gate of the third switching tube jumps from the off-level to the on-level.

64. The driving method according to claim 49, wherein: The pixel circuit further includes a first capacitor connected between the first power source and a first end of the second capacitor.

65. A display panel, characterized in that The display panel comprises the pixel circuit according to any one of claims 1 to 48.

66. A display device, characterized in that The display device includes the display panel as claimed in claim 65.

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