Pixel and display device

Abstract

The invention relates to a pixel and a display device. The pixel includes: a light emitting element including a first electrode and a second electrode connected to a third power line, the third power line transmitting a third power voltage; a pulse width modulator controlling an emission duration of the light emitting element in a frame period based on the data voltage; and a constant current generator that supplies a driving current having a constant level to the light emitting element based on a constant current generation voltage applied to the constant current generator, the second driving transistor includes a gate electrode connected to the third node, a first electrode connected to a second power line transmitting a second power voltage, and a second electrode connected to the first electrode of the light emitting element.

Description

Technical Field

[0001] The present invention relates to a pixel and a display device. More particularly, the present invention relates to a pixel driven by a pulse width modulation scheme and a display device including the pixel. Background Art

[0002] The display device may include a plurality of pixels, and each of the plurality of pixels may include a self-luminous element. The self-luminous element may include an organic light emitting diode, a quantum dot light emitting diode, a micro light emitting diode, or the like.

[0003] Generally, an organic light emitting diode may be driven by a pulse amplitude modulation (PAM) scheme that controls the brightness of light emitted from a pixel by controlling the magnitude of a driving current flowing through the organic light emitting diode.

[0004] When the micro-LED is driven by a pulse amplitude modulation scheme, the wavelength of light emitted from the micro-LED can be shifted according to the magnitude of the driving current flowing through the micro-LED. Therefore, the micro-LED can be driven by a pulse width modulation (PWM) scheme that controls the brightness of the light emitted from the pixel by controlling the emission duration of the micro-LED while keeping the magnitude of the driving current flowing through the micro-LED constant. Summary of the invention

[0005] Embodiments provide a pixel including a small number of transistors.

[0006] The embodiment provides a display device with high resolution.

[0007] According to an embodiment, a pixel includes: a light-emitting element including a first electrode and a second electrode connected to a third power line, the third power line transmitting a third power voltage; a pulse width modulator, which controls the emission duration of the light-emitting element in a frame period based on a data voltage; and a constant current generator, which provides a driving current with a constant level to the light-emitting element based on a constant current generating voltage applied to the constant current generator, wherein the constant current generator includes a second driving transistor, the second driving transistor including a gate electrode connected to a third node, a first electrode connected to a second power line transmitting the second power voltage, and a second electrode connected to the first electrode of the light-emitting element.

[0008] In an embodiment, during an emission period in which the light emitting element emits light, the third power voltage may have a low voltage level, and during at least a portion of a non-emission period in which the light emitting element does not emit light, the third power voltage may have a third high voltage level higher than the low voltage level.

[0009] In an embodiment, the second power voltage may have a second high voltage level during the transmission period, and may have a medium voltage level higher than the low voltage level and lower than the second high voltage level during at least a portion of the non-transmission period.

[0010] In an embodiment, a pulse width modulator may include: a first driving transistor including a gate electrode connected to a first node, a first electrode connected to a fourth node, and a second electrode connected to a fifth node; a first write transistor including a gate electrode receiving a scan signal, a first electrode connected to a data line transmitting a data voltage, and a second electrode connected to the fourth node; a first compensation transistor including a gate electrode receiving a scan signal, a first electrode connected to the fifth node, and a second electrode connected to the first node; and a first capacitor including a first electrode receiving a scan signal and a second electrode connected to the first node.

[0011] In an embodiment, the third power voltage has a third high voltage level during a cutoff period in which the light emitting element is cut off, a first initialization period in which the gate electrode of the second driving transistor is initialized, a second initialization period in which the gate electrode of the first driving transistor is initialized, a compensation period in which the threshold voltage of the second driving transistor is compensated, a first writing period in which a data voltage in which the threshold voltage of the first driving transistor is compensated is written to the gate electrode of the first driving transistor, and a second writing period in which a constant current generating voltage is written to the gate electrode of the second driving transistor, and in an emission period in which the light emitting element emits light, the third power voltage may have a low voltage level lower than the third high voltage level.

[0012] In an embodiment, in the first initialization period, the compensation period, the first write period, the second write period and the emission period, the second power voltage may have a second high voltage level, and in the cutoff period and the second initialization period, the second power voltage may have a medium voltage level lower than the second high voltage level and higher than the low voltage level.

[0013] In an embodiment, the pulse width modulator may further include: a first emission control transistor, including a gate electrode receiving an emission control signal, a first electrode connected to a first power line transmitting a first power voltage, and a second electrode connected to a fourth node; and a second emission control transistor, including a gate electrode receiving an emission control signal, a first electrode connected to a fifth node, and a second electrode connected to a third node.

[0014] In an embodiment, the pulse width modulator may further include an initialization transistor including a gate electrode receiving a first initialization gate signal, a first electrode receiving an initialization voltage, and a second electrode connected to the first node.

[0015] In an embodiment, each of the first write transistor, the first compensation transistor, and the initialization transistor may be an N-type transistor.

[0016] In an embodiment, the constant current generator may further include a second capacitor including a first electrode connected to the third node and a second electrode connected to the second power line.

[0017] In an embodiment, the constant current generator may further include: a second write transistor, including a gate electrode receiving a write gate signal, a first electrode connected to a data line transmitting a constant current generating voltage, and a second electrode connected to a second node; a second compensation transistor, including a gate electrode receiving a compensation gate signal, a first electrode connected to the second electrode of the second drive transistor, and a second electrode connected to a third node; and a third capacitor, including a first electrode connected to the second node and a second electrode connected to the third node.

[0018] In an embodiment, the second compensation transistor may be an N-type transistor.

[0019] In an embodiment, the constant current generator may further include a bypass transistor including a gate electrode receiving the second initialization gate signal, a first electrode connected to the first electrode of the light emitting element, and a second electrode connected to the second electrode of the light emitting element.

[0020] In an embodiment, the light emitting element may be a micro light emitting diode.

[0021] The display device according to the embodiment includes: a display panel including a plurality of pixels; a scan driver sequentially providing a plurality of scan signals to the plurality of pixels; and a data driver providing a data voltage and a constant current generating voltage to each of the plurality of pixels. In such an embodiment, each of the plurality of pixels may include: a light emitting element including a first electrode and a second electrode connected to a third power line, the third power line transmitting a third power voltage; a pulse width modulator controlling the emission duration of the light emitting element in a frame period based on the data voltage; and a constant current generator providing a driving current having a constant level to the light emitting element based on the constant current generating voltage, wherein the constant current generator includes a second driving transistor, the second driving transistor including a gate electrode connected to a third node, a first electrode connected to a second power line transmitting a second power voltage, and a second electrode connected to the first electrode of the light emitting element.

[0022] In an embodiment, during an emission period in which the light emitting element emits light, the third power voltage may have a low voltage level, and during at least a portion of a non-emission period in which the light emitting element does not emit light, the third power voltage may have a third high voltage level higher than the low voltage level.

[0023] In an embodiment, the second power voltage may have a second high voltage level during the transmission period, and a medium voltage level higher than the low voltage level and lower than the second high voltage level during at least a portion of the non-transmission period.

[0024] In an embodiment, the pulse width modulator may include: a first driving transistor including a gate electrode connected to a first node, a first electrode connected to a fourth node, and a second electrode connected to a fifth node; a first write transistor including a gate electrode receiving a scan signal among a plurality of scan signals, a first electrode connected to a data line transmitting a data voltage and a constant current generating voltage, and a second electrode connected to the fourth node; a first compensation transistor including a gate electrode receiving a scan signal, a first electrode connected to a fifth node, and a second electrode connected to the first node; a first emission control transistor including a gate electrode receiving an emission control signal, a first electrode connected to a first power line transmitting a first power voltage, and a second electrode connected to the fourth node; a second emission control transistor including a gate electrode receiving an emission control signal, a first electrode connected to the fifth node, and a second electrode connected to the third node; an initialization transistor including a gate electrode receiving a first initialization gate signal, a first electrode receiving an initialization voltage, and a second electrode connected to the first node; and a first capacitor including a first electrode receiving a sweep signal and a second electrode connected to the first node.

[0025] In an embodiment, the constant current generator may further include: a second write transistor, including a gate electrode receiving a write gate signal, a first electrode connected to a data line, and a second electrode connected to a second node; a second compensation transistor, including a gate electrode receiving a compensation gate signal, a first electrode connected to the second electrode of the second drive transistor, and a second electrode connected to a third node; a bypass transistor, including a gate electrode receiving a second initialization gate signal, a first electrode connected to the first electrode of the light-emitting element, and a second electrode connected to the second electrode of the light-emitting element; a second capacitor, including a first electrode connected to the third node, and a second electrode connected to the second power line; and a third capacitor, including a first electrode connected to the second node, and a second electrode connected to the third node.

[0026] In an embodiment, the display device may further include a power manager that commonly provides a first power voltage, a second power voltage, a third power voltage, an initialization voltage, an emission control signal, a first initialization gate signal, a second initialization gate signal, a sweep signal, a write gate signal, and a compensation gate signal to multiple pixels.

[0027] The constant current generator of the pixel according to the embodiment may not include an emission control transistor turned on in response to an emission control signal, so that the number of transistors included in the pixel may be reduced.

[0028] The display device according to the embodiment may include pixels having a small number of transistors, so that the resolution of the display device may be improved. BRIEF DESCRIPTION OF THE DRAWINGS

[0029] Illustrative, non-limiting embodiments will be more clearly understood from the following detailed description taken in conjunction with the accompanying drawings.

[0030] Figure 1 is a block diagram illustrating a display device according to an embodiment of the present disclosure.

[0031] Figure 2 It is shown that the Figure 1 A circuit diagram of an example of a pixel in a display device.

[0032] Figure 3 is shown to include Figure 1 FIG. 1 is a view of an example of signals and voltages for pixels in a display device. FIG.

[0033] Figures 4 to 12 It is shown Figure 2 Graph of pixel operations.

[0034] Fig.13 It is shown that the Figure 1 A circuit diagram of another example of a pixel in a display device.

[0035] Fig.14 is shown to include Figure 1 FIG. 1 is a view of another example of signals and voltages for pixels in a display device.

[0036] Fig.15 is a block diagram illustrating a display device according to an embodiment of the present disclosure.

[0037] Fig.16 It is shown that the Fig.15 A circuit diagram of a pixel in a display device.

[0038] Fig.17 is shown to include Fig.15 A view of the signals and voltages for pixels in a display device.

[0039] Fig.18 is a block diagram illustrating an electronic device according to an embodiment of the present disclosure.

[0040] Fig.19 It shows that Fig.18A view of an example in which the electronic device is implemented as a smart watch. DETAILED DESCRIPTION

[0041] The present disclosure will now be described more fully below with reference to the accompanying drawings, in which embodiments are shown. However, the present disclosure may be embodied in different forms and should not be construed as being limited to the embodiments set forth herein. Instead, these embodiments are provided so that the present disclosure will be thorough and complete and will fully convey the scope of the present disclosure to those skilled in the art. The same reference numerals represent the same elements throughout.

[0042] It will be understood that when an element is referred to as being “on” another element, the element can be directly on the other element or intervening elements may be present therebetween. In contrast, when an element is referred to as being “directly on” another element, there are no intervening elements present.

[0043] It will be understood that, although the terms "first", "second", "third", etc. can be used to describe various elements, components, regions, layers and / or parts in this article, these elements, components, regions, layers and / or parts should not be limited by these terms. These terms are only used to distinguish one element, component, region, layer or part from another element, component, region, layer or part. Therefore, without departing from the teachings of this article, the "first element", "first component", "first region", "first layer" or "first part" discussed below can be referred to as "second element", "second component", "second region", "second layer" or "second part".

[0044] The terms used herein are only used to describe the purpose of a particular embodiment, rather than being intended to limit. As used herein, unless the context clearly indicates otherwise, "one", "a kind of", "said (the)" and "at least one (kind)" do not represent the limitation of quantity, and are intended to include both singular and plural. Therefore, the "one" element mentioned in the claim as "said (the)" element thereafter includes one element and multiple elements. For example, unless the context clearly indicates otherwise, "element" has the same meaning as "at least one element". "At least one" should not be interpreted as limiting "one" or "a kind". "Or" means "and / or". As used herein, the term "and / or" includes any combination and all combinations of one or more related listed items. It will be further understood that, when used in this specification, the term "includes" and / or "comprising" or "containing" and / or "having" indicates the existence of stated features, regions, wholes, steps, operations, elements and / or components, but does not exclude the existence or addition of one or more other features, regions, wholes, steps, operations, elements, components and / or their groups.

[0045] In addition, relative terms such as "lower" or "bottom" and "upper" or "top" may be used herein to describe the relationship of one element to another element as shown in the drawings. It will be understood that relative terms are intended to cover different orientations of the device in addition to the orientation depicted in the drawings. For example, if the device is turned over in one drawing, the element described as being on the "lower" side of the other elements will subsequently be positioned on the "upper" side of the other elements. Therefore, depending on the specific orientation of the drawings, the exemplary term "lower" can cover both "lower" and "upper" orientations. Similarly, if the device is turned over in one drawing, the element described as being "below" or "below" the other elements will subsequently be positioned "above" the other elements. Therefore, the terms "below..." or "below..." can cover both upper and lower orientations.

[0046] As used herein, "about" or "approximately" is inclusive of the stated value and means within an acceptable range of deviation of the particular value determined by one of ordinary skill in the art, taking into account the measurement in question and the errors associated with the measurement of the particular quantity (i.e., the limitations of the measurement system). For example, "about" can mean within one or more standard deviations, or within ±30%, ±20%, ±10%, or ±5% of the stated value.

[0047] Unless otherwise defined, all terms (including technical and scientific terms) used herein have the same meaning as commonly understood by those of ordinary skill in the art to which the present disclosure belongs. It will also be understood that, unless explicitly defined as such herein, terms (such as those defined in general dictionaries) should be interpreted as having a meaning consistent with their meaning in the context of the relevant art, and will not be interpreted in an idealized or overly formal sense.

[0048] Hereinafter, a pixel and a display device according to embodiments of the present disclosure will be described in more detail with reference to the accompanying drawings.

[0049] Figure 1 is a block diagram illustrating a display device 100 according to an embodiment of the present disclosure.

[0050] Reference Figure 1 , an embodiment of the display device 100 may include a display panel 110 , a scan driver 120 , a data driver 130 , a power manager 140 , and a controller 150 .

[0051] The display panel 110 may include pixels PX. According to an embodiment, the pixels PX may include a first pixel configured to emit light having a first color, a second pixel configured to emit light having a second color, and a third pixel configured to emit light having a third color. In an embodiment, for example, the first color, the second color, and the third color may be red, green, and blue, respectively.

[0052] The scan driver 120 may sequentially provide the first to nth scan signals GC_PWM[1] to GC_PWM[n] (where n is a natural number greater than or equal to 2) to the pixels PX. The scan driver 120 may sequentially generate the first to nth scan signals GC_PWM[1] to GC_PWM[n] corresponding to the first to nth pixel rows, respectively, based on the first control signal CNT1. The first control signal CNT1 may include a scan clock signal or a scan start signal, etc.

[0053] The data driver 130 may provide a data signal DS to the pixel PX. The data signal DS may include a reference voltage VREF, a data voltage VDAT, and a constant current generating voltage VCCG. The data driver 130 may generate first to m-th data signals DS corresponding to the first to m-th pixel columns, respectively, based on the second image data IMD2 and the second control signal CNT2 (wherein m is a natural number greater than or equal to 2). According to an embodiment, the second image data IMD2 may include grayscale values ​​corresponding to the pixels PX, respectively. The second control signal CNT2 may include a data clock signal, a horizontal start signal, a load signal, or the like.

[0054] In an embodiment, the power manager 140 may provide the first power voltage VDD1, the second power voltage VDD2, the third power voltage VSS, the initialization voltage VINT, the emission control signal EM, the first initialization gate signal GI1, the second initialization gate signal GI2, the sweep signal SWP, the write gate signal GW, and the compensation gate signal SCCG to the pixels PX in common. The power manager 140 may change the voltage level of each of the first power voltage VDD1, the second power voltage VDD2, the third power voltage VSS, the initialization voltage VINT, the emission control signal EM, the first initialization gate signal GI1, the second initialization gate signal GI2, the sweep signal SWP, the write gate signal GW, and the compensation gate signal SCCG based on the third control signal CNT3.

[0055] The controller 150 may control the operation (or driving) of the scan driver 120, the operation (or driving) of the data driver 130, and the operation (or driving) of the power manager 140. The controller 150 may generate a first control signal CNT1, a second image data IMD2, a second control signal CNT2, and a third control signal CNT3 based on the first image data IMD1 and the control signal CNT. According to an embodiment, the first image data IMD1 may include grayscale values ​​corresponding to the pixels PX, respectively. The controller 150 may convert the first image data IMD1 into the second image data IMD2. The control signal CNT may include a main clock signal, a vertical synchronization signal, a horizontal synchronization signal, a data enable signal, or the like.

[0056] Figure 2 It is shown that the Figure 1 1 is a circuit diagram of an example of a pixel PX (eg, pixel PX[k]) in the display device 100 . Figure 2 Pixels PX[k] included in a k-th pixel row may be shown (where k is a natural number greater than or equal to 1 and less than or equal to n).

[0057] Reference Figure 1 and Figure 2 , an embodiment of the pixel PX[k] may include a light emitting element LED, a pulse width modulator (or pulse width modulation circuit) PWM, and a constant current generator (or constant current generating circuit) CCG. The light emitting element LED may emit light based on the driving current ILED. The light emitting element LED may include a first electrode and a second electrode connected to a third power line PL3 transmitting a third power voltage VSS.

[0058] According to an embodiment, the light emitting element LED may be a micro light emitting diode. A micro light emitting diode may refer to an ultra-small light emitting diode having a size of about 100 micrometers (μm) or less. According to another embodiment, the light emitting element LED may be an organic light emitting diode (OLED). According to yet another embodiment, the light emitting element LED may be a nano light emitting diode (NED), a quantum dot light emitting diode, an inorganic light emitting diode, or the like.

[0059] The pulse width modulator PWM can control the emission duration of the light emitting element LED in the frame period based on the data voltage VDAT. The pulse width modulator PWM may include a first driving transistor T1 (hereinafter referred to as "first transistor T1"), a first writing transistor T2 (hereinafter referred to as "second transistor T2"), a first compensation transistor T3 (hereinafter referred to as "third transistor T3"), a first emission control transistor T4 (hereinafter referred to as "fourth transistor T4"), a second emission control transistor T5 (hereinafter referred to as "fifth transistor T5"), an initialization transistor T6 (hereinafter referred to as "sixth transistor T6") and a first capacitor C1.

[0060] The constant current generator CCG can provide a driving current ILED having a constant level to the light emitting element LED based on the constant current generating voltage VCCG. The constant current generator CCG can include a second driving transistor T7 (hereinafter referred to as "seventh transistor T7"), a second writing transistor T8 (hereinafter referred to as "eighth transistor T8"), a second compensation transistor T9 (hereinafter referred to as "ninth transistor T9"), a bypass transistor T10 (hereinafter referred to as "tenth transistor T10"), a second capacitor C2, and a third capacitor C3.

[0061] In an embodiment, Figure 2 As shown in , the first transistor T1 may include a gate electrode connected to the first node A, a first electrode connected to the fourth node D, and a second electrode connected to the fifth node E. The first transistor T1 may be turned on based on a voltage difference between the fourth node D and the first node A.

[0062] The second transistor T2 may include a gate electrode receiving a scan signal GC_PWM[k] corresponding to the pixel PX[k], a first electrode connected to a data line DL transmitting a data signal DS, and a second electrode connected to a fourth node D. The second transistor T2 may transmit a data voltage VDAT to the fourth node D in response to the scan signal GC_PWM[k] having a turn-on level (e.g., a high voltage level).

[0063] The third transistor T3 may include a gate electrode receiving the scan signal GC_PWM[k], a first electrode connected to the fifth node E, and a second electrode connected to the first node A. The third transistor T3 may connect the fifth node E to the first node A in response to the scan signal GC_PWM[k] having a high voltage level. In an embodiment, the third transistor T3 may diode-connect the first transistor T1 in response to the scan signal GC_PWM[k] having a turn-on level (e.g., a high voltage level).

[0064] The fourth transistor T4 may include a gate electrode receiving the emission control signal EM, a first electrode connected to the first power line PL1 transmitting the first power voltage VDD1, and a second electrode connected to the fourth node D. The fourth transistor T4 may transmit the first power voltage VDD1 to the fourth node D in response to the emission control signal EM having a turn-on level (e.g., a low voltage level lower than the high voltage level).

[0065] The fifth transistor T5 may include a first electrode connected to the fifth node E, a gate electrode receiving the emission control signal EM, and a second electrode connected to the third node C. The fifth transistor T5 may connect the fifth node E to the third node C in response to the emission control signal EM having a turn-on level (e.g., a low voltage level).

[0066] The sixth transistor T6 may include a gate electrode receiving the first initialization gate signal GI1, a first electrode receiving the initialization voltage VINT, and a second electrode connected to the first node A. The sixth transistor T6 may transmit the initialization voltage VINT to the first node A in response to the first initialization gate signal GI1 having a turn-on level (e.g., a high voltage level).

[0067] The seventh transistor T7 may include a gate electrode connected to the third node C, a first electrode connected to the second power line PL2 transmitting the second power voltage VDD2, and a second electrode connected to the first electrode of the light emitting element LED. The seventh transistor T7 may generate a driving current ILED corresponding to the difference between the second power voltage VDD2 and the voltage of the third node C.

[0068] In an embodiment, the first electrode of the seventh transistor T7 may be directly connected to the second power line PL2. In such an embodiment, another component (eg, transistor) may not be provided between the first electrode of the seventh transistor T7 and the second power line PL2.

[0069] In an embodiment, the second electrode of the seventh transistor T7 may be directly connected to the first electrode of the light emitting element LED. In such an embodiment, another component (eg, transistor) may not be provided between the second electrode of the seventh transistor T7 and the first electrode of the light emitting element LED.

[0070] The eighth transistor T8 may include a gate electrode receiving the write gate signal GW, a first electrode connected to the data line DL, and a second electrode connected to the second node B. The eighth transistor T8 may transmit the reference voltage VREF and the constant current generating voltage VCCG to the second node B in response to the write gate signal GW having a turn-on level (e.g., a low voltage level).

[0071] The ninth transistor T9 may include a gate electrode receiving the compensation gate signal SCCG, a first electrode connected to the second electrode of the seventh transistor T7, and a second electrode connected to the third node C. The ninth transistor T9 may connect the second electrode of the seventh transistor T7 to the third node C in response to the compensation gate signal SCCG having a turn-on level (e.g., a high voltage level). In such an embodiment, the ninth transistor T9 may diode-connect the seventh transistor T7 in response to the compensation gate signal SCCG having a turn-on level (e.g., a high voltage level).

[0072] The tenth transistor T10 may include a gate electrode receiving the second initialization gate signal GI2, a first electrode connected to the first electrode of the light emitting element LED, and a second electrode connected to the second electrode of the light emitting element LED. The tenth transistor T10 may transmit the third power voltage VSS to the first electrode of the light emitting element LED in response to the second initialization gate signal GI2 having a turn-on level (e.g., a low voltage level).

[0073] According to an embodiment, each of the first transistor T1, the fourth transistor T4, the fifth transistor T5, the seventh transistor T7, the eighth transistor T8, and the tenth transistor T10 may be a P-type transistor (e.g., a P-channel metal oxide semiconductor (PMOS) transistor), and each of the second transistor T2, the third transistor T3, the sixth transistor T6, and the ninth transistor T9 may be an N-type transistor (e.g., an N-channel metal oxide semiconductor (NMOS) transistor). According to an embodiment, each of the first transistor T1, the fourth transistor T4, the fifth transistor T5, the seventh transistor T7, the eighth transistor T8, and the tenth transistor T10 may be a polysilicon transistor, and each of the second transistor T2, the third transistor T3, the sixth transistor T6, and the ninth transistor T9 may be an oxide semiconductor transistor.

[0074] The first capacitor C1 may include a first electrode receiving the sweep signal SWP and a second electrode connected to the first node A. The first capacitor C1 may store a voltage of the first node A.

[0075] The second capacitor C2 may include a first electrode connected to the third node C and a second electrode connected to the second power line PL2. The second capacitor C2 may store a voltage of the third node C.

[0076] The third capacitor C3 may include a first electrode connected to the second node B and a second electrode connected to the third node C. The third capacitor C3 may store a voltage difference between the second node B and the third node C.

[0077] Figure 3 is shown to include Figure 1FIG. 1 is a diagram showing an example of signals and voltages of a pixel PX in the display device 100. FIG.

[0078] Reference Figures 1 to 3 , the frame period FRM of the display device 100 may include a cut-off period P1 (hereinafter referred to as “first period P1”) in which the light emitting element LED is cut off, a first initialization period P2 (hereinafter referred to as “second period P2”) in which the gate electrode of the seventh transistor T7 is initialized, a second initialization period P3 (hereinafter referred to as “third period P3”) in which the gate electrode of the first transistor T1 is initialized, a compensation period P4 (hereinafter referred to as “fourth period P4”) in which the threshold voltage of the seventh transistor T7 is compensated, a first writing period P5 (hereinafter referred to as “fifth period P5”) in which the data voltage VDAT in which the threshold voltage of the first transistor T1 is compensated is written to the gate electrode of the first transistor T1, a second writing period P6 (hereinafter referred to as “sixth period P6”) in which the constant current generating voltage VCCG is written to the gate electrode of the seventh transistor T7, an emission period P7 (hereinafter referred to as “seventh period P7”) in which the light emitting element LED emits light, and a bypass period P8 (hereinafter referred to as “eighth period P8”) in which the light emitting element LED displays black. The seventh period P7 may include a first seventh period P7-1 in which a driving current ILED having a constant level flows through the light emitting element LED, and a second seventh period P7-2 in which the driving current ILED does not flow through the light emitting element LED. Periods P1 to P6 and P8 other than the emission period P7 in the frame period FRM may be non-emission periods.

[0079] The first power voltage VDD1, the second power voltage VDD2, the third power voltage VSS, the initialization voltage VINT, the first initialization gate signal GI1, the write gate signal GW, the compensation gate signal SCCG, the second initialization gate signal GI2, the emission control signal EM and the sweep signal SWP may be commonly provided to the pixel PX. According to an embodiment, the first power voltage VDD1, the second power voltage VDD2, the third power voltage VSS, the initialization voltage VINT, the first initialization gate signal GI1, the write gate signal GW, the compensation gate signal SCCG, the second initialization gate signal GI2, the emission control signal EM and the sweep signal SWP may be substantially simultaneously applied to at least two pixel rows, for example, the first pixel row to the nth pixel row. The scan signals GC_PWM[1], ..., GC_PWM[k], ... and GC_PWM[n] may be sequentially provided to the pixel PX based on the pixel row.

[0080] The first power voltage VDD1 may have a first high voltage level VDD1_H in the first to eighth periods P1 to P8 .

[0081] The second power voltage VDD2 may have a second high voltage level VDD2_H in the emission period P7, and have a medium voltage level VDD2_M that is lower than the second high voltage level VDD2_H and higher than the low voltage level VSS_L of the third power voltage VSS in at least a portion of the non-emission period. According to an embodiment, the second power voltage VDD2 may have a second high voltage level VDD2_H in the second period P2 and the fourth to eighth periods P4 to P8, and have a medium voltage level VDD2_M in the first period P1 and the third period P3.

[0082] The third power voltage VSS may have a low voltage level VSS_L in the emission period P7, and a third high voltage level VSS_H in at least a portion of the non-emission period. According to an embodiment, the third power voltage VSS may have a low voltage level VSS_L in the seventh period P7 and the eighth period P8, and have a third high voltage level VSS_H in the first period P1 to the sixth period P6.

[0083] According to an embodiment, the first high voltage level VDD1_H, the second high voltage level VDD2_H, and the third high voltage level VSS_H may be equal to or different from each other.

[0084] The data signal DS may have the reference voltage VREF in the first to fourth periods P1 to P4, the seventh period P7, and the eighth period P8, the data voltage VDAT in the fifth period P5, and the constant current generating voltage VCCG in the sixth period P6. The voltage level of the constant current generating voltage VCCG may be lower than the voltage level of the reference voltage VREF.

[0085] Each of the scanning signals GC_PWM[1], ..., GC_PWM[k], ..., and GC_PWM[n] may have a low voltage level L in the first to fourth periods P1 to P4 and the sixth to eighth periods P6 to P8, and have a high voltage level H in the fifth period P5. The scanning signals GC_PWM[1], ..., GC_PWM[k], ..., and GC_PWM[n] may be sequentially shifted by a predetermined period (e.g., one horizontal period).

[0086] The initialization voltage VINT may have a low voltage level L in the first to fourth periods P1 to P4, and a high voltage level H in the fifth to eighth periods P5 to P8. The first initialization gate signal GI1 may have a low voltage level L in the first, second, and fourth to eighth periods P4 to P8, and a high voltage level H in the third period P3. The write gate signal GW may have a high voltage level H in the first, third, and sixth periods P8, and a low voltage level L in the second, fourth, and sixth periods P6. The compensation gate signal SCCG may have a low voltage level L in the first to third periods P1 to P3 and fifth to eighth periods P5 to P8, and a high voltage level H in the fourth period P4. The second initialization gate signal GI2 may have a low voltage level L in the first and eighth periods P1 to P8, and a high voltage level H in the second to seventh periods P2 to P7. The emission control signal EM may have a high voltage level H in the first to sixth periods P1 to P6, and have a low voltage level L in the seventh and eighth periods P7 and P8. The sweep signal SWP may have a high voltage level H in the first to sixth periods P1 to P6, have a voltage linearly decreasing from the high voltage level H to the low voltage level L in the seventh period P7, and have a low voltage level L in the eighth period P8.

[0087] According to an embodiment, a high voltage level H of each of the scanning signals GC_PWM[1], ..., GC_PWM[k], ..., and GC_PWM[n], a high voltage level H of the initialization voltage VINT, a high voltage level H of the first initialization gate signal GI1, a high voltage level H of the write gate signal GW, a high voltage level H of the compensation gate signal SCCG, a high voltage level H of the second initialization gate signal GI2, a high voltage level H of the emission control signal EM, and a high voltage level H of the sweep signal SWP may be equal to or different from each other. According to an embodiment, a low voltage level L of each of the scanning signals GC_PWM[1], ..., GC_PWM[k], ..., and GC_PWM[n], a low voltage level L of the initialization voltage VINT, a low voltage level L of the first initialization gate signal GI1, a low voltage level L of the write gate signal GW, a low voltage level L of the compensation gate signal SCCG, a low voltage level L of the second initialization gate signal GI2, a low voltage level L of the emission control signal EM, and a low voltage level L of the sweep signal SWP may be equal to or different from each other.

[0088] Figures 4 to 12 It is shown Figure 2 Graph of the operation on pixel PX[k].

[0089] Reference Figure 3 and Figure 4 , in the first period P1, the second power voltage VDD2 may be converted from the second high voltage level VDD2_H to the middle voltage level VDD2_M, and the third power voltage VSS may be converted from the low voltage level VSS_L to the third high voltage level VSS_H. Therefore, the voltage level of the first electrode of the light emitting element LED may be lower than the voltage level of the second electrode of the light emitting element LED, and the light emitting element LED may be turned off.

[0090] Reference Figure 3 and Figure 5 , in the second period P2, the second power voltage VDD2 may be converted from the medium voltage level VDD2_M to the second high voltage level VDD2_H, and the write gate signal GW may be converted from the high voltage level H to the low voltage level L. Therefore, the eighth transistor T8 may be turned on, so that the reference voltage VREF may be applied to the second node B. The voltage of the third node C may change in response to the change in the second power voltage VDD2 and the voltage change of the second node B caused by the coupling effect of the second capacitor C2 and the third capacitor C3. Therefore, the gate electrode of the seventh transistor T7 may be initialized, and the seventh transistor T7 may be turned on.

[0091] Reference Figure 3 and Figure 6 , in the third period P3, the first initialization gate signal GI1 may be converted from the low voltage level L to the high voltage level H. Therefore, the sixth transistor T6 may be turned on, so that the initialization voltage VINT may be applied to the first node A, the gate electrode of the first transistor T1 may be initialized, and the first transistor T1 may be turned on. In addition, the second power voltage VDD2 may be converted from the second high voltage level VDD2_H to the middle voltage level VDD2_M, and the second power voltage VDD2 having the middle voltage level VDD2_M may be applied to the first electrode of the light emitting element LED through the seventh transistor T7.

[0092] Reference Figure 3 and Figure 7 , in the fourth period P4, the second power voltage VDD2 may be converted from the middle voltage level VDD2_M to the second high voltage level VDD2_H, and the compensation gate signal SCCG may be converted from the low voltage level L to the high voltage level H. Therefore, the ninth transistor T9 is turned on, so that the difference between the second power voltage VDD2 and the threshold voltage Vth2 of the seventh transistor T7 may be applied to the third node C through the seventh transistor T7 and the ninth transistor T9. In the fourth period P4, the write gate signal GW may be converted from the high voltage level H to the low voltage level L. Therefore, the eighth transistor T8 may be turned on, so that the reference voltage VREF may be applied to the second node B.

[0093] Reference Figure 3 and Figure 8 , in the fifth period P5, the scan signal GC_PWM[k] may be converted from the low voltage level L to the high voltage level H, and the data signal DS may have the data voltage VDAT. Therefore, the second transistor T2 and the third transistor T3 may be turned on, so that the difference between the data voltage VDAT and the threshold voltage Vth1 of the first transistor T1 may be applied to the first node A through the second transistor T2, the first transistor T1, and the third transistor T3.

[0094] Reference Figure 3 and Fig. 9 , in the sixth period P6, the write gate signal GW may be converted from the high voltage level H to the low voltage level L, and the data signal DS may have the constant current generating voltage VCCG. Therefore, the eighth transistor T8 may be turned on so that the constant current generating voltage VCCG may be applied to the second node B. The voltage of the third node C may change in response to the change (VCCG-VREF) of the voltage of the second node B caused by the coupling effect of the third capacitor C3.

[0095] Reference Figure 3 and Fig.10 , in the first seventh period P7-1, the seventh transistor T7 may generate a driving current ILED having a constant level corresponding to the voltage difference between the first electrode and the gate electrode of the seventh transistor T7 (i.e., the difference between the second power voltage VDD2 and the voltage of the third node C), and the light emitting element LED may emit light having a brightness corresponding to the driving current ILED. In the seventh period P7, the sweep signal SWP may be linearly reduced from the high voltage level H to the low voltage level L, and the emission control signal EM may be converted from the high voltage level H to the low voltage level L. Therefore, the voltage of the first node A may be reduced in response to the reduction of the sweep signal SWP caused by the coupling effect of the first capacitor C1, and the first power voltage VDD1 may be applied to the fourth node D. In the first seventh period P7-1, even when the voltage of the first node A is reduced, the voltage difference Vsg between the first electrode and the gate electrode of the first transistor T1 (i.e., the difference between the first power voltage VDD1 and the voltage of the first node A) may be less than the threshold voltage Vth1 of the first transistor T1, so that the first transistor T1 may be turned off. In other words, in the first seventh period P7 - 1 , since the voltage difference Vsg between the first electrode and the gate electrode of the first transistor T1 is less than the threshold voltage Vth1 of the first transistor T1 , the first transistor T1 may be turned off.

[0096] Reference Figure 3 and Fig.11, in the second seventh period P7-2, since the sweep signal SWP decreases linearly through the coupling effect of the first capacitor C1, the voltage of the first node A may be continuously reduced. Therefore, in the second seventh period P7-2, the voltage difference Vsg between the first electrode and the gate electrode of the first transistor T1 (i.e., the difference between the first power voltage VDD1 and the voltage of the first node A) may be greater than the threshold voltage Vth1 of the first transistor T1, and the first transistor T1 may be turned on. In other words, in the second seventh period P7-2, since the voltage difference Vsg between the first electrode and the gate electrode of the first transistor T1 is greater than the threshold voltage Vth1 of the first transistor T1, the first transistor T1 may be turned on. Therefore, the first power voltage VDD1 having the first high voltage level VDD1_H may be applied to the third node C through the fourth transistor T4, the first transistor T1, and the fifth transistor T5, and the seventh transistor T7 may be turned off. Therefore, the seventh transistor T7 may stop generating the drive current ILED, and the light emitting element LED may not emit light. In the seventh period P7, the driving current ILED corresponding to the constant current generating voltage VCCG may flow through the light emitting element LED for a time corresponding to the data voltage VDAT, and the light emitting element LED may emit light having a brightness corresponding to the constant current generating voltage VCCG for a time corresponding to the data voltage VDAT. Therefore, the brightness of the light emitted from the light emitting element LED may correspond to the emission duration of the light emitting element LED.

[0097] Reference Figure 3 and Fig.12 , in the eighth period P8, the second initialization gate signal GI2 may be converted from the high voltage level H to the low voltage level L. Therefore, the tenth transistor T10 may be turned on, so that the charge charged in the first electrode of the light emitting element LED by the parasitic capacitor of the light emitting element LED may be discharged to the third power line PL3 through the tenth transistor T10, and the display of black of the light emitting element LED may be improved.

[0098] Fig.13 It is shown that the Figure 1 1 is a circuit diagram of another example of a pixel PX (eg, pixel PX[k]) in the display device 100 .

[0099] Reference Figure 1 and Fig.13 , an embodiment of the pixel PX[k] may include a light emitting element LED, a pulse width modulator PWM and a constant current generator CCG. Fig.13 In the description of another example of the pixel PX[k], the reference to the above reference will be omitted. Figure 2 Any repeated detailed description of components of the described pixel PX[k] is substantially the same or similar components.

[0100] The second transistor T2 may include a gate electrode receiving a scan signal GC_PWM[k] corresponding to the pixel PX[k], a first electrode connected to a data line DL transmitting a data signal DS, and a second electrode connected to a fourth node D. The second transistor T2 may transmit the data voltage VDAT to the fourth node D in response to the scan signal GC_PWM[k] having a low voltage level.

[0101] The third transistor T3 may include a gate electrode receiving the scan signal GC_PWM[k], a first electrode connected to the fifth node E, and a second electrode connected to the first node A. The third transistor T3 may connect the fifth node E to the first node A in response to the scan signal GC_PWM[k] having a low voltage level.

[0102] The sixth transistor T6 may include a gate electrode receiving the first initialization gate signal GI1, a first electrode receiving the initialization voltage VINT, and a second electrode connected to the first node A. The sixth transistor T6 may transmit the initialization voltage VINT to the first node A in response to the first initialization gate signal GI1 having a low voltage level.

[0103] The ninth transistor T9 may include a gate electrode receiving the compensation gate signal SCCG, a first electrode connected to the second electrode of the seventh transistor T7, and a second electrode connected to the third node C. The ninth transistor T9 may connect the second electrode of the seventh transistor T7 to the third node C in response to the compensation gate signal SCCG having a low voltage level.

[0104] According to an embodiment, each of the first transistor T1, the second transistor T2, the third transistor T3, the fourth transistor T4, the fifth transistor T5, the sixth transistor T6, the seventh transistor T7, the eighth transistor T8, the ninth transistor T9 and the tenth transistor T10 may be a P-type transistor (e.g., a PMOS transistor). According to an embodiment, each of the first transistor T1, the second transistor T2, the third transistor T3, the fourth transistor T4, the fifth transistor T5, the sixth transistor T6, the seventh transistor T7, the eighth transistor T8, the ninth transistor T9 and the tenth transistor T10 may be a polysilicon transistor.

[0105] Fig.14 is shown to include Figure 1 FIG. 1 is a diagram of another example of signals and voltages for a pixel PX in the display device 100 .

[0106] In reference Fig.14 In the description of another example of the signal and the voltage, the reference Figure 3Any repeated description of the components of the signals and voltages described are substantially the same or similar components.

[0107] Reference Figure 1 , Fig.13 and Fig.14 In an embodiment, each of the scan signals GC_PWM[1], ..., GC_PWM[k], ..., and GC_PWM[n] may have a high voltage level H in the first to fourth periods P1 to P4 and the sixth to eighth periods P6 to P8, and have a low voltage level L in the fifth period P5. The scan signals GC_PWM[1], ..., GC_PWM[k], ..., and GC_PWM[n] may be sequentially shifted by a predetermined time (e.g., one horizontal time).

[0108] The first initialization gate signal GI1 may have a high voltage level H in the first period P1, the second period P2, and the fourth to eighth periods P4 to P8, and have a low voltage level L in the third period P3. The compensation gate signal SCCG may have a high voltage level H in the first to third periods P1 to P3 and the fifth to eighth periods P5 to P8, and have a low voltage level L in the fourth period P4.

[0109] Fig.15 is a block diagram showing a display device 101 according to an embodiment of the present disclosure.

[0110] Reference Fig.15 , an embodiment of the display device 101 may include a display panel 110, a scan driver 121, a data driver 130, a power manager 141, and a controller 150. Fig.15 In the description of the embodiment of the display device 101 shown in FIG. 1 , the above reference numerals will be omitted. Figure 1 Any repeated detailed description of components of the described display device 100 that are substantially the same or similar components.

[0111] The scan driver 121 may sequentially provide the first to nth scan signals GC_PWM[1] to GC_PWM[n], the first to nth write gate signals GW[1] to GW[n], and the first to nth compensation gate signals SCCG[1] to SCCG[n] to the pixels PX. The scan driver 121 may sequentially generate the first to nth scan signals GC_PWM[1] to GC_PWM[n], the first to nth write gate signals GW[1] to GW[n], and the first to nth compensation gate signals SCCG[1] to SCCG[n] corresponding to the first to nth pixel rows, respectively, based on the first control signal CNT1.

[0112] The power manager 141 may commonly provide the pixels PX with a first power voltage VDD1, a second power voltage VDD2, a third power voltage VSS, an initialization voltage VINT, an emission control signal EM, a first initialization gate signal GI1, a second initialization gate signal GI2, and a sweep signal SWP. The power manager 141 may change a voltage level of each of the first power voltage VDD1, the second power voltage VDD2, the third power voltage VSS, the initialization voltage VINT, the emission control signal EM, the first initialization gate signal GI1, the second initialization gate signal GI2, and the sweep signal SWP based on the third control signal CNT3.

[0113] Fig.16 It is shown that the Fig.15 1 is a circuit diagram of a pixel PX (eg, pixel PX[k]) in the display device 101.

[0114] Reference Fig.15 and Fig.16 , an embodiment of the pixel PX[k] may include a light emitting element LED, a pulse width modulator PWM and a constant current generator CCG. Fig.16 In the description of the embodiment of the pixel PX[k] shown in FIG. 1 , the above reference will be omitted. Figure 2 Any repeated detailed description of components of the described pixel PX[k] are substantially the same or similar components.

[0115] In an embodiment, the eighth transistor T8 may include a gate electrode receiving a write gate signal GW[k] corresponding to the pixel PX[k], a first electrode connected to the data line DL, and a second electrode connected to the second node B. The eighth transistor T8 may transmit the reference voltage VREF and the constant current generation voltage VCCG to the second node B in response to the write gate signal GW[k] having a turn-on level (e.g., a low voltage level).

[0116] The ninth transistor T9 may include a gate electrode receiving the compensation gate signal SCCG[k] corresponding to the pixel PX[k], a first electrode connected to the second electrode of the seventh transistor T7, and a second electrode connected to the third node C. The ninth transistor T9 may connect the second electrode of the seventh transistor T7 to the third node C in response to the compensation gate signal SCCG[k] having a turn-on level (e.g., a high voltage level).

[0117] Fig.17 is shown to include Fig.15 FIG. 1 is a diagram of signals and voltages for a pixel PX in a display device 101. FIG.

[0118] exist Fig.17 In the description of the signals and voltages shown in FIG. 1 , the same description as above with reference to FIG. 1 will be omitted. Figure 3Any repeated detailed description of components of the described signals and voltages is substantially the same or similar components.

[0119] In an embodiment, the first power voltage VDD1, the second power voltage VDD2, the third power voltage VSS, the initialization voltage VINT, the first initialization gate signal GI1, the second initialization gate signal GI2, the emission control signal EM and the sweep signal SWP may be commonly provided to the pixel PX. According to an embodiment, the first power voltage VDD1, the second power voltage VDD2, the third power voltage VSS, the initialization voltage VINT, the first initialization gate signal GI1, the second initialization gate signal GI2, the emission control signal EM and the sweep signal SWP may be substantially simultaneously applied to at least two pixel rows. The scanning signals GC_PWM[1], ..., GC_PWM[k], ..., and GC_PWM[n], the write gate signals GW[1], ..., GW[k], ..., and GW[n], and the compensation gate signals SCCG[1], ..., SCCG[k], ..., and SCCG[n] may be sequentially provided to the pixel PX based on the pixel row.

[0120] Each of the write gate signals GW[1], ..., GW[k], ..., and GW[n] may have a high voltage level H in the first period P1, the third period P3, the fifth period P5, the seventh period P7, and the eighth period P8, and have a low voltage level L in the second period P2, the fourth period P4, and the sixth period P6. In the fourth period P4, the pulses of the write gate signals GW[1], ..., GW[k], ..., and GW[n] having the low voltage level L may be sequentially shifted by a predetermined time (e.g., one horizontal time).

[0121] Each of the compensation gate signals SCCG[1], ..., SCCG[k], ..., and SCCG[n] may have a low voltage level L in the first to third periods P1 to P3 and the fifth to eighth periods P5 to P8, and have a high voltage level H in the fourth period P4. In the fourth period P4, the compensation gate signals SCCG[1], ..., SCCG[k], ..., and SCCG[n] having the high voltage level H may be sequentially shifted by a predetermined period (e.g., one horizontal period).

[0122] Fig.18 is a block diagram illustrating an electronic device 1000 according to an embodiment of the present disclosure. Fig.19 It shows that Fig.18 FIG. 1 is a diagram showing an example in which the electronic device 1000 is implemented as a smart watch.

[0123] Reference Fig.18 and Fig.19, an embodiment of the electronic device 1000 may include a processor 1010, a memory device 1020, a storage device 1030, an input / output (I / O) device 1040, a power supply 1050, and a display device 1060. The display device 1060 may correspond to Figure 1 The display device 100 or Fig.15 The electronic device 1000 may further include a plurality of ports capable of communicating with a video card, a sound card, a memory card, a universal serial bus (USB) device, etc., or with other systems.

[0124] According to the embodiment, Fig.19 As shown in , the electronic device 1000 may be implemented as a smart watch. However, the present disclosure is not limited thereto, and according to another embodiment, the electronic device 1000 may be implemented as a television, a mobile phone, a video phone, a smart tablet, a tablet personal computer (PC), a vehicle navigation device, a laptop computer, or a head-mounted display, etc.

[0125] The processor 1010 may perform a specific calculation or task. According to an embodiment, the processor 1010 may be a microprocessor or a central processing unit (CPU), etc. The processor 1010 may be connected to other components via an address bus, a control bus, or a data bus, etc. According to an embodiment, the processor 1010 may also be connected to an expansion bus, such as a peripheral component interconnect (PCI) bus. According to an embodiment, the processor 1010 may provide the first image data ( Figure 1 and Fig.15 The first image data IMD1) and the control signal ( Figure 1 and Fig.15 of the control signal CNT).

[0126] The memory device 1020 may store data used for the operation of the electronic device 1000. In an embodiment, for example, the memory device 1020 may include: a nonvolatile memory device (such as an erasable programmable read-only memory (EPROM), an electrically erasable programmable read-only memory (EEPROM), a flash memory, a phase change random access memory (PRAM), a resistive random access memory (RRAM), a nano floating gate memory (NFGM), a polymer random access memory (PoRAM), a magnetic random access memory (MRAM), or a ferroelectric random access memory (FRAM)) and / or a volatile memory device (such as a dynamic random access memory (DRAM), a static random access memory (SRAM), or a mobile DRAM).

[0127] The storage device 1030 may include a solid state drive (SSD), a hard disk drive (HDD), or a compact disk read-only memory (CD-ROM), etc. The I / O device 1040 may include: an input device such as a keyboard, a keypad, a touch pad, a touch screen, or a mouse; and an output device such as a speaker or a printer. The power supply 1050 may supply the power required for the operation of the electronic device 1000. The display device 1060 may be connected to other components through a bus or other communication links.

[0128] According to the display device 1060, the constant current generator of the pixel included in the display device 1060 may not include an emission control transistor turned on in response to an emission control signal, so that the number of transistors included in the pixel can be reduced. Therefore, the resolution of the display device 1060 can be improved.

[0129] The display device according to the embodiment can be applied to a display device included in a computer (such as a notebook computer or a smart tablet), a mobile phone, a smart phone, a smart watch, a portable media player (PMP), a personal digital assistant (PDA), or a Moving Picture Experts Group Audio Layer 3 (MP3) player, etc.

[0130] The present invention should not be interpreted as being limited to the embodiments described herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the concept of the present invention to those skilled in the art.

[0131] While the invention has been particularly shown and described with reference to embodiments thereof, it will be understood by those skilled in the art that various changes in form and details may be made without departing from the spirit or scope of the invention as defined by the following claims.

Claims

1. A pixel, wherein The pixels include: a light emitting element including a first electrode and a second electrode connected to a third power line transmitting a third power voltage; a pulse width modulator to control the emission duration of the light emitting element in a frame period based on the data voltage; and a constant current generator for providing a driving current having a constant level to the light emitting element based on a constant current generating voltage applied to the constant current generator, wherein the constant current generator comprises a second driving transistor, the second driving transistor comprising a gate electrode connected to a third node, a first electrode connected to a second power line transmitting a second power voltage, and a second electrode connected to the first electrode of the light emitting element.

2. The pixel according to claim 1, wherein: In an emission period in which the light emitting element emits light, the third power voltage has a low voltage level, and The third power voltage has a third high voltage level higher than the low voltage level in at least a portion of a non-emission period in which the light emitting element does not emit the light.

3. The pixel according to claim 2, wherein: During the transmission cycle, the second power voltage has a second high voltage level, and In at least a portion of the non-transmission period, the second power voltage has a medium voltage level that is higher than the low voltage level and lower than the second high voltage level.

4. The pixel according to claim 1, wherein: The pulse width modulator comprises: a first driving transistor including a gate electrode connected to the first node, a first electrode connected to the fourth node, and a second electrode connected to the fifth node; a first writing transistor including a gate electrode receiving a scanning signal, a first electrode connected to a data line transmitting the data voltage, and a second electrode connected to the fourth node; a first compensation transistor including a gate electrode receiving the scan signal, a first electrode connected to the fifth node, and a second electrode connected to the first node; and The first capacitor includes a first electrode receiving the sweep frequency signal and a second electrode connected to the first node.

5. The pixel according to claim 4, wherein: The third power voltage has a third high voltage level during a turn-off period in which the light emitting element is turned off, a first initialization period in which the gate electrode of the second driving transistor is initialized, a second initialization period in which the gate electrode of the first driving transistor is initialized, a compensation period in which the threshold voltage of the second driving transistor is compensated, a first writing period in which the data voltage whose threshold voltage of the first driving transistor is compensated is written to the gate electrode of the first driving transistor, and a second writing period in which the constant current generating voltage is written to the gate electrode of the second driving transistor, and The third power voltage has a low voltage level lower than the third high voltage level in an emission period in which the light emitting element emits light.

6. The pixel according to claim 5, wherein: In the first initialization period, the compensation period, the first writing period, the second writing period, and the emission period, the second power voltage has a second high voltage level, and In the off period and the second initialization period, the second power voltage has a middle voltage level that is lower than the second high voltage level and higher than the low voltage level.

7. The pixel according to claim 4, wherein: The pulse width modulator also includes: a first emission control transistor including a gate electrode receiving an emission control signal, a first electrode connected to a first power line transmitting a first power voltage, and a second electrode connected to the fourth node; and The second emission control transistor includes a gate electrode receiving the emission control signal, a first electrode connected to the fifth node, and a second electrode connected to the third node.

8. The pixel according to claim 7, wherein: The pulse width modulator further includes an initialization transistor including a gate electrode receiving a first initialization gate signal, a first electrode receiving an initialization voltage, and a second electrode connected to the first node.

9. The pixel according to claim 8, wherein: Each of the first write transistor, the first compensation transistor, and the initialization transistor is an N-type transistor.

10. The pixel according to claim 1, wherein: The constant current generator further includes a second capacitor including a first electrode connected to the third node and a second electrode connected to the second power line.

11. The pixel according to claim 10, wherein: The constant current generator also includes: a second write transistor including a gate electrode receiving a write gate signal, a first electrode connected to a data line transmitting the constant current generating voltage, and a second electrode connected to a second node; a second compensation transistor including a gate electrode receiving a compensation gate signal, a first electrode connected to the second electrode of the second driving transistor, and a second electrode connected to the third node; and The third capacitor includes a first electrode connected to the second node and a second electrode connected to the third node.

12. The pixel according to claim 11, wherein: The second compensation transistor is an N-type transistor.

13. The pixel according to claim 11, wherein: The constant current generator further includes a bypass transistor including a gate electrode receiving a second initialization gate signal, a first electrode connected to the first electrode of the light emitting element, and a second electrode connected to the second electrode of the light emitting element.

14. The pixel according to claim 1, wherein: The light emitting element is a micro light emitting diode.

15. A display device, wherein: The display device comprises: A display panel including a plurality of pixels; a scan driver that sequentially provides a plurality of scan signals to the plurality of pixels; and a data driver for supplying a data voltage and a constant current generating voltage to each of the plurality of pixels, Wherein, each of the plurality of pixels comprises: a light emitting element including a first electrode and a second electrode connected to a third power line transmitting a third power voltage; a pulse width modulator to control the emission duration of the light emitting element in a frame period based on the data voltage; and a constant current generator for providing a driving current having a constant level to the light emitting element based on the constant current generating voltage, wherein the constant current generator comprises a second driving transistor, the second driving transistor comprising a gate electrode connected to a third node, a first electrode connected to a second power line transmitting a second power voltage, and a second electrode connected to the first electrode of the light emitting element.

16. The display device according to claim 15, wherein: In an emission period in which the light emitting element emits light, the third power voltage has a low voltage level, and The third power voltage has a third high voltage level higher than the low voltage level in at least a portion of a non-emission period in which the light emitting element does not emit the light.

17. The display device according to claim 16, wherein: During the transmission cycle, the second power voltage has a second high voltage level, and In at least a portion of the non-transmission period, the second power voltage has a medium voltage level that is higher than the low voltage level and lower than the second high voltage level.

18. The display device according to claim 15, wherein: The pulse width modulator comprises: a first driving transistor including a gate electrode connected to the first node, a first electrode connected to the fourth node, and a second electrode connected to the fifth node; a first write transistor including a gate electrode receiving a scan signal among the plurality of scan signals, a first electrode connected to a data line transmitting the data voltage and the constant current generating voltage, and a second electrode connected to the fourth node; a first compensation transistor including a gate electrode receiving the scan signal, a first electrode connected to the fifth node, and a second electrode connected to the first node; a first emission control transistor including a gate electrode receiving an emission control signal, a first electrode connected to a first power line transmitting a first power voltage, and a second electrode connected to the fourth node; a second emission control transistor including a gate electrode receiving the emission control signal, a first electrode connected to the fifth node, and a second electrode connected to the third node; an initialization transistor including a gate electrode receiving a first initialization gate signal, a first electrode receiving an initialization voltage, and a second electrode connected to the first node; and The first capacitor includes a first electrode receiving the sweep frequency signal and a second electrode connected to the first node.

19. The display device according to claim 18, wherein: The constant current generator also includes: a second write transistor including a gate electrode receiving a write gate signal, a first electrode connected to the data line, and a second electrode connected to a second node; a second compensation transistor including a gate electrode receiving a compensation gate signal, a first electrode connected to the second electrode of the second driving transistor, and a second electrode connected to the third node; a bypass transistor including a gate electrode receiving a second initialization gate signal, a first electrode connected to the first electrode of the light emitting element, and a second electrode connected to the second electrode of the light emitting element; a second capacitor including a first electrode connected to the third node and a second electrode connected to the second power line; and The third capacitor includes a first electrode connected to the second node and a second electrode connected to the third node.

20. The display device according to claim 19, wherein: The display device further includes: A power manager commonly provides the first power voltage, the second power voltage, the third power voltage, the initialization voltage, the emission control signal, the first initialization gate signal, the second initialization gate signal, the sweep signal, the write gate signal, and the compensation gate signal to the plurality of pixels.

Images