Display data write-in method, write-in circuit and display equipment

Abstract

The invention relates to a display data write-in method, a write-in circuit and display equipment in the field of data display. The method comprises the following steps of: synchronously initializing storage intermediate voltage based on a first scanning signal for all pixel points of the display equipment within backlight opening time of a current frame display picture; after the initialization is completed, for all pixel points of the display equipment, on the basis of the initialized and stored intermediate voltage line by line, pre-storing data signal voltage required by a next frame of display picture; after the backlight of the current frame of display picture is turned off, resetting the pixel data voltage of the current frame of display picture as the common electrode voltage; and after resetting, for all pixel points of the display equipment, synchronously reading the pre-stored data signal voltage for displaying the next frame of display picture. According to the method, the overall display data writing time is shortened, and display products with higher refresh rate and higher resolution can be realized.

Description

Technical Field

[0001] The present invention relates to the field of data display, and in particular to a display data writing method, a writing circuit and a display device. Background Art

[0002] In traditional field sequential or color sequential display data writing, the backlight can only be turned on after all the screen data is written and the liquid crystal is deflected to a stable state, otherwise the screen will be chaotic. Therefore, the data writing and liquid crystal deflection time will greatly compress the backlight turn-on time, resulting in difficulties in improving the brightness of the display device, as well as difficulties in improving the refresh rate and resolution, increased power consumption and increased backlight material costs.

[0003] In an improved display data writing, the pixel data voltage of the next frame can be pre-stored by using the signal storage capacitor Cs1 during the backlight emission time, and when switching the screen, all pixels synchronously read the pixel data voltage in the corresponding Cs1. Through the design of this pixel data voltage register, the pixel number writing time can be saved and the backlight emission time can be increased accordingly. However, this pixel circuit design faces the problem of charge sharing, which is not conducive to the display device to achieve high refresh rate and high resolution. Summary of the invention

[0004] The technical problem to be solved by the present application is to provide a display data writing method, a writing circuit and a display device, which have the characteristics of being able to achieve a higher refresh rate and resolution of the display device.

[0005] In a first aspect, an embodiment provides a method for writing display data, comprising:

[0006] Initialize and store the intermediate voltage. During the backlight on time of the current frame display picture, for all pixels of the display device, synchronize and initialize and store the intermediate voltage, wherein the intermediate voltages of the pixels with the same voltage polarity of the data signal of the next frame are configured to be the same.

[0007] Pre-storing the data signal voltage, after the intermediate voltage is initialized, within the backlight on time of the current frame, for all pixels of the display device, pre-storing the data signal voltage required for the next frame of display picture on a row-by-row basis based on the intermediate voltage stored in the initialization;

[0008] Resetting the pixel data voltage: after the backlight of the current frame display picture is turned off, resetting the pixel data voltage of the current frame display picture to the common electrode voltage;

[0009] The data signal voltage is read, and after the pixel data voltage of the current frame display picture is reset to the common electrode voltage, the pre-stored data signal voltage is synchronously read for all pixel points of the display device for displaying the next frame display picture.

[0010] In a second aspect, an embodiment provides a display data writing circuit, including a first control circuit, a second control circuit, a third control circuit, a first signal storage capacitor Cs1 and a pixel capacitor Clc;

[0011] Based on the first control circuit, during the backlight on time of the current frame display picture, in the initialization writing stage, the first signal storage capacitors Cs1 corresponding to all the pixels are synchronously controlled to initialize and store the intermediate voltage, wherein the intermediate voltages of the pixels with the same polarity of the data signal voltage of the next frame are configured to be the same; in the data writing stage after the initialization writing stage, the first signal storage capacitors Cs1 corresponding to all the pixels of the display device are controlled to pre-store the data signal voltage required for the next frame display picture on the basis of the initialization stored intermediate voltage row by row;

[0012] Based on the second control circuit, after the backlight of the current frame display picture is turned off, the pixel data voltage of the current frame display picture in the pixel capacitor Clc corresponding to all the pixel points is reset to the common electrode voltage;

[0013] Based on the third control circuit, for all pixels of the display device, the data signal voltage pre-stored in the first signal storage capacitor Cs1 corresponding to all pixels is synchronously read into the pixel capacitor Clc for displaying the next frame of the display picture.

[0014] In a third aspect, an embodiment provides a display device, comprising the display data writing circuit of any one of the above embodiments.

[0015] In a fourth aspect, an embodiment provides a computer-readable storage medium, wherein the medium stores a program, and the program can be loaded by a processor to execute the display data writing method as described in any one of the above embodiments.

[0016] The beneficial effects of the present invention are:

[0017] Before pre-storing the data signal voltage required for the next frame of the picture, the intermediate voltage is initialized and stored first, wherein the intermediate voltages of the pixels with the same polarity of the data signal voltage of the next frame are configured to be the same, so that the charge required for writing the data signal voltage separately for pre-storing the data signal voltage required for the next frame of the picture can be reduced, thereby reducing the time for pre-storing the data signal voltage required for the next frame of the picture, thereby reducing the overall display data writing time, which is conducive to the realization of higher refresh rate and higher resolution display products, and the method is simple and easy to implement. BRIEF DESCRIPTION OF THE DRAWINGS

[0018] Figure 1 It is a schematic diagram of the structure of a display data writing circuit according to an embodiment of the prior art;

[0019] Figure 2 yes Figure 1 A schematic diagram of the timing of display data writing based on the circuit structure shown;

[0020] Figure 3 is a schematic diagram of the structure of a display data writing circuit according to another embodiment of the prior art;

[0021] Figure 4 yes Figure 3 A schematic diagram of the timing of display data writing based on the circuit structure shown;

[0022] Figure 5 It is a flow chart of the display data writing method of the present application;

[0023] Figure 6 is based on Figure 5 A schematic diagram of the control timing of the method shown;

[0024] Figure 7 It is a schematic diagram of the pixel region structure of a specific embodiment 1 of the display data writing circuit of the present application;

[0025] Figure 8 yes Figure 7 A schematic diagram of the peripheral circuit structure of the embodiment shown;

[0026] Fig. 9 is based on Figure 7 and Figure 8 A schematic diagram of the control timing of the embodiment shown;

[0027] Fig.10 It is a structural schematic diagram of a specific embodiment 2 of the display data writing circuit of the present application;

[0028] Fig.11 is based on Fig.10 A schematic diagram of the control timing of the embodiment shown;

[0029] Fig.12 It is a structural schematic diagram of a specific embodiment 3 of the circuit for writing display data;

[0030] Fig.13 is based on Fig.12 A schematic diagram of the control timing of the embodiment shown. DETAILED DESCRIPTION

[0031] The present invention is further described in detail below by specific embodiments in conjunction with the accompanying drawings. Wherein similar elements in different embodiments adopt associated similar element numbers. In the following embodiments, many detailed descriptions are for making the present application better understood. However, those skilled in the art can easily recognize that some features can be omitted in different situations, or can be replaced by other elements, materials, methods. In some cases, some operations related to the present application are not shown or described in the specification, this is to avoid the core part of the present application being overwhelmed by too much description, and for those skilled in the art, it is not necessary to describe these related operations in detail, and they can fully understand the related operations according to the description in the specification and the general technical knowledge in the art.

[0032] In addition, the features, operations or characteristics described in the specification can be combined in any appropriate manner to form various implementations. At the same time, the steps or actions in the method description can also be interchanged or adjusted in a manner that is obvious to those skilled in the art. Therefore, the various sequences in the specification and the drawings are only for the purpose of clearly describing a certain embodiment and are not meant to be a required sequence, unless otherwise specified that a certain sequence must be followed.

[0033] The serial numbers of the components in this document, such as "first", "second", etc., are only used to distinguish the objects described and do not have any order or technical meaning. The "connection" and "coupling" mentioned in this application, unless otherwise specified, include direct and indirect connections (couplings).

[0034] To facilitate the description of the inventive concept of the present application, the display data writing technology is briefly described below.

[0035] In the traditional field sequential or color sequential display driving technology, please refer to Figure 1 The display driving circuit shown is a writing circuit for a pixel of a display device, including a MOS tube and a pixel capacitor Clc. The connection node between the MOS tube and the pixel capacitor Clc is a pixel electrode node. The gate of the MOS tube is connected to the scan signal line Scan, and a source and drain are connected to the data signal voltage line Data. For its driving timing, please refer to Figure 2 , the backlight can be turned on for data display only after the data writing of all rows of the screen is completed and the liquid crystal deflection is in a stable state, otherwise there will be a chaotic picture. Therefore, the data writing and liquid crystal deflection time will greatly compress the backlight turn-on time, resulting in difficulties in improving the brightness of the display device, as well as difficulties in improving the refresh rate and resolution, increased power consumption and increased backlight material costs.

[0036] In order to reduce the liquid crystal driving time and increase the backlight start time, an improved solution can pre-store the data signal voltage required for the next frame of the picture during the backlight time, and when switching the picture, first eliminate the charge originally remaining on the pixel capacitor, and then synchronously read the pre-stored data signal voltage, so that the pixel data writing time can be saved and the backlight emission time can be correspondingly increased. The display driving circuit designed based on this control method can refer to Figure 3 , the display drive timing can refer to Figure 4 . Figure 3 The improved drive circuit and Figure 1 The difference between the traditional 1T2C pixel design and the conventional 1T2C pixel design is that it includes a pixel data signal write switch TFT T1, a first signal storage capacitor Cs1, a signal transfer switch TFT T2, a pixel capacitor Clc and a reset switch TFT T3. Among them, the first signal storage capacitor Cs1 is used to pre-store the data signal voltage required for the next frame of the picture, the signal transfer switch TFT T2 is used to transfer the pre-stored data signal voltage to the corresponding pixel capacitor Clc, and the reset switch TFT T3 is used to eliminate the charge originally remaining on the pixel capacitor Clc to prevent the effects such as color deviation and brightness difference caused by the residual charge. This circuit design can use the first signal storage capacitor Cs1 to pre-store the data signal voltage of the next frame of the picture during the backlight emission time, and when switching the picture, all pixels synchronously read the data signal voltage in the corresponding Cs1. Through the design of this pixel data voltage register, the pixel number writing time can be reduced, and the backlight emission time can be increased accordingly.

[0037] However, the applicant found in the research that the above pixel circuit design faces the problem of charge sharing, so a large first data storage capacitor Cs1 is required, which will result in a long charging time for each row of Cs1 in the pre-charging stage, which is not conducive to the display device to achieve high refresh rate and high resolution. At the same time, due to the need for polarity reversal of liquid crystal drive, the voltage difference of the data signal voltage between the two frames is large (for example, the data signal voltage of the previous frame is greater than the common electrode voltage Vcom, and the next frame needs to be less than Vcom, otherwise it will cause polarization of the liquid crystal, resulting in problems such as DC afterimage), so that when charging the first signal storage capacitor Cs1, the required charging voltage difference is large, and the charging difficulty is further increased. Due to the charging restriction, the increase of Cs1 voltage is also limited. Therefore, when sharing charge, Cs1 needs to be pre-charged with a higher voltage. Therefore, it is necessary to increase the data signal voltage supply range to meet the liquid crystal operating voltage range, and put forward higher requirements for the data signal IC output voltage range.

[0038] Based on this, the present application provides a display data writing method. Before pre-storing the data signal voltage required for the next frame of the picture, the intermediate voltage is first initialized and stored. The intermediate voltage is between the data signal voltage with the largest difference from the common electrode voltage Vcom under the corresponding polarity and Vcom. This can reduce the charge required for the subsequent separate pre-storage of the maximum data signal voltage, and also reduce the maximum time required for the subsequent separate pre-storage of the data signal voltage of each row, thereby reducing the overall pixel data writing time of the display device, which is conducive to the realization of higher refresh rate and higher resolution display devices. Please refer to Figure 5 , the display data writing method comprises:

[0039] Step S10, initializing and storing the intermediate voltage. During the backlight on time of the current frame, the intermediate voltage is synchronously initialized and stored for all pixels of the display device, wherein the intermediate voltages of the pixels with the same voltage polarity of the data signal of the next frame are configured to be the same.

[0040] Due to the existence of the intermediate voltage for initialization storage, the storage time of the data voltage required for each row of pixels under the corresponding polarity of the next frame for pre-storing each pixel row by row can be reduced. In this way, the time required for the data voltage for the next frame of the picture can be reduced as a whole, thereby reducing the overall display data writing time, which is conducive to the realization of higher refresh rate and higher resolution display products.

[0041] In one embodiment, synchronously initializing and storing the intermediate voltage includes: synchronously starting to load the first scanning signal and the intermediate voltage initialization storage signal, the loading time of the intermediate voltage initialization storage signal is greater than the loading time of the first scanning signal, thereby ensuring that the pre-storage node or the first storage capacitor Cs1 is charged to the required potential. In one embodiment, the intermediate voltage is the average value of the data signal voltage with the largest difference from the common electrode voltage Vcom and Vcom under the corresponding polarity of each pixel in the next frame, so as to minimize the writing time of the overall display data.

[0042] Step S20, pre-storing data signal voltages. After the intermediate voltage is initialized, during the backlight on time of the current frame, for all pixels of the display device, the data signal voltages required for the next frame are pre-stored row by row based on the initialized stored intermediate voltages.

[0043] After the intermediate voltage is initialized, the scanning signal is loaded row by row for all the pixels of the display device, and the data signal voltage required for the next frame of the picture is pre-stored to the required potential based on the initialized stored intermediate voltage. Since the storage time of the data voltage required for each row of pixels is reduced, the time required for the data voltage for the next frame of the picture is reduced as a whole.

[0044] Step S30, resetting the pixel data voltage: after the backlight of the current frame display picture is turned off, the pixel data voltage of the current frame display picture is reset to the common electrode voltage.

[0045] Step S40, data signal voltage reading: After resetting the pixel data voltage of the current frame display picture to the common electrode voltage, the pre-stored data signal voltage is synchronously read for all the pixels of the display device for displaying the next frame picture.

[0046] Before pre-storing the data signal voltage required for the next frame of the picture, the display data writing method first initializes and stores an intermediate voltage, where the intermediate voltage is between the data signal voltage with the largest difference from the common electrode voltage Vcom under the corresponding polarity and Vcom, thereby reducing the charge required for pre-storing the data signal voltage required for the next frame of the picture and writing the data signal voltage separately, thereby reducing the time for pre-storing the data signal voltage required for the next frame of the picture in the pixel, thereby reducing the overall display data writing time, which is conducive to the realization of higher refresh rate and higher resolution display products, and the method is simple and easy to implement.

[0047] In one embodiment of the present application, a display data writing circuit is provided, which is used to implement a display data writing method, including a first control circuit, a second control circuit, a third control circuit, a first signal storage capacitor Cs1 and a pixel capacitor Clc. Each pixel of the display device corresponds to a first signal storage capacitor Cs1 and a pixel capacitor Clc.

[0048] The first signal storage capacitor Cs1 is used to initialize and store an intermediate voltage during the backlight-on time of the current frame display image. The intermediate voltage is between the data signal voltage with the largest difference from the common electrode voltage Vcom under the corresponding polarity of the next frame display image and Vcom, and continues to pre-store the first signal storage capacitor Cs1 based on the intermediate voltage after a buffer time, so that the data voltage stored in the first signal storage capacitor Cs1 reaches the data signal voltage required for the next frame display image.

[0049] The pixel area of ​​the display device uses column inversion or row inversion to achieve polarity inversion. Please refer to Figure 6, the following takes column inversion as an example for explanation, that is, in a certain frame, the odd-numbered column pixel electrodes have positive polarity voltages, and the even-numbered column pixel electrodes have negative polarity voltages, and in the next frame, the odd-numbered column pixel electrodes have negative polarity voltages, and the even-numbered column pixel electrodes have positive polarity voltages, and so on. Taking the Vcom voltage as a reference, taking the odd-numbered column as an example, assuming that in the Nth frame (N is a natural number), the odd-numbered column pixel voltage is negative, then in the N+1st frame, the odd-numbered column pixel voltage is positive. According to the pre-stored working principle, during the luminous time of the Nth frame, the data signal voltage of the N+1st frame is written to the first signal storage capacitor Cs1 corresponding to the odd-numbered column, so it is necessary to write a positive polarity voltage, that is, a voltage greater than or equal to Vcom. For the even columns, assuming that in the Nth frame, the pixel voltage of the even columns is positive, then in the N+1th frame, the pixel voltage of the even columns is negative. According to the pre-storage working principle, during the luminous time of the Nth frame, the data signal voltage of the N+1th frame is written to the first signal storage capacitor Cs1 corresponding to the even columns. Therefore, a negative polarity voltage needs to be written, that is, a voltage less than or equal to Vcom.

[0050] For the first signal storage capacitor Cs1 of a certain odd pixel column a, in the Nth frame, assuming that the data signal voltage to be written is the maximum, that is, Vdata_max, then if the data signal voltage required for displaying the picture is to be satisfied when the positive polarity is used, the charge to be written is Q1 = C*V = C Cs1 *(Vdata_max-Vcom), where C Cs1 is the capacitance value of the first signal storage capacitor Cs1. If in the initialization charging stage, the first signal storage capacitor Cs1 has been pre-charged to the average value of the data signal voltage Vdata_max with the largest difference from the common electrode voltage Vcom under positive polarity and Vcom, that is,

[0051] Vcom+(Vdata_max-Vcom) / 2=(Vdata_max+Vcom) / 2, then when writing the data signal voltage to the pixel, the charge to be written is Q2=C*V=C Cs1 *(Vdata_max-(Vdata_max+Vcom) / 2)=C Cs1 *(Vdata_max-Vcom) / 2, that is, only half of the charge needs to be charged to complete the data signal writing.

[0052] For the first signal storage capacitor Cs1 of a pixel b in an odd column, in the Nth frame, assuming that the data signal voltage to be written is the minimum, that is, Vcom, then if the data signal voltage required for displaying the picture is to be satisfied in the positive polarity, the charge to be written is Q3 = C*V = C Cs1*(Vcom-Vcom), that is, no charge needs to be written. If in the initialization charging stage, the first signal storage capacitor Cs1 has been pre-charged to the average value of the data signal voltage Vdata_max and Vcom with the largest difference from the common electrode voltage Vcom under positive polarity, that is, (Vdata_max+Vcom) / 2, then when the data signal voltage is written to the pixel, the charge to be written is Q4=C*V=C Cs1 *(Vcom-(Vdata_max+Vcom) / 2)=C Cs1 *(Vcom-Vdata_max) / 2. It can be concluded that the required write charge amount is the same as the required write charge amount C of pixel a. Cs1 *(Vdata_max-Vcom) / 2 are equal in magnitude and opposite in direction. It can be concluded that, by adopting the driving method of the present proposal, in the stage of writing the data signal voltage row by row, the maximum charge required by the first signal storage capacitor Cs1 of all pixels is reduced by half.

[0053] Similarly, for even-numbered columns of pixels, the first signal storage capacitor Cs1 of the pixel needs to be pre-charged with a negative polarity data signal voltage (i.e., ≤Vcom) in the Nth frame. Therefore, in the initialization charging stage, the even-numbered columns of pixels are initialized to the intermediate value of the minimum data voltage signal Vdata_min and the Vcom voltage, for example, Vcom-(Vcom-Vdata_min) / 2=(Vcom-Vdata_min) / 2. This can also achieve the effect of halving the maximum charge required for the first signal storage capacitor Cs1 in the data signal voltage writing stage.

[0054] In the N+1th frame, due to the polarity reversal requirement, the odd columns are pre-charged with negative polarity voltages, and the even columns are pre-charged with positive polarity voltages. The initial charging method is similar to the above process, except that the initial intermediate voltage value of the odd columns becomes the intermediate value between the minimum data signal voltage and Vcom, and the initial intermediate voltage value of the even columns becomes the intermediate value between the maximum data signal voltage and Vcom.

[0055] This process is repeated, with odd and even frames as one cycle. While completing the polarity reversal, the initialization writing and data signal voltage writing corresponding to all frame images can be realized, achieving the effect described in this proposal.

[0056] Based on the above analysis, in one embodiment, the intermediate voltage is the average value of the data signal voltage with the largest difference from the common electrode voltage Vcom and Vcom at the corresponding polarity of each pixel in the next frame, so as to minimize the writing time of the overall display data.

[0057] After the backlight of the current frame (Nth frame) is turned off and before the backlight of the next frame is turned on, the pixel capacitor Clc is first reset to eliminate the charge remaining inside, and then the data signal voltage pre-stored in the corresponding first signal storage capacitor Cs1 is transferred to the pixel capacitor Clc to prepare for the display of the next frame.

[0058] To realize the control of the action process of the first signal storage capacitor Cs1 and the pixel capacitor Clc, please refer to Figure 6 , the first control circuit, the second control circuit and the third control circuit are described below.

[0059] Based on the first control circuit, during the backlight on time of the current frame display image (display time of the current frame), in the initialization write phase, the first signal storage capacitor Cs1 corresponding to all pixel points of the display device are synchronously controlled to initialize and store an intermediate voltage, wherein the intermediate voltages of the pixel points with the same polarity of the next frame data signal voltage are configured to be the same.

[0060] During the backlight on time of the current frame display image, in the initialization writing stage, based on the first control circuit, the first signal storage capacitor Cs1 corresponding to each of the pixels of the display device is initialized to store an intermediate voltage, and the intermediate voltage is between the data signal voltage with the largest difference from the common electrode voltage Vcom and Vcom under the corresponding polarity of each pixel in the next frame, and the intermediate voltages of the pixels with the same polarity of the data signal voltage in the next frame are configured to be the same, which can reduce the charge required for the subsequent separate pre-storage of the maximum data signal voltage, and also reduce the maximum time required for the subsequent separate pre-storage of the data signal voltage of each row, thereby reducing the overall pixel data writing time of the display device, which is conducive to the realization of higher refresh rate and higher resolution display devices. At the same time, the increase of the first signal storage capacitor Cs1 can be less restricted, so when charging the pixel electrode, under the same data signal voltage, it can be charged to a higher potential (it can be charged to a lower potential when it is negative polarity), which also reduces the voltage range requirements for the data signal IC output.

[0061] In one embodiment, the intermediate voltage is an average value of a data signal voltage with the largest difference from the common electrode voltage Vcom and Vcom at a corresponding polarity of each pixel in the next frame.

[0062] In the data writing phase after the initialization writing phase, the first control circuit controls the first signal storage capacitors Cs1 corresponding to all pixels of the display device to pre-store the data signal voltage required for the next frame display based on the intermediate voltage stored in the initialization.

[0063] Based on the initialization writing stage, in the data writing stage, the maximum time required for the individual pre-storage of the data signal voltage of each row is reduced, and the voltage range requirement of the data signal IC output is also reduced.

[0064] Based on the second control circuit, after the backlight of the current frame display picture is turned off, the pixel data voltage of the current frame display picture in the pixel capacitor Clc corresponding to all pixel points is reset to the common electrode voltage (Reset signal). In this way, the charge originally remaining on the pixel capacitor is eliminated to prevent the effect problems such as color change and brightness difference caused by the residual charge.

[0065] Based on the third control circuit, for all pixels of the display device, the data signal voltage pre-stored in the first signal storage capacitor Cs1 corresponding to all pixels is synchronously read into the pixel capacitor Clc (Tran signal) for displaying the next frame of the display screen. In this way, when switching the display screen, all pixels synchronously read the pre-stored pixel data voltage, saving the writing time of the pixel data voltage.

[0066] The following is a detailed description in conjunction with three specific embodiments of the writing circuit. Specific embodiment 1

[0068] Please refer to Figure 7 and Figure 8 The writing circuit includes a pixel point data voltage writing array, and the data voltage writing array includes a plurality of pixel point data voltage writing units, each writing unit corresponding to a pixel point. To clearly show in the drawings, Figure 7 What is shown in the figure is a 2×2 pixel point data voltage writing array, but it is not limited to 2×2.

[0069] For each writing unit, it includes a scan signal input terminal, a data signal voltage input terminal, a reset signal terminal, a reference potential connection terminal, a pre-stored data signal voltage transfer control terminal, a signal writing switch T1, a signal transfer switch T2, a reset switch T3, a first signal storage capacitor Cs1 and a pixel capacitor Clc.

[0070] Please refer to Figure 7 , wherein the scan signal input terminal is used to connect the scan signal line Scan, and the scan signal input terminals of different row writing units are connected to different scan signal lines. Figure 7In the figure, since it is a 2×2 pixel data voltage writing array, only two rows are shown here. Therefore, the scan signal line only shows the first scan signal line Scan1 corresponding to the first row write unit and the second scan signal line Scan2 corresponding to the second row write unit. The data signal voltage input terminal is used to connect the data signal voltage line Data, and the data signal voltage input terminals of the write units in different columns are connected to different data signal voltage lines Data. Only two columns are shown here. Therefore, the data signal voltage line Data only shows the first data signal voltage line Data1 corresponding to the first column write unit and the second data signal voltage line Data2 corresponding to the second column write unit. The reset signal terminal is used to connect the reset signal line Reset. The reference voltage connection terminal is used to connect the reference electrode Com, and the reference electrode Com is used to provide a reference voltage Vcom. The pre-stored data signal voltage transfer control terminal is used to connect the data signal voltage transfer control signal line Tran. The signal write switch T1, the signal transfer switch T2 and the reset switch T3 are all MOS tubes. The MOS tube here can be an NMOS tube or a PMOS tube. If it is an NMOS tube, it is turned on based on a high-level signal, and if it is a PMOS tube, it is turned on based on a low-level signal. Therefore, it is possible to choose to use an NMOS tube or a PMOS tube based on a control signal. In the specific embodiments of the present application, NMOS tubes are used, but this does not limit the protection scope of the present application. Those skilled in the art can adaptively change all or part of the switches to PMOS tubes based on the control principle.

[0071] For the specific internal connection structure, the gate of the signal writing switch T1 is connected to the scanning signal input terminal, and one source and drain is connected to the data signal voltage input terminal; the other source and drain of the signal writing switch T1 is connected to a source and drain of the signal transfer switch T2, and the connection node between them is used as a pre-charge node, one end of the first signal storage capacitor Cs1 is connected to the pre-charge node, and the other end is connected to a fixed potential, which includes any one of the scanning signal input terminal, the reference voltage connection terminal, and the pre-stored data signal voltage transfer control terminal. The other end of the first signal storage capacitor Cs1 is connected to a fixed potential, here, it can be connected to the corresponding scanning signal line Scan, the reference electrode Com, or the data signal voltage transfer control signal line Tran.

[0072] In one embodiment, in order to stabilize the pixel node voltage and reduce flicker caused by voltage changes, the writing unit further includes a second signal storage capacitor Cs2, one end of which is connected to the pixel node, and similar to the first signal storage capacitor Cs1, the other end of the second signal storage capacitor Cs2 is connected to a fixed potential. Here, it can be connected to the corresponding scan signal line Scan, the reference electrode Com or the data signal voltage transfer control signal line Tran.

[0073] The gate of the signal transfer switch T2 is connected to the pre-stored data signal voltage transfer control terminal. The other source and drain of the signal transfer switch T2 is connected to a source and drain of the reset switch T3, and the connection point between them is used as a pixel electrode node. One end of the pixel capacitor Clc is connected to the pixel electrode node, and the other end is connected to the reference voltage connection terminal.

[0074] A gate of the reset switch T3 is connected to the reset signal input terminal, and another source and drain are connected to the reference voltage connection terminal.

[0075] The second control circuit includes a reset switch T3, and the third control circuit includes a signal transfer switch T2.

[0076] Please refer to Figure 8 Based on the above circuit, after the backlight of the current frame display picture is turned off, a high-level signal can be first given to the reset switch T3 through the reset signal line Reset to eliminate the charge originally remaining on the pixel capacitor to prevent the effects such as color deviation and brightness difference caused by the residual charge. After the high-level signal ends, a high-level signal is given to the signal transfer switch T2 through the data signal voltage transfer control signal line Tran, so that all the pixels of the display device can synchronously read the pre-stored data signal voltage in the first signal storage capacitor Cs1 corresponding to all the pixels to the pixel capacitor Clc, so that when the screen is switched, it is ready for the display of the next frame of the display picture.

[0077] Please refer to Figure 7 and Figure 8 In the first specific embodiment, in addition to the writing unit described above, it also includes a peripheral circuit, such as Figure 8 As shown, Figure 8 The inside of the dashed box is Figure 7 The pixel data voltage shown is written into the array (pixel area).

[0078] from Figure 7 and Figure 8 It can be seen that there are multiple scanning signal lines Scan, and the multiple scanning signal lines Scan are connected one-to-one to multiple rows of the pixel data voltage write array; there are multiple data signal voltage lines Data, and the multiple data signal voltage lines Data are connected one-to-one to multiple columns of the pixel data voltage write array.

[0079] In one embodiment, based on Figure 8 The first control circuit includes a write switch T1, a plurality of scan signal switches (T11, T12) and a plurality of data voltage switches (T21, T22).

[0080] There is a one-to-one correspondence between the multiple scan signal switches, the multiple scan signal enable input terminals, and the multiple scan signal enable output terminals. The multiple scan signal enable input terminals are used to connect to the scan signal enable line En_Scan, and the multiple scan signal enable output terminals are used to connect to the corresponding scan signal lines Scan. For any scan signal switch, it is a MOS tube, the gate of the MOS tube is connected to the corresponding scan signal enable input terminal, one source and drain is connected to the corresponding scan signal enable output terminal, and the other source and drain is connected to the high level signal line VGH, and the high level signal line VGH is used to provide a high potential when the scan signal line Scan works normally, so as to open the write switch T1.

[0081] In one embodiment, the plurality of scan signal switches (T11, T12) and the plurality of data voltage switches (T21, T22) are all NMOS tubes.

[0082] Multiple data voltage switches correspond to multiple input voltage enable input terminals and multiple input voltage enable output terminals one by one. Multiple input voltage enable input terminals are used to connect to data voltage signal enable lines En_Data, and multiple input voltage enable output terminals are used to connect to corresponding data signal voltage lines Data respectively; any data voltage switch is a MOS tube, the gate of which is connected to its corresponding voltage enable input terminal, one source and drain is connected to its corresponding voltage enable output terminal, and the other source and drain is connected to its corresponding reference voltage VREF; wherein, the data voltage switches of odd columns are connected to the first reference voltage VREF1, and the data voltage switches of even columns are connected to the second reference voltage VREF2.

[0083] In one embodiment, EN_Scan, EN_Data, VREF1 and VREF2 are all global power signals, provided by T-con IC or other signal generating units, and are arranged around the pixel display area through thin film technology.

[0084] Based on the above specific circuit, the column inversion method is used to achieve polarity inversion. Please refer to Fig. 9In the current frame (Nth frame), the odd-numbered pixel electrodes have negative voltages, and the precharge nodes need to be charged with positive voltages. The even-numbered pixel electrodes have positive voltages, and the precharge nodes need to be charged with negative voltages. The next frame (N+1th frame) is the opposite. During the initialization write phase of the Nth frame, the scan signal enable line En_Scan is switched to a high level, and multiple scan signal switches (T11, T12) are turned on, connecting the scan signal lines Scan of all rows to the high level voltage of the high level signal line VGH, so that the write switch T1 of each write unit can be turned on. When the scan signal enable line En_Scan is switched to a high level, the data voltage signal enable line En_Data is also switched to a high level, and multiple data voltage switches (T21, T22) are turned on, connecting the data signal voltage line Data (Data1) of the odd columns to the first reference voltage VREF1, so that the data signal voltage line Data voltage of the odd columns is charged to the positive polarity intermediate voltage Vcom+(Vdata_max-Vcom) / 2, and connecting the data signal voltage line Data (Data2) of the even columns to the second reference voltage VREF2, so that the data signal voltage line Data voltage of the even columns is charged to the negative polarity intermediate voltage Vcom-(Vcom-Vdata_min) / 2. Subsequently, the scan signal enable line En_Scan and the data voltage signal enable line En_Data are switched to a low level, ensuring that multiple scan signal switches (T11, T12) and multiple data voltage switches (T21, T22) are turned off, so that the scan signal line Scan of each row and the data signal voltage line Data of each column achieve the required charge and timing to complete the initialization writing phase.

[0085] In one embodiment, to ensure that the data signal voltage line Data of each column is charged to a required potential, the high level time of the data voltage signal enable line En_Data is greater than the high level time of the scan signal enable line En_Scan.

[0086] Taking odd columns as an example, assuming that in the Nth frame, the pixel voltage of the first column is a negative polarity voltage (Vpixel-Vcom≤0, Vpixel is the pixel node voltage), then the pixel voltage corresponding to the N+1th frame should be a positive polarity voltage (Vpixel-Vcom≥0). According to the working principle of the pre-storage method, the light-emitting time of the Nth frame corresponds to the data signal voltage of the N+1th frame written to the storage capacitor Cs1, so a positive polarity voltage needs to be written.

[0087] Before writing the data absorption voltage to the first signal storage capacitor Cs1 of each row, all the row Scan control lines are set to high voltage square wave pulses at the same time, and the write switch T1 is turned on. The signal of the data signal voltage line Data initializes the intermediate potential of the first signal storage capacitor Cs1 through the write switch T1, which can be the average value of the data signal voltage with the largest difference from the common electrode voltage Vcom and Vcom at the corresponding polarity of each pixel in the next frame.

[0088] Since the screen switches at any time during the display process, a certain pixel can display all grayscales from the lowest grayscale to the highest grayscale, so when each row of Cs1 is charged, the charging time is generally set to the same width, and the charging must be completed at the grayscale with the maximum voltage difference. Therefore, based on the circuit structure of the first specific embodiment, in the data signal voltage writing stage, the maximum charging charge required by Cs1 is halved, so the writing time of each row can be greatly reduced, thereby reducing the total time required for the data writing stage, which is conducive to the driving realization of higher refresh rate and higher resolution display products.

[0089] The same is true for even-numbered columns, which will not be repeated here.

[0090] During this process, the corresponding outputs of the scan signal IC and data signal IC connected to the Scan line and the Data line are set to high impedance (Hi-Z) to ensure that the output signal of the signal scan IC is not short-circuited with VGH. The output of the data signal IC is not short-circuited with VREF1 and VREF2. After multiple scan signal switches (T11, T12) and multiple data voltage switches (T21, T22) are turned off, the scan signal IC and the data signal IC are output normally to complete the subsequent data writing process.

[0091] In the N+1th frame, the working process is similar. According to the polarity inversion requirement, the VREF1 and VREF2 voltages will switch with each other. This process is repeated with odd and even frames as one cycle to achieve the above functions.

[0092] The gate control unit and data signal unit used in the control circuit are not limited to the scan signal IC and the data signal IC, but may also be other similar signal output units, such as GOA (Gate IC on array) and SOA (Source IC on array) made on the periphery of the display area by thin film technology.

[0093] If the scan signal IC and the data signal IC can directly realize the data signal voltage and timing of the scan signal in the required initialization phase, it is also feasible and no longer necessary Figure 7 and Figure 8 Required peripheral control circuits and corresponding power supply signals. Specific embodiment 2

[0095] Please refer to Fig.10 , which is different from the specific circuit structure of the specific embodiment 1, the write unit also includes a first pre-charge control switch T4, and the reference voltage connection end is used to connect the reference electrode, wherein the reference voltage connection end of the odd-numbered row write unit is connected to the first reference electrode Com_Odd, and the reference voltage connection end of the even-numbered row write unit is connected to the second reference electrode Com_Even. The first pre-charge control switch T4 is a MOS tube, the gate is connected to the scan signal input end, one source and drain are connected to the pre-charge node, and the other source and drain are connected to the reference voltage connection end. The first control circuit includes a signal write switch T1 and a first pre-charge control switch T4.

[0096] In this specific embodiment, the Vdata signal is not used to provide the initialization write signal, but is provided by the first reference signal Vcom_Odd and the second reference signal Vcom_Even, so that the initialization process of the first signal storage capacitor Cs1 under the row inversion drive can be realized. Fig.11 , can achieve similar technical effects as the first embodiment, but compared with the first embodiment, the advantage is that the peripheral control circuit can be simplified and the additional required signals VREF1 / VREF2 can be reduced. Similarly, Vcom_Odd and Vcom_Even can also be routed according to odd and even columns, and the initialization process of the first signal storage capacitor Cs1 in the column inversion mode can also be realized, which will not be repeated here. Specific embodiment three

[0098] Please refer to Fig.12 , which is different from the specific circuit structure of the specific embodiment 1, the write unit also includes a second pre-charge control switch T5 and a pre-charge signal control terminal, and the pre-charge control signal input terminal is used to connect the pre-charge control signal line, wherein the pre-charge control signal input terminal of the odd-numbered column write unit is used to connect the first control signal line VREF_Odd, and the pre-charge control signal input terminal of the even-numbered column write unit is used to connect the second control signal line VREF_Even. The second pre-charge control switch T5 is a MOS tube, the gate is connected to the scan signal input terminal, one source and drain are connected to the pre-charge node, and the other source and drain are connected to the pre-charge control signal input terminal. The first control circuit includes a signal write switch T1 and a second pre-charge control switch T5.

[0099] In this specific embodiment, the Vdata signal is not shared to provide the initialization write signal, but an additional global signal (the first control signal line VREF_Odd and the second control signal line VREF_Even) is used as a signal source, so that the initialization process of the first signal storage capacitor Cs1 under column inversion driving can be realized. Fig.13, can achieve similar technical effects as the specific embodiment 1, but compared with the specific embodiment 1, the advantage is that the peripheral control circuit can be simplified and the additional required signals VREF1 / VREF2 can be reduced. Similarly, the first control signal line VREF_Odd and the second control signal line VREF_Even can also be routed according to odd and even rows, and the initialization process of the first signal storage capacitor Cs1 in the row inversion mode can also be realized, which will not be repeated here.

[0100] In one embodiment of the present application, a display device is provided, which includes the display data writing circuit in any one of the above embodiments. Based on the display data writing circuit in the above embodiments, the refresh rate and resolution of the display device can be higher.

[0101] In one embodiment of the present application, a computer-readable storage medium is provided. A program is stored on the storage medium. The stored program includes a display data writing method that can be loaded by a processor and process any one of the above embodiments.

[0102] Those skilled in the art will appreciate that all or part of the functions of the various methods in the above-mentioned embodiments can be implemented by hardware or by computer programs. When all or part of the functions in the above-mentioned embodiments are implemented by computer programs, the program can be stored in a computer-readable storage medium, and the storage medium can include: read-only memory, random access memory, disk, optical disk, hard disk, etc., and the program is executed by a computer to implement the above-mentioned functions. For example, the program is stored in the memory of the device, and when the program in the memory is executed by the processor, all or part of the above-mentioned functions can be implemented. In addition, when all or part of the functions in the above-mentioned embodiments are implemented by computer programs, the program can also be stored in a storage medium such as a server, another computer, disk, optical disk, flash disk or mobile hard disk, and can be downloaded or copied and saved in the memory of the local device, or the system of the local device is updated, and when the program in the memory is executed by the processor, all or part of the functions in the above-mentioned embodiments can be implemented.

[0103] The above specific examples are used to illustrate the present invention, which is only used to help understand the present invention and is not intended to limit the present invention. For those skilled in the art, according to the concept of the present invention, some simple deductions, modifications or substitutions can be made.

Claims

1. A method for writing display data, characterized in that: include: Initialize and store the intermediate voltage. During the backlight on time of the current frame display picture, for all pixels of the display device, synchronize and initialize and store the intermediate voltage, wherein the intermediate voltages of the pixels with the same voltage polarity of the data signal of the next frame are configured to be the same. Pre-storing the data signal voltage, after the intermediate voltage is initialized, within the backlight on time of the current frame, for all pixels of the display device, pre-storing the data signal voltage required for the next frame of display picture on a row-by-row basis based on the intermediate voltage stored in the initialization; Resetting the pixel data voltage: after the backlight of the current frame display picture is turned off, resetting the pixel data voltage of the current frame display picture to the common electrode voltage; The data signal voltage is read, and after the pixel data voltage of the current frame display picture is reset to the common electrode voltage, the pre-stored data signal voltage is synchronously read for all pixel points of the display device for displaying the next frame display picture.

2. The display data writing method according to claim 1, characterized in that: The intermediate voltage is an average value of the data signal voltage with the largest difference from the common electrode voltage Vcom and Vcom at the corresponding polarity of each pixel in the next frame.

3. A display data writing circuit, characterized in that: It includes a first control circuit, a second control circuit, a third control circuit, a first signal storage capacitor Cs1 and a pixel capacitor Clc; Based on the first control circuit, during the backlight on time of the current frame display picture, in the initialization writing stage, the first signal storage capacitors Cs1 corresponding to all the pixels are synchronously controlled to initialize and store the intermediate voltage, wherein the intermediate voltages of the pixels with the same polarity of the data signal voltage of the next frame are configured to be the same; in the data writing stage after the initialization writing stage, the first signal storage capacitors Cs1 corresponding to all the pixels of the display device are controlled to pre-store the data signal voltage required for the next frame display picture on the basis of the initialization stored intermediate voltage row by row; Based on the second control circuit, after the backlight of the current frame display picture is turned off, the pixel data voltage of the current frame display picture in the pixel capacitor Clc corresponding to all the pixel points is reset to the common electrode voltage; Based on the third control circuit, for all pixels of the display device, the data signal voltage pre-stored in the first signal storage capacitor Cs1 corresponding to all pixels is synchronously read into the pixel capacitor Clc for displaying the next frame of the display picture.

4. The display data writing circuit according to claim 3, characterized in that: The writing circuit includes a pixel point data voltage writing array, and the pixel point data voltage writing array includes a plurality of pixel point data voltage writing units, each writing unit corresponding to a pixel point; For each writing unit, it includes a scanning signal input terminal, a data signal voltage input terminal, a reset signal terminal, a reference potential connection terminal, a pre-stored data signal voltage transfer control terminal, a signal writing switch T1, a signal transfer switch T2, a reset switch T3, a first signal storage capacitor Cs1 and a pixel capacitor Clc; The scan signal input terminal is used to connect the scan signal line Scan, and the scan signal input terminals of the write units in different rows are connected to different scan signal lines; the data signal voltage input terminal is used to connect the data signal voltage line Data, and the data signal voltage input terminals of the write units in different columns are connected to different data signal voltage lines; the reset signal terminal is used to connect the reset signal line Reset, the reference voltage connection terminal is used to connect the reference electrode Com, and the pre-stored data signal voltage transfer control terminal is used to control the connection data signal voltage transfer control signal line Tran; the signal write switch T1, the signal transfer switch T2 and the reset switch T3 are all MOS tubes; The gate of the signal writing switch T1 is connected to the scanning signal input terminal, and one source and drain are connected to the data signal voltage input terminal; the other source and drain of the signal writing switch T1 is connected to a source and drain of the signal transfer switch T2, and the connection node between them is used as a pre-charge node; one end of the first signal storage capacitor Cs1 is connected to the pre-charge node, and the other end is connected to a fixed potential, and the fixed potential includes any one of the scanning signal input terminal, the reference voltage connection terminal and the pre-stored data signal voltage transfer control terminal; The gate of the signal transfer switch T2 is connected to the pre-stored data signal voltage transfer control terminal; the other source and drain of the signal transfer switch T2 is connected to a source and drain of the reset switch T3, and the connection point between them is used as a pixel electrode node; the gate of the reset switch T3 is connected to the reset signal input terminal, and the other source and drain is connected to the reference voltage connection terminal; one end of the pixel capacitor Clc is connected to the pixel electrode node, and the other end is connected to the reference voltage connection terminal; The second control circuit includes a reset switch T3, and the third control circuit includes a signal transfer switch T2; There are multiple scanning signal lines Scan, and the multiple scanning signal lines Scan are connected to multiple rows of the pixel point data voltage writing array in a one-to-one correspondence; there are multiple data signal voltage lines Data, and the multiple data signal voltage lines Data are connected to multiple columns of the pixel point data voltage writing array in a one-to-one correspondence; The first control circuit includes a write switch T1, a plurality of scan signal switches and a plurality of data voltage switches; The plurality of scan signal switches correspond to the plurality of scan signal enable input terminals and the plurality of scan signal enable output terminals one by one, the plurality of scan signal enable input terminals are used to connect to the scan signal enable line En_Scan, and the plurality of scan signal enable output terminals are used to connect to the scan signal lines Scan corresponding thereto respectively; any scan signal switch is a MOS transistor, a gate of the MOS transistor is connected to the scan signal enable input terminal corresponding thereto, a source and drain are connected to the scan signal enable output terminal corresponding thereto, and the other source and drain are connected to the high level signal line VGH, the high level signal line VGH is used to provide a high potential when the scan signal line Scan works normally, so as to open the write switch T1; The multiple data voltage switches correspond one-to-one to the multiple input voltage enable input terminals and the multiple input voltage enable output terminals, the multiple input voltage enable input terminals are used to connect to the data voltage signal enable line En_Data, and the multiple input voltage enable output terminals are used to connect to the corresponding data signal voltage lines Data respectively; for any data voltage switch, it is a MOS tube, the gate of the MOS tube is connected to the corresponding voltage enable input terminal, one source and drain is connected to the corresponding voltage enable output terminal, and the other source and drain is connected to the corresponding reference voltage VREF; wherein, the data voltage switches of odd columns are connected to the first reference voltage VREF1, and the data voltage switches of even columns are connected to the second reference voltage VREF2.

5. The display data writing circuit according to claim 3, characterized in that: The writing circuit includes a pixel point data voltage writing array, the pixel point data voltage writing array includes a plurality of pixel point data voltage writing units, each writing unit corresponds to a pixel point; For each writing unit, it includes a scanning signal input terminal, a data signal voltage input terminal, a reset signal terminal, a reference potential connection terminal, a pre-stored data signal voltage transfer control terminal, a signal writing switch T1, a signal transfer switch T2, a reset switch T3, a first pre-charge control switch T4, a first signal storage capacitor Cs1 and a pixel capacitor Clc; The scan signal input terminal is used to connect the scan signal line Scan, and the scan signal input terminals of the write units in different rows are connected to different scan signal lines; the data signal voltage input terminal is used to connect the data signal voltage line Data, and the data signal voltage input terminals of the write units in different columns are connected to different data signal voltage lines; the reset signal terminal is used to connect the reset signal line Reset, and the pre-stored data signal voltage transfer control terminal is used to control the data signal voltage transfer control signal line Tran; the reference voltage connection terminal is used to connect the reference electrode, wherein the reference voltage connection terminal of the write unit in the odd rows is connected to the first reference electrode Com_Odd, and the reference voltage connection terminal of the write unit in the even rows is connected to the second reference electrode Com_Even; the signal write switch T1, the signal transfer switch T2, the reset switch T3 and the first pre-charge control switch T4 are all MOS tubes; The gate of the signal writing switch T1 is connected to the scanning signal input terminal, and one source and drain are connected to the data signal voltage input terminal; the other source and drain of the signal writing switch T1 is connected to a source and drain of the signal transfer switch T2, and the connection node between them is used as a pre-charge node; one end of the first signal storage capacitor Cs1 is connected to the pre-charge node, and the other end is connected to a fixed potential, and the fixed potential includes any one of the scanning signal input terminal, the reference voltage connection terminal and the pre-stored data signal voltage transfer control terminal; The gate of the signal transfer switch T2 is connected to the pre-stored data signal voltage transfer control terminal; the other source and drain of the signal transfer switch T2 is connected to a source and drain of the reset switch T3, and the connection point between them is used as a pixel electrode node; the gate of the reset switch T3 is connected to the reset signal input terminal, and the other source and drain is connected to the reference voltage connection terminal; one end of the pixel capacitor Clc is connected to the pixel electrode node, and the other end is connected to the reference voltage connection terminal; The gate of the first pre-charge control switch T4 is connected to the scan signal input terminal, one source and drain is connected to the pre-charge node, and the other source and drain is connected to the reference voltage connection terminal. The first control circuit includes a signal writing switch T1 and a first pre-charge control switch T4, the second control circuit includes a reset switch T3, and the third control circuit includes a signal transfer switch T2.

6. The display data writing circuit according to claim 3, characterized in that: The writing circuit includes a pixel point data voltage writing array, the pixel point data voltage writing array includes a plurality of pixel point data voltage writing units, each writing unit corresponds to a pixel point; For each writing unit, it includes a scanning signal input terminal, a data signal voltage input terminal, a reset signal terminal, a reference potential connection terminal, a pre-stored data signal voltage transfer control terminal, a pre-charge control signal input terminal, a signal writing switch T1, a signal transfer switch T2, a reset switch T3, a second pre-charge control switch T5, a first signal storage capacitor Cs1 and a pixel capacitor Clc; The scan signal input terminal is used to connect the scan signal line Scan, and the scan signal input terminals of the write units in different rows are connected to different scan signal lines; the data signal voltage input terminal is used to connect the data signal voltage line Data, and the data signal voltage input terminals of the write units in different columns are connected to different data signal voltage lines; the reset signal terminal is used to connect the reset signal line Reset, and the pre-stored data signal voltage transfer control terminal is used to control the data signal voltage transfer control signal line Tran; the reference voltage connection terminal is used to connect the reference electrode Com; the pre-charge control signal input terminal is used to connect the pre-charge control signal line, wherein the pre-charge control signal input terminal of the write unit in the odd columns is used to connect the first control signal line VREF_Odd, and the pre-charge control signal input terminal of the write unit in the even columns is used to connect the second control signal line VREF_Even; the signal write switch T1, the signal transfer switch T2, the reset switch T3 and the second pre-charge control switch T5 are all MOS tubes; The gate of the signal writing switch T1 is connected to the scanning signal input terminal, and one source and drain are connected to the data signal voltage input terminal; the other source and drain of the signal writing switch T1 is connected to a source and drain of the signal transfer switch T2, and the connection node between them is used as a pre-charge node; one end of the first signal storage capacitor Cs1 is connected to the pre-charge node, and the other end is connected to a fixed potential, and the fixed potential includes any one of the scanning signal input terminal, the reference voltage connection terminal and the pre-stored data signal voltage transfer control terminal; The gate of the signal transfer switch T2 is connected to the pre-stored data signal voltage transfer control terminal; the other source and drain of the signal transfer switch T2 is connected to a source and drain of the reset switch T3, and the connection point between them is used as a pixel electrode node; the gate of the reset switch T3 is connected to the reset signal input terminal, and the other source and drain is connected to the reference voltage connection terminal; one end of the pixel capacitor Clc is connected to the pixel electrode node, and the other end is connected to the reference voltage connection terminal; The gate of the second pre-charge control switch T5 is connected to the scan signal input terminal, one source and drain is connected to the pre-charge node, and the other source and drain is connected to the pre-charge control signal input terminal. The first control circuit includes a signal writing switch T1 and a second pre-charge control switch T5, the second control circuit includes a reset switch T3, and the third control circuit includes a signal transfer switch T2.

7. The display data writing circuit according to claim 3, characterized in that: The writing unit further includes a second signal storage capacitor Cs2, one end of which is connected to the pixel-level node, and the other end of which is connected to the fixed potential.

8. The display data writing circuit according to claim 3, characterized in that: The intermediate voltage is an average value of the data signal voltage with the largest difference from the common electrode voltage Vcom and Vcom at the corresponding polarity of each pixel in the next frame.

9. The display data writing circuit according to claim 3, characterized in that: The signal writing switch T1, signal transfer switch T2 and reset switch T3 are all NMOS tubes.

10. A display device, characterized in that: A display data writing circuit comprising the display data writing circuit as claimed in any one of claims 4 to 9.

11. A computer-readable storage medium, characterized in that: The medium stores a program, which can be loaded by a processor and execute the display data writing method according to any one of claims 1 to 2.

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