Memory device

Abstract

The invention relates to a divisional application of which the application number is 2021111607925. The invention discloses a memory device, the memory device comprises a first chip and a second chip, the second chip is stacked above the first chip along a third direction, the first chip comprises a memory array, the memory array comprises at least one memory block, and the memory block comprises at least one memory block. The second chip comprises a first local bit line decoder, a second local bit line decoder, a first word line decoder and a second word line decoder which are electrically connected with the storage block; a first local bit line decoder block, a second local bit line decoder block, a first word line decoder block and a second word line decoder block are constructed to be located in an overlook projection area of a storage block in a second chip, so that the occupied area after a first chip and a second chip are stacked can be reduced; and therefore, the plane occupied space of the memory device is reduced, and the minimum size of the memory device can be realized.

Description

[0001] This application is a divisional application of the invention patent with application number "2021111607925", application date "2021.09.30", and name "Memory device and preparation method thereof". Technical Field

[0002] The present application relates to the field of storage technology, and in particular to a storage device and a method for preparing the same. Background Art

[0003] like Figure 1 As shown, the memory device in the conventional technical solution includes a plurality of memory arrays 510, a plurality of local bit line decoders 520, a plurality of word line decoders 540, a plurality of global bit line decoders 530 and a peripheral circuit 550, wherein the construction area of ​​the memory array 510, the construction area of ​​the local bit line decoder 520, the construction area of ​​the word line decoder 540, the construction area of ​​the global bit line decoder 530 and the construction area of ​​the peripheral circuit 550 do not overlap with each other, for example, the construction area of ​​the local bit line decoder 520 is located on one side of the construction area of ​​the corresponding memory array 510, the word line decoder 540 is located on the other side of the construction area of ​​the corresponding local bit line decoder 520 and / or the construction area of ​​the memory array 510, and the construction area of ​​the global bit line decoder 530 is located between the construction area of ​​the corresponding local bit line decoder 520 and the construction area of ​​the peripheral circuit area 550.

[0004] Specifically, Figure 2 As shown, a memory block 511 in the memory array 510 is electrically connected to a local bit line decoder 520 through a plurality of first connection lines 531, and the memory block 511 is electrically connected to a word line decoder 540 through a plurality of second connection lines 532, wherein the local bit line decoder 520 is located on one side of the memory block 511, and the word line decoder 540 is located on the other side of the memory block 511. Similarly, Figure 2 The structural area of ​​the middle memory block 511, the structural area of ​​the local bit line decoder 520, and the structural area of ​​the word line decoder 540 also do not overlap with each other.

[0005] As such, the storage device in the above-mentioned conventional technical solution needs to occupy a relatively large space to integrate the above-mentioned various structures, which is not conducive to minimizing the size of the storage device.

[0006] It should be noted that the above introduction to the background technology is only for the purpose of facilitating a clear and complete understanding of the technical solution of the present application. Therefore, it cannot be considered that the above technical solution is well known to those skilled in the art simply because it appears in the background technology of the present application. Summary of the invention

[0007] The present application provides a memory device and a method for preparing the same, so as to alleviate the technical problem that the memory device needs to occupy a large space.

[0008] In a first aspect, the present application provides a memory device, comprising a first chip and a second chip, wherein the second chip is stacked on top of the first chip along a third direction, the first chip comprises a memory array, the memory array comprises at least one memory block, the memory block comprises a plurality of word lines extending along a first direction and a plurality of bit lines extending along a second direction; the second chip comprises a first local bit line decoder, a second local bit line decoder, a first word line decoder and a second word line decoder electrically connected to the memory block, the second chip has a top-view projection area of ​​the memory block, and the first local bit line decoder, the second local bit line decoder, the first word line decoder and the second word line decoder respectively form a first local bit line decoder block, a second local bit line decoder block, a first word line decoder block and a second word line decoder block that do not overlap each other in the top-view projection area.

[0009] In some embodiments, in the first direction, the sum of the first length of the first local bit line decoder block and the second length of the second local bit line decoder block is less than or equal to the length of the top-view projection area, and the projections of the first local bit line decoder block and the second local bit line decoder block in the second direction do not overlap each other; in the second direction, the sum of the third length of the first word line decoder block and the fourth length of the second word line decoder block is less than or equal to the width of the top-view projection area, and the projections of the first word line decoder block and the second word line decoder block in the first direction do not overlap each other.

[0010] In some embodiments, the first length is different from the second length; and the third length is different from the fourth length.

[0011] In some embodiments, a portion of the plurality of bit lines is electrically connected to a first local bit line decoder, and another portion of the plurality of bit lines is electrically connected to a second local bit line decoder; a portion of the plurality of word lines is electrically connected to a first word line decoder, and another portion of the plurality of word lines is electrically connected to a second word line decoder.

[0012] In some embodiments, in the first direction, the first word line decoder block is located between the first edge of the top-view projection area extending along the second direction and the first local bit line decoder block, and the width of the first local bit line decoder block in the second direction is less than the length of the first word line decoder block in the second direction; in the second direction, the first word line decoder block is located between the second edge of the top-view projection area extending along the first direction and the second local bit line decoder block, and the length of the second local bit line decoder block in the first direction is greater than the width of the first word line decoder block in the first direction.

[0013] In some embodiments, in the first direction, the second word line decoder block is located between the third edge of the top-view projection area extending along the second direction and the second local bit line decoder block, and the width of the second local bit line decoder block in the second direction is less than the length of the second word line decoder block in the second direction; in the second direction, the second word line decoder block is located between the fourth edge of the top-view projection area extending along the first direction and the first local bit line decoder block, and the length of the first local bit line decoder block in the first direction is greater than the width of the second word line decoder block in the first direction.

[0014] In some embodiments, the first local bit line decoder and the second local bit line decoder each have a plurality of first transmission terminals, and a first transmission terminal is electrically connected to a bit line through a first through silicon via or a pair of first bonding pads.

[0015] In some embodiments, the first word line decoder and the second word line decoder each have a plurality of second transmission terminals, and a second transmission terminal is electrically connected to a word line through a second through silicon via or a pair of second bonding pads.

[0016] In some embodiments, the first chip includes a first bonding layer, the first bonding layer includes at least one first bonding pad and / or a second bonding pad; the second chip includes a second bonding layer, the second bonding layer includes at least one first bonding pad and / or a second bonding pad; the first bonding pad located in the first bonding layer is bonded to the first bonding pad located in the second bonding layer, and / or the second bonding pad located in the first bonding layer is bonded to the second bonding pad located in the second bonding layer.

[0017] In some embodiments, the top-view projection area is rectangular, the first local bit line decoder block is located at one of the first right angle or the third right angle of the top-view projection area, and the second local bit line decoder block is located at the other of the first right angle or the third right angle of the top-view projection area; the first word line decoder block is located at one of the second right angle or the fourth right angle of the top-view projection area, and the second word line decoder block is located at the other of the second right angle or the fourth right angle of the top-view projection area; or, the first local bit line decoder block is located at one of the second right angle or the fourth right angle of the top-view projection area, and the second local bit line decoder block is located at the other of the second right angle or the fourth right angle of the top-view projection area; the first word line decoder block is located at one of the first right angle or the third right angle of the top-view projection area, and the second word line decoder block is located at the other of the first right angle or the third right angle of the top-view projection area; wherein the first right angle and the third right angle are respectively located at two ends of a diagonal of the top-view projection area, and the second right angle and the fourth right angle are respectively located at two ends of another diagonal of the top-view projection area.

[0018] In some embodiments, in the first direction, the first word line decoder block is located between the left end of the second local bit line decoder block and the left end of the first local bit line decoder block; in the first direction, the second word line decoder block is located between the right end of the first local bit line decoder block and the right end of the second local bit line decoder block.

[0019] In some embodiments, in the second direction, the first local bit line decoder block is located between the upper end of the first word line decoder block and the upper end of the second word line decoder block; in the second direction, the second local bit line decoder block is located between the lower end of the second word line decoder block and the lower end of the first word line decoder block.

[0020] In some embodiments, in the first direction, the length of the first local bit line decoder block and the length of the second local bit line decoder block are both less than or equal to the length of the top-view projection area; in the second direction, the first word line decoder block is located between the first local bit line decoder block and the second local bit line decoder block, and the second word line decoder block is located between the first local bit line decoder block and the second local bit line decoder block.

[0021] In some embodiments, in the second direction, the length of the first word line decoder block and the length of the second word line decoder block are both less than or equal to the width of the top-view projection area; in the first direction, the first local bit line decoder block is located between the first word line decoder block and the second word line decoder block, and the second local bit line decoder block is located between the first word line decoder block and the second word line decoder block.

[0022] In a second aspect, the present application provides a method for preparing a memory device, comprising: constructing a memory array on a first chip, the memory array comprising at least one memory block, the memory block comprising a plurality of word lines extending along a first direction and a plurality of bit lines extending along a second direction; constructing a first local bit line decoder, a second local bit line decoder, a first word line decoder and a second word line decoder on a second chip, the second chip having a top-view projection area of ​​the memory block, the first local bit line decoder, the second local bit line decoder, the first word line decoder and the second word line decoder being electrically connected to the memory block, and forming a first local bit line decoder block, a second local bit line decoder block, a first word line decoder block and a second word line decoder block that are not overlapped with each other in the top-view projection area; and stacking the second chip on top of the first chip along a third direction.

[0023] In some embodiments, the preparation method further includes: in the first direction, the sum of the first length of the first local bit line decoder block and the second length of the second local bit line decoder block is less than or equal to the length of the top-view projection area, and the projections of the first local bit line decoder block and the second local bit line decoder block in the second direction do not overlap each other; in the second direction, the sum of the third length of the first word line decoder block and the fourth length of the second word line decoder block is less than or equal to the width of the top-view projection area, and the projections of the first word line decoder block and the second word line decoder block in the second direction do not overlap each other.

[0024] In some of the embodiments, the preparation method also includes: electrically connecting a portion of the multiple bit lines to a first local bit line decoder; electrically connecting another portion of the multiple bit lines to a second local bit line decoder; electrically connecting a portion of the multiple word lines to a first word line decoder; and electrically connecting another portion of the multiple word lines to a second word line decoder.

[0025] In some embodiments, the preparation method also includes: constructing a first bonding layer on the first chip; constructing a second bonding layer on the second chip; and stacking the second chip on top of the first chip, and forming a bonding structure through the first bonding layer and the second bonding layer to electrically connect the first chip and the second chip.

[0026] The memory device and preparation method provided in the present application can reduce the occupied area of ​​the first chip and the second chip after stacking by constructing a first local bit line decoder block, a second local bit line decoder block, a first word line decoder block and a second word line decoder block to be located in the top view projection area of ​​the memory block of the second chip, thereby reducing the plane occupied space of the memory device and helping to minimize the size of the memory device.

[0027] In the first direction, the first length of the first local bit line decoder block and the second length of the second local bit line decoder block are less than or equal to the length of the top-view projection area, and the projections of the first local bit line decoder block and the second local bit line decoder block in the second direction do not overlap each other; in the second direction, the third length of the first word line decoder block and the fourth length of the second word line decoder block are less than or equal to the width of the top-view projection area, and the first word line decoder block and the second word line decoder block do not overlap each other in the first direction, so as to facilitate the corresponding electrical connection between the word lines, bit lines and the first local bit line decoder, the second local bit line decoder, the first word line decoder and the second word line decoder in the storage block, and the first local bit line decoder, the second local bit line decoder, the first word line decoder and the second word line decoder.

[0028] At the same time, by constructing the first local bit line decoder block, the second local bit line decoder block, the first word line decoder block and the second word line decoder block so as not to overlap each other, the local bit line decoder block and the word line decoder block can be arranged within the projection range of the memory array / memory block, thereby reducing the cross-relationship of the electrical connections in the second chip, further reducing the chip size, and facilitating the second chip to achieve electrical connection with the first chip with a thinner thickness.

[0029] Since the word line decoder and / or the bit line decoder are divided into two sub-modules, the word line decoder and the bit line decoder can all be set within the projection range of the storage array / storage block. Based on the setting of the decoder completely within the projection range and the stacking structure of the two chips, the decoder can be vertically connected to the storage array without being connected through additional horizontal wiring. Therefore, no wiring space is required between the two sub-modules, which can further reduce the area of ​​the first chip and the second chip. BRIEF DESCRIPTION OF THE DRAWINGS

[0030] The technical solution and other beneficial effects of the present application will be made apparent by describing in detail the specific implementation methods of the present application in conjunction with the accompanying drawings.

[0031] Figure 1 A schematic diagram of the distribution of the structures of various parts in a storage device provided by a conventional technical solution.

[0032] Figure 2 Another schematic diagram of the distribution of the various parts of the storage device provided by the traditional technical solution.

[0033] Figure 3 A schematic diagram of the first structural distribution of the storage device provided in an embodiment of the present application.

[0034] Figure 4 A schematic diagram of a second structural distribution of a storage device provided in an embodiment of the present application.

[0035] Figure 5 A schematic diagram of a third structural distribution of the storage device provided in an embodiment of the present application.

[0036] Figure 6 A schematic diagram of a fourth structural distribution of the storage device provided in an embodiment of the present application.

[0037] Figure 7 A fifth structural distribution diagram of the storage device provided in the embodiment of the present application.

[0038] Figure 8 A schematic flow chart of a method for preparing a storage device provided in an embodiment of the present application. DETAILED DESCRIPTION

[0039] The technical solutions in the embodiments of the present application will be described clearly and completely below in conjunction with the drawings in the embodiments of the present application. Obviously, the described embodiments are only part of the embodiments of the present application, rather than all of the embodiments. Based on the embodiments in the present application, all other embodiments obtained by those skilled in the art without creative work are within the scope of protection of the present application.

[0040] In the description of the present disclosure, the word line decoder is also described as X-DEC, and the bit line decoder can be described as a bit line selector, a bit line multiplexer or a Y-MUX, which is used to locate the majority of memory cells in the memory array for further reading and writing operations on the memory cells.

[0041] In the description of the present disclosure, it should be understood that the terms "center", "longitudinal", "lateral", "length", "width", "thickness", "up", "down", "front", "back", "left", "right", "vertical", "horizontal", "top", "bottom", "inside", "outside", "clockwise", "counterclockwise" and the like indicating the orientation or position relationship indicated are all based on the orientation or position relationship shown in the accompanying drawings, and are only for the convenience of simplifying the description of the present disclosure, rather than indicating or implying that the device or component referred to must have a specific orientation, be constructed and operated in a specific orientation, and therefore cannot be understood as a limitation of the present disclosure. In addition, the terms "first" and "second" are only used for descriptive purposes, and cannot be understood as indicating or implying relative importance or implicitly indicating the number of technical features indicated. Therefore, the features defined as "first" and "second" may explicitly or implicitly include one or more of the said features. In the description of the present disclosure, the meaning of "multiple" is two or more, unless otherwise clearly and specifically defined.

[0042] In the description of the present disclosure, it should be noted that, unless otherwise clearly specified and limited, the terms "installed", "connected", and "connected" should be understood in a broad sense, for example, it can be a fixed connection, a detachable connection, or an integral connection; it can be a mechanical connection, an electrical connection, or can communicate with each other; it can be a direct connection, or it can be indirectly connected through an intermediate medium, it can be the internal connection of two components or the interaction relationship between two components. For ordinary technicians in this field, the specific meanings of the above terms in the present disclosure can be understood according to specific circumstances.

[0043] In the present disclosure, unless otherwise clearly specified and limited, a first feature being “above” or “below” a second feature may include the first feature being in direct contact with the second feature, or may include the first feature being in contact with the second feature not being in direct contact but being in contact through a third feature other than the first feature. Moreover, a first feature being “above”, “above”, and “above” a second feature may include the first feature being directly above and obliquely above the second feature, or may simply mean that the first feature is higher in level than the second feature. A first feature being “below”, “below”, and “below” a second feature may include the first feature being directly below and obliquely below the second feature, or may simply mean that the first feature is lower in level than the second feature.

[0044] See also Figures 3 to 8 The present embodiment provides a memory device, which includes a first chip 100 and a second chip 200. The second chip 200 is stacked on the first chip 100 along a third direction DR3. The first chip 100 includes a memory array 10. The memory array 10 includes at least one memory block 11. The memory block 11 includes a plurality of word lines extending along a first direction DR1 and a plurality of bit lines extending along a second direction DR2. The second chip 200 includes a first local bit line decoder, a second local bit line decoder, a first word line decoder, and a second word line decoder electrically connected to the memory block 11. The second chip 200 has a top-view projection area of ​​the memory block 11, and the first local bit line decoder, the second local bit line decoder, the first word line decoder, and the second word line decoder respectively form a first local bit line decoder block, a second local bit line decoder block, a first word line decoder block, and a second word line decoder block that do not overlap each other in the top-view projection area.

[0045] It can be understood that the memory device provided in this embodiment can reduce the occupied area of ​​the first chip 100 and the second chip 200 after being stacked by constructing the first local bit line decoder block, the second local bit line decoder block, the first word line decoder block and the second word line decoder block to be located in the top view projection area of ​​the second chip 200, thereby reducing the planar occupied space of the memory device and helping to minimize the size of the memory device.

[0046] In the first direction DR1, the sum of the first length of the first local bit line decoder block and the second length of the second local bit line decoder block is less than or equal to the length of the top projection area, and the projections of the first local bit line decoder block and the second local bit line decoder block in the second direction DR2 do not overlap each other; in the second direction DR2, the sum of the third length of the first word line decoder block and the fourth length of the second word line decoder block is less than or equal to the width of the top projection area, and the projections of the first word line decoder block and the second word line decoder block in the second direction DR1 do not overlap each other. In this way, it is convenient to realize the corresponding electrical connection between the word lines and bit lines in the storage block 11 and the first local bit line decoder 21, the second local bit line decoder 22, the first word line decoder 31 and the second word line decoder 32, and the first local bit line decoder 21, the second local bit line decoder 22, the first word line decoder 31 and the second word line decoder 32.

[0047] At the same time, by constructing the first local bit line decoder block, the second local bit line decoder block, the first word line decoder block and the second word line decoder block so as not to overlap each other, the cross-relationship of the electrical connections in the second chip 200 is reduced, which is beneficial for the second chip 200 to achieve electrical connection with the first chip 100 with a thinner thickness and reduce delay.

[0048] In one embodiment, a continuous portion of the plurality of bit lines is electrically connected to the first local bit line decoder 21, and another continuous portion of the plurality of bit lines is electrically connected to the second local bit line decoder 22; a continuous portion of the plurality of word lines is electrically connected to the first word line decoder 31, and another continuous portion of the plurality of word lines is electrically connected to the second word line decoder 32.

[0049] In one of the embodiments, in the first direction DR1, the first word line decoder block is located between the first edge of the top-view projection area extending along the second direction DR2 and the first local bit line decoder block, and the width of the first local bit line decoder block in the second direction DR2 is smaller than the length of the first word line decoder block in the second direction DR2; in the second direction DR2, the first word line decoder block is located between the second edge of the top-view projection area extending along the first direction DR1 and the second local bit line decoder block, and the length of the second local bit line decoder block in the first direction DR1 is greater than the width of the first word line decoder block in the first direction DR1.

[0050] In one of the embodiments, in the first direction DR1, the second word line decoder block is located between the third edge of the top-view projection area extending along the second direction DR2 and the second local bit line decoder block, and the width of the second local bit line decoder block in the second direction DR2 is smaller than the length of the second word line decoder block in the second direction DR2; in the second direction DR2, the second word line decoder block is located between the fourth edge of the top-view projection area extending along the first direction DR1 and the first local bit line decoder block, and the length of the first local bit line decoder block in the first direction DR1 is greater than the width of the second word line decoder block in the first direction DR1.

[0051] In one embodiment, the first local bit line decoder 21 and the second local bit line decoder 22 each have a plurality of first transmission terminals, and a first transmission terminal is electrically connected to a bit line through a first through silicon via or a pair of first bonding pads.

[0052] In one embodiment, the first word line decoder 31 and the second word line decoder 32 each have a plurality of second transmission terminals, and a second transmission terminal is electrically connected to a word line through a second through silicon via or a pair of second bonding pads.

[0053] Wherein, any transmission end may be, but is not limited to, a metal pad, such as a copper pad or a metal block.

[0054] It should be noted that the first edge may be one of the left edge or the right edge of the overhead projection area, and the third edge may be the other of the left edge or the right edge of the overhead projection area. The second edge may be one of the lower edge or the upper edge of the overhead projection area, and the fourth edge may be the other of the lower edge or the upper edge of the overhead projection area.

[0055] In one embodiment, the first chip 100 and the second chip 200 are electrically connected via a bonding structure, and the bonding structure includes a first bonding layer located on the first chip 100 and a second bonding layer located on the second chip 200 .

[0056] Specifically, the first chip includes a first bonding layer, the first bonding layer includes at least one first bonding pad and / or a second bonding pad; the second chip includes a second bonding layer, the second bonding layer includes at least one first bonding pad and / or a second bonding pad; the first bonding pad located in the first bonding layer is bonded to the first bonding pad located in the second bonding layer, and / or the second bonding pad located in the first bonding layer is bonded to the second bonding pad located in the second bonding layer.

[0057] It should be noted that, in the present embodiment, the first chip 100 and the second chip 200 can both achieve the required electrical connection through a bonding structure. Specifically, the conventional technology can be used to implement the specific bonding process, which will not be described in detail here.

[0058] like Figure 3 As shown, this embodiment provides a memory device, which includes a first chip 100 and a second chip 200, the first chip 100 includes a memory array 10, the memory array 10 includes at least one memory block 11, and the area where one memory block 11 is located is a top-view projection area; the second chip 200 includes a logic control circuit, the logic control circuit includes a first local bit line decoder 21 and a second local bit line decoder 22, one memory block 11 is electrically connected to the first local bit line decoder 21 and the second local bit line decoder 22, a first local bit line decoder block formed by the first local bit line decoder 21 at least partially overlaps with the top-view projection area, a second local bit line decoder block formed by the second local bit line decoder 22 at least partially overlaps with the top-view projection area, and the relative positions of the first local bit line decoder block and the second local bit line decoder block diagonally are set at a first diagonal.

[0059] It can be understood that the memory device provided in the present embodiment can reduce the occupied area of ​​the first chip 100 and the second chip 200 after being stacked by at least partially overlapping the top-view projection area formed by one of the memory blocks 11 with the first local bit line decoder block and the second local bit line decoder block, thereby reducing the occupied space of the memory device and helping to minimize the size of the memory device; and the relative positions of the first local bit line decoder block and the second local bit line decoder block are set at the first diagonal, so as to facilitate the electrical connection between one of the memory blocks 11 and the first local bit line decoder 21 and the second local bit line decoder 22.

[0060] The storage device may be, but is not limited to, NOR Flash, and may also be other types of storage chips.

[0061] It should be noted that each structural region and / or each sub-structural region may be, but is not limited to, a rectangular shape, a regular polygon, or a circular shape or other shapes.

[0062] The logic control circuit includes a local bit line decoder 20, which includes a first local bit line sub-decoder 20A, which includes a first local bit line decoder 21 and a second local bit line decoder 22. Any memory block 11 may be configured with a corresponding local bit line sub-decoder.

[0063] In one embodiment, one of the memory blocks 11 includes a plurality of bit lines, a portion of the plurality of bit lines is electrically connected to the first local bit line decoder 21 , and another portion of the plurality of bit lines is electrically connected to the second local bit line decoder 22 .

[0064] It should be noted that the plurality of bit lines may be arranged along the first direction DR1.

[0065] In one embodiment, one of the memory blocks 11 further includes a plurality of word lines, a portion of the plurality of word lines is electrically connected to the first local bit line decoder 21 , and another portion of the plurality of word lines is electrically connected to the second local bit line decoder 22 .

[0066] It should be noted that the plurality of word lines may be arranged along the second direction DR2.

[0067] In one embodiment, the thickness direction of the stacked first chip 100 and the second chip 200 may be defined as a third direction DR3.

[0068] like Figure 3 and Figure 4 As shown, in one embodiment, the first local bit line decoder block at least partially overlaps with the first upper right structural area or the first lower right structural area of ​​the overhead projection area; if the first local bit line decoder block at least partially overlaps with the first upper right structural area of ​​the overhead projection area, the second local bit line decoder block at least partially overlaps with the first lower left structural area of ​​the overhead projection area; if the first local bit line decoder block at least partially overlaps with the first lower right structural area of ​​the overhead projection area, the second local bit line decoder block at least partially overlaps with the first upper left structural area of ​​the overhead projection area.

[0069] In one embodiment, the first local bit line decoder block at least partially overlaps with the first upper left structural area or the first lower left structural area of ​​the overhead projection area; if the first local bit line decoder block at least partially overlaps with the first upper left structural area of ​​the overhead projection area, the second local bit line decoder block at least partially overlaps with the first lower right structural area of ​​the overhead projection area; if the first local bit line decoder block at least partially overlaps with the first lower left structural area of ​​the overhead projection area, the second local bit line decoder block at least partially overlaps with the first upper right structural area of ​​the overhead projection area.

[0070] In one embodiment, the logic control circuit further includes a first word line decoder 31 and a second word line decoder 32, wherein one storage block 11 is electrically connected to the first word line decoder 31 and the second word line decoder 32, a first word line decoder block formed by the first word line decoder 31 overlaps at least partially with the top-view projection area, a second word line decoder block formed by the second word line decoder 32 overlaps at least partially with the top-view projection area, and the relative positions of the first word line decoder block and the second word line decoder block are set at a second diagonal angle, wherein the second diagonal angle is different from the first diagonal angle.

[0071] It should be noted that the logic control circuit includes a word line decoder 30, which includes a first word line sub-decoder 30A, which includes a first word line decoder 31 and a second word line decoder 32. Each storage block 11 may be configured with a corresponding word line sub-decoder.

[0072] like Figure 3 and Figure 4 As shown, in one embodiment, the first word line decoder block at least partially overlaps with the second upper left structural area or the second lower left structural area of ​​the overhead projection area; if the first word line decoder block at least partially overlaps with the second upper left structural area of ​​the overhead projection area, the second word line decoder block at least partially overlaps with the second lower right structural area of ​​the overhead projection area; if the first word line decoder block at least partially overlaps with the second lower left structural area of ​​the overhead projection area, the second word line decoder block at least partially overlaps with the second upper right structural area of ​​the overhead projection area.

[0073] In one embodiment, the first word line decoder block at least partially overlaps with the second upper right structural area or the second lower right structural area of ​​the overhead projection area; if the first word line decoder block at least partially overlaps with the second upper right structural area of ​​the overhead projection area, the second word line decoder block at least partially overlaps with the second lower left structural area of ​​the overhead projection area; if the first word line decoder block at least partially overlaps with the second lower right structural area of ​​the overhead projection area, the second word line decoder block at least partially overlaps with the second upper left structural area of ​​the overhead projection area.

[0074] like Figure 3 and Figure 4As shown, in one embodiment, the present embodiment provides a memory device, which includes a first chip 100 and a second chip 200, the first chip 100 includes a memory array 10, the memory array 10 includes at least one memory block 11, and the area where one memory block 11 is located is a top-view projection area; the second chip 200 includes a logic control circuit, the logic control circuit includes a first word line decoder 31 and a second word line decoder 32, one memory block 11 is electrically connected to the first word line decoder 31 and the second word line decoder 32, a first word line decoder block formed by the first word line decoder 31 at least partially overlaps with the top-view projection area, a second word line decoder block formed by the second word line decoder 32 at least partially overlaps with the top-view projection area, and the relative positions of the first word line decoder block and the second word line decoder block are set at a second diagonal.

[0075] It can be understood that the memory device provided in the present embodiment can reduce the occupied area of ​​the first chip 100 and the second chip 200 after being stacked by at least partially overlapping the top-view projection area formed by one of the memory blocks 11 with the first word line decoder block and the second word line decoder block, thereby reducing the occupied space of the memory device and helping to minimize the size of the memory device; and the relative positions of the first word line decoder block and the second word line decoder block are set at the second diagonal, so as to facilitate the electrical connection between one of the memory blocks 11 and the first word line decoder 31 and the second word line decoder 32.

[0076] In one embodiment, the logic control circuit further includes a first local bit line decoder 21 and a second local bit line decoder 22, wherein a storage block 11 is electrically connected to the first local bit line decoder 21 and the second local bit line decoder 22, a first local bit line decoder block formed by the first local bit line decoder 21 at least partially overlaps with a top-view projection area, a second local bit line decoder block formed by the second local bit line decoder 22 at least partially overlaps with a top-view projection area, and the relative positions of the first local bit line decoder block and the second local bit line decoder block are set at a first diagonal angle, wherein the first diagonal angle is different from the second diagonal angle.

[0077] Specifically, the top-view projection area can be a rectangle, the first local bit line decoder block is located at one of the first right angle or the third right angle of the top-view projection area, and the second local bit line decoder block is located at the other of the first right angle or the third right angle of the top-view projection area; the first word line decoder block is located at one of the second right angle or the fourth right angle of the top-view projection area, and the second word line decoder block is located at the other of the second right angle or the fourth right angle of the top-view projection area. Alternatively, the first local bit line decoder block is located at one of the second right angle or the fourth right angle of the top-view projection area, and the second local bit line decoder block is located at the other of the second right angle or the fourth right angle of the top-view projection area; the first word line decoder block is located at one of the first right angle or the third right angle of the top-view projection area, and the second word line decoder block is located at the other of the first right angle or the third right angle of the top-view projection area. Wherein, the first right angle and the third right angle are respectively located at the two ends of a diagonal line of the top-view projection area, and the second right angle and the fourth right angle are respectively located at the two ends of another diagonal line of the top-view projection area.

[0078] In one embodiment, the first word line decoder 31 and the second word line decoder 32 may exchange their respective sub-structure regions.

[0079] In one embodiment, the first local bit line decoder 21 and the second local bit line decoder 22 may also exchange their respective sub-structure regions.

[0080] like Figure 5 As shown, in one embodiment, the positions of the first word line decoder block and the second word line decoder block can be flexibly set in the first direction DR1. For example, the first word line decoder block can be located between the left end of the second local bit line decoder block and the left end of the first local bit line decoder block in the first direction DR1, for example, can be externally connected to the first local bit line decoder block; similarly, the second word line decoder block can be located between the right end of the first local bit line decoder block and the right end of the second local bit line decoder block in the first direction DR1, for example, can be externally connected to the second local bit line decoder block.

[0081] The positions of the first local bit line decoder block and the second local bit line decoder block can be flexibly set in the second direction DR2. For example, the first local bit line decoder block can be located between the upper end of the first word line decoder block and the upper end of the second word line decoder block in the second direction DR2, for example, can be externally connected to the second word line decoder block; similarly, the second local bit line decoder block can be located between the lower end of the second word line decoder block and the lower end of the first word line decoder block in the second direction DR2, for example, can be externally connected to the first word line decoder block.

[0082] like Figure 6As shown, in one of the embodiments, in the first direction DR1, the length of the first local bit line decoder block and the length of the second local bit line decoder block are both less than or equal to the length of the top view projection area; in the second direction DR2, the first word line decoder block is located between the first local bit line decoder block and the second local bit line decoder block, and the second word line decoder block is located between the first local bit line decoder block and the second local bit line decoder block.

[0083] like Figure 7 As shown, in one of the embodiments, in the second direction DR2, the length of the first word line decoder block and the length of the second word line decoder block are both less than or equal to the width of the top-view projection area; in the first direction DR1, the first local bit line decoder block is located between the first word line decoder block and the second word line decoder block, and the second local bit line decoder block is located between the first word line decoder block and the second word line decoder block.

[0084] like Figure 8 As shown, in one embodiment, this embodiment provides a method for preparing a memory device, which includes the following steps:

[0085] Step S10: constructing a memory array on the first chip, the memory array comprising at least one memory block, the memory block comprising a plurality of word lines extending along a first direction and a plurality of bit lines extending along a second direction.

[0086] Step S20: construct a first local bit line decoder, a second local bit line decoder, a first word line decoder and a second word line decoder on a second chip, the second chip having a top-view projection area of ​​a storage block, the first local bit line decoder, the second local bit line decoder, the first word line decoder and the second word line decoder are electrically connected to the storage block, and form a first local bit line decoder block, a second local bit line decoder block, a first word line decoder block and a second word line decoder block in the top-view projection area, respectively, which are not overlapped with each other.

[0087] And step S30: stacking the second chip on the first chip along the third direction.

[0088] It can be understood that the preparation method provided in this embodiment can reduce the occupied area of ​​the first chip 100 and the second chip 200 after stacking by constructing the first local bit line decoder block, the second local bit line decoder block, the first word line decoder block and the second word line decoder block to be located in the top view projection area of ​​the storage block 11, thereby reducing the planar occupied space of the storage device and helping to minimize the size of the storage device.

[0089] In the first direction DR1, the sum of the first length of the first local bit line decoder block and the second length of the second local bit line decoder block is less than or equal to the length of the top-view projection area, and the projections of the first local bit line decoder block and the second local bit line decoder block in the second direction DR2 do not overlap with each other; in the second direction DR2, the sum of the third length of the first word line decoder block and the fourth length of the second word line decoder block is less than or equal to the width of the top-view projection area, and the projections of the first word line decoder block and the second word line decoder block in the second direction DR1 do not overlap with each other, which facilitates the corresponding electrical connection between the word lines and bit lines in the storage block 11 and the first local bit line decoder 21, the second local bit line decoder 22, the first word line decoder 31 and the second word line decoder 32, the first local bit line decoder 21, the second local bit line decoder 22, the first word line decoder 31 and the second word line decoder 32.

[0090] At the same time, by constructing the first local bit line decoder block, the second local bit line decoder block, the first word line decoder block and the second word line decoder block so as not to overlap each other, the cross-relationship of the electrical connections in the second chip 200 is reduced, which is beneficial for the second chip 200 to achieve electrical connection with the first chip 100 with a thinner thickness and reduce delay.

[0091] In one embodiment, the preparation method also includes: electrically connecting a continuous portion of the plurality of bit lines to a first local bit line decoder 21; electrically connecting another continuous portion of the plurality of bit lines to a second local bit line decoder 22; electrically connecting a continuous portion of the plurality of word lines to a first word line decoder 31; and electrically connecting another continuous portion of the plurality of word lines to a second word line decoder 32.

[0092] In one embodiment, the preparation method also includes: constructing a first bonding layer on the first chip 100; constructing a second bonding layer on the second chip 200; and stacking the second chip 200 on top of the first chip 100, and forming a bonding structure through the first bonding layer and the second bonding layer to electrically connect the first chip 100 and the second chip 200.

[0093] In one embodiment, the present embodiment provides a method for preparing a memory device, which comprises the following steps:

[0094] A memory array 10 is constructed on the first chip 100 . The memory array 10 includes at least one memory block 11 , wherein an area where one memory block 11 is located is a top-view projection area.

[0095] A logic control circuit is constructed on the second chip 200, and the logic control circuit includes a first local bit line decoder 21 and a second local bit line decoder 22. The area where the first local bit line decoder 21 is located is a first local bit line decoder block, and the area where the second local bit line decoder 22 is located is a second local bit line decoder block.

[0096] At least a portion of the stacked first local bit line decoder block is on a side of an upper right region of the top-view projection area, and / or at least a portion of the second local bit line decoder block is on a side of a lower left region of the top-view projection area, and the relative positions of the first local bit line decoder block and the second local bit line decoder block are set at a first diagonal.

[0097] It can be understood that the preparation method provided in this embodiment can reduce the occupied area of ​​the first chip 100 and the second chip 200 after being stacked by at least partially overlapping the top-view projection area formed by one of the storage blocks 11 with the first local bit line decoder block and the second local bit line decoder block, thereby reducing the occupied space of the storage device and helping to minimize the size of the storage device; and the relative positions of the first local bit line decoder block and the second local bit line decoder block are set at the first diagonal, so as to facilitate the electrical connection between one of the storage blocks 11 and the first local bit line decoder 21 and the second local bit line decoder 22.

[0098] In one embodiment, the preparation method further includes: constructing a plurality of bit lines in one of the memory blocks 11 ; configuring a portion of the plurality of bit lines to be electrically connected to a first local bit line decoder 21 ; and configuring another portion of the plurality of bit lines to be electrically connected to a second local bit line decoder 22 .

[0099] In one of the embodiments, the preparation method further includes: constructing a first word line decoder 31 and a second word line decoder 32 in a logic control circuit, wherein the area where the first word line decoder 31 is located is a first word line decoder block, and the area where the second word line decoder 32 is located is a second word line decoder block; configuring one of the storage blocks 11 to be electrically connected to the first word line decoder 31 and the second word line decoder 32; and stacking at least a portion of the first word line decoder block on one side of the upper left area of ​​the top-view projection area, and / or, at least a portion of the second word line decoder block on one side of the lower right area of ​​the top-view projection area, and setting the relative positions of the first word line decoder block and the second word line decoder block at a second diagonal angle, wherein the second diagonal angle is different from the first diagonal angle.

[0100] It should be noted that the projections of the first word line decoder block and the second word line decoder block in the first direction DR1 do not overlap each other. This means that along the first direction DR1, the first word line decoder block may have a projection of the first word line decoder block, and the second word line decoder block may have a projection of the second word line decoder block; and in the first direction DR1, the projection of the first word line decoder block and the projection of the second word line decoder block do not overlap each other on any plane perpendicular to the first direction DR1.

[0101] The projections of the first local bit line decoder block and the second local bit line decoder block in the second direction DR2 do not overlap each other. This means that along the second direction DR2, the first local bit line decoder block may have a projection of the first local bit line decoder block, and the second local bit line decoder block may have a projection of the second local bit line decoder block; and in the second direction DR2, the projection of the first local bit line decoder block and the projection of the second local bit line decoder block do not overlap each other on any plane perpendicular to the second direction DR2.

[0102] In the above embodiments, the description of each embodiment has its own emphasis. For parts that are not described in detail in a certain embodiment, reference can be made to the relevant descriptions of other embodiments.

[0103] The storage device and the preparation method thereof provided in the embodiments of the present application are introduced in detail above. Specific examples are used herein to illustrate the principles and implementation methods of the present application. The description of the above embodiments is only used to help understand the technical solution and the core idea of ​​the present application. Ordinary technicians in this field should understand that they can still modify the technical solutions recorded in the aforementioned embodiments, or replace some of the technical features therein with equivalents. However, these modifications or replacements do not make the essence of the corresponding technical solutions deviate from the scope of the technical solutions of the embodiments of the present application.

Claims

1. A storage device, characterized in that: include: A first chip, wherein the first chip includes a memory array, the memory array includes at least one memory block, and the memory block includes a plurality of word lines extending along a first direction and a plurality of bit lines extending along a second direction; a second chip, stacked on the first chip along a third direction, the second chip comprising a first local bit line decoder, a second local bit line decoder, a first word line decoder and a second word line decoder electrically connected to the memory block, the second chip having a top-view projection area of ​​the memory block, and the first local bit line decoder, the second local bit line decoder, the first word line decoder and the second word line decoder respectively forming a first local bit line decoder block, a second local bit line decoder block, a first word line decoder block and a second word line decoder block which are not overlapped with each other in the top-view projection area; In the first direction, the sum of the first length of the first local bit line decoder block and the second length of the second local bit line decoder block is equal to the length of the top-view projection area, and the projections of the first local bit line decoder block and the second local bit line decoder block in the second direction do not overlap each other; and / or, in the second direction, the sum of the third length of the first word line decoder block and the fourth length of the second word line decoder block is equal to the width of the top-view projection area, and the projections of the first word line decoder block and the second word line decoder block in the first direction do not overlap each other.

2. The memory device according to claim 1, wherein: The first length is different from the second length; and the third length is different from the fourth length.

3. The memory device according to claim 1, wherein: A portion of the plurality of bit lines is electrically connected to the first local bit line decoder, and another portion of the plurality of bit lines is electrically connected to the second local bit line decoder; A portion of the word lines is electrically connected to the first word line decoder, and another portion of the word lines is electrically connected to the second word line decoder.

4. The memory device according to claim 1, wherein: In the first direction, the second word line decoder block is located between the third edge of the top-view projection area extending along the second direction and the second local bit line decoder block, and the width of the second local bit line decoder block in the second direction is smaller than the length of the second word line decoder block in the second direction; in the second direction, the second word line decoder block is located between the fourth edge of the top-view projection area extending along the first direction and the first local bit line decoder block, and the length of the first local bit line decoder block in the first direction is greater than the width of the second word line decoder block in the first direction.

5. The memory device according to claim 3, wherein: The first local bit line decoder and the second local bit line decoder each have a plurality of first transmission terminals, and a first transmission terminal is electrically connected to a bit line through a first through silicon via or a pair of first bonding pads.

6. The memory device according to claim 5, characterized in that The first word line decoder and the second word line decoder each have a plurality of second transmission terminals, and a second transmission terminal is electrically connected to a word line through a second through silicon via or a pair of second bonding pads.

7. The storage device according to claim 5 or 6, characterized in that: The first chip includes a first bonding layer, the first bonding layer includes at least one of the first bonding pads and / or the second bonding pad; the second chip includes a second bonding layer, the second bonding layer includes at least one of the first bonding pads and / or the second bonding pad; the first bonding pad located in the first bonding layer is bonded to the first bonding pad located in the second bonding layer, and / or the second bonding pad located in the first bonding layer is bonded to the second bonding pad located in the second bonding layer.

8. The memory device according to claim 1, wherein: The top-view projection area is rectangular, the first local bit line decoder block is located at one of the first right angle or the third right angle of the top-view projection area, and the second local bit line decoder block is located at the other of the first right angle or the third right angle of the top-view projection area; the first word line decoder block is located at one of the second right angle or the fourth right angle of the top-view projection area, and the second word line decoder block is located at the other of the second right angle or the fourth right angle of the top-view projection area; Alternatively, the first local bit line decoder block is located at one of the second right angle or the fourth right angle of the top-view projection area, and the second local bit line decoder block is located at the other of the second right angle or the fourth right angle of the top-view projection area; the first word line decoder block is located at one of the first right angle or the third right angle of the top-view projection area, and the second word line decoder block is located at the other of the first right angle or the third right angle of the top-view projection area; The first right angle and the third right angle are respectively located at two ends of a diagonal line of the overhead projection area, and the second right angle and the fourth right angle are respectively located at two ends of another diagonal line of the overhead projection area.

9. The memory device according to claim 1, wherein: In the first direction, the first word line decoder block is located between the left end of the second local bit line decoder block and the left end of the first local bit line decoder block; In the first direction, the second word line decoder block is located between the right end of the first local bit line decoder block and the right end of the second local bit line decoder block.

10. The memory device according to claim 1, wherein: In the second direction, the first local bit line decoder block is located between the upper end of the first word line decoder block and the upper end of the second word line decoder block; In the second direction, the second local bit line decoder block is located between a lower end of the second word line decoder block and a lower end of the first word line decoder block.

11. The memory device according to claim 1, wherein: In the first direction, the length of the first local bit line decoder block and the length of the second local bit line decoder block are both less than or equal to the length of the top-view projection area; in the second direction, the first word line decoder block is located between the first local bit line decoder block and the second local bit line decoder block, and the second word line decoder block is located between the first local bit line decoder block and the second local bit line decoder block.

12. The memory device according to claim 1, wherein: In the second direction, the length of the first word line decoder block and the length of the second word line decoder block are both less than or equal to the width of the top-view projection area; in the first direction, the first local bit line decoder block is located between the first word line decoder block and the second word line decoder block, and the second local bit line decoder block is located between the first word line decoder block and the second word line decoder block.

13. A storage device, characterized in that: include: A first chip, wherein the first chip includes a memory array, the memory array includes at least one memory block, and the memory block includes a plurality of word lines extending along a first direction and a plurality of bit lines extending along a second direction; a second chip, stacked on the first chip along a third direction, the second chip comprising a first local bit line decoder, a second local bit line decoder, a first word line decoder and a second word line decoder electrically connected to the memory block, the second chip having a top-view projection area of ​​the memory block, and the first local bit line decoder, the second local bit line decoder, the first word line decoder and the second word line decoder respectively forming a first local bit line decoder block, a second local bit line decoder block, a first word line decoder block and a second word line decoder block which are not overlapped with each other in the top-view projection area; The first local bit line decoder block, the second local bit line decoder block, the first word line decoder block, and the second word line decoder block are all located within the top-view projection area.

14. The memory device according to claim 13, wherein: In the first direction, the sum of the first length of the first local bit line decoder block and the second length of the second local bit line decoder block is less than or equal to the length of the top-view projection area, and the projections of the first local bit line decoder block and the second local bit line decoder block in the second direction do not overlap each other; in the second direction, the sum of the third length of the first word line decoder block and the fourth length of the second word line decoder block is less than or equal to the width of the top-view projection area, and the projections of the first word line decoder block and the second word line decoder block in the first direction do not overlap each other.

15. The memory device according to claim 14, wherein: The first length is different from the second length; and the third length is different from the fourth length.

16. The memory device according to claim 14, wherein: A portion of the plurality of bit lines is electrically connected to the first local bit line decoder, and another portion of the plurality of bit lines is electrically connected to the second local bit line decoder; A portion of the word lines is electrically connected to the first word line decoder, and another portion of the word lines is electrically connected to the second word line decoder.

17. The memory device according to claim 14, wherein: In the first direction, the second word line decoder block is located between the third edge of the top-view projection area extending along the second direction and the second local bit line decoder block, and the width of the second local bit line decoder block in the second direction is smaller than the length of the second word line decoder block in the second direction; in the second direction, the second word line decoder block is located between the fourth edge of the top-view projection area extending along the first direction and the first local bit line decoder block, and the length of the first local bit line decoder block in the first direction is greater than the width of the second word line decoder block in the first direction.

18. The memory device according to claim 16, wherein: The first local bit line decoder and the second local bit line decoder each have a plurality of first transmission terminals, and a first transmission terminal is electrically connected to a bit line through a first through silicon via or a pair of first bonding pads.

19. The memory device according to claim 18, wherein: The first word line decoder and the second word line decoder each have a plurality of second transmission terminals, and a second transmission terminal is electrically connected to a word line through a second through silicon via or a pair of second bonding pads.

20. The storage device according to claim 18 or 19, characterized in that: The first chip includes a first bonding layer, the first bonding layer includes at least one of the first bonding pads and / or the second bonding pad; the second chip includes a second bonding layer, the second bonding layer includes at least one of the first bonding pads and / or the second bonding pad; the first bonding pad located in the first bonding layer is bonded to the first bonding pad located in the second bonding layer, and / or the second bonding pad located in the first bonding layer is bonded to the second bonding pad located in the second bonding layer.

21. The memory device according to claim 13, wherein: The top-view projection area is rectangular, the first local bit line decoder block is located at one of the first right angle or the third right angle of the top-view projection area, and the second local bit line decoder block is located at the other of the first right angle or the third right angle of the top-view projection area; the first word line decoder block is located at one of the second right angle or the fourth right angle of the top-view projection area, and the second word line decoder block is located at the other of the second right angle or the fourth right angle of the top-view projection area; Alternatively, the first local bit line decoder block is located at one of the second right angle or the fourth right angle of the top-view projection area, and the second local bit line decoder block is located at the other of the second right angle or the fourth right angle of the top-view projection area; the first word line decoder block is located at one of the first right angle or the third right angle of the top-view projection area, and the second word line decoder block is located at the other of the first right angle or the third right angle of the top-view projection area; The first right angle and the third right angle are respectively located at two ends of a diagonal line of the overhead projection area, and the second right angle and the fourth right angle are respectively located at two ends of another diagonal line of the overhead projection area.

22. The memory device according to claim 13, wherein: In the first direction, the first word line decoder block is located between the left end of the second local bit line decoder block and the left end of the first local bit line decoder block; In the first direction, the second word line decoder block is located between the right end of the first local bit line decoder block and the right end of the second local bit line decoder block.

23. The memory device according to claim 13, wherein: In the second direction, the first local bit line decoder block is located between the upper end of the first word line decoder block and the upper end of the second word line decoder block; In the second direction, the second local bit line decoder block is located between a lower end of the second word line decoder block and a lower end of the first word line decoder block.

24. The memory device according to claim 13, wherein: In the first direction, the length of the first local bit line decoder block and the length of the second local bit line decoder block are both less than or equal to the length of the top-view projection area; in the second direction, the first word line decoder block is located between the first local bit line decoder block and the second local bit line decoder block, and the second word line decoder block is located between the first local bit line decoder block and the second local bit line decoder block.

25. The memory device according to claim 13, wherein: In the second direction, the length of the first word line decoder block and the length of the second word line decoder block are both less than or equal to the width of the top-view projection area; in the first direction, the first local bit line decoder block is located between the first word line decoder block and the second word line decoder block, and the second local bit line decoder block is located between the first word line decoder block and the second word line decoder block.

Images