Inverter circuit control method, controller, inverter circuit and storage medium

Abstract

The present application discloses a control method, controller, inverter circuit, and storage medium for an inverter circuit. The inverter circuit is used to convert a DC power supply into an AC power supply. The inverter circuit includes a first capacitor, a second capacitor, a first switch tube, a second switch tube, a third switch tube, a fourth switch tube, a fifth switch tube, a sixth switch tube, a seventh switch tube, and an eighth switch tube. The method includes: obtaining a first voltage across the first capacitor and a second voltage across the second capacitor, and calculating the difference between the first voltage and the second voltage; based on the difference and the AC power supply, controlling the first switch tube to be turned off at a different time than the third switch tube is turned off in the same working cycle, or controlling the second switch tube to be turned off at a different time than the fourth switch tube is turned off in the same working cycle. Through the above method, the inverter circuit can maintain high operating efficiency and performance, and reduce the risk of damage to devices in the inverter circuit.

Description

Technical Field

[0001] Embodiments of the present application relate to the field of switch tube control technology, and in particular to a control method, a controller, an inverter circuit, and a storage medium for an inverter circuit. Background Art

[0002] Inverter circuit is a basic circuit type in power electronics technology. Its main function is to convert DC power into AC power. The specific circuit structure of an inverter circuit is as follows: Figure 1 As shown. Figure 1 In the inverter circuit shown, when it works normally, the first switch tube and the third switch tube are usually turned on and turned off at the same time, and the second switch tube and the fourth switch tube are usually turned on and turned off at the same time.

[0003] However, due to possible differences in the switching tubes or asynchrony of the signals output by the software to the switching tubes, the conduction of the first switching tube and the third switching tube may be asynchronous, and / or the conduction of the second switching tube and the fourth switching tube may be asynchronous. This may cause the voltage across the first capacitor to be different from the voltage across the second capacitor, which may not only affect the working efficiency and performance of the inverter circuit but may also cause damage to the components in the inverter circuit. Summary of the Invention

[0004] The embodiments of the present application provide a control method, a controller, an inverter circuit, and a storage medium for an inverter circuit, which can enable the inverter circuit to maintain high operating efficiency and performance and reduce the risk of damage to devices in the inverter circuit.

[0005] In a first aspect, an embodiment of the present application provides a control method for an inverter circuit, wherein the inverter circuit is used to convert a DC power supply into an AC power supply, the inverter circuit comprising first to second capacitors and first to eighth switching tubes, wherein the first capacitor and the second capacitor, the first switching tube and the fourth switching tube, and the second switching tube and the third switching tube are all connected in series between the positive electrode of the DC power supply and the negative electrode of the DC power supply, the fifth switching tube and the sixth switching tube are connected in series between a first node and a second node, and the seventh switching tube and the eighth switching tube are connected in series between the second node and a third node, wherein the first switching tube and the fourth switching tube, the second switching tube and the third switching tube are all connected in series in the same direction, the fifth switching tube and the sixth switching tube, and the seventh switching tube and the eighth switching tube are all connected in series in opposite directions, the first node is the connection point of the first switching tube and the fourth switching tube, the second node is the connection point of the first capacitor and the second capacitor, and the third node is the connection point of the second switching tube and the third switching tube. The method comprises:

[0006] Obtaining a first voltage across the first capacitor and a second voltage across the second capacitor, respectively, and calculating a difference between the two;

[0007] According to the difference and the AC power supply, the time when the first switch tube is turned off is different from the time when the third switch tube is turned off in the same working cycle, or the time when the second switch tube is turned off is different from the time when the fourth switch tube is turned off in the same working cycle.

[0008] Furthermore, the controlling of the first switch tube to be turned off at a different time from the third switch tube to be turned off, or the controlling of the second switch tube to be turned off at a different time from the fourth switch tube to be turned off, in the same working cycle, according to the difference and the AC power supply, includes: when the difference is greater than zero, according to the AC power supply, controlling the first switch tube to be turned off at a later time than the third switch tube to be turned off, or controlling the second switch tube to be turned off at a later time than the fourth switch tube to be turned off, in the same working cycle; when the difference is less than zero, according to the AC power supply, controlling the third switch tube to be turned off at a later time than the first switch tube to be turned off, or controlling the fourth switch tube to be turned off at a later time than the second switch tube to be turned off, in the same working cycle.

[0009] Furthermore, when the difference is greater than zero, according to the AC power supply, the moment when the first switch tube is controlled to be turned off is later than the moment when the third switch tube is turned off in the same working cycle, or the moment when the second switch tube is controlled to be turned off is later than the moment when the fourth switch tube is turned off in the same working cycle, including: when the difference is greater than zero, if the AC power supply is in the positive half cycle, the moment when the first switch tube is controlled to be turned off is later than the moment when the third switch tube is turned off in the same working cycle.

[0010] Furthermore, when the difference is greater than zero, according to the AC power supply, the moment when the first switch tube is controlled to be turned off is later than the moment when the third switch tube is turned off in the same working cycle, or the moment when the second switch tube is controlled to be turned off is later than the moment when the fourth switch tube is turned off in the same working cycle, including: when the difference is greater than zero, if the AC power supply is in the negative half cycle, the moment when the second switch tube is controlled to be turned off is later than the moment when the fourth switch tube is turned off in the same working cycle.

[0011] Furthermore, when the difference is less than zero, according to the AC power supply, the timing of controlling the third switch tube to be turned off is later than the timing of controlling the first switch tube to be turned off in the same working cycle, or the timing of controlling the fourth switch tube to be turned off is later than the timing of controlling the second switch tube to be turned off in the same working cycle, including: when the difference is less than zero, if the AC power supply is in the positive half cycle, the timing of controlling the third switch tube to be turned off is later than the timing of controlling the first switch tube to be turned off in the same working cycle.

[0012] Furthermore, when the difference is less than zero, according to the AC power supply, the timing of controlling the third switch tube to be turned off is later than the timing of controlling the first switch tube to be turned off in the same working cycle, or the timing of controlling the fourth switch tube to be turned off is later than the timing of controlling the second switch tube to be turned off in the same working cycle, including: when the difference is less than zero, if the AC power supply is in the negative half cycle, the timing of controlling the fourth switch tube to be turned off is later than the timing of controlling the second switch tube to be turned off in the same working cycle.

[0013] Furthermore, the method also includes: applying a proportional-integral algorithm to the difference to obtain a compensation duration; setting the compensation duration to the duration between the moment when the first switch tube is turned off and the moment when the third switch tube is turned off, or setting the compensation duration to the duration between the moment when the second switch tube is turned off and the moment when the fourth switch tube is turned off.

[0014] In a second aspect, an embodiment of the present application provides a controller comprising: at least one processor and a memory; the memory is coupled to the processor, and the memory is used to store instructions or programs, and when the instructions or programs are executed by the at least one processor, the at least one processor executes the control method as described above.

[0015] In a third aspect, an embodiment of the present application provides an inverter circuit, including a first capacitor, a second capacitor, a first switch tube, a second switch tube, a third switch tube, a fourth switch tube, a fifth switch tube, a sixth switch tube, a seventh switch tube, an eighth switch tube and the controller; the first capacitor and the second capacitor, the first switch tube and the fourth switch tube, the second switch tube and the third switch tube are all connected in series between the positive electrode of the DC power supply and the negative electrode of the DC power supply, the fifth switch tube and the sixth switch tube are connected in series between the first node and the second node, and the seventh switch tube and the eighth switch tube are connected in series between the second node and the third node, wherein the The first switch tube and the fourth switch tube, the second switch tube and the third switch tube are all connected in series in the same direction, the fifth switch tube and the sixth switch tube, the seventh switch tube and the eighth switch tube are all connected in series in the opposite direction, the first node is the connection point between the first switch tube and the fourth switch tube, the second node is the connection point between the first capacitor and the second capacitor, and the third node is the connection point between the second switch tube and the third switch tube; the controller is connected to the first switch tube, the second switch tube, the third switch tube, the fourth switch tube, the fifth switch tube, the sixth switch tube, the seventh switch tube and the eighth switch tube respectively.

[0016] In a fourth aspect, an embodiment of the present application provides a computer storage medium, which stores instructions or programs. When the instructions or programs are executed by at least one processor, the at least one processor executes the control method as described above.

[0017] The beneficial effect of the present application is that the inverter circuit in the control method of the inverter circuit in the embodiment of the present application is used to convert a DC power supply into an AC power supply, and the inverter circuit includes a first capacitor, a second capacitor, a first switching tube, a second switching tube, a third switching tube, a fourth switching tube, a fifth switching tube, a sixth switching tube, a seventh switching tube, and an eighth switching tube. The first capacitor and the second capacitor, the first switching tube and the fourth switching tube, and the second switching tube and the third switching tube are all connected in series between the positive electrode of the DC power supply and the negative electrode of the DC power supply. The fifth switching tube and the sixth switching tube are connected in series between the first node and the second node, and the seventh switching tube and the eighth switching tube are connected in series between the second node and the third node. The first switching tube and the fourth switching tube, the second switching tube and the third switching tube are all connected in series in the same direction, and the fifth switching tube and the sixth switching tube, and the seventh switching tube and the eighth switching tube are all connected in series in opposite directions. The first node is the connection point of the first switching tube and the fourth switching tube, the second node is the connection point of the first capacitor and the second capacitor, and the third node is the connection point of the second switching tube and the third switching tube. The control method first obtains a first voltage across the first capacitor and a second voltage across the second capacitor, and calculates the difference between the first voltage and the second voltage. Based on the difference, it can be determined whether it is necessary to adjust the time when the first to fourth switch tubes are turned off. Based on the AC power supply, the switch tube whose turn-off time needs to be adjusted can be determined. It can be seen that, combined with the difference and the AC power supply, the switch tube whose turn-off time needs to be adjusted can be accurately found when the first voltage and the second voltage are unbalanced. Then, by adjusting the switch tube whose turn-off time needs to be adjusted, it can be achieved that the time when the first switch tube is turned off is different from the time when the third switch tube is turned off in the same working cycle, or the time when the second switch tube is turned off is different from the time when the fourth switch tube is turned off in the same working cycle, so as to reduce the difference between the first voltage and the second voltage, thereby making the first voltage and the second voltage tend to be balanced, which is beneficial to maintaining high working efficiency and performance of the inverter circuit and reducing the risk of damage to devices in the inverter circuit. BRIEF DESCRIPTION OF THE DRAWINGS

[0018] One or more embodiments are exemplarily described by the figures in the accompanying drawings, which are not intended to limit the embodiments. Elements with the same reference numerals in the drawings represent similar elements.

[0019] Figure 1 1 is a schematic diagram of the circuit structure of the inverter circuit provided in an embodiment of the present application;

[0020] Figure 2 yes Figure 1 The control method 1 of the inverter circuit shown;

[0021] Figure 3 yes Figure 1 The second control method of the inverter circuit shown;

[0022] Figure 4 This is the process of the control method of the inverter circuit provided by the embodiment of the present application Figure 1 ;

[0023] Figure 5 This embodiment of the present application provides Figure 4 A schematic diagram of an embodiment of step 402 is shown in FIG.

[0024] Figure 6 This embodiment of the present application provides Figure 5 A schematic diagram of an embodiment of step 501 is shown in FIG.

[0025] Figure 7 yes Figure 1 The control method three of the inverter circuit shown;

[0026] Figure 8 This embodiment of the present application provides Figure 5 A schematic diagram of another embodiment of step 501 is shown in FIG.

[0027] Figure 9 yes Figure 1 The control method 4 of the inverter circuit shown;

[0028] Figure 10 This embodiment of the present application provides Figure 5 A schematic diagram of an embodiment of step 502 is shown in FIG.

[0029] Figure 11 yes Figure 1 The control method of the inverter circuit shown is five;

[0030] Figure 12 This embodiment of the present application provides Figure 5 A schematic diagram of another embodiment of step 502 is shown in FIG.

[0031] Figure 13 yes Figure 1 The control method of the inverter circuit shown is six;

[0032] Figure 14 This is the process of the control method of the inverter circuit provided by the embodiment of the present application Figure 2 ;

[0033] Figure 15 This is the process of the control method of the inverter circuit provided by the embodiment of the present application Figure 3 ;

[0034] Figure 16 It is a schematic diagram of the structure of the controller provided in an embodiment of the present application. DETAILED DESCRIPTION

[0035] To make the objectives, technical solutions, and advantages of the embodiments of the present application more clear, the technical solutions in the embodiments of the present application will be described in detail below in conjunction with the accompanying drawings. Obviously, the described embodiments are only part of the embodiments of the present application, not all of them. It should be understood that the specific embodiments described herein are only used to explain the present application and are not intended to limit the present application.

[0036] It should be noted that, when an element is referred to as being “connected to” another element, it may be directly connected to the other element, or one or more intervening elements may exist therebetween.

[0037] In addition, the technical features involved in the various embodiments of the present application described below can be combined with each other as long as there is no structural conflict between them.

[0038] Please refer to Figure 1 , Figure 1 Schematic diagram of the circuit structure of the inverter circuit provided in the embodiment of the present application. Figure 1 As shown, the inverter circuit 10 is used to convert a DC power source 20 into an AC power source 30. The inverter circuit 10 includes a first capacitor C1, a second capacitor C2, a first switch tube Q1, a second switch tube Q2, a third switch tube Q3, a fourth switch tube Q4, a fifth switch tube Q5, a sixth switch tube Q6, a seventh switch tube Q7, and an eighth switch tube Q8.

[0039] The first capacitor C1 and the second capacitor C2 are connected in series between the positive electrode and the negative electrode of the DC power supply 20, the first switch Q1 and the fourth switch Q4 are connected in series between the positive electrode and the negative electrode of the DC power supply 20, the second switch Q2 and the third switch Q3 are connected in series between the positive electrode and the negative electrode of the DC power supply 20, the fifth switch Q5 and the sixth switch Q6 are connected in series between the first node P1 and the second node P2, and the seventh switch Q7 and the eighth switch Q8 are connected in series between the second node P2 and the third node P3. The first switch Q1 and the fourth switch Q4 are connected in series in the same direction, i.e., the upper ends of the first switch Q1 and the fourth switch Q4 are both the third end, and the lower ends are both the second end. The second switch Q2 and the third switch Q3 are connected in series in the same direction. The fifth switch Q5 and the sixth switch Q6 are connected in reverse series. The upper end of the fifth switch Q5 is the second terminal, while the upper end of the sixth switch Q6 is the third terminal. The lower end of the fifth switch Q5 is the third terminal, while the lower end of the sixth switch Q6 is the second terminal. The seventh switch Q7 and the eighth switch Q8 are connected in reverse series. A first node P1 is the connection point between the first switch Q1 and the fourth switch Q4. A second node P2 is the connection point between the first capacitor C1 and the second capacitor C2. A third node P3 is the connection point between the second switch Q2 and the third switch Q3.

[0040] In this embodiment, all switching transistors (including the first switching transistor Q1 to the eighth switching transistor Q8) are IGBT switching transistors. The gate of the IGBT switching transistor is the first terminal of each switching transistor, the emitter of the IGBT switching transistor is the second terminal of each switching transistor, and the collector of the IGBT switching transistor is the third terminal of each switching transistor.

[0041] In addition, each switch tube can be any controllable switch, such as an integrated gate-commutated thyristor (IGCT) device, a gate-turn-off thyristor (GTO) device, a silicon-controlled rectifier (SCR) device, a junction-gate field-effect transistor (JFET) device, a MOS-controlled thyristor (MCT) device, etc.

[0042] In some embodiments, the inverter circuit 10 further includes a first inductor L1 , a second inductor L2 , a third capacitor C3 , a fourth capacitor C4 , a first switch K1 , and a second switch K2 .

[0043] The first end of the first inductor L1 is connected to the first node P1, the second end of the first inductor L1 is connected to the first end of the third capacitor C3 and the first end of the first switch K1, respectively. The second end of the third capacitor C3 and the first end of the fourth capacitor C4 are both connected to the second node P2. The second end of the fourth capacitor C4 is connected to the second end of the second inductor L2 and the first end of the second switch K2, respectively. The first end of the second inductor L2 is connected to the third node P3. An AC power source 30 is connected between the second end of the first switch K1 and the second end of the second switch K2.

[0044] Please refer to Figure 1-Figure 3 ,in, Figure 2 An example is shown Figure 1 The inverter circuit 10 shown is a control method for each switch tube (including the first switch tube Q1 to the eighth switch tube Q8) when the inverter circuit 10 is operating normally and the AC power source 30 is in the positive half cycle (i.e., the working stage of the inverter circuit 10 is the positive half cycle excitation stage of the AC power source 30); Figure 3 An example is shown Figure 1 The inverter circuit 10 shown is in normal operation and the AC power supply 30 is in the negative half cycle (i.e., the working phase of the inverter circuit 10 is the negative half cycle excitation phase of the AC power supply 30). Figure 2 and Figure 3 In the figure, the horizontal axis represents time, and the vertical axis represents voltage. The eight curves from top to bottom represent the control signals of the first switch Q1 to the eighth switch Q8. When the control signal is at a high level, the corresponding switch is turned on, and when the control signal is at a low level, the corresponding switch is turned off. Normal operation of the inverter circuit 10 means that all components in the inverter circuit 10 are operating normally and the control signals of each switch are normal.

[0045] like Figure 2 As shown, the duration between time T1 and time T3 is one operating cycle TA. Taking this operating cycle TA as an example, and only describing the first through fourth switches Q1 through Q4, at time T1, both the first and third switches Q1 and Q3 are controlled to conduct. The current loop is: the positive electrode of the DC power supply 20, the first switch Q1, the first inductor L1, the first switch K1, the AC power supply 30, the second switch K2, the second inductor L2, the third switch Q3, and the negative electrode of the DC power supply 20. At this point, the first voltage across the first capacitor C1 (denoted as VC1) and the second voltage across the second capacitor C2 (denoted as VC2) are equal, meaning that the first voltage VC1 and the second voltage VC2 are balanced.

[0046] like Figure 3 As shown, the duration between time T4 and time T6 is one operating cycle TA. Taking this operating cycle TA as an example, and only describing the first through fourth switches Q1 through Q4, the second and fourth switches Q2 and Q4 are both controlled to conduct. The current loop is: the negative electrode of the DC power supply 20, the fourth switch Q4, the first inductor L1, the first switch K1, the AC power supply 30, the second switch K2, the second inductor L2, the second switch Q2, and the positive electrode of the DC power supply 20. At this point, the first voltage VC1 and the second voltage VC2 are equal, meaning that the first and second voltages VC1 and VC2 are balanced.

[0047] It can be understood that the duty cycle TA is the duty cycle of the inverter circuit 10, and its value is the inverse of the switching frequency of the inverter circuit 10. For example, in one embodiment, the switching frequency of the inverter circuit 10 ranges from 10kHz to 100kHz, and other values can also be selected as needed.

[0048] However, for Figure 1 As for the circuit structure shown, in actual applications, due to possible differences in the switching tubes or asynchronous signals output by the software to the switching tubes, the first switching tube Q1 and the third switching tube Q3 are turned on asynchronously, and / or the second switching tube Q2 and the fourth switching tube Q4 are turned on asynchronously. This will cause the voltage across the first capacitor to be different from the voltage across the second capacitor.

[0049] For example, Figure 2 For example, assuming there's a difference between the first switch Q1 and the third switch Q3, it's possible that although the first switch Q1 receives a signal controlling its conduction at time T1, it only turns on at time T2. Therefore, the first switch Q1 turns on later than the third switch Q3. Consequently, when the third switch Q3 turns on, the first switch Q1 is not yet turned on. The current loop is: second node P2, the body diode of the sixth switch Q6, the fifth switch Q5, the first inductor L1, the first switch K1, the AC power supply 30, the second switch K2, the second inductor L2, the third switch Q3, and the negative electrode of the DC power supply 20. In this case, the first capacitor C1 is charging while the second capacitor C2 is discharging, resulting in an imbalance between the first voltage VC1 and the second voltage VC2. Specifically, the first voltage VC1 is greater than the second voltage VC2.

[0050] Again Figure 2 For example, assuming a software anomaly causes a high level to be output to the third switch Q3 only at time T2, then the third switch Q3 turns on at time T2, while the first switch Q1 turns on at time T1. Therefore, the third switch Q3 turns on later than the first switch Q1. Therefore, when the first switch Q1 turns on, the third switch Q3 is not yet turned on. The current loop is: the positive electrode of the DC power supply 20, the first switch Q1, the first inductor L1, the first switch K1, the AC power supply 30, the second switch K2, the second inductor L2, the body diode of the eighth switch Q8, the seventh switch Q7, and the second node P2. At this point, the first capacitor C1 is discharging while the second capacitor C2 is charging, resulting in an imbalance between the first voltage VC1 and the second voltage VC2. Specifically, the first voltage VC1 is lower than the second voltage VC2.

[0051] For example, Figure 3For example, assuming a software anomaly causes a high level to be output to the second switch Q2 only at time T5, then the second switch Q2 turns on at time T5, and the time when the second switch Q2 turns on is later than the time when the fourth switch Q4 turns on. Therefore, when the fourth switch Q4 turns on, the second switch Q2 is not yet turned on. The current loop is: second node P2, the body diode of the seventh switch Q7, the eighth switch Q8, the second inductor L2, the second switch K2, the AC power supply 30, the first switch K1, the first inductor L1, the fourth switch Q4, and the negative electrode of the DC power supply 20. At this point, the first capacitor C1 is charging, the second capacitor C2 is discharging, and the first voltage VC1 and the second voltage VC2 are unbalanced. Specifically, the first voltage VC1 is greater than the second voltage VC2.

[0052] Again Figure 3 For example, assuming there's a difference between the second switch Q2 and the fourth switch Q4, it's possible that although the fourth switch Q4 receives a signal controlling its conduction at time T4, it only turns on at time T5. Therefore, the fourth switch Q4 turns on later than the second switch Q2. Consequently, when the second switch Q2 turns on, the fourth switch Q4 has not yet turned on. The current loop is: the positive electrode of the DC power supply 20, the second switch Q2, the second inductor L2, the second switch K2, the AC power supply 30, the first switch K1, the first inductor L1, the body diode of the fifth switch Q5, the sixth switch Q6, and the second node P2. At this point, the first capacitor C1 is discharging while the second capacitor C2 is charging, resulting in an imbalance between the first voltage VC1 and the second voltage VC2. Specifically, the first voltage VC1 is lower than the second voltage VC2.

[0053] In summary, due to the asynchronous conduction of the first switch tube Q1 and the third switch tube Q3, and / or the asynchronous conduction of the second switch tube Q2 and the fourth switch tube Q4, the first voltage VC1 and the second voltage VC2 will be unbalanced, which will not only affect the working efficiency and performance of the inverter circuit 10, but may also cause damage to the components in the inverter circuit 10.

[0054] Based on the above reasons, an embodiment of the present application provides a control method for an inverter circuit, which can adjust the turn-off moment of at least one switch tube from the first switch tube Q1 to the fourth switch tube Q4 when the first voltage VC1 and the second voltage VC2 are unbalanced, so that the first voltage VC1 and the second voltage VC2 tend to be balanced, or even reach a balance. Therefore, the inverter circuit 10 can maintain high working efficiency and performance and reduce the risk of damage to devices in the inverter circuit 10.

[0055] It should be noted that the above embodiment uses the example of a situation where the first switch Q1 and the third switch Q3 are turned on asynchronously, and / or the second switch Q2 and the fourth switch Q4 are turned on asynchronously due to differences in the switch tubes or asynchronous signals output by the software to the switch tubes. In other embodiments, if other reasons cause the first switch Q1 and the third switch Q3 to be turned on asynchronously, and / or the second switch Q2 and the fourth switch Q4 to be turned on asynchronously, the methods provided in the embodiments of the present application can also be used to balance the first voltage VC1 and the second voltage VC2, or even achieve equilibrium.

[0056] Please refer to Figure 4 , Figure 4 A flow chart of a control method for an inverter circuit provided in an embodiment of the present application. Wherein, the inverter circuit is used to convert a DC power supply into an AC power supply, and the inverter circuit includes a first capacitor, a second capacitor, a first switch tube, a second switch tube, a third switch tube, a fourth switch tube, a fifth switch tube, a sixth switch tube, a seventh switch tube and an eighth switch tube. The first capacitor and the second capacitor, the first switch tube and the fourth switch tube, the second switch tube and the third switch tube are all connected in series between the positive electrode of the DC power supply and the negative electrode of the DC power supply. The fifth switch tube and the sixth switch tube are connected in series between the first node and the second node, and the seventh switch tube and the eighth switch tube are connected in series between the second node and the third node. Wherein, the first switch tube and the fourth switch tube, the second switch tube and the third switch tube are all connected in series in the same direction, the fifth switch tube and the sixth switch tube, the seventh switch tube and the eighth switch tube are all connected in series in the opposite direction, the first node is the connection point of the first switch tube and the fourth switch tube, the second node is the connection point of the first capacitor and the second capacitor, and the third node is the connection point of the second switch tube and the third switch tube. In some specific embodiments, the inverter circuit here can be connected by Figure 1 The circuit structure shown in the figure is implemented. The specific implementation process has been described in detail in the above embodiment and will not be repeated here. Figure 4 As shown, the control method of the inverter circuit includes the following method steps:

[0057] Step 401: Obtain a first voltage across a first capacitor and a second voltage across a second capacitor, and calculate a difference between the first voltage and the second voltage.

[0058] Step 402: Based on the difference and the AC power supply, the first switch is turned off at a different time than the third switch in the same duty cycle, or the second switch is turned off at a different time than the fourth switch in the same duty cycle.

[0059] by Figure 1The circuit structure shown in FIG. is used as an example for illustration. By calculating the difference between the first voltage VC1 and the second voltage VC2, it is possible to determine whether the first voltage VC1 and the second voltage VC2 are balanced, thereby determining whether there is a conduction asynchrony between the first switch Q1 and the third switch Q3, and / or the conduction asynchrony between the second switch Q2 and the fourth switch Q4, and further determining whether the turn-off timings of the first through fourth switches Q1 through Q4 need to be adjusted. For example, as described in the above embodiment, if the difference is greater than zero, i.e., the first voltage VC1 is greater than the second voltage VC2, this may be because the turn-on timing of the first switch Q1 is later than the turn-on timing of the third switch Q3, or the turn-on timing of the second switch Q2 is later than the turn-on timing of the fourth switch Q4. In this case, the turn-off timing of the first switch Q1 or the second switch Q2 can be adjusted accordingly to compensate for the difference, bringing the difference closer to zero and balancing the first and second voltages VC1 and VC2. Secondly, according to whether the AC power supply 30 is in the positive half cycle or the negative half cycle, the switch tube currently on can be determined, and then the switch tube whose turn-off time needs to be adjusted can be determined. Figure 2 In the embodiment, according to the AC power source 30 being in the positive half cycle, it can be determined that the currently conducting switch tubes should be the first switch tube Q1 and the third switch tube Q3, and then it can be determined that the switch tube whose turn-off moment needs to be adjusted is the first switch tube Q1 or the third switch tube Q3.

[0060] In summary, it can be seen that, by combining the difference between the first voltage VC1 and the second voltage VC2 and the AC power supply 30, the switch tube whose turn-off time needs to be adjusted can be accurately found when the first voltage VC1 and the second voltage VC2 are unbalanced. Then, by adjusting the switch tube whose turn-off time needs to be adjusted, it can be achieved that the time when the first switch tube Q1 is controlled to be turned off is different from the time when the third switch tube Q3 is turned off in the same working cycle, or the time when the second switch tube Q2 is controlled to be turned off is different from the time when the fourth switch tube Q4 is turned off in the same working cycle, so as to reduce the difference between the first voltage VC1 and the second voltage VC2, thereby making the first voltage VC1 and the second voltage VC2 tend to be balanced, which is beneficial for maintaining high working efficiency and performance of the inverter circuit 10 and reducing the risk of damage to devices in the inverter circuit 10.

[0061] In some embodiments, as Figure 5 As shown, the specific implementation process of step 402 includes the following method steps:

[0062] Step 501: When the difference is greater than zero, according to the AC power supply, the first switch tube is controlled to be turned off later than the third switch tube in the same working cycle, or the second switch tube is controlled to be turned off later than the fourth switch tube in the same working cycle.

[0063] According to the above embodiment, when the first voltage VC1 is greater than the second voltage VC2 (corresponding to a difference greater than zero), the first switch Q1 may be turned on later than the third switch Q3, or the second switch Q2 may be turned on later than the fourth switch Q4. In this case, the adjustment difference can be reduced, or even reduced to zero, by controlling the first switch Q1 to be turned off later than the third switch Q3, or by controlling the second switch Q2 to be turned off later than the fourth switch Q4, within the same operating cycle.

[0064] In some embodiments, as Figure 6 As shown, the specific implementation process of step 501 includes the following method steps:

[0065] Step 601: When the difference is greater than zero, if the AC power source is in the positive half cycle, then in the same working cycle, the time when the first switch tube is turned off is later than the time when the third switch tube is turned off.

[0066] As the above embodiment for Figure 2 As explained above, when the AC power supply 30 is in the positive half cycle, if the first switch tube Q1 is turned on later than the third switch tube Q3, the first voltage VC1 will be greater than the second voltage VC2, that is, the difference will be greater than zero. In this case, in the same working cycle, the time when the first switch tube Q1 is turned off is later than the time when the third switch tube Q3 is turned off, which can reduce the adjustment difference or even make it zero. The specific control method can be as follows: Figure 7 As shown, Figure 7 An example is shown in Figure 2 The control mode shown is controlled Figure 1 When the inverter circuit 10 is operated as shown, a high level is output to the first switch Q1 at time T2 due to a software anomaly (when the inverter circuit 10 is operating normally, the high level should be output to the first switch Q1). Figure 2 As shown, a high level is output to the first switch tube Q1 at time T1, thereby causing the first voltage VC1 and the second voltage VC2 to be unbalanced.

[0067] Please follow Figure 1 and Figure 7As described in the above embodiment, because the first switch Q1 turns on later than the third switch Q3, the first voltage VC1 becomes greater than the second voltage VC2. Subsequently, at time T7, the third switch Q3 is controlled to turn off first, while the first switch Q1 is not yet turned off (the first switch Q1 is turned off at time T8). At this point, the current loop is: the positive electrode of the DC power supply 20, the first switch Q1, the first inductor L1, the first switch K1, the AC power supply 30, the second switch K2, the second inductor L2, the body diode of the eighth switch Q8, the seventh switch Q7, and the second node P2. Consequently, the first capacitor C1 is discharging, while the second capacitor C2 is charging. The difference between the first voltage VC1 and the second voltage VC2 gradually decreases. By properly configuring the time between the first switch Q1 and the third switch Q3 turning off, the difference between the first voltage VC1 and the second voltage VC2 can be reduced to zero, achieving equilibrium between the first and second voltages VC1 and VC2.

[0068] In some embodiments, as Figure 8 As shown, the specific implementation process of step 501 includes the following method steps:

[0069] Step 801: When the difference is greater than zero, if the AC power source is in the negative half cycle, then in the same working cycle, the second switch tube is controlled to be turned off later than the fourth switch tube.

[0070] As the above embodiment for Figure 3 As explained above, when the AC power supply 30 is in the negative half cycle, if the second switch tube Q2 is turned on later than the fourth switch tube Q4, the first voltage VC1 will be greater than the second voltage VC2, that is, the difference will be greater than zero. In this case, in the same working cycle, the second switch tube Q2 can be turned off later than the fourth switch tube Q4, so that the adjustment difference can be reduced or even zero. The specific control method can be as follows: Figure 9 As shown, Figure 9 An example is shown in Figure 3 The control mode shown is controlled Figure 1 When the inverter circuit 10 is operated as shown, a high level is output to the second switch tube Q2 at time T5 due to a software anomaly (when the inverter circuit 10 is operating normally, the high level should be output to the second switch tube Q2 at time T5). Figure 3 As shown, a high level is output to the second switch tube Q2 at time T4, thereby causing the first voltage VC1 and the second voltage VC2 to be unbalanced.

[0071] Please follow Figure 1 and Figure 9As described in the above embodiment, because the second switch Q2 turns on later than the fourth switch Q4, the first voltage VC1 becomes greater than the second voltage VC2. Subsequently, at time T9, the fourth switch Q4 is controlled to turn off first, while the second switch Q2 is not yet turned off (the second switch Q2 is turned off at time T10). At this point, the current loop is: the positive electrode of the DC power supply 20, the second switch Q2, the second inductor L2, the second switch K2, the AC power supply 30, the first switch K1, the first inductor L1, the body diode of the fifth switch Q5, the sixth switch Q6, and the second node P2. Consequently, the first capacitor C1 is discharging, while the second capacitor C2 is charging. The difference between the first voltage VC1 and the second voltage VC2 gradually decreases. By properly configuring the time between the turn-off of the second switch Q2 and the turn-off of the fourth switch Q4, the difference between the first voltage VC1 and the second voltage VC2 can be reduced to zero, achieving equilibrium between the first voltage VC1 and the second voltage VC2.

[0072] Step 502: When the difference is less than zero, according to the AC power supply, the third switch is controlled to be turned off later than the first switch in the same working cycle, or the fourth switch is controlled to be turned off later than the second switch in the same working cycle.

[0073] According to the above embodiment, when the first voltage VC1 is less than the second voltage VC2 (corresponding to a difference less than zero), the third switch Q3 may turn on later than the first switch Q1, or the fourth switch Q4 may turn on later than the second switch Q2. In this case, the adjustment difference can be reduced, or even reduced to zero, by controlling the third switch Q3 to turn off later than the first switch Q1, or by controlling the fourth switch Q4 to turn off later than the second switch Q2, within the same operating cycle.

[0074] In some embodiments, as Figure 10 As shown, the specific implementation process of step 502 includes the following method steps:

[0075] Step 1001: When the difference is less than zero, if the AC power source is in the positive half cycle, then in the same working cycle, the time when the third switch tube is turned off is later than the time when the first switch tube is turned off.

[0076] As the above embodiment Figure 2As explained above, when the AC power supply 30 is in the positive half cycle, if the third switch tube Q3 is turned on later than the first switch tube Q1, the first voltage VC1 will be less than the second voltage VC2, that is, the difference will be less than zero. In this case, if the third switch tube Q3 is turned off later than the first switch tube Q1 in the same working cycle, the adjustment difference can be reduced or even zero. The specific control method can be as follows: Figure 11 As shown, Figure 11 An example is shown in Figure 2 The control mode shown is controlled Figure 1 When the inverter circuit 10 is operated as shown, a high level is output to the third switch Q3 at time T2 due to a software anomaly (when the inverter circuit 10 is operating normally, the high level should be output to the third switch Q3). Figure 2 As shown, a high level is output to the third switch tube Q3 at time T1, thereby causing the first voltage VC1 and the second voltage VC2 to be unbalanced.

[0077] Please follow Figure 1 and Figure 11 As described in the above embodiment, because the third switch Q3 turns on later than the first switch Q1, the first voltage VC1 becomes smaller than the second voltage VC2. Subsequently, at time T11, the first switch Q1 is controlled to turn off first, while the third switch Q3 is not yet turned off (the third switch Q3 is turned off at time T12). At this point, the current loop is: the second node P2, the body diode of the sixth switch Q6, the fifth switch Q5, the first inductor L1, the first switch K1, the AC power supply 30, the second switch K2, the second inductor L2, the third switch Q3, and the negative electrode of the DC power supply 20. Consequently, the first capacitor C1 is charging and the second capacitor C2 is discharging. The difference between the first voltage VC1 and the second voltage VC2 gradually decreases. By properly configuring the time between the first switch Q1 and the third switch Q3 turning off, the difference between the first voltage VC1 and the second voltage VC2 can be reduced to zero, achieving equilibrium between the first and second voltages VC1 and VC2.

[0078] In some embodiments, as Figure 12 As shown, the specific implementation process of step 502 includes the following method steps:

[0079] Step 1201: When the difference is less than zero, if the AC power source is in the negative half cycle, then in the same working cycle, the fourth switch tube is controlled to be turned off later than the second switch tube.

[0080] As the above embodiment Figure 3As explained above, when the AC power supply 30 is in the negative half cycle, if the fourth switch tube Q4 is turned on later than the second switch tube Q2, the first voltage VC1 will be less than the second voltage VC2, that is, the difference will be less than zero. In this case, in the same working cycle, the fourth switch tube Q4 can be turned off later than the second switch tube Q2 to reduce the adjustment difference, or even to zero. The specific control method can be as follows: Figure 13 As shown, Figure 13 An example is shown in Figure 3 The control mode shown is controlled Figure 1 When the inverter circuit 10 is operated as shown, a high level is output to the fourth switch tube Q4 at time T5 due to a software anomaly (the inverter circuit 10 should be operated as shown in FIG. Figure 3 The control method shown is when a high level is output to the fourth switch tube Q4 at time T4, thereby causing an imbalance between the first voltage VC1 and the second voltage VC2.

[0081] Please follow Figure 1 and Figure 13 As described in the above embodiment, because the fourth switch Q4 turns on later than the second switch Q2, the first voltage VC1 becomes smaller than the second voltage VC2. Subsequently, at time T13, the second switch Q2 is controlled to turn off first, while the fourth switch Q4 is not yet turned off (the fourth switch Q4 is turned off at time T14). At this point, the current loop is: the second node P2, the body diode of the seventh switch Q7, the eighth switch Q8, the second inductor L2, the second switch K2, the AC power supply 30, the first switch K1, the first inductor L1, the fourth switch Q4, and the negative electrode of the DC power supply 20. Consequently, the first capacitor C1 is charging and the second capacitor C2 is discharging. The difference between the first voltage VC1 and the second voltage VC2 gradually decreases. By properly configuring the time between the turn-off of the second switch Q2 and the turn-off of the fourth switch Q4, the difference between the first voltage VC1 and the second voltage VC2 can be reduced to zero, achieving equilibrium between the first voltage VC1 and the second voltage VC2.

[0082] It should be noted that when the difference between the first voltage VC1 and the second voltage VC2 is zero, the first voltage VC1 and the second voltage VC2 are balanced, and there is no need to adjust the time when any switch is turned off.

[0083] In some embodiments, as Figure 14 As shown, the control method of the inverter circuit also includes the following method steps:

[0084] Step 1401: The difference is processed through a proportional integral algorithm to obtain a compensation duration.

[0085] Step 1402: Set the compensation time to the time between when the first switch is turned off and when the third switch is turned off, or set the compensation time to the time between when the second switch is turned off and when the fourth switch is turned off.

[0086] Specifically, the proportional-integral algorithm consists of a proportional control component and an integral control component. The proportional control component adjusts the output by multiplying the error (the difference between the setpoint and the actual value, where the setpoint is zero and the actual value is the difference) by a proportional constant, Kp. The integral control component integrates the error and then multiplies it by an integral constant, Ki. This eliminates the steady-state error of the system, gradually correcting the error to zero over time. The proportional-integral algorithm combines the proportional and integral control components, resulting in an output composed of two parts: one proportional to the current error and the other proportional to the accumulation of past errors. This allows the proportional-integral algorithm to both quickly respond to input changes and ultimately eliminate errors.

[0087] Then, the compensation time obtained by the proportional-integral algorithm of the difference is set as the time between the moment when the first switch tube Q1 is turned off and the moment when the third switch tube Q3 is turned off, or as the time between the moment when the second switch tube Q2 is turned off and the moment when the fourth switch tube Q4 is turned off. For example, the compensation time is set to Figure 7 The duration between time T7 and time T8 shown, or the compensation duration is set to Figure 9 The duration between time T9 and time T10 shown, or the compensation duration is set to Figure 11 The duration between the time T11 and the time T12 shown, or the compensation duration is set to Figure 13 The time length between the time T13 and the time T14 is shown. Then, the difference between the first voltage VC1 and the second voltage VC2 can be made zero eventually, so that the first voltage VC1 and the second voltage VC2 are balanced.

[0088] Please refer to Figure 15 , Figure 15 This is a flow chart of a control method for an inverter circuit provided by another embodiment of the present application. Figure 15 As shown, first, it is determined whether the inverter circuit 10 is operating. If the inverter circuit 10 is not operating, the process ends. If the inverter circuit 10 is operating, the difference between the first voltage VC1 and the second voltage VC2 is calculated. Next, the difference is processed through a proportional-integral algorithm to obtain the compensation time TS.

[0089] If the compensation time TS is greater than 0, it can be determined that the first switch Q1 turns on earlier than the third switch Q3, or that the second switch Q2 turns on earlier than the fourth switch Q4. Next, it is determined whether the AC power source 30 is in the positive half cycle. If the AC power source 30 is in the positive half cycle, the first switch Q1 is controlled to turn off later than the third switch Q3, and the time between the first and third switch Q3 turns off is the compensation time TS. In this way, the difference between the first and second voltages VC1 and VC2 is eliminated to zero, and the first and second voltages VC1 and VC2 are balanced. If the AC power source 30 is in the negative half cycle, the second switch Q2 is controlled to turn off later than the fourth switch Q4, and the time between the second and fourth switch Q4 turns off is the compensation time TS. In this way, the difference between the first and second voltages VC1 and VC2 is eliminated to zero, and the first and second voltages VC1 and VC2 are balanced.

[0090] If the compensation time TS is less than 0, it can be determined that the third switch Q3 turns on earlier than the first switch Q1, or that the fourth switch Q4 turns on earlier than the second switch Q2. Next, it is determined whether the AC power source 30 is in the positive half cycle. If the AC power source 30 is in the positive half cycle, the third switch Q3 is controlled to turn off later than the first switch Q1, and the time between the first switch Q1 and the third switch Q3 turns off is the compensation time TS. In this way, the difference between the first voltage VC1 and the second voltage VC2 is eliminated to zero, and the first voltage VC1 and the second voltage VC2 are balanced. If the AC power source 30 is in the negative half cycle, the fourth switch Q4 is controlled to turn off later than the second switch Q2, and the time between the second switch Q2 and the fourth switch Q4 turns off is the compensation time TS. In this way, the difference between the first voltage VC1 and the second voltage VC2 is eliminated to zero, and the first voltage VC1 and the second voltage VC2 are balanced.

[0091] Please refer to Figure 16 , Figure 16 This is a schematic diagram of the structure of the controller provided in the embodiment of the present application. Figure 16 As shown, Figure 16 As shown, the controller 1600 includes one or more processors 1601 and a memory 1602. Figure 16 A processor 1601 is taken as an example.

[0092] The processor 1601 and the memory 1602 may be connected via a bus or other means. Figure 16In the example, a bus connection is used. Memory 1602, as a non-volatile computer-readable storage medium, can be used to store non-volatile software programs, non-volatile computer executable programs, and modules, such as the program instructions / modules corresponding to the inverter circuit control method in the embodiment of the present application. Processor 1601 executes the various functional applications and data processing of the terminal interaction device by running the non-volatile software programs, instructions, and modules stored in memory 1602, thereby implementing the inverter circuit control method in the above method embodiment.

[0093] Memory 1602 may include high-speed random access memory and non-volatile memory, such as at least one disk storage device, flash memory device, or other non-volatile solid-state memory device. In some embodiments, memory 1602 may optionally include memory remotely located relative to processor 1601, and such remote memory may be connected to processor 1601 via a network. Examples of such networks include, but are not limited to, the Internet, an intranet, a local area network, a mobile communication network, and combinations thereof.

[0094] The program instructions / modules are stored in the memory 1602, and when executed by the one or more processors 1601, the control method of the inverter circuit in any of the above method embodiments is executed, for example, the control method of the inverter circuit described above is executed. Figure 4-Figure 6 、 Figure 8 、 Figure 10 、 Figure 12 、 Figure 14 and Figure 15 The steps shown.

[0095] An embodiment of the present application also provides an inverter circuit, which includes a first capacitor, a second capacitor, a first switch tube, a second switch tube, a third switch tube, a fourth switch tube, a fifth switch tube, a sixth switch tube, a seventh switch tube, an eighth switch tube and the controller 1600 in any embodiment of the present application.

[0096] Among them, the first capacitor and the second capacitor, the first switch tube and the fourth switch tube, the second switch tube and the third switch tube are all connected in series between the positive electrode of the DC power supply and the negative electrode of the DC power supply, the fifth switch tube and the sixth switch tube are connected in series between the first node and the second node, and the seventh switch tube and the eighth switch tube are connected in series between the second node and the third node. Among them, the first switch tube and the fourth switch tube, the second switch tube and the third switch tube are all connected in series in the same direction, the fifth switch tube and the sixth switch tube, the seventh switch tube and the eighth switch tube are all connected in series in the opposite direction, the first node is the connection point of the first switch tube and the fourth switch tube, the second node is the connection point of the first capacitor and the second capacitor, and the third node is the connection point of the second switch tube and the third switch tube. The controller is connected to the first switch tube, the second switch tube, the third switch tube, the fourth switch tube, the fifth switch tube, the sixth switch tube, the seventh switch tube and the eighth switch tube respectively. In some specific embodiments, the inverter circuit here (except the controller 1600) can be connected as follows Figure 1 The circuit structure shown is implemented, and the specific implementation process has been described in detail in the above embodiment, which will not be repeated here.

[0097] The present application also provides a non-volatile computer-readable storage medium, wherein the computer-readable storage medium stores computer-executable instructions, which are executed by one or more processors, for example, to execute the above-described Figure 4-Figure 6 、 Figure 8 、 Figure 10 、 Figure 12 、 Figure 14 and Figure 15 method steps.

[0098] The present application also provides a computer program product, including a computer program stored on a non-volatile computer-readable storage medium, wherein the computer program includes program instructions. When the program instructions are executed by a computer, the computer executes the control method of the inverter circuit in any of the above method embodiments, for example, executing the above described Figure 4-Figure 6 、 Figure 8 、 Figure 10 、 Figure 12 、 Figure 14 and Figure 15 method steps.

[0099] The above description is merely an embodiment of the present application and does not limit the patent scope of the present application. Any equivalent structure or equivalent process transformation made using the contents of the present application specification and drawings, or directly or indirectly applied in other related technical fields, are also included in the patent protection scope of the present application.

[0100] The above embodiments are only used to illustrate the technical solutions of the present application, and are not intended to limit them. Based on the concept of the present application, the technical features in the above embodiments or different embodiments may be combined, and the steps may be implemented in any order. A person skilled in the art should understand that the technical solutions described in the above embodiments may be modified, or some of the technical features may be replaced by equivalents. However, such modifications or replacements do not deviate the essence of the corresponding technical solutions from the scope of the technical solutions of the embodiments of the present application.

Claims

1. A control method for an inverter circuit, characterized in that: The inverter circuit is used to convert a DC power supply into an AC power supply. The inverter circuit includes first to second capacitors and first to eighth switching transistors. The first capacitor and the second capacitor, the first switching transistor and the fourth switching transistor, and the second switching transistor and the third switching transistor are all connected in series between the positive electrode of the DC power supply and the negative electrode of the DC power supply. The fifth switching transistor and the sixth switching transistor are connected in series between a first node and a second node, and the seventh switching transistor and the eighth switching transistor are connected in series between the second node and a third node. The first switching transistor and the fourth switching transistor, and the second switching transistor and the third switching transistor are all connected in series in the same direction, and the fifth switching transistor and the sixth switching transistor, and the seventh switching transistor and the eighth switching transistor are all connected in series in opposite directions. The first node is the connection point between the first switching transistor and the fourth switching transistor, the second node is the connection point between the first capacitor and the second capacitor, and the third node is the connection point between the second switching transistor and the third switching transistor. The method includes: Obtaining a first voltage across the first capacitor and a second voltage across the second capacitor, respectively, and calculating a difference between the two; According to the difference and the AC power supply, the first switch tube is controlled to be turned off at a different time than the third switch tube in the same working cycle, or the second switch tube is controlled to be turned off at a different time than the fourth switch tube in the same working cycle; When the difference is greater than zero, if the AC power supply is in a positive half cycle, then in the same working cycle, the first switch tube is controlled to be turned off later than the third switch tube. During the compensation period, the first capacitor is discharged and the second capacitor is charged. Specifically, the first capacitor is discharged through the first switch tube, the AC power supply, the body diode of the eighth switch tube, and the seventh switch tube, and the second capacitor is charged through the left DC power supply. When the difference is greater than zero, if the AC power supply is in a negative half cycle, then in the same working cycle, the second switch tube is controlled to be turned off later than the fourth switch tube. During the compensation period, the first capacitor is discharged and the second capacitor is charged. Specifically, the first capacitor is discharged through the second switch tube, the AC power supply, the body diode of the fifth switch tube, and the sixth switch tube, and the second capacitor is charged through the DC power supply on the left. When the difference is less than zero, if the AC power supply is in a positive half cycle, then in the same working cycle, the third switch tube is controlled to be turned off later than the first switch tube. During the compensation period, the first capacitor is charged and the second capacitor is discharged. Specifically, the first capacitor is charged by the DC power supply on the left, and the second capacitor is discharged through the body diode of the sixth switch tube, the fifth switch tube, the AC power supply, and the third switch tube. When the difference is less than zero, if the AC power supply is in a negative half cycle, the fourth switch tube is controlled to be turned off later than the second switch tube in the same working cycle; during the compensation period, the first capacitor is charged and the second capacitor is discharged. Specifically, the first capacitor is charged by the DC power supply on the left, and the second capacitor is discharged through the body diode of the seventh switch tube, the eighth switch tube, the AC power supply, and the fourth switch tube. The compensation time is the time between when the first switch tube is turned off and when the third switch tube is turned off, or the compensation time is set to the time between when the second switch tube is turned off and when the fourth switch tube is turned off.

2. The method according to claim 1, characterized in that The method further comprises: The difference is subjected to a proportional integral algorithm to obtain the compensation duration.

3. A controller, characterized in that: include: at least one processor and memory; The memory is coupled to the processor, and is used to store instructions or programs. When the instructions or programs are executed by the at least one processor, the at least one processor executes the control method according to any one of claims 1 to 2.

4. An inverter circuit, characterized in that: comprising a first capacitor, a second capacitor, a first switch tube, a second switch tube, a third switch tube, a fourth switch tube, a fifth switch tube, a sixth switch tube, a seventh switch tube, an eighth switch tube, and the controller according to claim 3; The first capacitor and the second capacitor, the first switching transistor and the fourth switching transistor, and the second switching transistor and the third switching transistor are all connected in series between the positive electrode of the DC power supply and the negative electrode of the DC power supply. The fifth switching transistor and the sixth switching transistor are connected in series between a first node and a second node, and the seventh switching transistor and the eighth switching transistor are connected in series between the second node and a third node. The first switching transistor and the fourth switching transistor, and the second switching transistor and the third switching transistor are all connected in series in the same direction, and the fifth switching transistor and the sixth switching transistor, and the seventh switching transistor and the eighth switching transistor are all connected in series in opposite directions. The first node is the connection point of the first switching transistor and the fourth switching transistor, the second node is the connection point of the first capacitor and the second capacitor, and the third node is the connection point of the second switching transistor and the third switching transistor. The controller is connected to the first switch tube, the second switch tube, the third switch tube, the fourth switch tube, the fifth switch tube, the sixth switch tube, the seventh switch tube and the eighth switch tube respectively.

5. A computer storage medium, characterized in that The computer storage medium stores instructions or programs, and when the instructions or programs are executed by at least one processor, the at least one processor is caused to execute the control method according to any one of claims 1 to 2.

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