AI correction-based ADC sampling conversion method and system

Abstract

The invention discloses an ADC sampling conversion method and system based on AI correction, and relates to the technical field of sampling conversion, and the method comprises the steps: initializing a system architecture, and configuring each single-chip microcomputer; for each configured single-chip microcomputer, calculating a noise interference coefficient and a sampling cooperation disqualification coefficient to obtain an overall disqualification coefficient of the single-chip microcomputer, comparing the overall disqualification coefficient with a preset threshold value, and judging whether each configured single-chip microcomputer can be subjected to sampling conversion or not according to a comparison result; when the configured single-chip microcomputers can perform sampling conversion, the sub single-chip microcomputers complete data acquisition and storage in order, and the master control single-chip microcomputer collects sampling data from the sub single-chip microcomputers, integrates the sampling data and stores the sampling data to the upper computer; and the data storage is completed step by step according to the sampling sequence until all the data are read, so that the system complexity and cost of ADC sampling conversion can be reduced, and the limitation of the high-speed data acquisition system in a miniaturized, low-cost and easy-to-implement application scene is relatively small.

Description

Technical Field

[0001] The present invention relates to the field of sampling conversion technology, and in particular to an ADC sampling conversion method and system based on AI correction. Background Art

[0002] In the field of high-speed signal processing, such as medical testing (ECG signals, ultrasound), industrial monitoring (pressure fluctuations, vibration analysis) and communication systems (RF signal acquisition), it is often necessary to perform real-time, high-speed data acquisition and processing of high-frequency signals. The core of realizing these functions is the high-speed analog-to-digital converter (ADC), which converts continuous analog signals into discrete digital signals for subsequent digital processing.

[0003] However, the high-speed ADC chips currently on the market are expensive, especially when the sampling rate reaches 10MSPS (10 million samples per second) or above, the price of a single chip may be as high as hundreds or even thousands of yuan. In addition, many high-performance ADCs have stringent requirements on peripheral circuits (such as high-frequency signal conditioning and precision clock control), which further increases the complexity and cost of the system; this limits the high-speed data acquisition system in small, low-cost, and easy-to-implement application scenarios. Summary of the invention

[0004] The purpose of the present invention is to solve the above-mentioned problems and provide an ADC sampling conversion method and system based on AI correction.

[0005] In a first aspect of the implementation of the present invention, an ADC sampling conversion method based on AI correction is first proposed, and the method includes:

[0006] Initialize the system architecture and configure each MCU; for each configured MCU, obtain the noise signal around each MCU, and analyze the noise signal to calculate the noise interference coefficient;

[0007] Send the same external clock signal to the configured clock input terminals of each MCU, record the timestamp of the MCU clock signal, and calculate the sampling coordination failure coefficient;

[0008] The overall unqualified coefficient of the single-chip microcomputer is obtained according to the noise interference coefficient and the sampling coordination unqualified coefficient, and the overall unqualified coefficient is compared with the preset overall unqualified coefficient threshold, and it is judged whether each configured single-chip microcomputer can perform sampling conversion according to the comparison result;

[0009] When each configured single-chip microcomputer can perform sampling conversion, each sub-chip microcomputer completes data acquisition and storage in an orderly manner, and the master control single-chip microcomputer collects sampling data from each sub-chip microcomputer, integrates the sampling data and stores it in the host computer; and the data storage is completed step by step according to the sampling sequence until all data are read.

[0010] Optionally, initialize the system architecture and configure each microcontroller as follows:

[0011] The system architecture includes single chip microcomputer 0 (master control single chip microcomputer) and single chip microcomputers 1 to n (sub-single chip microcomputers), external memory, and host computer;

[0012] MCU 0 is responsible for sending instructions and summarizing data, MCU 1 to n are responsible for ADC data acquisition and storage; external memory saves data, and the host computer saves or displays data.

[0013] Optionally, calculating the noise interference coefficient includes:

[0014] Obtain the noise signal around each single-chip microcomputer and mark it as K(s), where s=1, 2, 3, 4, ..., n+1, n+1 is a positive integer, and n+1 represents the total number of all single-chip microcomputers;

[0015] Morlet wavelet is used to perform continuous wavelet transform on the noise signal K(s) around each single-chip microcomputer. The noise signal is decomposed in the time domain and frequency domain through continuous wavelet transform (CWT). Continuous wavelet transform is realized through convolution. The calculation formula is as follows: Where K(s) is the input signal, ψ(s) is the selected wavelet basis function, a is the scale parameter used to adjust the scale of the wavelet basis function; b is the translation parameter used to adjust the position of the wavelet basis function; s represents the time coordinate of the signal, that is, the position on the time axis;

[0016] For each scale a and translation b, the result calculated using wavelet transform is called wavelet coefficient;

[0017] Extract the energy characteristics of the wavelet coefficients. According to the calculated wavelet coefficients, further extract the energy characteristics, calculate the energy of the wavelet coefficients at each scale, and then perform weighted summation of the energies at different scales to obtain the comprehensive energy characteristics. The calculation formula is as follows: Where E(a) is the energy at scale a, CWT(a,b) is the wavelet coefficient;

[0018] Calculate the noise interference index of each scale, and the calculation expression is: FK(s)=E(a) where FK(s) is the noise interference index;

[0019] Add the noise interference index FK(s) of each scale to get the noise interference coefficient. The calculation formula is: Where ED is the noise interference coefficient.

[0020] Optionally, calculating the sampling coordination failure coefficient includes:

[0021] Send the same external clock signal to the configured clock input terminals of each microcontroller, and record the timestamp of the microcontroller's clock signal. Set the timestamp of each microcontroller as T i , where i is the number of the microcontroller, i = 1, 2, 3....n;

[0022] For each microcontroller i, calculate its timestamp T i The deviation ΔT from the timestamp T0 of the master control microcontroller i :ΔT i =|T i -T0|;

[0023] Calculate the sampling coordination unqualified coefficient, the calculation formula is: Where SD is the sampling coordination failure coefficient.

[0024] Optionally, obtaining an overall unqualified coefficient of the single chip microcomputer according to the noise interference coefficient and the sampling coordination unqualified coefficient includes:

[0025]

[0026] Where Wsx is the overall qualified coefficient, ED and SD are the noise interference coefficient and sampling coordination unqualified coefficient respectively, α and β are the preset proportional coefficients of the noise interference coefficient and sampling coordination unqualified coefficient respectively, and α and β are both greater than 0.

[0027] Optionally, comparing the overall unqualified coefficient with a preset overall unqualified coefficient threshold, and judging whether each configured single-chip microcomputer can perform sampling conversion according to the comparison result includes:

[0028] The overall unqualified coefficient is compared with the preset overall unqualified coefficient threshold. If the overall unqualified coefficient is not less than the preset overall unqualified coefficient threshold, it means that each configured single-chip microcomputer cannot perform sampling conversion;

[0029] If the overall unqualified coefficient is less than the preset overall unqualified coefficient threshold, it means that each configured single-chip microcomputer can perform sampling conversion.

[0030] Optionally, each sub-MCU completes data acquisition and storage in order, the master control MCU collects sampling data from each sub-MCU, integrates the sampling data and stores it in the host computer; and the data storage is completed step by step according to the sampling sequence until all data are read, including:

[0031] The master control microcontroller triggers the ADC modules of the sub-microcontrollers 1 to n to sample in turn at time interval t1. Each sampling duration is t0. The collected data is transferred to the internal SRAM by the DMA module of each microcontroller without CPU participation. The startup interval t1·n of adjacent sub-microcontrollers is greater than t0 to avoid sampling conflicts.

[0032] The master control microcontroller reads the sampled data in the SRAM of the sub-microcontrollers in sequence through the serial bus. The reading order is completed one by one according to the microcontroller number to ensure data integrity and transmission order;

[0033] Integrate sampled data and store or output to the host computer, store the aggregated data in external memory, and send it to the host computer via serial communication; support real-time data display and processing;

[0034] Repeatedly read the sampled data in the SRAM of the sub-microcontroller, and execute the next round of sampling according to the set sampling frequency and timing strategy until all data are read.

[0035] In a second aspect of the present invention, an ADC sampling conversion system based on AI correction is proposed, the system comprising:

[0036] Noise interference module: initialize the system architecture and configure each MCU; for each configured MCU, obtain the noise signal around each MCU, analyze the noise signal and calculate the noise interference coefficient;

[0037] Collaboration failure module: sends the same external clock signal to the configured clock input terminals of each MCU, records the timestamp of the MCU clock signal, and calculates the sampling coordination failure coefficient;

[0038] Comparison and judgment module: obtain the overall unqualified coefficient of the single-chip microcomputer according to the noise interference coefficient and the sampling coordination unqualified coefficient, and compare the overall unqualified coefficient with the preset overall unqualified coefficient threshold, and judge whether each configured single-chip microcomputer can perform sampling conversion according to the comparison result;

[0039] Sampling conversion module: When the configured MCUs are ready for sampling conversion, each sub-MCU completes data acquisition and storage in an orderly manner, and the master control MCU collects sampling data from each sub-MCU, integrates the sampling data and stores it in the host computer; and data storage is completed step by step according to the sampling sequence until all data are read.

[0040] Beneficial effects of the present invention:

[0041] 1. The present invention proposes an ADC sampling conversion method and system based on AI correction, so that the sampling conversion rate is high and can exceed the sampling rate of professional high-speed ADC chips. In the present invention, when the time t1 is smaller and the sampling points are denser, the overall ADC sampling rate is higher. When t1 is very small and n is larger, the overall ADC sampling rate is very high and will exceed the sampling rate of professional high-speed ADC chips;

[0042] 2: The overall price is much lower than the price of professional high-speed ADC chips on the market, which can reduce the system complexity and cost of ADC sampling conversion, which makes the high-speed data acquisition system less restricted in miniaturized, low-cost and easy-to-implement application scenarios. BRIEF DESCRIPTION OF THE DRAWINGS

[0043] The present invention will be further described below in conjunction with the accompanying drawings.

[0044] Figure 1 It is a flow chart of the ADC sampling conversion method based on AI correction;

[0045] Figure 2 It is the system architecture diagram;

[0046] Figure 3 It is the flow chart of ADC data acquisition subroutine;

[0047] Figure 4 It is a schematic diagram of data cycle collection;

[0048] Figure 5 It is a flow chart of the data reading and storage subroutine;

[0049] Figure 6 The framework diagram of the ADC sampling and conversion system based on AI correction. DETAILED DESCRIPTION

[0050] The following will be combined with the drawings in the embodiments of the present invention to clearly and completely describe the technical solutions in the embodiments of the present invention. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present invention.

[0051] Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in the field without making any creative work shall fall within the scope of protection of the present invention.

[0052] The embodiment of the present invention provides an ADC sampling conversion method based on AI correction. Figure 1 , Figure 1 A flowchart of an ADC sampling conversion method based on AI correction provided by an embodiment of the present invention. The method comprises the following steps:

[0053] Initialize the system architecture and configure each MCU; for each configured MCU, obtain the noise signal around each MCU, and analyze the noise signal to calculate the noise interference coefficient;

[0054] Send the same external clock signal to the configured clock input terminals of each MCU, record the timestamp of the MCU clock signal, and calculate the sampling coordination failure coefficient;

[0055] The overall unqualified coefficient of the single-chip microcomputer is obtained according to the noise interference coefficient and the sampling coordination unqualified coefficient, and the overall unqualified coefficient is compared with the preset overall unqualified coefficient threshold, and it is judged whether each configured single-chip microcomputer can perform sampling conversion according to the comparison result;

[0056] When each configured single-chip microcomputer can perform sampling conversion, each sub-chip microcomputer completes data acquisition and storage in an orderly manner, and the master control single-chip microcomputer collects sampling data from each sub-chip microcomputer, integrates the sampling data and stores it in the host computer; and the data storage is completed step by step according to the sampling sequence until all data are read.

[0057] Based on the AI-corrected ADC sampling conversion method provided in the embodiment of the present invention, the system complexity and cost of ADC sampling conversion can be reduced through the above-mentioned method, which makes the high-speed data acquisition system less restricted in miniaturized, low-cost, and easy-to-implement application scenarios.

[0058] In one embodiment, the system architecture is initialized and each single-chip microcomputer is configured as follows:

[0059] The system architecture includes single chip microcomputer 0 (master control single chip microcomputer) and single chip microcomputer 1 to single chip microcomputer n (sub-single chip microcomputers), external memory, and host computer.

[0060] MCU 0 is responsible for sending instructions and summarizing data, MCU 1 to n are responsible for ADC data acquisition and storage; external memory saves data, and the host computer saves or displays data.

[0061] It should be noted that if Figure 2The system architecture structure diagram shown in the figure includes MCU 0, MCU 1, ... and MCU n, external memory, host computer, etc., where MCU 0 is the master control MCU, responsible for issuing ADC acquisition processing commands and data summary and collation to each sub-MCU, and MCU 1 to MCU n are sub-MCUs, responsible for ADC data acquisition and storage. The external memory is responsible for saving the data sent by the master control MCU 0 to the external memory (such as TF card), and the host computer mainly saves the data sent by the master control MCU 0 to the host computer, or displays the results in real time on the host computer. All MCUs 0 to MCU n are connected together through a serial bus (preferred solution). Each MCU has a serial bus inside, and each MCU has a DMA (direct memory access) module integrated inside. MCU 1-MCU n preferably uses the same type and model MCU, because their parameters are consistent and easy to control. MCU 0 is the master control MCU, and its parameters can be different from those of MCU 1 to MCU n, because MCU 0 is not responsible for ADC data acquisition and conversion.

[0062] At present, most single-chip microcomputers have integrated ADC modules, but the conversion speed is low and cannot realize high-speed ADC sampling and conversion. Single-chip microcomputers are cheap, usually only a few yuan a piece, and even cheaper ones can be bought for a few cents. These single-chip microcomputers are combined, and the ADC inside each single-chip microcomputer is queued, and the samples are converted in chronological order. Then, the DMA module inside the single-chip microcomputer is used to move the ADC-converted data from the background to the SRAM memory inside each single-chip microcomputer, and store them in order. Then, the master control single-chip microcomputer 0 reads the data stored in the SRAM of each sub-single-chip microcomputer 1-single-chip microcomputer n through instructions and stores them in order to the external memory, or sends them to the host computer for storage and real-time display.

[0063] In one implementation, the advantage of this architecture is that it utilizes multiple microcontrollers to work in parallel, effectively improving the overall sampling rate and avoiding the sampling speed bottleneck of a single microcontroller. At the same time, it achieves high efficiency of data transmission through time-sharing sampling and DMA modules, reducing the use of CPU resources. In addition, the use of low-cost microcontroller combinations not only reduces the overall cost of the system, but also improves the scalability and maintenance convenience of the system through modular design; the master control microcontroller centrally manages the data collection and aggregation of each microcontroller, simplifies the overall logical structure, and makes the system more stable and efficient, suitable for large-scale data collection scenarios.

[0064] In one embodiment, obtaining noise signals around each single-chip microcomputer and analyzing the noise signals to calculate the noise interference coefficient includes:

[0065] Obtain the noise signal around each single-chip microcomputer and mark it as K(s), where s=1, 2, 3, 4, ..., n+1, n+1 is a positive integer, and n+1 represents the total number of all single-chip microcomputers;

[0066] Morlet wavelet is used to perform continuous wavelet transform on the noise signal K(s) around each single-chip microcomputer. The noise signal is decomposed in the time domain and frequency domain through continuous wavelet transform (CWT). Continuous wavelet transform is realized through convolution. The calculation formula is as follows: Where K(s) is the input signal, ψ(s) is the selected wavelet basis function, a is the scale parameter used to adjust the scale of the wavelet basis function; b is the translation parameter used to adjust the position of the wavelet basis function; s represents the time coordinate of the signal, that is, the position on the time axis;

[0067] For each scale a and translation b, the result calculated using wavelet transform is called wavelet coefficient;

[0068] Extract the energy characteristics of the wavelet coefficients. According to the calculated wavelet coefficients, further extract the energy characteristics, calculate the energy of the wavelet coefficients at each scale, and then perform weighted summation of the energies at different scales to obtain the comprehensive energy characteristics. The calculation formula is as follows: Where E(a) is the energy at scale a, CWT(a,b) is the wavelet coefficient;

[0069] Calculate the noise interference index of each scale, and the calculation expression is: FK(s)=E(a) where FK(s) is the noise interference index;

[0070] Add the noise interference index FK(s) of each scale to get the noise interference coefficient. The calculation formula is: Where ED is the noise interference coefficient.

[0071] It should be noted that the data acquisition method involved in the above calculation mainly relies on the capture of environmental signals around each single-chip microcomputer. Specifically, each single-chip microcomputer obtains the surrounding noise signals in real time through the sensor or signal acquisition module connected to it, forming an original signal sequence in the time domain. These signals are transmitted to the memory of the single-chip microcomputer for storage, and then the noise signal is subjected to continuous wavelet transform using a built-in or external signal processing module (such as a DSP or MCU software algorithm) to decompose it into wavelet coefficients under multiple scales and translation parameters. By controlling the sampling frequency and resolution of the original noise signal, it is ensured that the collected data is detailed enough to cover the full frequency domain characteristics of the signal. After completing the calculation of the wavelet coefficients, each single-chip microcomputer further extracts the energy characteristics, and calculates the noise interference index and the final noise interference coefficient at different scales by cumulative summation. The data acquisition in these processes includes the acquisition, digital conversion and real-time analysis of the time domain noise signal, and through a unified algorithm process, it is ensured that the calculation results of each single-chip microcomputer are consistent and comparable.

[0072] It should be noted that the noise interference coefficient is used to measure the degree of signal interference around each microcontroller configured in the system architecture. The microcontroller ADC module is sensitive to the signal input range, frequency range and noise, and high-speed signals usually need to pass through precise front-end signal conditioning circuits (such as filtering and gain control) to meet the sampling requirements; if the surrounding noise signal interference is large, it may cause problems with the data of each microcontroller configured in the system architecture, because if the surrounding noise signal interference is large, it may cause problems with the data of each microcontroller configured in the system architecture, mainly because the noise signal will directly affect the input signal quality of the ADC module. The ADC module is usually very sensitive to the amplitude, frequency and noise of the input signal, especially in the case of high-speed sampling, the slight fluctuation of the signal or unstable noise will cause the sampling accuracy to decrease. When the noise signal intensity is high, it may be superimposed on the original signal, thereby causing interference during the sampling process, causing signal distortion or data loss. Even with precise front-end signal conditioning circuits, such as filters and gain control circuits, it is difficult to completely eliminate the influence of high-frequency or random noise, especially when the noise source frequency is close to the signal frequency, the interference is more obvious. In addition, noise may also affect the stability of the microcontroller through electromagnetic interference and other channels, resulting in internal circuit timing errors or signal processing errors, which further affects the accuracy of data acquisition. Therefore, noise interference is one of the key factors affecting system performance and data reliability. Effective noise control measures must be taken to ensure the stable operation of the system and the accuracy of the data.

[0073] In one implementation, the benefits of analyzing the noise interference coefficient for the well-architected ADC sampling conversion are: First, by real-time monitoring and calculating the noise interference coefficient, the degree of interference of the surrounding environment on the ADC input signal can be effectively evaluated, which provides data support for system optimization. If the noise interference coefficient is high, the system can promptly identify potential signal quality problems and take corresponding measures, such as adjusting the sampling frequency, strengthening signal conditioning, or using a higher-precision filter circuit to reduce the impact of noise. In addition, the noise interference coefficient can also be used as an indicator of the health of the system to help engineers discover risks that may cause sampling errors or inaccurate data in advance, so as to effectively optimize in the design stage, or adjust parameters during actual operation to ensure that the signals collected by the system are more stable and reliable. In this way, the noise interference coefficient not only improves the fault tolerance of the system, but also improves the accuracy and reliability of data acquisition, which helps to ensure the efficiency and accuracy of the entire sampling and conversion process.

[0074] In one embodiment, the same external clock signal is sent to each configured single-chip computer clock input terminal, and the timestamp of the single-chip computer clock signal is recorded. The sampling coordination failure coefficient is calculated including:

[0075] Send the same external clock signal to the configured clock input terminals of each microcontroller, and record the timestamp of the microcontroller's clock signal. Set the timestamp of each microcontroller as T i , where i is the number of the microcontroller, i = 1, 2, 3....n;

[0076] For each microcontroller i, calculate its timestamp T i The deviation ΔT from the timestamp T0 of the master control microcontroller i :ΔT i =|T i -T0|;

[0077] Calculate the sampling coordination unqualified coefficient, the calculation formula is: Where SD is the sampling coordination failure coefficient.

[0078] It should be noted that after receiving an external clock pulse, each microcontroller will start the timer and record the current timestamp. These timestamps reflect the actual time when each microcontroller receives the clock signal; the external clock signal comes from a high-precision clock source or a synchronization signal generator, and this signal is connected to the clock input of each microcontroller through hardware. All microcontrollers receive the same clock signal to ensure that they work under the same time reference. This signal can be a precise clock pulse (such as a crystal oscillator with a stable frequency or a synchronization pulse signal); each microcontroller is configured with a timer inside, and when it receives an external clock pulse, it starts the timer and records the current timestamp. The recording of timestamps can be achieved in the following ways: the timer inside the microcontroller is triggered by an external clock signal, records the current timing value, and transmits this timestamp to the master control microcontroller or stores it in local memory for subsequent comparisons.

[0079] It should be noted that the sampling coordination failure coefficient is used to measure the degree of sampling coordination inconsistency of each sub-MCU and the master control MCU configured in the system architecture. If the sampling coordination failure coefficient is large, it means that there is a significant deviation in the clock synchronization between each sub-MCU and the master control MCU in the system architecture, which may cause inconsistent sampling timing of each MCU. This inconsistency can cause a variety of problems. For example, when multiple MCUs are collecting data at the same time, if there is a large deviation in their sampling moments, the collected data may have timing disorder or data loss. Specifically, the data may not accurately reflect the real signal changes, especially for sampling tasks that require high synchronization (such as high-speed signal acquisition or multi-channel data processing), the deviation in timing will directly affect the reliability and accuracy of the data. In addition, coordination inconsistency may also cause spectrum distortion or phase error, causing the frequency domain characteristics of the signal to be distorted, thereby affecting the subsequent signal analysis and processing process. Therefore, a large sampling coordination failure coefficient may cause the system to be unable to provide stable and high-quality sampling data, thereby affecting the performance and results of the entire system.

[0080] In one implementation method, the benefit of analyzing the sampling coordination failure coefficient for the well-structured ADC sampling conversion is that the introduction of the sampling coordination failure coefficient plays an important optimization role in the well-structured ADC sampling conversion system. By calculating and monitoring the sampling coordination failure coefficient, the clock synchronization accuracy between each single-chip microcomputer and the master control single-chip microcomputer can be effectively evaluated and ensured, thereby ensuring that the sampling timing of multiple single-chip microcomputers is highly consistent. If it is found that the sampling coordination failure coefficient is large, the system can take timely measures to calibrate or adjust it to avoid timing confusion and data inconsistency. In this way, the system can provide higher quality and more accurate sampling data, reduce errors and signal distortion caused by sampling asynchrony, especially in multi-channel signal acquisition and high-frequency sampling occasions, it is particularly important to maintain synchronization. By controlling and optimizing the sampling coordination failure coefficient, the system can effectively avoid the influence of adverse factors such as noise interference and clock drift, ensure the stability and reliability of the ADC sampling conversion results, thereby improving the performance of the overall system and improving the accuracy of data processing and analysis.

[0081] In one embodiment, obtaining the overall unqualified coefficient of the single chip microcomputer according to the noise interference coefficient and the sampling coordination unqualified coefficient includes:

[0082]

[0083] Where Wsx is the overall qualified coefficient, ED and SD are the noise interference coefficient and sampling coordination unqualified coefficient respectively, α and β are the preset proportional coefficients of the noise interference coefficient and sampling coordination unqualified coefficient respectively, and α and β are both greater than 0.

[0084] It should be noted that comparing the overall unqualified coefficient with the preset overall unqualified coefficient threshold, and judging whether each configured single-chip microcomputer can perform sampling conversion according to the comparison result includes:

[0085] The overall unqualified coefficient is compared with the preset overall unqualified coefficient threshold. If the overall unqualified coefficient is not less than the preset overall unqualified coefficient threshold, it means that each configured single-chip microcomputer cannot perform sampling conversion;

[0086] If the overall unqualified coefficient is less than the preset overall unqualified coefficient threshold, it means that each configured single-chip microcomputer can perform sampling conversion.

[0087] In one implementation, the overall unqualified coefficient is compared with a preset overall unqualified coefficient threshold, which can effectively determine whether each configured single-chip microcomputer has the conditions for sampling conversion. Specifically, if the overall unqualified coefficient is greater than or equal to the preset threshold, it means that there are large deviations in the clock synchronization, sampling coordination and other aspects of the system, which may lead to inconsistent data collection or large measurement errors. The system is not suitable for sampling conversion at this time. On the contrary, if the overall unqualified coefficient is less than the preset threshold, it means that the various single-chip microcomputers in the system work well together, clock synchronization and sampling conversion can proceed smoothly, and the data collection results are more accurate and stable. This approach can effectively avoid data errors or system failures caused by problems such as clock asynchrony and sampling asynchrony, improve the reliability and stability of the system, and ensure the quality of sampling conversion, thereby providing a reliable foundation for subsequent data processing and analysis.

[0088] In one embodiment, when the overall unqualified coefficient is not less than the preset overall unqualified coefficient threshold, it means that there are major problems with the synchronization or coordination between the single-chip microcomputers of the system, and sampling conversion cannot be performed directly at this time. AI-based measures can include using machine learning models to predict and identify factors that may cause high unqualified coefficients, such as clock synchronization delays, network communication problems, hardware failures, etc. The AI ​​model can perform pattern recognition based on historical data and real-time collected parameters (such as the stability of clock signals, sampling errors of each single-chip microcomputer, etc.), automatically adjust the system configuration or issue an early warning. For example, the AI ​​system can reduce the unqualified coefficient by dynamically adjusting the clock frequency, optimizing the data transmission path, predicting and correcting the time deviation between each single-chip microcomputer, or recommending reconfiguration of hardware and software parameters. In addition, AI can also provide an adaptive adjustment mechanism by analyzing anomalies in the data stream in real time to ensure that the system is restored to a state where efficient sampling conversion can be performed, thereby avoiding data errors and system failures caused by inconsistent coordination, and improving the stability and reliability of the overall system.

[0089] In one embodiment, each sub-MCU completes data collection and storage in order, the master control MCU collects sampling data from each sub-MCU, integrates the sampling data and stores it in the host computer; and the data storage is completed step by step according to the sampling sequence until all data are read, including:

[0090] The master control microcontroller triggers the ADC modules of the sub-microcontrollers 1 to n to sample in turn at time interval t1. Each sampling duration is t0. The collected data is transferred to the internal SRAM by the DMA module of each microcontroller without CPU participation. The startup interval t1·n of adjacent sub-microcontrollers is greater than t0 to avoid sampling conflicts.

[0091] The master control microcontroller reads the sampled data in the SRAM of the sub-microcontrollers in sequence through the serial bus. The reading order is completed one by one according to the microcontroller number to ensure data integrity and transmission order.

[0092] Integrate sampled data and store or output to the host computer, store the aggregated data in external memory, and send it to the host computer via serial communication; support real-time data display and processing;

[0093] Repeatedly read the sampled data in the SRAM of the sub-microcontroller, and execute the next round of sampling according to the set sampling frequency and timing strategy until all data are read.

[0094] It should be noted that in step 1: Figure 3 As shown in the ADC data acquisition subroutine flow chart, all MCUs are initialized first, including ADC initialization, DMA initialization, IO port initialization, serial communication initialization, etc. (Master control MCU 0 does not need ADC initialization because master control MCU 0 is not responsible for ADC data acquisition). The function implemented by DMA initialization is: DMA stores the data collected and converted by ADC to SRAM in the background, which does not occupy the CPU resources of the MCU and greatly improves the ADC conversion speed and efficiency.

[0095] Step 2: The master control microcontroller 0 commands the microcontroller 1 to start the data acquisition conversion of the internal integrated ADC1 through the serial bus. The time required for the conversion is t0 (the time t0 is determined by the parameters of the ADC inside the microcontroller). After the ADC data conversion is completed, the DMA1 inside the microcontroller 1 automatically stores the converted data in sequence to SRAM1.

[0096] Step 3: Delay time t1, which is the time interval mentioned above;

[0097] Step 4: The master control microcontroller 0 instructs the microcontroller 2 to start the data acquisition conversion of the ADC2 integrated inside it through the serial bus. The time required for the conversion is t0. After the ADC2 data conversion is completed, the DMA2 inside the microcontroller 2 automatically stores the converted data in sequence to SRAM2.

[0098] Step 5: Delay time t1;

[0099] Step 6: The master control microcontroller 0 commands the microcontroller 3 to start the data acquisition conversion of the ADC3 integrated inside it through the serial bus. The time required for the conversion is t0. After the ADC3 data conversion is completed, the DMA3 inside the microcontroller 3 automatically stores the converted data in sequence to SRAM3.

[0100] Step 7: Delay time t1;

[0101] …

[0102] Step m-1: The master control microcontroller 0 commands the microcontroller n to start the data acquisition conversion of the ADCn integrated inside it through the serial bus. The time required for the conversion is t0. After the ADCn data conversion is completed, the DMAn inside the microcontroller n automatically stores the converted data in sequence to SRAMn.

[0103] Step m: delay time t1;

[0104] Repeat the above steps 2 to m k times.

[0105] Then, the master control microcontroller 0 obtains the data stored in the SRAM of each microcontroller 1 to microcontroller n in sequence through the serial bus, and sends it to the external memory for storage or to the host computer for storage and display. The details are as follows: Figure 4 The data cycle collection diagram and Figure 5 The data reading and storage subroutine flow chart shown:

[0106] The master control microcontroller 0 first obtains the data of the first storage unit in SRAM1 through the serial bus, and then saves it to the first storage unit of the external memory, or saves it to the first storage unit of the host computer;

[0107] The master control microcontroller 0 first obtains the data of the first storage unit in SRAM2 through the serial bus, and then saves it to the second storage unit of the external memory, or saves it to the second storage unit of the host computer;

[0108] The master control microcontroller 0 first obtains the data of the first storage unit in SRAM3 through the serial bus, and then saves it to the third storage unit of the external memory, or saves it to the third storage unit of the host computer;

[0109] …

[0110] The master control microcontroller 0 first obtains the data of the first storage unit in SRAMn through the serial bus, and then saves it to the nth storage unit of the external memory, or saves it to the nth storage unit of the host computer;

[0111] To this end, the first cycle of data collection is completed and the second cycle of data collection begins:

[0112] The master control microcontroller 0 first obtains the data of the second storage unit in SRAM1 through the serial bus, and then saves it to the n+1th storage unit of the external memory, or saves it to the n+1th storage unit of the host computer;

[0113] The master control microcontroller 0 first obtains the data of the second storage unit in SRAM2 through the serial bus, and then saves it to the n+2th storage unit of the external memory, or saves it to the n+2th storage unit of the host computer;

[0114] The master control microcontroller 0 first obtains the data of the second storage unit in SRAM3 through the serial bus, and then saves it to the n+3th storage unit of the external memory, or saves it to the n+3th storage unit of the host computer;

[0115] …

[0116] The master control microcontroller 0 first obtains the data of the second storage unit in SRAMn through the serial bus, and then saves it to the n+nth storage unit of the external memory, or saves it to the n+nth storage unit of the host computer;

[0117] To this end, the second cycle of data collection is completed and the third cycle of data collection begins:

[0118] …

[0119] The master control microcontroller 0 first obtains the data of the kth storage unit in SRAM1 through the serial bus, and then saves it to the (k-1)n+1th storage unit of the external memory, or saves it to the (k-1)n+1th storage unit of the host computer;

[0120] The master control microcontroller 0 first obtains the data of the kth storage unit in SRAM2 through the serial bus, and then saves it to the (k-1)n+2th storage unit of the external memory, or saves it to the (k-1)n+2th storage unit of the host computer;

[0121] The master control microcontroller 0 first obtains the data of the kth storage unit in SRAM3 through the serial bus, and then saves it to the (k-1)n+3th storage unit of the external memory, or saves it to the (k-1)n+3th storage unit of the host computer;

[0122] …

[0123] The master control microcontroller 0 first obtains the data of the kth storage unit in SRAMn through the serial bus, and then saves it to the k*nth storage unit of the external memory, or saves it to the k*nth storage unit of the host computer;

[0124] The above data is read until the kth cycle of data collection, from which all the collected data are read and stored. The system has completed all the work.

[0125] It should be noted that t0 is the time required for each MCU's on-chip ADC to convert once. This time is determined by the performance of the MCU itself. Generally, MCU 1 to MCU n use MCUs of the same model and brand, and try to ensure that s0 of each MCU is consistent.

[0126] t1 is the time interval between two adjacent ADC samplings, which is manually set and can be adjusted. When time t1 is smaller, n is larger (the more microcontrollers there are), the sampling points are denser, and the overall ADC sampling rate is higher. However, when each cycle of acquisition is completed, it must be ensured that the data of the first point of the cycle has been collected. Otherwise, the data of the first point of the next cycle cannot be started. Therefore, s1 and s0 need to satisfy: t1·n>t0.

[0127] In one implementation, the benefits of the above steps are:

[0128] 1. The sampling conversion rate is high and can exceed the sampling rate of professional high-speed ADC chips. In the present invention, when the time t1 is smaller and the sampling points are denser, the overall ADC sampling rate is higher. When t1 is very small and n is larger, the overall ADC sampling rate is very high and will exceed the sampling rate of professional high-speed ADC chips.

[0129] 2: The overall price is much lower than the price of professional high-speed ADC chips on the market. As we all know, professional high-speed ADC chips are expensive, while the single-chip microcomputer chips used in the present invention are very cheap. Even if they are combined, the overall price is generally less than one-fifth of that of professional high-speed ADC chips, or even one-tenth;

[0130] 3: The time interval t1 between two adjacent samplings is manually controllable, so the sampling rate can be adjusted at any time, which brings convenience to users;

[0131] Based on the same inventive concept, the embodiment of the present invention also provides an ADC sampling conversion system based on AI correction. Figure 6 , Figure 6 A framework diagram of an ADC sampling and conversion system based on AI correction provided by an embodiment of the present invention, the system comprising:

[0132] Noise interference module: initialize the system architecture and configure each MCU; for each configured MCU, obtain the noise signal around each MCU, analyze the noise signal and calculate the noise interference coefficient;

[0133] Collaboration failure module: sends the same external clock signal to the configured clock input terminals of each MCU, records the timestamp of the MCU clock signal, and calculates the sampling coordination failure coefficient;

[0134] Comparison and judgment module: obtain the overall unqualified coefficient of the single-chip microcomputer according to the noise interference coefficient and the sampling coordination unqualified coefficient, and compare the overall unqualified coefficient with the preset overall unqualified coefficient threshold, and judge whether each configured single-chip microcomputer can perform sampling conversion according to the comparison result;

[0135] Sampling conversion module: When the configured MCUs are ready for sampling conversion, each sub-MCU completes data acquisition and storage in an orderly manner, and the master control MCU collects sampling data from each sub-MCU, integrates the sampling data and stores it in the host computer; and data storage is completed step by step according to the sampling sequence until all data are read.

[0136] Based on the AI-corrected ADC sampling and conversion system provided in the embodiment of the present invention, the system complexity and cost of ADC sampling and conversion can be reduced through the above-mentioned method, which makes the high-speed data acquisition system less restricted in miniaturized, low-cost, and easy-to-implement application scenarios.

[0137] The above is a detailed description of an embodiment of the present invention, but the content is only a preferred embodiment of the present invention and cannot be used to artificially limit the scope of implementation of the present invention. All equivalent changes and improvements made within the scope of the present invention should still fall within the scope of the patent coverage of the present invention.

Claims

1. The ADC sampling conversion method based on AI correction is characterized in that: The following steps are involved: Initialize the system architecture and configure each MCU; for each configured MCU, obtain the noise signal around each MCU, and analyze the noise signal to calculate the noise interference coefficient; Send the same external clock signal to the configured clock input terminals of each MCU, record the timestamp of the MCU clock signal, and calculate the sampling coordination failure coefficient; The overall unqualified coefficient of the single-chip microcomputer is obtained according to the noise interference coefficient and the sampling coordination unqualified coefficient, and the overall unqualified coefficient is compared with the preset overall unqualified coefficient threshold, and it is judged whether each configured single-chip microcomputer can perform sampling conversion according to the comparison result; When each configured single-chip microcomputer can perform sampling conversion, each sub-chip microcomputer completes data acquisition and storage in an orderly manner, and the master control single-chip microcomputer collects sampling data from each sub-chip microcomputer, integrates the sampling data and stores it in the host computer; and the data storage is completed step by step according to the sampling sequence until all data are read.

2. The ADC sampling conversion method based on AI correction according to claim 1, characterized in that: Initialize the system architecture and configure each microcontroller as follows: The system architecture includes single chip microcomputer 0 and single chip microcomputer 1 to single chip microcomputer n, external memory, and host computer; MCU 0 is responsible for sending instructions and summarizing data, MCU 1 to n are responsible for ADC data acquisition and storage; external memory saves data, and the host computer saves or displays data.

3. The ADC sampling conversion method based on AI correction according to claim 1, characterized in that: Calculating the noise interference factor includes: Obtain the noise signal around each single-chip microcomputer and mark it as K(s), where s=1, 2, 3, 4, ..., n+1, n+1 is a positive integer, and n+1 represents the total number of all single-chip microcomputers; Morlet wavelet is used to perform continuous wavelet transform on the noise signal K(s) around each single-chip microcomputer. The noise signal is decomposed in the time domain and frequency domain through continuous wavelet transform (CWT). Continuous wavelet transform is realized through convolution. The calculation formula is as follows: Where K(s) is the input signal, ψ(s) is the selected wavelet basis function, a is the scale parameter used to adjust the scale of the wavelet basis function; b is the translation parameter used to adjust the position of the wavelet basis function; s represents the time coordinate of the signal, that is, the position on the time axis; For each scale a and translation b, the result calculated using wavelet transform is called wavelet coefficient; Extract the energy characteristics of the wavelet coefficients. According to the calculated wavelet coefficients, further extract the energy characteristics, calculate the energy of the wavelet coefficients at each scale, and then perform weighted summation of the energies at different scales to obtain the comprehensive energy characteristics. The calculation formula is as follows: Where E(a) is the energy at scale a, CWT(a,b) is the wavelet coefficient; Calculate the noise interference index of each scale, and the calculation expression is: FK(s)=E(a) where FK(s) is the noise interference index; Add the noise interference index FK(s) of each scale to get the noise interference coefficient. The calculation formula is: Where ED is the noise interference coefficient.

4. The ADC sampling conversion method based on AI correction according to claim 1, characterized in that: Calculation of sampling coordination failure coefficient includes: Send the same external clock signal to the configured clock input terminals of each microcontroller, and record the timestamp of the microcontroller's clock signal. Set the timestamp of each microcontroller as T i , where i is the number of the microcontroller, i = 1, 2, 3....n; For each microcontroller i, calculate its timestamp T i The deviation ΔT from the timestamp T0 of the master control microcontroller i :ΔT i =|T i -T0|; Calculate the sampling coordination unqualified coefficient, the calculation formula is: Where SD is the sampling coordination failure coefficient.

5. The ADC sampling conversion method based on AI correction according to claim 1, characterized in that: The overall unqualified coefficient of the microcontroller obtained according to the noise interference coefficient and the sampling coordination unqualified coefficient includes: Where Wsx is the overall qualified coefficient, ED and SD are the noise interference coefficient and sampling coordination unqualified coefficient respectively, α and β are the preset proportional coefficients of the noise interference coefficient and sampling coordination unqualified coefficient respectively, and α and β are both greater than 0.

6. The ADC sampling conversion method based on AI correction according to claim 1, characterized in that: Compare the overall unqualified coefficient with the preset overall unqualified coefficient threshold, and judge whether each configured microcontroller can perform sampling conversion according to the comparison result, including: The overall unqualified coefficient is compared with the preset overall unqualified coefficient threshold. If the overall unqualified coefficient is not less than the preset overall unqualified coefficient threshold, it means that each configured single-chip microcomputer cannot perform sampling conversion; If the overall unqualified coefficient is less than the preset overall unqualified coefficient threshold, it means that each configured single-chip microcomputer can perform sampling conversion.

7. The ADC sampling conversion method based on AI correction according to claim 1, characterized in that: Each sub-MCU completes data collection and storage in order. The master control MCU collects sampling data from each sub-MCU, integrates the sampling data and stores it in the host computer. The data storage is completed step by step according to the sampling sequence until all data are read, including: The master control microcontroller triggers the ADC modules of the sub-microcontrollers 1 to n to sample in turn at time interval t1. Each sampling duration is t0. The collected data is transferred to the internal SRAM by the DMA module of each microcontroller without CPU participation. The startup interval t1·n of adjacent sub-microcontrollers is greater than t0 to avoid sampling conflicts. The master control microcontroller reads the sampled data in the SRAM of the sub-microcontrollers in sequence through the serial bus. The reading order is completed one by one according to the microcontroller number to ensure data integrity and transmission order; Integrate sampled data and store or output to the host computer, store the aggregated data in external memory, and send it to the host computer via serial communication; support real-time data display and processing; Repeatedly read the sampled data in the SRAM of the sub-microcontroller, and execute the next round of sampling according to the set sampling frequency and timing strategy until all data are read.

8. An ADC sampling conversion system based on AI correction, used to implement the ADC sampling conversion method based on AI correction according to any one of claims 1 to 7 above, characterized in that: The system comprises: Noise interference module: initialize the system architecture and configure each MCU; for each configured MCU, obtain the noise signal around each MCU, analyze the noise signal and calculate the noise interference coefficient; Collaboration failure module: sends the same external clock signal to the configured clock input terminals of each MCU, records the timestamp of the MCU clock signal, and calculates the sampling coordination failure coefficient; Comparison and judgment module: obtain the overall unqualified coefficient of the single-chip microcomputer according to the noise interference coefficient and the sampling coordination unqualified coefficient, and compare the overall unqualified coefficient with the preset overall unqualified coefficient threshold, and judge whether each configured single-chip microcomputer can perform sampling conversion according to the comparison result; Sampling conversion module: When the configured MCUs are ready for sampling conversion, each sub-MCU completes data acquisition and storage in an orderly manner, and the master control MCU collects sampling data from each sub-MCU, integrates the sampling data and stores it in the host computer; and data storage is completed step by step according to the sampling sequence until all data are read.

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