Downlink fault detection method and apparatus, access network device, and medium

Abstract

The application discloses a downlink fault detection method and device, an access network device and a medium, and relates to the field of wireless communication. The specific implementation scheme is as follows: when it is monitored that the downlink of a target cell is faulty, reading test parameters of the target cell in a current radio frame from a storage module in a processing chip of a BBU; determining scheduling parameters and cell parameters according to the test parameters; serially inputting the scheduling parameters and the cell parameters into a bit-level processing module, a symbol-level processing module, a compression module and a CA exchange module in the processing chip; and determining a fault cause of the downlink according to the output of at least one of the CA exchange module, the bit-level processing module and the symbol-level processing module. Thus, the processing chip of the BBU is divided into modules, when the downlink between the BBU and an AAU is faulty, each module in the processing chip is tested based on the test parameters, so that the fault cause of the downlink can be accurately located according to the actual output of each module.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of wireless communication, and in particular to a downlink fault detection method and device, an access network device and a medium. BACKGROUND

[0002] In a wireless communication system (such as a LTE (Long Term Evolution) communication system or a NR (New Radio) communication system), a simple structure can be divided into two subsystems, namely a BBU (Building Baseband Unit) and an AAU (Active Antenna Unit). When a downlink fault occurs between the BBU and the AAU, it is very important to locate the fault cause and to repair the downlink according to the fault cause, so as to improve the stability of the downlink and the reliability and effectiveness of data transmission. SUMMARY

[0003] The present application provides a downlink fault detection method and device, an access network device and a medium.

[0004] According to an aspect of the present application, a downlink fault detection method is provided, which comprises: reading test parameters of a target cell in a current radio frame from a storage module in a processing chip of a BBU (Building Baseband Unit) when a downlink fault of the target cell is monitored; wherein the downlink comprises a communication link between the BBU and an AAU (Active Antenna Unit) corresponding to the target cell; determining scheduling parameters and cell parameters according to the test parameters; inputting the scheduling parameters and the cell parameters into a bit-level processing module, a symbol-level processing module, a compression module and a CA (Carrier Antenna) switching module in the processing chip in series; and determining a fault cause of the downlink according to an output of at least one of the CA switching module, the bit-level processing module and the symbol-level processing module.

[0005] As a possible implementation manner, the determination of the fault cause of the downlink according to the output of at least one of the CA switching module, the bit-level processing module and the symbol-level processing module comprises: obtaining a first actual output of the CA switching module, and determining whether the processing chip has a fault according to the first actual output; if the processing chip has a fault, obtaining a second actual output of a target processing module; wherein the target processing module comprises the bit-level processing module and / or the symbol-level processing module; and determining a fault cause of the processing chip in the downlink according to the second actual output.

[0006] As a possible implementation manner, the determining whether the processing chip is faulty according to the first actual output comprises: querying a first standard output corresponding to the CA exchange module under a current radio frame; the first standard output is obtained by simulating and testing the CA exchange module according to test parameters; in a case where the first standard output does not match the first actual output, it is determined that the processing chip is faulty; in a case where the first standard output matches the first actual output, it is determined that the processing chip is not faulty.

[0007] As a possible implementation manner, the determining the fault cause of the processing chip in the downlink according to the second actual output comprises: obtaining a second actual output of a symbol-level processing module in the processing chip; querying a second standard output corresponding to the symbol-level processing module under a current radio frame; the second standard output is obtained by simulating and testing the symbol-level processing module according to test parameters; in a case where the second actual output of the symbol-level processing module matches the second standard output, it is determined that the fault cause of the processing chip in the downlink is that the compression module and / or the CA exchange module is faulty.

[0008] As a possible implementation manner, the determining the fault cause of the processing chip in the downlink according to the second actual output further comprises: in a case where the second actual output of the symbol-level processing module does not match the second standard output, obtaining a second actual output of a bit-level processing module; querying a third standard output corresponding to the bit-level processing module under a current radio frame; the third standard output is obtained by simulating and testing the bit-level processing module according to test parameters; in a case where the second actual output of the bit-level processing module matches the third standard output, it is determined that the fault cause of the processing chip in the downlink is that the symbol-level processing module is faulty.

[0009] As a possible implementation manner, the determining the fault cause of the processing chip in the downlink according to the second actual output further comprises: in a case where the second actual output of the bit-level processing module does not match the third standard output, it is determined that the fault cause of the processing chip in the downlink is that the bit-level processing module is faulty.

[0010] As a possible implementation manner, the determining the fault cause of the downlink according to the output of at least one of the CA exchange module, the bit-level processing module and the symbol-level processing module further comprises: if the processing chip is not faulty, it is determined that the fault cause of the downlink is that layer 2 in the BBU is faulty or the AAU is faulty.

[0011] As a possible implementation manner, the storage module is configured to store a parameter file of at least one cell, wherein the parameter file comprises a test parameter of a corresponding cell in a current radio frame, the current radio frame comprises M subframes, and M is a positive integer; and when a downlink fault of a target cell is monitored, the test parameter of the target cell in the current radio frame is read from a storage module in a processing chip in an indoor baseband processing unit (BBU) corresponding to the target cell, comprising: performing M first reading processes on the storage module when the downlink fault in the target cell is monitored; reading data read by the i th first reading process as a sub-test parameter of an i th subframe; wherein i is a positive integer not greater than M; and determining the test parameter according to the sub-test parameters of the M subframes.

[0012] As a possible implementation manner, when the downlink fault in the target cell is monitored, the M first reading processes are performed on the storage module, comprising: determining candidate storage addresses from each storage address of the storage module; wherein the candidate storage addresses are configured to store the parameter file of the target cell; determining a target storage address from each candidate storage address for the i th first reading process; wherein the target storage address is configured to store the sub-test parameter of the i th subframe; performing N second reading processes on the storage module according to a target data amount and a total data amount stored in the target storage address; wherein the target data amount is configured to indicate a data amount of a single reading; N is determined according to a ratio of the total amount and the target data amount; and reading data read by the N second reading processes as data read by the i th first reading process.

[0013] As a possible implementation manner, the first second reading process comprises: determining a base address starting to be read by the first second reading process according to a first storage address in each target storage address; reading data of the target data amount from the base address starting to be read by the first second reading process, and taking the data as data read by the first second reading process; determining a base address starting to be read by the second second reading process according to an end address ending to be read by the first second reading process; and the non-first second reading process comprises: reading data of the target data amount from the base address starting to be read by the second reading process, and taking the data as data read by the second reading process; and determining a base address starting to be read by the next second reading process according to an end address ending to be read by the second reading process.

[0014] As a possible implementation manner, the scheduling parameter and the cell parameter are determined according to the test parameter, comprising: sequentially storing data read by each second reading process into a cache module in the processing chip; reading the scheduling parameter from a first storage area in the cache module; and reading the cell parameter from a second storage area in the cache module.

[0015] As a possible implementation manner, the data read by each second reading process is sequentially stored in a cache module in the processing chip, including: for any second reading process, extracting a first sub-parameter related to scheduling and a second sub-parameter related to a cell from the data read by the second reading process; performing format conversion on the first sub-parameter according to a first output format of a PCIE interface in the processing chip to obtain the first sub-parameter in the first output format; wherein the first output format is determined according to a data format of an actual scheduling parameter sent by the PCIE interface to a bit-level processing module, and the actual scheduling parameter is sent by layer 2 in the BBU to the processing chip; performing format conversion on the second sub-parameter according to a second output format of the PCIE interface in the processing chip to obtain the second sub-parameter in the second output format; wherein the second output format is determined according to a data format of an actual cell parameter sent by the PCIE interface to the bit-level processing module, and the actual cell parameter is sent by layer 2 to the processing chip; and caching the first sub-parameter in the first output format to a first storage area and caching the second sub-parameter in the second output format to a second storage area.

[0016] As a possible implementation manner, when it is monitored that the downlink of the target cell fails, the method further includes: disconnecting the communication link between the PCIE interface and the bit-level processing module; and establishing a communication link between the storage unit and the bit-level processing module.

[0017] As a possible implementation manner, the processing chip is a field programmable logic gate array (FPGA), and the storage module is a double data rate synchronous dynamic random access memory (DDR SDRAM).

[0018] According to another aspect of the present application, an access network device is provided, including:

[0019] a memory, a transceiver, and a processor:

[0020] a memory for storing a computer program, a transceiver for transceiving data under the control of a processor, and a processor for reading the computer program in the memory and performing the following operations: when it is monitored that the downlink of the target cell fails, reading the test parameters of the target cell in the current radio frame from a storage module in a processing chip of a BBU; wherein the downlink includes a communication link between the BBU and an AAU corresponding to the target cell; determining the scheduling parameters and the cell parameters according to the test parameters; serially inputting the scheduling parameters and the cell parameters to a bit-level processing module, a symbol-level processing module, a compression module, and a CA switching module in the processing chip; and determining the cause of the failure of the downlink according to the output of at least one of the CA switching module, the bit-level processing module, and the symbol-level processing module.

[0021] As a possible implementation manner, the processor performs determination of the fault cause of the downlink according to an output of at least one of the CA exchange module, the bit-level processing module and the symbol-level processing module, specifically: obtaining a first actual output of the CA exchange module, and determining whether the processing chip is faulty according to the first actual output; if the processing chip is faulty, obtaining a second actual output of a target processing module; wherein the target processing module comprises the bit-level processing module and / or the symbol-level processing module; and determining the fault cause of the processing chip in the downlink according to the second actual output.

[0022] As a possible implementation manner, the processor performs determination of whether the processing chip is faulty according to the first actual output, specifically: querying a first standard output corresponding to the CA exchange module under a current radio frame; wherein the first standard output is obtained by performing simulation test on the CA exchange module according to test parameters; and determining that the processing chip is faulty in a case where the first standard output does not match the first actual output; and determining that the processing chip is not faulty in a case where the first standard output matches the first actual output.

[0023] As a possible implementation manner, the processor performs determination of the fault cause of the processing chip in the downlink according to the second actual output, specifically: obtaining a second actual output of the symbol-level processing module in the processing chip; querying a second standard output corresponding to the symbol-level processing module under a current radio frame; wherein the second standard output is obtained by performing simulation test on the symbol-level processing module according to test parameters; and determining that the fault cause of the processing chip in the downlink is that the compression module and / or the CA exchange module are faulty in a case where the second actual output of the symbol-level processing module matches the second standard output.

[0024] As a possible implementation manner, the processor performs determination of the fault cause of the processing chip in the downlink according to the second actual output, specifically: obtaining a second actual output of the bit-level processing module in a case where the second actual output of the symbol-level processing module does not match the second standard output; querying a third standard output corresponding to the bit-level processing module under a current radio frame; wherein the third standard output is obtained by performing simulation test on the bit-level processing module according to test parameters; and determining that the fault cause of the processing chip in the downlink is that the symbol-level processing module is faulty in a case where the second actual output of the bit-level processing module matches the third standard output.

[0025] As a possible implementation manner, the processor performs determination of the fault cause of the processing chip in the downlink according to the second actual output, specifically: determining that the fault cause of the processing chip in the downlink is that the bit-level processing module is faulty in a case where the second actual output of the bit-level processing module does not match the third standard output.

[0026] As a possible implementation manner, the processor executes the output of at least one of the CA exchange module, the bit-level processing module and the symbol-level processing module, and determines the fault cause of the downlink, specifically: if the processing chip does not fail, it is determined that the fault cause of the downlink is that layer 2 in the BBU fails or the AAU fails.

[0027] As a possible implementation manner, the storage module is configured to store a parameter file of at least one cell, wherein the parameter file comprises test parameters of the corresponding cell in a current radio frame, and the current radio frame comprises M subframes, and M is a positive integer; and the processor is configured to read, when monitoring that a downlink of a target cell fails, the test parameters of the target cell in the current radio frame from the storage module in a processing chip in an indoor baseband processing unit (BBU) corresponding to the target cell, specifically: performing M first reading processes on the storage module when monitoring that the downlink in the target cell fails; taking the data read by the i th first reading process as the sub-test parameters of the i th subframe; wherein i is a positive integer not greater than M; and determining the test parameters according to the sub-test parameters of the M subframes.

[0028] As a possible implementation manner, the processor is configured to perform M first reading processes on the storage module when monitoring that the downlink in the target cell fails, specifically: determining candidate storage addresses from the storage addresses of the storage module; wherein the candidate storage addresses are configured to store the parameter file of the target cell; determining target storage addresses from the candidate storage addresses for the i th first reading process; wherein the target storage addresses are configured to store the sub-test parameters of the i th subframe; performing N second reading processes on the storage module according to the target data amount and the total data amount stored in the target storage addresses; wherein the target data amount is configured to indicate the data amount of a single reading; N is determined according to the ratio of the total amount to the target data amount; and taking the data read by the N second reading processes as the data read by the i th first reading process.

[0029] As a possible implementation manner, the processor is configured to perform the first second reading process, specifically: determining a base address starting to be read by the first second reading process according to a first storage address in the target storage addresses; reading the target data amount of data starting from the base address read by the first second reading process, and taking the data as the data read by the first second reading process; determining a base address starting to be read by the second second reading process according to an end address ending the reading of the first second reading process; and the processor is configured to perform the non-first second reading process, specifically: reading the target data amount of data starting from the base address read by the second reading process, and taking the data as the data read by the second reading process; and determining a base address starting to be read by the next second reading process according to an end address ending the reading of the second reading process.

[0030] As a possible implementation manner, the processor performs determining the scheduling parameter and the cell parameter according to the test parameter, specifically: sequentially storing the data read by each second reading process into a cache module in the processing chip; reading the scheduling parameter from a first storage area in the cache module; reading the cell parameter from a second storage area in the cache module.

[0031] As a possible implementation manner, the processor performs sequentially storing the data read by each second reading process into a cache module in the processing chip, specifically: for any second reading process, extracting a first sub-parameter related to scheduling and a second sub-parameter related to a cell from the data read by the second reading process; performing format conversion on the first sub-parameter according to a first output format of a PCIE interface in the processing chip, to obtain the first sub-parameter in the first output format; wherein the first output format is determined according to a data format of an actual scheduling parameter sent by the PCIE interface to the bit-level processing module, and the actual scheduling parameter is sent by layer 2 in the BBU to the processing chip; performing format conversion on the second sub-parameter according to a second output format of the PCIE interface in the processing chip, to obtain the second sub-parameter in the second output format; wherein the second output format is determined according to a data format of an actual cell parameter sent by the PCIE interface to the bit-level processing module, and the actual cell parameter is sent by layer 2 to the processing chip; caching the first sub-parameter in the first output format to a first storage area, and caching the second sub-parameter in the second output format to a second storage area.

[0032] As a possible implementation manner, the processor is further configured to perform the following operation: when monitoring that the downlink of the target cell fails, disconnecting the communication link between the PCIE interface and the bit-level processing module; and establishing a communication link between the storage unit and the bit-level processing module.

[0033] As a possible implementation manner, the processing chip is a field programmable logic gate array (FPGA), and the storage module is a double data rate synchronous dynamic random access memory (DDR SDRAM).

[0034] According to another aspect of the present application, a downlink failure detection apparatus is provided, comprising:

[0035] a reading unit configured to read, when monitoring that the downlink of the target cell fails, a test parameter of the target cell in a current radio frame from a storage module in a processing chip of an indoor baseband processing unit (BBU); wherein the downlink comprises a communication link between the BBU and an active antenna unit (AAU) corresponding to the target cell;

[0036] a first determining unit configured to determine a scheduling parameter and a cell parameter according to the test parameter;

[0037] The input unit is configured to serially input the scheduling parameters and the cell parameters to the bit-level processing module, the symbol-level processing module, the compression module and the carrier antenna (CA) switching module in the processing chip.

[0038] The second determination unit is configured to determine the cause of the failure of the downlink according to the output of at least one of the CA switching module, the bit-level processing module and the symbol-level processing module.

[0039] As a possible implementation, the second determination unit is specifically configured to: acquire the first actual output of the CA switching module, and determine whether the processing chip fails according to the first actual output; if the processing chip fails, acquire the second actual output of the target processing module; wherein the target processing module includes the bit-level processing module and / or the symbol-level processing module; and determine the cause of the failure of the processing chip in the downlink according to the second actual output.

[0040] As a possible implementation, the second determination unit is specifically configured to: query the first standard output corresponding to the CA switching module under the current radio frame; wherein the first standard output is obtained by simulating and testing the CA switching module according to the test parameters; and determine that the processing chip fails in a case where the first standard output does not match the first actual output; and determine that the processing chip does not fail in a case where the first standard output matches the first actual output.

[0041] As a possible implementation, the second determination unit is specifically configured to: acquire the second actual output of the symbol-level processing module in the processing chip; and query the second standard output corresponding to the symbol-level processing module under the current radio frame; wherein the second standard output is obtained by simulating and testing the symbol-level processing module according to the test parameters; and determine that the cause of the failure of the processing chip in the downlink is that the compression module and / or the CA switching module fails in a case where the second actual output of the symbol-level processing module matches the second standard output.

[0042] As a possible implementation, the second determination unit is further configured to: acquire the second actual output of the bit-level processing module in a case where the second actual output of the symbol-level processing module does not match the second standard output; query the third standard output corresponding to the bit-level processing module under the current radio frame; wherein the third standard output is obtained by simulating and testing the bit-level processing module according to the test parameters; and determine that the cause of the failure of the processing chip in the downlink is that the symbol-level processing module fails in a case where the second actual output of the bit-level processing module matches the third standard output.

[0043] As a possible implementation, the second determining unit is further configured to determine, in a case where the second actual output of the bit-level processing module does not match the third standard output, that a failure cause of the processing chip in the downlink is that the bit-level processing module fails.

[0044] As a possible implementation, the second determining unit is further configured to determine, in a case where the processing chip does not fail, that a failure cause of the downlink is that a layer 2 in the BBU fails or the AAU fails.

[0045] As a possible implementation, the storage module is configured to store a parameter file of at least one cell, wherein the parameter file comprises test parameters of a corresponding cell in a current radio frame, the current radio frame comprises M subframes, and M is a positive integer; and the reading unit is specifically configured to perform M first reading processes on the storage module when monitoring that a downlink in a target cell fails; read data obtained in the i th first reading process as sub-test parameters of an i th subframe, wherein i is a positive integer not greater than M; and determine the test parameters according to the sub-test parameters of the M subframes.

[0046] As a possible implementation, the reading unit is specifically configured to determine candidate storage addresses from each storage address of the storage module, wherein the candidate storage addresses are used to store parameter files of the target cell; determine a target storage address from each candidate storage address for the i th first reading process, wherein the target storage address is used to store sub-test parameters of an i th subframe; perform N second reading processes on the storage module according to a target data amount and a total data amount stored in the target storage address, wherein the target data amount is used to indicate a data amount of a single reading; N is determined according to a ratio of the total amount and the target data amount; and read data obtained in the N second reading processes as data obtained in the i th first reading process.

[0047] As a possible implementation, the first second reading process comprises: determining a base address at which the first second reading process starts reading according to a first storage address in each target storage address; reading data of the target data amount from the base address at which the first second reading process starts reading, and taking the data as data obtained in the first second reading process; determining a base address at which a second second reading process starts reading according to an end address at which the first second reading process ends reading; and the non-first second reading process comprises: reading data of the target data amount from a base address at which the second second reading process starts reading, and taking the data as data obtained in the second second reading process; and determining a base address at which a next second reading process starts reading according to an end address at which the second second reading process ends reading.

[0048] As a possible implementation manner, the first determining unit is specifically configured to: sequentially store the data read by each second reading process into a cache module in the processing chip; read the scheduling parameter from a first storage area in the cache module; and read the cell parameter from a second storage area in the cache module.

[0049] As a possible implementation manner, the first determining unit is specifically configured to: for any second reading process, extract the first sub-parameter related to scheduling and the second sub-parameter related to the cell from the data read by the second reading process; perform format conversion on the first sub-parameter according to a first output format of the PCIE interface in the processing chip, to obtain the first sub-parameter in the first output format; wherein the first output format is determined according to a data format of an actual scheduling parameter sent by the PCIE interface to the bit-level processing module, and the actual scheduling parameter is sent by layer 2 in the BBU to the processing chip; perform format conversion on the second sub-parameter according to a second output format of the PCIE interface in the processing chip, to obtain the second sub-parameter in the second output format; wherein the second output format is determined according to a data format of an actual cell parameter sent by the PCIE interface to the bit-level processing module, and the actual cell parameter is sent by layer 2 to the processing chip; and cache the first sub-parameter in the first output format to the first storage area, and cache the second sub-parameter in the second output format to the second storage area.

[0050] As a possible implementation manner, the apparatus further comprises:

[0051] The disconnecting unit is configured to disconnect the communication link between the PCIE interface and the bit-level processing module when it is monitored that the downlink of the target cell fails.

[0052] The establishing unit is configured to establish the communication link between the storage unit and the bit-level processing module.

[0053] As a possible implementation manner, the processing chip is a field programmable logic gate array (FPGA), and the storage module is a double data rate synchronous dynamic random access memory (DDR SDRAM).

[0054] According to another aspect of the present application, a processor-readable storage medium is provided, and the processor-readable storage medium stores a computer program, and the computer program is configured to enable a processor to execute the downlink failure detection method of the above-mentioned embodiments.

[0055] According to another aspect of the present application, a computer program product is provided, and the computer program product comprises a computer program, and the computer program is configured to enable a processor to implement the downlink failure detection method of the above-mentioned embodiments of the present application when executed by the processor.

[0056] The downlink fault detection method, device, access network equipment and medium provided by the embodiments of the present application can realize module division on the processing chip of the BBU, and when the downlink between the BBU and the AAU fails, each module in the processing chip is tested based on the test parameters, so that the actual output of each module can be used to accurately locate the fault cause of the downlink, and then the downlink can be repaired according to the fault cause, so as to improve the stability of the downlink and the reliability and effectiveness of data transmission.

[0057] It should be understood that the content described in this part is not intended to identify the key or important features of the embodiments of the present application, nor is it used to limit the scope of the present application. Other features of the present application will become apparent from the following description. BRIEF DESCRIPTION OF DRAWINGS

[0058] The accompanying drawings are used to better understand the present application, and do not limit the present application. Among them:

[0059] Figure 1 An architecture diagram for capturing time domain data using an optical port in the related art;

[0060] Figure 2 A flowchart of a downlink fault detection method provided by an embodiment of the present application;

[0061] Figure 3 A flowchart of another downlink fault detection method provided by an embodiment of the present application;

[0062] Figure 4 A flowchart of another downlink fault detection method provided by an embodiment of the present application;

[0063] Figure 5 A flowchart of another downlink fault detection method provided by an embodiment of the present application;

[0064] Figure 6 An implementation principle diagram of a closed-loop debugging link pile driving number troubleshooting provided by an embodiment of the present application;

[0065] Figure 7 A detailed diagram of a processing flow of a bit-level processing module provided by an embodiment of the present application;

[0066] Figure 8 A detailed diagram of a processing flow of a symbol-level processing module provided by an embodiment of the present application;

[0067] Figure 9 A software implementation flowchart of a closed-loop pile driving number troubleshooting provided by an embodiment of the present application;

[0068] Figure 10 A structure diagram of a pile driving module provided in an embodiment of the present application;

[0069] Figure 11 A pile driving control implementation flowchart of three cells provided in an embodiment of the present application;

[0070] Figure 12 An implementation flowchart of single-subframe reading DDR provided in an embodiment of the present application;

[0071] Figure 13 A structure diagram of an access network device provided in an embodiment of the present application;

[0072] Figure 14 A structure diagram of a downlink fault detection device provided in an embodiment of the present application. DETAILED DESCRIPTION

[0073] In the embodiments of the present application, the term "and / or" describes the association relationship of the associated objects, which means that there can be three relationships, for example, A and / or B can represent the following three cases: A exists alone, A and B exist simultaneously, and B exists alone. The character " / " generally represents an "or" relationship between the associated objects before and after it.

[0074] In the embodiments of the present application, the term "multiple" means two or more, and other quantifiers are similar.

[0075] The technical solutions in the embodiments of the present application will be described clearly and completely in combination with the drawings in the embodiments of the present application. Obviously, the described embodiments are only some of the embodiments of the present application, not all the embodiments. Based on the embodiments in the present application, all other embodiments obtained by those skilled in the art without creative labor fall within the scope of protection of the present application.

[0076] In a wireless communication system, if a new function is developed, or in a commercial field operation and maintenance scene, the following two problems can exist:

[0077] First, in the development process of the new function, how to efficiently and completely verify the correctness of the downlink between the BBU and the AAU;

[0078] Second, in the field operation scene, various faults often occur between the BBU and the AAU in the downlink. When a fault occurs in the downlink, how to efficiently locate the cause of the fault to determine whether the cause of the fault is attributed to the BBU or the AAU, and when the cause of the fault is attributed to the BBU, how to determine whether the cause of the fault is caused by a processing chip (such as an FPGA (Field Programmable Gate Array)) in the BBU, and if the cause of the fault is not caused by the processing chip, how to efficiently and quickly confirm that the problem is not caused by a module inside the processing chip.

[0079] Currently, a scheduling parameter of capturing an L2 (Layer 2) in the BBU to the processing chip can be increased, and the downlink is tested for faults based on the scheduling parameter.

[0080] Although this scheme can largely distinguish the problem between the processing chip and the L2, there is no way to exclude the problem between the processing chip and the AAU. Moreover, if the scheme determines that the cause of the fault is caused by the processing chip, there is no way to determine which node inside the processing chip introduces the problem.

[0081] In the related art, the downlink between the BBU and the AAU is mainly tested for faults by the following two schemes:

[0082] First, a traditional debugging scheme: from the entrance of the PCIE (Peripheral Component Interconnect Express) interface of the processing chip to the exit of the downlink link level (that is, the entrance of the optical port of the processing chip), an ila (integrated logic analyzer) is inserted inside the processing chip according to nodes, the data signals, address signals, and write enable signals and other related signals that need to be observed are put into the ila core, and then a simulator is used to connect the JTAG (Joint Test Action Group) debugging interface of the processing chip outside the board card, the other end of the simulator is connected to a computer to locate the cause of the fault by real-time online capturing.

[0083] However, this scheme is limited by the hardware environment and can only be used in the laboratory, and cannot be used in the field. In addition, the way of increasing the ila core needs to occupy the storage resources of the processing chip, and different ila needs to be recompiled into a new version in many times, so the diagnosis efficiency of the fault is low, and the visible data length is short and cannot master comprehensive information.

[0084] Second, the scheme of using the optical port to capture data: according to the 80ms time domain data captured from the optical port of the processing chip, the fault reason is located.

[0085] However, the time domain data in this scheme needs to be used with parameters. Since the corresponding parameter information cannot be extracted at the same time as the time domain data is obtained, only whether the time domain data from the optical port is non-zero can be seen, which has no substantial guiding significance.

[0086] As an example, taking the processing chip as an FPGA, the architecture diagram of using the optical port to capture time domain data can be as shown in Figure 1 , wherein CA refers to the abbreviation of carrier antenna, and DDR refers to the abbreviation of double data rate SRAM (synchronous dynamic random access memory).

[0087] In summary, the first scheme has at least the following disadvantages: increasing the version of ila, increasing resources, long version cycle (6-7 hours at a time), relatively short length of viewable data, incomplete information, resulting in low fault diagnosis efficiency; only suitable for laboratory use, not for field use.

[0088] The second scheme has at least the following disadvantages: no parameter analysis, time domain data can only determine whether it is non-zero, and lacks guiding significance.

[0089] Therefore, in order to solve at least one of the above problems, the embodiments of the present application provide a downlink fault detection method and device, an access network device and a medium, wherein the method and the device are based on the same application concept. Since the principles of the method and the device for solving problems are similar, the implementation of the device and the method can be mutually referred to, and the repeated parts will not be described again.

[0090] The downlink fault detection method, device, access network device and medium provided by the present application are described below with reference to the accompanying drawings.

[0091] Figure 2 The flowchart of the downlink fault detection method provided by the embodiments of the present application is shown in the figure.

[0092] The downlink fault detection method of the embodiments of the present application can be executed by an access network device.

[0093] The access network device can be a base station, where the base station can include multiple cells that serve terminal devices. Depending on the particular application, the base station can also be referred to as an access point, or can be a device that communicates with wireless terminal devices over an air interface through one or more sectors, or other names. The base station can be configured to exchange received air frames with Internet Protocol (IP) packets, as a router between the wireless terminal devices and the rest of the access network, which can include an Internet Protocol (IP) communications network. The base station can also coordinate management of properties of the air interface. For example, the base station can be a Base Transceiver Station (BTS) in Global System for Mobile communications (GSM) or Code Division Multiple Access (CDMA), a NodeB in Wide-band Code Division Multiple Access (WCDMA), an evolved Node B (eNB or e-NodeB) in long term evolution (LTE) systems, a 5G base station (gNB) in next generation system (5G network architecture), a Home evolved Node B (HeNB), a relay node, a femto, a pico, etc., without limitation in the embodiments of the present application. In some network structures, the base station can include a Centralized Unit (CU) node and a Distributed Unit (DU) node, and the centralized unit and the distributed unit can also be geographically separated.

[0094] The terminal device can be a device providing voice and / or data connectivity to a user, a handheld device having wireless connection capability, or other processing devices connected to a wireless modem, etc. In different systems, the name of the terminal device can also be different, for example, in the 5G system, the terminal device can be called user equipment (User Equipment, UE for short). The wireless terminal device can communicate with one or more core networks (Core Network, CN for short) through a radio access network (Radio Access Network, RAN for short). The wireless terminal device can be a mobile terminal device, such as a mobile phone (or called "cellular" phone) and a computer with a mobile terminal device, for example, it can be a portable, pocket, handheld, built-in computer or vehicle-mounted mobile device, which exchanges language and / or data with the radio access network. For example, personal communication service (Personal Communication Service, PCS for short) phones, cordless phones, session initiation protocol (Session Initiated Protocol, SIP for short) phones, wireless local loop (Wireless Local Loop, WLL for short) stations, personal digital assistants (Personal Digital Assistant, PDA for short) and other devices. The wireless terminal device can also be called a system, a subscriber unit, a subscriber station, a mobile station, a mobile, a remote station, an access point, a remote terminal, an access terminal, a user terminal, a user agent, a user device, which is not limited in the embodiments of the present application.

[0095] As shown in the figure, the downlink fault detection method can include the following steps: Figure 2

[0096] Step S201, when the downlink of the target cell is monitored to fail, the test parameters of the target cell in the current radio frame are read from the storage module in the processing chip of the BBU; wherein the downlink includes the communication link between the BBU and the AAU corresponding to the target cell.

[0097] The current radio frame can include a plurality of subframes, for example, the current radio frame (10ms) can include 10 subframes (1ms). ​

[0098] In the embodiment of the present application, when it is monitored that the downlink between the BBU and the AAU of the target cell fails, the test parameters (or referred to as driving parameters) of the target cell under the current radio frame can be read from the storage module in the processing chip of the BBU.

[0099] In step S202, the scheduling parameters and the cell parameters are determined according to the test parameters.

[0100] In the embodiment of the present application, the scheduling parameters (used for scheduling each terminal device in the target cell) and the cell parameters can be determined according to the test parameters.

[0101] In step S203, the scheduling parameters and the cell parameters are serially input to the bit-level processing module, the symbol-level processing module, the compression module and the CA exchange module in the processing chip.

[0102] In the embodiment of the present application, the scheduling parameters and the cell parameters can be input to the bit-level processing module in the processing chip, then the actual output of the bit-level processing module is input to the symbol-level processing module in the processing chip, then the actual output of the symbol-level processing module is input to the compression module in the processing chip, and then the actual output of the compression module can be input to the CA exchange module.

[0103] In step S204, the failure cause of the downlink is determined according to the output of at least one of the CA exchange module, the bit-level processing module and the symbol-level processing module.

[0104] In the embodiment of the present application, the failure cause of the downlink can be determined according to the output of at least one of the CA exchange module, the bit-level processing module and the symbol-level processing module.

[0105] It should be noted that the downlink of the target cell can be detected for failure every radio frame, and in the present application, the test parameters of the target cell under each radio frame (or one radio frame) can be read from the storage module, and each module in the processing chip can be tested based on the test parameters to determine the failure cause of the downlink.

[0106] The downlink fault detection method of the embodiment of the present application reads the test parameters of the target cell in the current radio frame from the storage module in the BBU processing chip when a downlink fault is detected in the target cell; determines the scheduling parameters and cell parameters based on the test parameters; serially inputs the scheduling parameters and cell parameters into the bit-level processing module, symbol-level processing module, compression module, and CA switching module in the processing chip; and determines the cause of the downlink fault based on the output of at least one of the CA switching module, bit-level processing module, and symbol-level processing module. Thus, the BBU processing chip is divided into modules. When a downlink fault occurs between the BBU and the AAU, each module in the processing chip is tested based on the test parameters. Thus, the cause of the downlink fault can be accurately located based on the actual output of each module, and the downlink fault can be repaired based on the cause of the fault, thereby improving the stability of the downlink and improving the reliability and effectiveness of data transmission.

[0107] In order to clearly explain how to determine the cause of a downlink failure in any embodiment of the present application, the present application also proposes a downlink failure detection method.

[0108] Figure 3 A flowchart of another downlink fault detection method provided in an embodiment of the present application.

[0109] like Figure 3 As shown, the downlink fault detection method may include the following steps:

[0110] Step S301 : when a downlink failure of a target cell is detected, the test parameters of the target cell in the current radio frame are read from a storage module in a processing chip of a BBU.

[0111] The downlink includes the communication link between the BBU and the AAU corresponding to the target cell.

[0112] For the explanation of step S301, please refer to the relevant description in any embodiment of the present application and will not be repeated here.

[0113] In any embodiment of the present application, the processing chip may be an FPGA, and the storage module may be a DDR SDRAM.

[0114] Step S302: Determine scheduling parameters and cell parameters according to the test parameters.

[0115] Step S303: The scheduling parameters and cell parameters are serially input into the bit-level processing module, symbol-level processing module, compression module and CA switching module in the processing chip.

[0116] The explanation of steps S302 to S303 can refer to the related description in any embodiment of the present application, which will not be repeated here.

[0117] In step S304, the first actual output of the CA exchange module is obtained, and whether the processing chip is faulty is determined according to the first actual output. If yes, steps S305 to S306 are executed, and if no, step S307 is executed.

[0118] In the embodiments of the present application, the actual output (denoted as the first actual output in the present application) of the CA exchange module can be obtained or extracted, and whether the processing chip is faulty is determined according to the first actual output. If yes, steps S305 to S306 are executed, and if no, step S307 is executed.

[0119] It should be noted that steps S305 to S306 and step S307 are two parallel implementation modes, and only one of them is executed in actual application.

[0120] In any embodiment of the present application, the determination mode of whether the processing chip is faulty is, for example:

[0121] 1. The standard output (denoted as the first standard output in the present application) corresponding to the CA exchange module under the current radio frame is queried, wherein the first standard output is obtained by simulating and testing the CA exchange module according to the test parameters of the target cell under the current radio frame.

[0122] 2. Whether the first standard output matches the first actual output is determined. If the first standard output matches or is consistent with the first actual output, it can be determined that the processing chip is not faulty.

[0123] 3. If the first standard output does not match or is not consistent with the first actual output, it can be determined that the processing chip is faulty.

[0124] As an example, for step S302, the scheduling parameters and cell parameters of multiple subframes in the current radio frame can be determined according to the test parameters, respectively. For step S303, the scheduling parameters and cell parameters of each subframe can be serially input into the bit-level processing module, symbol-level processing module, compression module and CA exchange module in the processing chip, to obtain the actual output of each module in each subframe.

[0125] At this time, for step S304, the first standard output of the CA exchange module can include the standard output of the CA exchange module under multiple subframes, and correspondingly, the first actual output can include the actual output of the CA exchange module under multiple subframes. In this application, it can be determined whether the standard output and the actual output of the CA exchange module under each subframe match, and in the case that the standard output and the actual output of all subframes match, it can be determined that the processing chip does not malfunction, and in the case that the standard output and the actual output of at least one subframe do not match, it can be determined that the processing chip malfunctions.

[0126] Therefore, according to the actual output and the standard output of the CA exchange module under each subframe, whether the processing chip malfunctions can be detected, which can improve the accuracy and reliability of the detection result.

[0127] Step S305: obtaining a second actual output of the target processing module.

[0128] In the embodiments of the present application, in the case that it is determined that the processing chip malfunctions, the second actual output of the target processing module can be further obtained or extracted. The target processing module includes a bit-level processing module and / or a symbol-level processing module.

[0129] Step S306: determining the cause of the malfunction of the processing chip in the downlink according to the second actual output.

[0130] In the embodiments of the present application, the cause of the malfunction of the processing chip in the downlink can be determined according to the second actual output of the target processing module.

[0131] Step S307: determining that the cause of the malfunction of the downlink is that layer 2 in the BBU malfunctions or the AAU malfunctions.

[0132] In the embodiments of the present application, in the case that it is determined that the processing chip does not malfunction, it can be determined that the cause of the malfunction of the downlink is that layer 2 in the BBU malfunctions or the AAU malfunctions.

[0133] The downlink malfunction detection method of the embodiments of the present application can detect which module in the processing chip malfunctions when it is determined that the processing chip in the BBU malfunctions, and can determine that layer 2 in the BBU or the AAU malfunctions when it is determined that the processing chip in the BBU does not malfunction, which can realize accurate positioning of the cause of the malfunction of the downlink, so that the downlink can be repaired according to the cause of the malfunction to improve the stability of the downlink.

[0134] In order to clearly illustrate how the cause of the malfunction of the downlink is determined in any embodiment of the present application, the present application further provides a downlink malfunction detection method.

[0135] Figure 4A flowchart of another downlink fault detection method provided by the embodiments of the present application is shown in FIG. 4.

[0136] As shown in FIG. 4, the downlink fault detection method can include the following steps: Figure 4

[0137] In step S401, when it is monitored that the downlink of the target cell is faulty, the test parameters of the target cell in the current radio frame are read from a storage module in a processing chip of the BBU.

[0138] The downlink includes a communication link between the BBU and the AAU corresponding to the target cell.

[0139] In step S402, the scheduling parameters and the cell parameters are determined according to the test parameters.

[0140] In step S403, the scheduling parameters and the cell parameters are serially input to a bit-level processing module, a symbol-level processing module, a compression module and a CA switching module in the processing chip.

[0141] In step S404, the first actual output of the CA switching module is obtained, and it is determined whether the processing chip is faulty according to the first actual output.

[0142] The explanation of steps S401-S404 can be referred to the related description in any embodiment of the present application, which will not be repeated here.

[0143] In step S405, if the processing chip is faulty, the second actual output of the symbol-level processing module in the processing chip is obtained.

[0144] In the embodiments of the present application, in the case where it is determined that the processing chip is faulty, the actual output (referred to as the second actual output in the present application) of the symbol-level processing module in the processing chip can be further obtained or extracted.

[0145] In step S406, the second standard output corresponding to the symbol-level processing module in the current radio frame is queried.

[0146] The second standard output is obtained by simulating and testing the symbol-level processing module according to the test parameters.

[0147] In the embodiments of the present application, the standard output (referred to as the second standard output in the present application) corresponding to the symbol-level processing module in the current radio frame can be queried, wherein the second standard output is obtained by simulating and testing the symbol-level processing module according to the test parameters of the target cell in the current radio frame.

[0148] In step S407, it is determined whether the second actual output of the symbol-level processing module matches the second standard output, if yes, step S408 is executed, if not, step S409 is executed.​

[0149] In the embodiment of the present application, it can be determined whether the second actual output of the symbol level processing module matches or is consistent with the second standard output, if yes, step S408 is executed, if not, step S409 is executed.

[0150] It should be noted that step S408 and step S409 are two parallel implementation modes, and only one of them needs to be executed in actual application.

[0151] As an example, for step S402, the scheduling parameters and the cell parameters of the plurality of subframes in the current radio frame can be determined respectively according to the test parameters, for step S403, the scheduling parameters and the cell parameters of each subframe can be input into the bit level processing module, the symbol level processing module, the compression module and the CA exchange module in the processing chip in series to obtain the actual output of each module in each subframe.

[0152] At this time, for step S407, the second standard output of the symbol level processing module can include the standard output of the symbol level processing module under the plurality of subframes, and correspondingly, the second actual output of the symbol level processing module can include the actual output of the symbol level processing module under the plurality of subframes, in the present application, it can be determined whether the standard output and the actual output of the symbol level processing module under each subframe match or are consistent, in the case that the standard output and the actual output of all subframes match, it can be determined that the second actual output matches the second standard output, and in the case that the standard output and the actual output of at least one subframe do not match, it can be determined that the second actual output does not match the second standard output.

[0153] Step S408, determining that the fault cause of the processing chip in the downlink is that the compression module and / or the CA exchange module fails.

[0154] In the embodiment of the present application, in the case that the second actual output of the symbol level processing module matches the second standard output, it can be determined that the fault cause of the processing chip in the downlink is that the compression module and / or the CA exchange module fails.

[0155] Step S409, obtaining the second actual output of the bit level processing module, and querying the third standard output corresponding to the bit level processing module under the current radio frame.

[0156] The third standard output is obtained by simulating and testing the bit level processing module according to the test parameters.

[0157] In the embodiment of the present application, in the case that the second actual output of the symbol level processing module does not match the second standard output, the actual output (denoted as the second actual output in the present application) of the bit level processing module can be further acquired or extracted, and the standard output (denoted as the third standard output in the present application) corresponding to the bit level processing module under the current radio frame can also be inquired, wherein the third standard output is obtained by simulating and testing the bit level processing module according to the test parameters of the target cell under the current radio frame.

[0158] In step S410, it is determined whether the second actual output of the bit level processing module matches the third standard output, if yes, step S411 is executed, and if no, step S412 is executed.

[0159] In the embodiment of the present application, it can be determined whether the second actual output of the bit level processing module matches or is consistent with the third standard output, if yes, step S411 is executed, and if no, step S412 is executed.

[0160] It should be noted that step S411 and step S412 are two parallel implementation modes, and only one of them needs to be executed in actual application.

[0161] As an example, for step S402, the scheduling parameters and the cell parameters of the plurality of subframes in the current radio frame can be respectively determined according to the test parameters, for step S403, the scheduling parameters and the cell parameters of each subframe can be respectively serially input into the bit level processing module, the symbol level processing module, the compression module and the CA exchange module in the processing chip to obtain the actual output of each module in each subframe.

[0162] At this time, for step S410, the third standard output can include the standard output of the bit level processing module under the plurality of subframes, and correspondingly, the second actual output of the bit level processing module can include the actual output of the bit level processing module under the plurality of subframes, in the present application, it can be determined whether the standard output and the actual output of the bit level processing module under each subframe match or are consistent, in the case that the standard output and the actual output of all subframes match, it can be determined that the second actual output of the bit level processing module matches the third standard output, and in the case that the standard output and the actual output of at least one subframe do not match, it can be determined that the second actual output of the bit level processing module does not match the third standard output.

[0163] In step S411, it is determined that the fault cause of the processing chip in the downlink is that the symbol level processing module fails.

[0164] In the embodiment of the present application, in the case that the second actual output of the bit level processing module matches the third standard output, it can be determined that the fault cause of the processing chip in the downlink is that the symbol level processing module fails.

[0165] Step S412, determining that the failure cause of the processing chip in the downlink is that the bit-level processing module fails.

[0166] In the embodiment of the application, in the case that the second actual output of the bit-level processing module does not match the third standard output, it can be determined that the failure cause of the processing chip in the downlink is that the bit-level processing module fails.

[0167] The failure detection method of the downlink in the embodiment of the application can detect which specific module in the processing chip fails when it is determined that the processing chip in the BBU fails, thereby improving the efficiency and effectiveness of failure detection, so that the failed module can be repaired in a targeted manner to improve the stability of the downlink.

[0168] In order to clearly illustrate any of the above embodiments, the application further provides a failure detection method of a downlink.

[0169] Figure 5 Another flowchart of a failure detection method of a downlink provided by the embodiment of the application.

[0170] As shown in the figure, the failure detection method of the downlink can include the following steps: Figure 5

[0171] Step S501, when it is monitored that the downlink of the target cell fails, performing M first reading processes on the storage module in the processing chip of the BBU.

[0172] The downlink includes a communication link between the BBU and the AAU corresponding to the target cell.

[0173] M is the number of subframes contained in the current radio frame, and M is a positive integer, for example, M can be 10.

[0174] The storage module is used to store a parameter file (also known as a stake file) of at least one cell, wherein the parameter file includes test parameters of the corresponding cell in the current radio frame.

[0175] In the embodiment of the application, when it is monitored that the downlink in the target cell fails, the storage module in the processing chip of the BBU can be executed M times first reading process.

[0176] In any one of the embodiments of the application, the execution mode of each first reading process can be, for example:

[0177] 1. From each storage address of the storage module, determine a candidate storage address, wherein the candidate storage address is used to store the parameter file of the target cell. ​

[0178] In the present application, the storage addresses of the parameter files of each cell in the storage module are fixed, and the storage addresses for storing the parameter files of the target cell can be determined from the storage addresses of the storage module according to the cell identifier (e.g. cell index) of the target cell, and are used as candidate storage addresses.

[0179] 2. For the i-th (i is a positive integer not greater than M) first reading process, the target storage address can be determined from the candidate storage addresses, wherein the target storage address is used to store the test parameters of the i-th subframe (denoted as sub-test parameters in the present application).

[0180] In the present application, the storage addresses of the test parameters of each cell under each subframe (i.e. sub-test parameters) in the storage module are fixed, and the storage addresses for storing the sub-test parameters of the i-th subframe can be determined from the candidate storage addresses according to the cell identifier (e.g. cell index) of the target cell and the subframe number of the i-th subframe.

[0181] 3. According to the target data amount and the total data amount stored in the target storage address, the storage module is executed N times of the second reading process; wherein the target data amount is used to indicate the data amount of a single reading; and N is determined according to the ratio of the total amount and the target data amount.

[0182] In the present application, the data amount of each reading (denoted as target data amount in the present application) can be determined according to the bit width of the storage module, and the storage module is executed N times of the second reading process according to the target data amount and the total amount stored in the target storage address, wherein N is determined according to the ratio of the total amount and the target data amount.

[0183] That is, in each second reading process, the target data amount of data is read from the target storage address.

[0184] As an example, for the first second reading process: the first storage address in the target storage addresses can be used as the base address (i.e. starting address) for the first second reading process to start reading, and the target data amount of data is read from the base address for the first second reading process to start reading, and is used as the data read by the first second reading process. In addition, the base address for the second second reading process to start reading can also be determined according to the end address for the first second reading process to end reading.

[0185] For the j-th (j = 2, 3, …, N-1) second reading process: the target data amount of data is read from the base address for the j-th second reading process to start reading, and is used as the data read by the j-th second reading process. In addition, the base address for the j+1-th second reading process to start reading can also be determined according to the end address for the j-th second reading process to end reading.

[0186] For the last (ie, Nth) second reading process: starting from the base address read in the Nth second reading process, data of a target data volume may be read and used as the data read in the Nth second reading process.

[0187] 4. The data read in the N second reading processes are used as the data read in the i-th first reading process.

[0188] In the embodiment of the present application, the data read in the N second reading processes may be used as the data read in the i-th first reading process.

[0189] Step S502 : Using the data read in the i-th first reading process as the sub-test parameter of the i-th sub-frame.

[0190] In the embodiment of the present application, the data read in the i-th first reading process may be used as the sub-test parameter of the i-th sub-frame.

[0191] Step S503: Determine the test parameters according to the sub-test parameters of the M sub-frames.

[0192] In this embodiment of the present application, the sub-test parameters of M subframes may be used as the test parameters of the current radio frame.

[0193] Step S504: Determine scheduling parameters and cell parameters according to the test parameters.

[0194] The execution process of step S504 can refer to the relevant description in any embodiment of the present application and will not be repeated here.

[0195] In any embodiment of the present application, the scheduling parameters and cell parameters in the current radio frame are determined, for example, as follows:

[0196] 1. The data read in each second reading process is sequentially stored in the cache module in the processing chip.

[0197] As an example, for any second reading process, the first sub-parameter related to scheduling can be extracted from the data read in the second reading process, and the first sub-parameter can be format converted according to the first output format of the PCIE interface in the processing chip to obtain the first sub-parameter of the first output format. After that, the first sub-parameter of the first output format can be cached to the first storage area of ​​the cache module.

[0198] The first output format is determined according to the data format of the actual scheduling parameters sent by the PCIE interface to the bit-level processing module, and the actual scheduling parameters are the scheduling parameters sent by layer 2 in the BBU to the processing chip.

[0199] And, for any one second reading process, a second sub-parameter related to the cell can also be extracted from the data read by the second reading process, and the second sub-parameter is format-converted according to a second output format of the PCIE interface in the processing chip to obtain the second sub-parameter in the second output format, and then the second sub-parameter in the second output format can be cached to the second storage area of the cache module.

[0200] The second output format is determined according to a data format of the actual cell parameter sent by the PCIE interface to the bit-level processing module, and the actual cell parameter is a cell parameter sent by layer 2 to the processing chip.

[0201] 2. Read the scheduling parameter from the first storage area in the cache module.

[0202] 3. Read the cell parameter from the second storage area in the cache module.

[0203] Step S505: serially input the scheduling parameter and the cell parameter to the bit-level processing module, the symbol-level processing module, the compression module and the CA exchange module in the processing chip.

[0204] The execution process of step S505 can refer to the related description in any embodiment of the present application, which will not be repeated here.

[0205] In any embodiment of the present application, the sub-scheduling parameters of the M sub-frames can be determined from the scheduling parameter of the current radio frame, and the sub-cell parameters of the M sub-frames can be determined from the cell parameter of the current radio frame. In the present application, the sub-scheduling parameter and the sub-cell parameter of each sub-frame can be serially input to the bit-level processing module, the symbol-level processing module, the compression module and the CA exchange module in the processing chip to obtain the actual output of each module in each sub-frame.

[0206] Step S506: determine the failure cause of the downlink according to the output of at least one of the CA exchange module, the bit-level processing module and the symbol-level processing module.

[0207] The execution process of step S506 can refer to the related description in any embodiment of the present application, which will not be repeated here.

[0208] In any embodiment of the present application, in order to avoid the case that layer 2 in the BBU sends the cell parameter and the scheduling parameter to the processing chip, which interferes with the actual detection result, when it is monitored that the downlink of the target cell fails, the communication link between the PCIE interface and the bit-level processing module can be disconnected, and the communication link between the storage unit and the bit-level processing module can be established.

[0209] The downlink fault detection method of the embodiment of the application can realize multiple reading processes on the storage module in the processing chip of the BBU to effectively obtain the test parameters of the current wireless frame, thereby improving the effectiveness of fault detection.

[0210] In any one of the embodiments of the application, when the downlink between the BBU and the AAU fails, it can be determined whether the fault reason is caused by the processing chip of the BBU, if not, it can be further determined whether the fault reason is caused by the previous L2 of the processing chip or the next AAU, if caused by the processing chip, the modules can be split on the link node set inside the processing chip, the problem is shortened on a specific module, and finally the fault reason or problem reason is located through the simulation vector (standard output of the module in the application), so as to achieve the purpose of quickly identifying the problem attribution and quickly iterating the problem solving, and improve the diagnosis efficiency of the fault or problem.

[0211] Specifically, the pile driving function can be added at the downlink service level entrance, the PCIE interface for L2 communication in the processing chip is disconnected, the vector source is input from the entrance of the downlink service level, the scheduling parameters and original bits sent by L2 are completely simulated and replaced in terms of interface and timing content, the parameter distribution, parameter calculation, encoding, pre-modulation, layer mapping, resource mapping, IFFT (Inverse Fast Fourier Transform), CP (Cyclic Prefix) addition, antenna interleaving, compression, CA exchange and other downlink service processing links are realized inside the processing chip, and the operation of extracting 80ms of time domain data is performed at the exit of the downlink service processing link (i.e. the entrance of the optical port of the processing chip).

[0212] Among them, pile driving corresponds to reading the data of the storage module (such as DDR) in the processing chip (such as FPGA), and the number of extraction corresponds to storing the data into the storage module. Taking DDR4 (a new generation of memory specification) as an example, the high-speed read-write characteristics of DDR4 can be utilized, the user side can simultaneously operate the read-write DDR, that is, pile driving is performed while the results of pile driving are collected, and the selection of read-write is completed by the DDR arbitrator, and the storage and writing rate of DDR is lower than the effective read-write bandwidth of DDR. The high-speed read-write characteristics of DDR can ensure that read-write DDR will not send conflicts. In this way, a closed-loop debugging link integrating pile driving and extraction can be realized, the extracted data can be compared with the standard output (or standard vector), and the correctness of the downlink between the entire BBU and AAU can be determined according to the comparison result.

[0213] As an example, taking the processing chip as an FPGA and the storage module as a DDR4 as an example, the implementation principle of the fault troubleshooting of the closed-loop debugging link can be as shown in Figure 6 When the actual output of the CA exchange module is successfully compared with the standard output, it indicates that the fault problem does not occur in the FPGA, otherwise, it indicates that the fault problem occurs in the FPGA. At this time, in order to further narrow down the occurrence range of the fault problem, the exit extraction function of the bit level processing module and the exit extraction function of the symbol level processing module in the downlink can be increased at the same time. Both are in different positions. The results of the pile driving are collected. By introducing the extraction function of multiple nodes (or modules), when the problem occurs in the FPGA, it can be determined that the problem occurs in which node (or module).

[0214] In order to further narrow down the occurrence range of the fault problem and facilitate the analysis of the fault reason, as shown in Figure 6 Compared with the time domain data extraction structure (i.e. Figure 1 ) in the related art, Figure 6 The pile driving module, the selection module and the format conversion module are added. These three newly added core modules and the original optical port time domain data extraction function cooperate to complete the fault troubleshooting of the entire downlink.

[0215] As shown in Figure 6 , the entrance of the downlink service is the PCIE interface, and the exit is the optical port. Taking these two interfaces as the front and back demarcation points of the downlink service level data link, when the downlink between the BBU and the AAU occurs, the parameter pile file (denoted as a parameter file in the application) can be written into the DDR4 storage module through the PCIE interface by driving layer software. In the "selection module", the pile parameters (denoted as debugging parameters in the application) are selected to input this data valid. The "pile driving module" is responsible for reading out the debugging parameters in the parameter file from the DDR4 and converting the debugging parameters into the same data format as the real parameters sent by the PCIE interface, to replace the real parameters sent by the PCIE interface. In the internal processing of the downlink service level module, after passing through the bit level processing module, the symbol level processing module, the compression module and the CA exchange module, the actual output of the CA module is extracted at the exit of the CA module and sent to the soft demux module. The soft demux module is responsible for selecting one way from multiple data and converting the data into a data format conforming to the entrance of the DDR4, and storing it into the DDR4. The driving layer software accesses the DDR4 through the PCIE interface, reads out the data and prints it into a result file, and uses the result file to complete the comparison with the vector result file of the pile. The vector result file of the pile includes the standard output of each module.

[0216] The details of the processing flow of the bit level processing module can be as shown in Figure 7As shown, the details of the processing flow of the symbol level processing module can be as shown in FIG. 4. Figure 8

[0217] Specifically, the software implementation flow of the closed-loop pile driving parameter troubleshooting can be as shown in FIG. 5, mainly including the following steps: Figure 9

[0218] When the downlink between the BBU and the AAU fails, first, the channel is switched through the "selection module" (only the pile parameter (i.e., test parameter) input this channel is selected, and the real parameter input this channel is closed), the channel reading the parameter pile file (denoted as the parameter file in the present application) from the DDR4 is selected as the input, the pile enabling instruction is input to enable the "pile module", the pile function is executed, the parameter file is read from the DDR4 to the entrance of the bit level processing module for pile driving, and the output data of the pile driving is extracted from the outlet of the CA exchange module. The length of the output data can support up to 80ms, i.e., 8 radio frame lengths. The extracted output data and the standard output (or standard vector) corresponding to the CA exchange module are compared. If the vector comparison is successful, it means that the entrance to the outlet of the downlink of the FPGA works normally, and the fault caused by the FPGA is excluded.

[0219] If the vector comparison is not successful, it means that the problem occurs in the FPGA (it may be caused by the FPGA, or it may be a parameter configuration error). At this time, in order to find out the fault point, the outlet data of the previous node (i.e., the symbol level processing module) is switched to compare with the standard output (or standard vector) corresponding to the symbol level processing module. If the vector comparison is successful, it means that the problem occurs in the compression module and / or the CA exchange module. If the vector comparison is not successful, it means that the problem occurs in the previous node (i.e., the bit level processing module) of the symbol level processing module.

[0220] The outlet data of the bit level processing module is compared with the standard output (or standard vector) of the bit level processing module. If the vector comparison is successful, it means that the problem occurs in the symbol level processing module, otherwise, the problem occurs in the bit level processing module.

[0221] The module of the locked problem is further analyzed and positioned, the cause of the fault is found out, and the code is modified. Then, the pile driving is verified again until the problem is solved.

[0222] ​​That is, the core module is a newly added bit-level piling module, which replaces the PCIE interface of L2 to input the vector source file to the business-level entry. Its core is to read the parameter pile file stored in DDR4 (referred to as parameter file in this application) and convert the data format of the parameter file into the data format of the business-level entry to ensure the invisibility of the business-level code program to the input source of the previous level, that is, the parameters of the invisible input are the real parameters sent by L2, or the piling parameters stored in DDR4 (referred to as test parameters in this application). The structure of the piling module can be as follows: Figure 10 As shown:

[0223] It should be noted that a single board on the access network device side can support N (for example, N can be 3) cell piling, and the piling module can be responsible for the control process of 3 cell piling. For example, the FPGA can include a bit-level processing module, and one bit-level processing module can be connected to three symbol-level processing modules in the FAGA, wherein one symbol-level processing module corresponds to one cell, and each symbol-level processing module is connected to a compression module and a CA switching module, and the CA switching module is connected to an optical port. For example, the FPGA can include three optical ports, each optical port is connected to an AAU, wherein each AAU corresponds to one cell, or the FPGA can include only one optical port, one optical port can be connected to one AAU, and one AAU corresponds to three cells.

[0224] Among them, the state machine can be used to control whether the piling of the current cell is completed, when the piling of the next cell is enabled, and how the three cells are cyclically controlled.

[0225] in, Figure 10 DDR base address reading calculation module: The storage address of the test parameters of each cell in each subframe in DDR4 is fixed. The reading of DDR4 adopts the burst operation mode. Therefore, it is necessary to calculate the amount of data read each time according to the bit width of DDR4 (referred to as the target data amount in this application), and calculate the base address for the next read based on the size of the target data amount.

[0226] DDR read data control module: Initiates a burst read request operation on DDR4 according to the interface format and process of reading DDR4.

[0227] DDR readback data processing module: The clock rates and bit widths of the DDR4 interface and PCIE interface may be different. The read DDR4 data needs to be cached, cross-clock processed, and bit width converted.

[0228] User parameter interface conversion module: selects the scheduling parameters from the fixed position in the DDR readback data and converts them into the data format of the actual scheduling parameters of the PCIE interface.

[0229] Cell parameter interface conversion module: select cell parameters from a fixed position in DDR read data, and convert them into the data format of real cell parameters of PCIE interface.

[0230] As an example, the implementation flow of pile driving control for 3 cells can be as shown in Figure 11 The judgment of the pile driving means to be used is shown. A single board supports pile driving for 3 cells. In this application, pile driving can be performed for any one cell or for 3 cells simultaneously. However, each cell is executed serially.

[0231] Specifically, the "trigger pile driving enable" detects whether any cell is pile driving. If so, the first cell (referred to as cell 1) is first judged according to the polling mechanism. If cell 1 is not pile driving enabled, it directly enters the judgment state of the second cell (referred to as cell 2). If cell 1 is pile driving enabled, it is processed according to the single subframe read operation DDR. It is judged whether one subframe of cell 1 is pile driving completed. If so, it enters the judgment state of cell 2. In the judgment state of cell 2, it is first judged whether cell 2 is pile driving enabled. If cell 2 is not pile driving enabled, it directly enters the judgment state of the third cell (referred to as cell 3). If cell 2 is pile driving enabled, it is processed according to the single subframe read operation DDR. It is judged whether one subframe of cell 2 is pile driving completed. If so, it enters the judgment state of cell 3. In the judgment state of cell 3, it is first judged whether cell 3 is pile driving enabled. If cell 3 is not pile driving enabled, it directly returns to the judgment state of cell 1 to perform the judgment state of the next subframe. If cell 3 is pile driving enabled, it is processed according to the single subframe read operation DDR. It is judged whether one subframe of cell 3 is pile driving completed. If so, it enters the judgment state of the first cell to perform the judgment state of the next subframe.

[0232] Figure 11 The function of the pile driving control flow module for 3 cells is realized. The function of reading a single subframe parameter file (referred to as sub test parameter in this disclosure) is realized in the "single subframe read DDR" flow. The specific implementation flow can be as shown in Figure 12 The main steps include the following:

[0233] 1. In the implementation process, it is first judged whether the cell pile driving is enabled. If so, in "calculate 1 read address", the initial address (i.e. base address) of reading DDR4 needs to be determined according to the cell index and the current subframe number. The initial address to be read next time is calculated according to the burst length.

[0234] Each subframe parameter file of each cell occupies a unique storage space in DDR4.

[0235] 2、After obtaining the initial address of reading DDR4, read the DDR data in burst operation in "read DDR", and one burst operation reads data of fixed length.

[0236] 3, "Receive data" buffers the read DDR data.

[0237] 4, "Data format conversion" completes the picking of scheduling parameters, interface conversion, and the picking of cell parameters and interface conversion.

[0238] Among them, the length of the parameter file is fixed, and the length of the data read by each burst is also fixed, so the number of burst reads required by a cell in a subframe is also fixed, for example, a single cell needs 8 times of burst transmission for the data of a parameter file in a subframe, and the counter is incremented once for each burst transmission read.

[0239] 5, "Whether to read a subframe" judges the value of the counter, if the accumulation is 8 times, it is considered that a single cell in a single subframe is completed, and the "cell enable" flow is returned to prepare for the next round of operation.

[0240] 6, If it is judged that a single subframe is not completed, enter the "calculate 1 reading address" flow to calculate the base address of the next reading.

[0241] In summary, when the downlink of the cell fails, it can be effectively judged whether the failure reason is caused by the FPGA subsystem, that is, by adding the pile driving function, the pile driving at the entrance of the FPGA is performed at the same time, and the number is extracted at the exit. This self-generating and self-receiving closed loop method can verify the correctness of the downlink, achieve the purpose of self-vindication and troubleshooting of the failure reason; and the bit-level processing module and the symbol-level processing module are added. When the failure occurs in the internal of the FPGA subsystem, it can be used to judge the fault node position and the positioning range of the convergence problem; in addition, for the development stage of new functions, the state of the entire downlink can be verified, and the unit test in the early stage can be efficiently completed.

[0242] Compared with the prior art, the downlink fault detection method provided by the present application has at least the following advantages:

[0243] 1, Efficiency, this method can quickly judge whether the problem is caused by FPGA (i.e. whether the failure reason is caused by FPGA) through simple pile driving, number extraction and data comparison operations, so as to achieve the purpose of quickly transferring the bug and improve the problem convergence speed;

[0244] 2, Strong flexibility, suitable for any field and laboratory environment, without other auxiliary equipment, and widely used in various application scenarios;

[0245] 3. The general-purpose is stronger, and there is no need to recompile the positioning version for specific problems, saving test time;

[0246] 4. As a maintenance means, it will not destroy the fault scene, so that the occasional problem needs to be reproduced.

[0247] The technical solutions provided by the embodiments of the present application can be applied to various systems, especially 5G systems. For example, the applicable systems can be Global System of Mobile communication (GSM) system, Code Division Multiple Access (CDMA) system, Wideband Code Division Multiple Access (WCDMA) General Packet Radio Service (GPRS) system, long term evolution (LTE) system, LTE Frequency Division Duplex (FDD) system, LTE time division duplex (TDD) system, Long Term Evolution Advanced (LTE-A) system, Universal Mobile Telecommunication System (UMTS), Worldwide interoperability for Microwave Access (WiMAX) system, 5G New Radio (NR) system, etc. Among these various systems, there are terminal and network devices. The system can also include a core network part, such as Evloved Packet System (EPS), 5G system (5GS), etc.

[0248] In order to realize the above-mentioned embodiments, the present application also provides an access network device.

[0249] Figure 13 The structure diagram of an access network device provided by the embodiments of the present application.

[0250] As shown in Figure 13 , the access network device can include: a transceiver 1300, a processor 1310, a memory 1320.

[0251] The memory 1320 is configured to store a computer program; the transceiver 1300 is configured to transceive data under the control of the processor 1310; and the processor 1310 is configured to read the computer program in the memory 1320 and perform the following operations: reading, from a storage module in a processing chip of a BBU, a test parameter of a target cell in a current radio frame when it is monitored that a downlink of the target cell fails; wherein the downlink includes a communication link between the BBU and an AAU corresponding to the target cell; determining a scheduling parameter and a cell parameter according to the test parameter; serially inputting the scheduling parameter and the cell parameter to a bit-level processing module, a symbol-level processing module, a compression module and a CA exchange module in the processing chip; and determining a failure cause of the downlink according to an output of at least one of the CA exchange module, the bit-level processing module and the symbol-level processing module.

[0252] The transceiver 1300 is configured to receive and send data under the control of the processor 1310.

[0253] In the above method, the bus architecture can include any number of interconnected buses and bridges, which are linked together by various circuits of the processor 1310, which represents one or more processors, and the memory 1320, which represents a memory. Figure 13 The bus interface provides an interface to the bus architecture. The transceiver 1300 can be multiple elements, i.e., including a transmitter and a receiver, which provide units for communicating with various other devices over transmission media, including wireless channels, wired channels, optical cables, etc. The processor 1310 is responsible for managing the bus architecture and general processing, and the memory 1320 can store data used by the processor 1310 when performing operations.

[0254] The processor 1310 can be a CPU, an ASIC, an FPGA or a CPLD, and the processor 1310 can also adopt a multi-core architecture.

[0255] As a possible implementation manner, the processor 1310 performs the operation of determining the failure cause of the downlink according to the output of at least one of the CA exchange module, the bit-level processing module and the symbol-level processing module, specifically: obtaining a first actual output of the CA exchange module, and determining whether the processing chip fails according to the first actual output; if the processing chip fails, obtaining a second actual output of a target processing module; wherein the target processing module includes the bit-level processing module and / or the symbol-level processing module; and determining the failure cause of the processing chip in the downlink according to the second actual output.

[0256] As a possible implementation, the processor 1310 performs determining whether the processing chip is faulty according to the first actual output, specifically: querying the first standard output corresponding to the CA exchange module under the current radio frame; wherein the first standard output is obtained by simulating and testing the CA exchange module according to the test parameters; in the case that the first standard output does not match the first actual output, it is determined that the processing chip is faulty; in the case that the first standard output matches the first actual output, it is determined that the processing chip is not faulty.

[0257] As a possible implementation, the processor 1310 performs determining the fault cause of the processing chip in the downlink according to the second actual output, specifically: obtaining the second actual output of the symbol-level processing module in the processing chip; querying the second standard output corresponding to the symbol-level processing module under the current radio frame; wherein the second standard output is obtained by simulating and testing the symbol-level processing module according to the test parameters; in the case that the second actual output of the symbol-level processing module matches the second standard output, it is determined that the fault cause of the processing chip in the downlink is that the compression module and / or the CA exchange module is faulty.

[0258] As a possible implementation, the processor 1310 performs determining the fault cause of the processing chip in the downlink according to the second actual output, specifically: in the case that the second actual output of the symbol-level processing module does not match the second standard output, obtaining the second actual output of the bit-level processing module; querying the third standard output corresponding to the bit-level processing module under the current radio frame; wherein the third standard output is obtained by simulating and testing the bit-level processing module according to the test parameters; in the case that the second actual output of the bit-level processing module matches the third standard output, it is determined that the fault cause of the processing chip in the downlink is that the symbol-level processing module is faulty.

[0259] As a possible implementation, the processor 1310 performs determining the fault cause of the processing chip in the downlink according to the second actual output, specifically: in the case that the second actual output of the bit-level processing module does not match the third standard output, it is determined that the fault cause of the processing chip in the downlink is that the bit-level processing module is faulty.

[0260] As a possible implementation, the processor 1310 performs determining the fault cause of the downlink according to the output of at least one of the CA exchange module, the bit-level processing module and the symbol-level processing module, specifically: if the processing chip is not faulty, it is determined that the fault cause of the downlink is that layer 2 in the BBU is faulty or the AAU is faulty.

[0261] As a possible implementation manner, the storage module is configured to store a parameter file of at least one cell, wherein the parameter file comprises a test parameter of a corresponding cell in a current radio frame, the current radio frame comprises M subframes, and M is a positive integer; and the processor 1310 is configured to read the test parameter of the target cell in the current radio frame from the storage module in the processing chip in the indoor baseband processing unit (BBU) corresponding to the target cell when monitoring that the downlink in the target cell fails, specifically: performing M first reading processes on the storage module when monitoring that the downlink in the target cell fails; taking data read by the i th first reading process as a sub-test parameter of an i th subframe; wherein i is a positive integer not greater than M; and determining the test parameter according to the sub-test parameters of the M subframes.

[0262] As a possible implementation manner, the processor 1310 is configured to perform M first reading processes on the storage module when monitoring that the downlink in the target cell fails, specifically: determining candidate storage addresses from the storage addresses of the storage module; wherein the candidate storage addresses are configured to store the parameter file of the target cell; determining a target storage address from the candidate storage addresses for the i th first reading process; wherein the target storage address is configured to store a sub-test parameter of an i th subframe; performing N second reading processes on the storage module according to a target data amount and a total data amount stored in the target storage address; wherein the target data amount is configured to indicate a data amount of a single reading; N is determined according to a ratio of the total amount and the target data amount; and taking data read by the N second reading processes as data read by the i th first reading process.

[0263] As a possible implementation manner, the processor 1310 is configured to perform a first second reading process, specifically: determining a base address starting to be read by the first second reading process according to a first storage address in the target storage addresses; reading data of the target data amount from the base address starting to be read by the first second reading process, and taking the data as data read by the first second reading process; determining a base address starting to be read by a second second reading process according to an end address ending to be read by the first second reading process; and performing a non-first second reading process by the processor, specifically: reading data of the target data amount from the base address starting to be read by the second reading process, and taking the data as data read by the second reading process; and determining a base address starting to be read by a next second reading process according to an end address ending to be read by the second reading process.

[0264] As a possible implementation manner, the processor 1310 is configured to determine the scheduling parameter and the cell parameter according to the test parameter, specifically: sequentially storing data read by the second reading processes into a cache module in the processing chip; reading the scheduling parameter from a first storage area in the cache module; and reading the cell parameter from a second storage area in the cache module.

[0265] As a possible implementation manner, the processor 1310 executes a cache module for sequentially storing data read by each second reading process into the processing chip, specifically: for any second reading process, extracting the first sub-parameter related to scheduling and the second sub-parameter related to the cell from the data read by any second reading process; performing format conversion on the first sub-parameter according to a first output format of the PCIE interface in the processing chip, to obtain the first sub-parameter in the first output format; wherein the first output format is determined according to a data format of an actual scheduling parameter sent by the PCIE interface to the bit-level processing module, and the actual scheduling parameter is sent by layer 2 in the BBU to the processing chip; performing format conversion on the second sub-parameter according to a second output format of the PCIE interface in the processing chip, to obtain the second sub-parameter in the second output format; wherein the second output format is determined according to a data format of an actual cell parameter sent by the PCIE interface to the bit-level processing module, and the actual cell parameter is sent by layer 2 to the processing chip; caching the first sub-parameter in the first output format to a first storage area, and caching the second sub-parameter in the second output format to a second storage area.

[0266] As a possible implementation manner, the processor 1310 is further configured to perform the following operation: when monitoring that the downlink of the target cell fails, disconnecting the communication link between the PCIE interface and the bit-level processing module; and establishing a communication link between the storage unit and the bit-level processing module.

[0267] As a possible implementation manner, the processing chip is an FPGA, and the storage module is a DDR SDRAM.

[0268] It should be noted that the access network device provided by the embodiment of the present application can implement all the method steps achieved by the method embodiment and achieve the same technical effects. Therefore, the same parts and beneficial effects of the method embodiment will not be described in detail in the embodiment. Figures 2 to 5 Method embodiment, and the same technical effects can be achieved. Therefore, the same parts and beneficial effects of the method embodiment will not be described in detail in the embodiment.

[0269] Corresponding to the downlink failure detection method provided by the above-mentioned Figures 2 to 5 embodiment, the present application also provides a downlink failure detection device. Since the downlink failure detection device provided by the embodiment of the present application corresponds to the downlink failure detection method provided by the above-mentioned Figures 2 to 5 embodiment, the implementation manner of the downlink failure detection method is also applicable to the downlink failure detection device provided by the embodiment of the present application. Therefore, the downlink failure detection device will not be described in detail in the embodiment of the present application.

[0270] Figure 14 A structure diagram of a downlink failure detection device provided by the embodiment of the present application.

[0271] like Figure 14 As shown, the downlink fault detection device 1400 is applied to an access network device and may include: a reading unit 1410 , a first determining unit 1420 , an input unit 1430 and a second determining unit 1440 .

[0272] Among them, the reading unit 1410 is used to read the test parameters of the target cell in the current wireless frame from the storage module in the processing chip of the indoor baseband processing unit BBU when a downlink failure of the target cell is detected; wherein the downlink includes the communication link between the BBU and the active antenna unit AAU corresponding to the target cell.

[0273] The first determining unit 1420 is configured to determine scheduling parameters and cell parameters according to the test parameters.

[0274] The input unit 1430 is used to serially input the scheduling parameters and cell parameters into the bit-level processing module, symbol-level processing module, compression module and carrier antenna CA switching module in the processing chip.

[0275] The second determining unit 1440 is configured to determine a cause of a downlink failure according to an output of at least one of the CA switching module, the bit-level processing module, and the symbol-level processing module.

[0276] As a possible implementation, the second determination unit 1440 is specifically configured to: obtain a first actual output of the CA switching module, and determine whether a processing chip fails based on the first actual output; if the processing chip fails, obtain a second actual output of a target processing module; wherein the target processing module includes a bit-level processing module and / or a symbol-level processing module; and determine a cause of the failure of the processing chip in the downlink based on the second actual output.

[0277] As a possible implementation, the second determination unit 1440 is specifically configured to: query a first standard output corresponding to the CA switching module in the current wireless frame; wherein the first standard output is obtained by performing a simulation test on the CA switching module according to test parameters; if the first standard output does not match the first actual output, determine that a processing chip has failed; and if the first standard output matches the first actual output, determine that the processing chip has not failed.

[0278] As a possible implementation, the second determining unit 1440 is specifically configured to: obtain a second actual output of the symbol-level processing module in the processing chip; query a second standard output corresponding to the symbol-level processing module under a current radio frame; the second standard output is obtained by simulating and testing the symbol-level processing module according to the test parameter; and in a case where the second actual output of the symbol-level processing module matches the second standard output, determine that the fault cause of the processing chip in the downlink is that the compression module and / or the CA switching module is faulty.

[0279] As a possible implementation, the second determining unit 1440 is further configured to: in a case where the second actual output of the symbol-level processing module does not match the second standard output, obtain a second actual output of the bit-level processing module; query a third standard output corresponding to the bit-level processing module under the current radio frame; the third standard output is obtained by simulating and testing the bit-level processing module according to the test parameter; and in a case where the second actual output of the bit-level processing module matches the third standard output, determine that the fault cause of the processing chip in the downlink is that the symbol-level processing module is faulty.

[0280] As a possible implementation, the second determining unit 1440 is further configured to: in a case where the second actual output of the bit-level processing module does not match the third standard output, determine that the fault cause of the processing chip in the downlink is that the bit-level processing module is faulty.

[0281] As a possible implementation, the second determining unit 1440 is further configured to: if the processing chip is not faulty, determine that the fault cause of the downlink is that layer 2 in the BBU is faulty or the AAU is faulty.

[0282] As a possible implementation, the storage module is configured to store a parameter file of at least one cell, wherein the parameter file includes a test parameter of a corresponding cell under a current radio frame, and the current radio frame includes M subframes, and M is a positive integer; and the reading unit 1410 is specifically configured to: when monitoring that a downlink in a target cell is faulty, perform M first reading processes on the storage module; take data read by the i th first reading process as a sub-test parameter of an i th subframe; wherein i is a positive integer not greater than M; and determine the test parameter according to the sub-test parameters of the M subframes.

[0283] As a possible implementation manner, the reading unit 1410 is specifically configured to: determine candidate storage addresses from the storage addresses of the storage module; the candidate storage addresses are used to store parameter files of target cells; determine a target storage address from the candidate storage addresses for the i th first reading process; the target storage address is used to store sub-test parameters of the i th subframe; perform N second reading processes on the storage module according to the target data amount and a total data amount stored in the target storage address; the target data amount is used to indicate a data amount of a single reading; N is determined according to a ratio of the total amount and the target data amount; and data read by the N second reading processes is taken as data read by the i th first reading process.

[0284] As a possible implementation manner, the first second reading process includes: determining a base address of the first second reading process according to a first storage address in the target storage addresses; reading data of the target data amount from the base address of the first second reading process, and taking the data as data read by the first second reading process; determining a base address of the second second reading process according to an end address of the first second reading process; and the non-first second reading process includes: reading data of the target data amount from the base address of the current second reading process, and taking the data as data read by the current second reading process; and determining a base address of the next second reading process according to an end address of the current second reading process.

[0285] As a possible implementation manner, the first determining unit 1420 is specifically configured to: sequentially store data read by each second reading process into a cache module in the processing chip; read scheduling parameters from a first storage area in the cache module; and read cell parameters from a second storage area in the cache module.

[0286] As a possible implementation manner, the first determining unit 1420 is specifically configured to: for any one second reading process, extract the first sub-parameter related to scheduling and the second sub-parameter related to the cell from the data read by the any one second reading process; perform format conversion on the first sub-parameter according to a first output format of the PCIE interface in the processing chip to obtain the first sub-parameter in the first output format; wherein the first output format is determined according to a data format of an actual scheduling parameter sent by the PCIE interface to the bit-level processing module, and the actual scheduling parameter is sent by layer 2 in the BBU to the processing chip; perform format conversion on the second sub-parameter according to a second output format of the PCIE interface in the processing chip to obtain the second sub-parameter in the second output format; wherein the second output format is determined according to a data format of an actual cell parameter sent by the PCIE interface to the bit-level processing module, and the actual cell parameter is sent by layer 2 to the processing chip; cache the first sub-parameter in the first output format to the first storage area, and cache the second sub-parameter in the second output format to the second storage area.

[0287] As a possible implementation manner, the downlink fault detection apparatus 1400 can further include:

[0288] The disconnecting unit is configured to disconnect the communication link between the PCIE interface and the bit-level processing module when it is monitored that the downlink of the target cell fails.

[0289] The establishing unit is configured to establish a communication link between the storage unit and the bit-level processing module.

[0290] As a possible implementation manner, the processing chip is an FPGA, and the storage module is a DDR SDRAM.

[0291] It should be noted that the above downlink fault detection apparatus provided by the embodiments of the present application can realize all the method steps achieved by the method embodiments and achieve the same technical effects, and thus the same parts and beneficial effects of the embodiments as the method embodiments will not be repeated in detail. Figures 2 to 5

[0292] It should be noted that each functional unit in each embodiment of the present application can be integrated in one processing unit, or each unit can exist physically, or two or more units can be integrated in one unit. The integrated unit can be realized in the form of hardware or in the form of a software functional unit.

[0293] ​If the integrated unit is implemented in the form of a software function unit and sold or used as an independent product, it can be stored in a processor-readable storage medium. Based on such an understanding, the technical solutions of the present application essentially or in other words the part that contributes to the prior art or the whole or part of the technical solutions can be embodied in the form of a software product. The computer software product is stored in a storage medium and includes a plurality of instructions for causing a computer device (which can be a personal computer, a server, or a network device, etc.) or a processor to perform all or part of the steps of the embodiments of the present application. The aforementioned storage medium includes: a U disk, a mobile hard disk, a read-only memory (ROM), a random access memory (RAM), a magnetic disk or an optical disk, and various media that can store program codes.

[0294] To achieve the above-embodiments, the present application further provides a processor-readable storage medium.

[0295] The processor-readable storage medium stores a computer program for causing the processor to execute the embodiments of the present application. Figures 2 to 5 The downlink fault detection method of any embodiment.

[0296] The processor-readable storage medium can be any available medium or data storage device that the processor can access, including but not limited to a magnetic memory (such as a floppy disk, a hard disk, a magnetic tape, a magneto-optical disk (MO), etc.), an optical memory (such as a CD, a DVD, a BD, a HVD, etc.), and a semiconductor memory (such as a ROM, an EPROM, an EEPROM, a non-volatile memory (NAND FLASH), a solid-state hard disk (SSD)), etc.

[0297] To achieve the above-embodiments, the present application further provides a computer program product.

[0298] The computer program product includes a computer program that, when executed by a processor, implements the embodiments of the present application. Figures 2 to 5 The downlink fault detection method of any embodiment.

[0299] Those skilled in the art should understand that the embodiments of the present application can be provided as a method, a system, or a computer program product. Therefore, the present application can take the form of a complete hardware embodiment, a complete software embodiment, or an embodiment combining software and hardware aspects. Moreover, the present application can take the form of a computer program product implemented on one or more computer-usable storage media (including but not limited to magnetic disk storage and optical storage, etc.) containing computer-usable program codes.

[0300] The computer executable instructions can also be loaded onto a computer or other programmable data processing apparatus to cause a series of operations steps to be performed on the computer or other programmable apparatus to produce a computer implemented process such that the instructions which execute on the computer or other programmable apparatus provide steps for implementing the functions specified in the flowchart Figure 1 one or more flows and / or functions specified in the flowchart Figure 1 one or more flows and / or functions specified in the flowchart

[0301] These processor-executable instructions can also be stored in a processor-readable memory that can direct a computer or other programmable data processing apparatus to function in a particular manner, such that the instructions stored in the processor-readable memory produce an article of manufacture including instructions which implement the functions specified in the flowchart Figure 1 one or more flows and / or functions specified in the flowchart Figure 1 one or more flows and / or functions specified in the flowchart

[0302] These processor-executable instructions can also be loaded onto a computer or other programmable data processing apparatus to cause a series of operations steps to be performed on the computer or other programmable apparatus to produce a computer implemented process such that the instructions which execute on the computer or other programmable apparatus provide steps for implementing the functions specified in the flowchart Figure 1 one or more flows and / or functions specified in the flowchart Figure 1 one or more flows and / or functions specified in the flowchart

[0303] Obviously, numerous modifications and variations of the present application are possible in light of the above teachings. It is therefore to be understood that within the scope of the claims and their equivalents, the application can be practiced otherwise than as specifically described.

Claims

1. A downlink fault detection method, characterized in that: include: When a downlink failure of a target cell is detected, test parameters of the target cell in a current radio frame are read from a storage module in a processing chip of an indoor baseband processing unit (BBU); wherein the downlink includes a communication link between the BBU and an active antenna unit (AAU) corresponding to the target cell; Determining scheduling parameters and cell parameters according to the test parameters; Inputting the scheduling parameters and the cell parameters serially into the bit-level processing module, the symbol-level processing module, the compression module, and the carrier antenna CA switching module in the processing chip; The cause of the downlink fault is determined based on the output of at least one of the CA switching module, the bit-level processing module, and the symbol-level processing module. The output of the CA switching module is used to determine whether the processing chip has failed; the output of the bit-level processing module is used to determine whether the symbol-level processing module or the bit-level processing module has failed; and the output of the symbol-level processing module is used to determine whether the compression module and / or the CA switching module has failed.

2. The method according to claim 1, characterized in that The determining the cause of the downlink failure according to an output of at least one of the CA switching module, the bit-level processing module, and the symbol-level processing module includes: Obtaining a first actual output of the CA switching module, and determining whether the processing chip fails based on the first actual output; If the processing chip fails, obtaining a second actual output of a target processing module; wherein the target processing module includes the bit-level processing module and / or the symbol-level processing module; A fault cause of the processing chip in the downlink is determined according to the second actual output.

3. The method according to claim 2, characterized in that The determining, based on the first actual output, whether the processing chip fails includes: querying a first standard output corresponding to the CA switching module in the current radio frame; wherein the first standard output is obtained by performing a simulation test on the CA switching module according to the test parameters; If the first standard output does not match the first actual output, determining that the processing chip fails; When the first standard output matches the first actual output, it is determined that the processing chip has not failed.

4. The method according to claim 2, characterized in that The determining, according to the second actual output, a fault cause of the processing chip in the downlink includes: Obtaining a second actual output of the symbol-level processing module in the processing chip; querying a second standard output corresponding to the symbol-level processing module in the current radio frame; wherein the second standard output is obtained by performing a simulation test on the symbol-level processing module according to the test parameters; When the second actual output of the symbol-level processing module matches the second standard output, it is determined that the cause of the failure of the processing chip in the downlink is a failure of the compression module and / or the CA switching module.

5. The method according to claim 4, characterized in that The determining, according to the second actual output, a fault cause of the processing chip in the downlink further includes: If the second actual output of the symbol-level processing module does not match the second standard output, obtaining the second actual output of the bit-level processing module; querying a third standard output corresponding to the bit-level processing module in the current radio frame; wherein the third standard output is obtained by performing a simulation test on the bit-level processing module according to the test parameters; When the second actual output of the bit-level processing module matches the third standard output, it is determined that the cause of the failure of the processing chip in the downlink is a failure of the symbol-level processing module.

6. The method according to claim 5, characterized in that The determining, according to the second actual output, a fault cause of the processing chip in the downlink further includes: When the second actual output of the bit-level processing module does not match the third standard output, it is determined that the cause of the failure of the processing chip in the downlink is a failure of the bit-level processing module.

7. The method according to claim 2, characterized in that The determining the cause of the downlink failure according to the output of at least one of the CA switching module, the bit-level processing module, and the symbol-level processing module further includes: If the processing chip is not faulty, it is determined that the cause of the downlink fault is a fault in layer 2 of the BBU or a fault in the AAU.

8. The method according to any one of claims 1 to 7, characterized in that The storage module is configured to store a parameter file of at least one cell, wherein the parameter file includes test parameters of the corresponding cell in the current radio frame, where the current radio frame includes M subframes, where M is a positive integer; When a downlink failure of the target cell is detected, reading the test parameters of the target cell in the current radio frame from a storage module in a processing chip in an indoor baseband processing unit (BBU) corresponding to the target cell includes: When a downlink failure is detected in the target cell, performing a first reading process M times on the storage module; The data read in the i-th first reading process is used as the sub-test parameter of the i-th subframe; wherein i is a positive integer not greater than M; The test parameter is determined according to the sub-test parameters of the M subframes.

9. The method according to claim 8, characterized in that When a downlink failure in the target cell is detected, performing a first reading process M times on the storage module includes: Determining a candidate storage address from each storage address of the storage module; wherein the candidate storage address is used to store the parameter file of the target cell; For the i-th first reading process, determining a target storage address from each of the candidate storage addresses; wherein the target storage address is used to store the sub-test parameters of the i-th subframe; Performing N second read processes on the storage module according to a target data amount and a total amount of data stored at the target storage address; wherein the target data amount is used to indicate an amount of data read in a single time; and N is determined according to a ratio of the total data amount to the target data amount; The data read in the N second reading processes are used as the data read in the i-th first reading process.

10. The method according to claim 9, characterized in that The first second reading process includes: determining a base address for starting reading in the first second reading process according to a first storage address among the target storage addresses; reading the target data amount from the base address read in the first second reading process and using the data as the data read in the first second reading process; and determining a base address for starting reading in the second second reading process according to an end address at which reading ends in the first second reading process; The non-first second reading process includes: starting from the base address read by the second reading process this time, reading the target data volume and using it as the data read by the second reading process this time; and determining the base address for starting reading by the next second reading process based on the end address where the second reading process ends reading.

11. The method according to claim 9, characterized in that The determining, according to the test parameters, scheduling parameters and cell parameters includes: storing the data read in each second reading process in sequence into a cache module in the processing chip; Reading the scheduling parameter from the first storage area in the cache module; The cell parameters are read from the second storage area in the cache module.

12. The method according to claim 11, characterized in that The step of sequentially storing the data read in each of the second reading processes into the cache module in the processing chip includes: For any second reading process, extracting a first sub-parameter related to scheduling and a second sub-parameter related to the cell from data read in any second reading process; Performing format conversion on the first sub-parameter according to a first output format of the PCIE interface in the processing chip to obtain a first sub-parameter in the first output format; wherein the first output format is determined according to a data format of actual scheduling parameters sent by the PCIE interface to the bit-level processing module, and the actual scheduling parameters are sent by layer 2 in the BBU to the processing chip; performing format conversion on the second sub-parameter according to a second output format of the PCIE interface in the processing chip to obtain a second sub-parameter in the second output format; wherein the second output format is determined according to a data format of actual cell parameters sent by the PCIE interface to the bit-level processing module, and the actual cell parameters are sent by the layer 2 to the processing chip; The first sub-parameter of the first output format is cached in the first storage area, and the second sub-parameter of the second output format is cached in the second storage area.

13. The method according to claim 12, characterized in that When a downlink failure of the target cell is detected, the method further includes: Disconnecting the communication link between the PCIE interface and the bit-level processing module; A communication link is established between the storage module and the bit-level processing module.

14. The method according to any one of claims 1 to 7, characterized in that The processing chip is a field programmable gate array (FPGA), and the storage module is a double data rate synchronous dynamic random access memory (DDR SDRAM).

15. An access network device, characterized in that: Including memory, transceiver, processor; memory for storing computer programs; a transceiver, configured to transmit and receive data under the control of the processor; A processor is configured to read the computer program in the memory and perform the following operations: When a downlink failure of a target cell is detected, test parameters of the target cell in a current radio frame are read from a storage module in a processing chip of an indoor baseband processing unit (BBU); wherein the downlink includes a communication link between the BBU and an active antenna unit (AAU) corresponding to the target cell; Determining scheduling parameters and cell parameters according to the test parameters; Inputting the scheduling parameters and the cell parameters serially into the bit-level processing module, the symbol-level processing module, the compression module, and the carrier antenna CA switching module in the processing chip; The cause of the downlink fault is determined based on the output of at least one of the CA switching module, the bit-level processing module, and the symbol-level processing module. The output of the CA switching module is used to determine whether the processing chip has failed; the output of the bit-level processing module is used to determine whether the symbol-level processing module or the bit-level processing module has failed; and the output of the symbol-level processing module is used to determine whether the compression module and / or the CA switching module has failed.

16. The access network device according to claim 15, characterized in that: The processor determines the cause of the downlink failure according to an output of at least one of the CA switching module, the bit-level processing module, and the symbol-level processing module, specifically: Obtaining a first actual output of the CA switching module, and determining whether the processing chip fails based on the first actual output; If the processing chip fails, obtaining a second actual output of a target processing module; wherein the target processing module includes the bit-level processing module and / or the symbol-level processing module; A fault cause of the processing chip in the downlink is determined according to the second actual output.

17. The access network device according to claim 16, wherein: The processor determines, based on the first actual output, whether the processing chip fails, specifically: querying a first standard output corresponding to the CA switching module in the current radio frame; wherein the first standard output is obtained by performing a simulation test on the CA switching module according to the test parameters; If the first standard output does not match the first actual output, determining that the processing chip fails; When the first standard output matches the first actual output, it is determined that the processing chip has not failed.

18. The access network device according to claim 16, wherein: The processor determines, based on the second actual output, a fault cause of the processing chip in the downlink, specifically: Obtaining a second actual output of the symbol-level processing module in the processing chip; querying a second standard output corresponding to the symbol-level processing module in the current radio frame; wherein the second standard output is obtained by performing a simulation test on the symbol-level processing module according to the test parameters; When the second actual output of the symbol-level processing module matches the second standard output, it is determined that the cause of the failure of the processing chip in the downlink is a failure of the compression module and / or the CA switching module.

19. The access network device according to claim 18, wherein: The processor determines, based on the second actual output, a fault cause of the processing chip in the downlink, specifically: If the second actual output of the symbol-level processing module does not match the second standard output, obtaining the second actual output of the bit-level processing module; querying a third standard output corresponding to the bit-level processing module in the current radio frame; wherein the third standard output is obtained by performing a simulation test on the bit-level processing module according to the test parameters; When the second actual output of the bit-level processing module matches the third standard output, it is determined that the cause of the failure of the processing chip in the downlink is a failure of the symbol-level processing module.

20. The access network device according to claim 19, wherein: The processor determines, based on the second actual output, a fault cause of the processing chip in the downlink, specifically: When the second actual output of the bit-level processing module does not match the third standard output, it is determined that the cause of the failure of the processing chip in the downlink is a failure of the bit-level processing module.

21. The access network device according to claim 16, wherein: The processor determines the cause of the downlink failure according to an output of at least one of the CA switching module, the bit-level processing module, and the symbol-level processing module, specifically: If the processing chip is not faulty, it is determined that the cause of the downlink fault is a fault in layer 2 of the BBU or a fault in the AAU.

22. The access network device according to any one of claims 15 to 21, characterized in that: The storage module is configured to store a parameter file of at least one cell, wherein the parameter file includes test parameters of the corresponding cell in the current radio frame, where the current radio frame includes M subframes, where M is a positive integer; The processor executes, when monitoring a downlink failure of the target cell, reading the test parameters of the target cell in the current radio frame from a storage module in a processing chip in an indoor baseband processing unit BBU corresponding to the target cell, specifically: When a downlink failure is detected in the target cell, performing a first reading process M times on the storage module; The data read in the i-th first reading process is used as the sub-test parameter of the i-th subframe; wherein i is a positive integer not greater than M; The test parameter is determined according to the sub-test parameters of the M subframes.

23. The access network device according to claim 22, wherein: When the processor detects that a downlink failure occurs in the target cell, the processor executes a first reading process M times on the storage module, specifically: Determining a candidate storage address from each storage address of the storage module; wherein the candidate storage address is used to store the parameter file of the target cell; For the i-th first reading process, determining a target storage address from each of the candidate storage addresses; wherein the target storage address is used to store the sub-test parameters of the i-th subframe; Performing N second read processes on the storage module according to a target data amount and a total amount of data stored at the target storage address; wherein the target data amount is used to indicate an amount of data read in a single time; and N is determined according to a ratio of the total data amount to the target data amount; The data read in the N second reading processes are used as the data read in the i-th first reading process.

24. The access network device according to claim 23, wherein: The processor performs the second reading process for the first time, specifically: determining a base address for starting reading in the second reading process for the first time according to a first storage address in each of the target storage addresses; Starting from the base address read by the first second reading process, reading the target data amount of data and using it as the data read by the first second reading process; Determining a base address for starting reading of the second reading process for the second time according to an end address at which reading of the second reading process ends for the first time; The processor executes the non-first second reading process, specifically: starting from the base address read by the second reading process this time, reads the target data volume and uses it as the data read by the second reading process this time; based on the end address where the second reading process ends reading this time, determines the base address for starting reading by the next second reading process.

25. The access network device according to claim 23, wherein: The processor determines scheduling parameters and cell parameters according to the test parameters, specifically: storing the data read in each second reading process in sequence into a cache module in the processing chip; Reading the scheduling parameter from the first storage area in the cache module; The cell parameters are read from the second storage area in the cache module.

26. The access network device according to claim 25, characterized in that: The processor executes the step of sequentially storing the data read in each second reading process into a cache module in the processing chip, specifically: For any second reading process, extracting a first sub-parameter related to scheduling and a second sub-parameter related to the cell from data read in any second reading process; Performing format conversion on the first sub-parameter according to a first output format of the PCIE interface in the processing chip to obtain a first sub-parameter in the first output format; wherein the first output format is determined according to a data format of actual scheduling parameters sent by the PCIE interface to the bit-level processing module, and the actual scheduling parameters are sent by layer 2 in the BBU to the processing chip; performing format conversion on the second sub-parameter according to a second output format of the PCIE interface in the processing chip to obtain a second sub-parameter in the second output format; wherein the second output format is determined according to a data format of actual cell parameters sent by the PCIE interface to the bit-level processing module, and the actual cell parameters are sent by the layer 2 to the processing chip; The first sub-parameter of the first output format is cached in the first storage area, and the second sub-parameter of the second output format is cached in the second storage area.

27. The access network device according to claim 26, wherein: The processor is further configured to perform the following operations: When a downlink failure of the target cell is detected, disconnecting the communication link between the PCIE interface and the bit-level processing module; A communication link is established between the storage module and the bit-level processing module.

28. The access network device according to any one of claims 15 to 21, characterized in that: The processing chip is a field programmable gate array (FPGA), and the storage module is a double data rate synchronous dynamic random access memory (DDR SDRAM).

29. A downlink fault detection device, characterized in that: include: A reading unit is configured to read the test parameters of the target cell in the current radio frame from a storage module in a processing chip of an indoor baseband processing unit (BBU) when a downlink failure of the target cell is detected; wherein the downlink includes a communication link between the BBU and an active antenna unit (AAU) corresponding to the target cell; A first determining unit, configured to determine scheduling parameters and cell parameters according to the test parameters; An input unit, configured to serially input the scheduling parameters and the cell parameters into a bit-level processing module, a symbol-level processing module, a compression module, and a carrier antenna CA switching module in the processing chip; A second determining unit is configured to determine a cause of the downlink fault based on an output of at least one of the CA switching module, the bit-level processing module, and the symbol-level processing module; wherein the output of the CA switching module is used to determine whether the processing chip has failed; the output of the bit-level processing module is used to determine whether the symbol-level processing module or the bit-level processing module has failed; and the output of the symbol-level processing module is used to determine whether the compression module and / or the CA switching module has failed.

30. A processor-readable storage medium, characterized in that: The processor-readable storage medium stores a computer program, and the computer program is configured to cause the processor to execute the method according to any one of claims 1 to 14.

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