Storage unit, storage structure, storage array and electronic equipment
By optimizing capacitor design and line sharing technology in memory cells, the problem of poor design area of memory cells in the prior art is solved, and more efficient device density and smaller design area are achieved.
Patent Information
- Application Number
- CN202311258126.4
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2023-09-27
- Publication Date
- 2025-03-28
AI Technical Summary
The memory cell design area of the device in the prior art is not optimal, making it difficult to achieve the need to make as many device cells as possible on a limited substrate.
A memory cell is designed, including bit lines, transistors and capacitors. The design area of the memory cell is reduced by optimizing the length-to-width ratio of the capacitor (1.05~1.55), and the design area of the memory structure and array is further reduced by sharing bit lines and word lines between the memory cells.
By optimizing the design of capacitors, the design area of the storage unit can be effectively reduced, thereby increasing the storage density, and further reducing the design area of the storage structure and array through shared lines, achieving a more efficient device density.
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Figure CN119730234A_ABST
Abstract
Description
Technical Field
[0001] The present application relates to the field of semiconductor technology, and in particular to a storage unit, a storage structure, a storage array and an electronic device. Background Art
[0002] With the development of integrated circuit technology, the critical dimensions of devices are shrinking, and the types and numbers of devices contained in a single chip are increasing accordingly, so that any slight difference in process production may affect device performance.
[0003] In order to reduce the cost of products as much as possible, people hope to make as many device units as possible on a limited substrate. Since the advent of Moore's Law, the industry has proposed various semiconductor structure designs and process optimizations to meet people's needs for current products. However, the design area of the memory unit of the device in the current technology is not optimal. Summary of the invention
[0004] Based on this, it is necessary to provide a storage unit, a storage structure, a storage array and an electronic device that can reduce the design area of the storage unit.
[0005] In a first aspect, the present application provides a storage unit, comprising:
[0006] A bit line extending along a first direction;
[0007] A transistor, comprising a first electrode, a second electrode and a gate, wherein the first electrode and the second electrode of the transistor are arranged at intervals along a second direction, the first electrode of the transistor is connected to the bit line, and the first direction intersects with the second direction;
[0008] A capacitor is connected to the second electrode of the transistor, and a ratio of a length of the capacitor along the second direction to a width of the capacitor along the first direction is 1.05-1.55.
[0009] The above-mentioned storage unit includes: a bit line, a transistor and a capacitor. The bit line extends along a first direction. The transistor includes a first electrode, a second electrode and a gate, wherein the first electrode and the second electrode of the transistor are arranged at intervals along a second direction, the first electrode of the transistor is connected to the bit line, and the first direction intersects with the second direction. The capacitor is connected to the second electrode of the transistor. According to the results of theoretical calculation and simulation, the ratio of the length of the capacitor along the second direction to the width along the first direction is designed to be 1.05~1.55, so that the design area of the storage unit can be fully utilized, thereby reducing the design area of the storage unit.
[0010] In one embodiment, the capacitor comprises:
[0011] A first electrode, the first electrode is in contact with the second electrode of the transistor;
[0012] a dielectric layer, covering a surface of the first electrode;
[0013] The second electrode covers the surface of the dielectric layer and is arranged around the dielectric layer.
[0014] In one embodiment, the first electrode comprises a plate-shaped electrode plate, and one end of the electrode plate is in contact with the second electrode of the transistor.
[0015] In one embodiment, the first electrode includes a first sub-electrode plate, a second sub-electrode plate and a connecting portion; the first sub-electrode plate and the second sub-electrode plate are arranged at intervals along a third direction; the connecting portion is integrally connected to the first sub-electrode plate and the second sub-electrode plate, and the surface of the connecting portion away from the first sub-electrode plate and the second sub-electrode plate is in contact with the second pole of the transistor; the first direction, the second direction and the third direction intersect each other.
[0016] In one of the embodiments, the first electrode includes an annular sub-electrode plate and a connecting portion, wherein the connecting portion is integrally connected to the annular sub-electrode plate, and a surface of the connecting portion away from the annular sub-electrode plate is in contact with the second pole of the transistor.
[0017] In one embodiment, the annular sub-electrode plate includes an inner surface located inside the annular shape and an outer surface located outside the annular shape, and both the inner surface and the outer surface are covered with the dielectric layer and the second electrode.
[0018] In one of the embodiments, a ratio of a length of the capacitor along the second direction to a width of the capacitor along the first direction is 1.05-1.35.
[0019] In one embodiment, a width of the capacitor along the first direction is greater than a width of the transistor along the first direction.
[0020] In one embodiment, the memory cell further includes an isolation dielectric layer located at least between the capacitor and the bit line and surrounding the transistor.
[0021] In one embodiment, the transistor includes a gate and a gate insulating layer and an active layer that surround the outer surface of the gate from the inside to the outside; the first electrode and the second electrode of the transistor are both located in the active layer and are respectively located on both sides of the gate.
[0022] In the second aspect, the present application also provides a storage structure, including a first storage unit and a second storage unit, the first storage unit and the second storage unit are the storage units described in any one of the above embodiments, the first storage unit and the second storage unit share the same bit line, and the first storage unit and the second storage unit are respectively located on opposite sides of the bit line.
[0023] The above-mentioned storage structure includes a first storage unit and a second storage unit, wherein the first storage unit and the second storage unit are the storage units described in any one of the above-mentioned embodiments, the first storage unit and the second storage unit share the same bit line, and the first storage unit and the second storage unit are respectively located on two opposite sides of the bit line. Since the design area of the storage unit can be fully utilized, the design area of the storage structure can be reduced. At the same time, since the first storage unit and the second storage unit share the same bit line, the design area of the storage structure can be further reduced.
[0024] In a third aspect, the present application also provides a storage array, comprising a plurality of storage cells as described in any of the above embodiments and a plurality of word lines; wherein the plurality of storage cells are arranged in multiple layers, each layer comprises a plurality of storage cells, and the plurality of storage cells located in the same layer are arranged in multiple rows at least along the first direction, and the plurality of storage cells arranged along the first direction share the same bit line; the plurality of storage cells located in different layers of the same row share the same word line.
[0025] The above-mentioned memory array comprises a plurality of memory cells as described in any of the above-mentioned embodiments and a plurality of word lines; wherein the plurality of memory cells are arranged in multiple layers, each layer comprises a plurality of memory cells, the plurality of memory cells located in the same layer are arranged in multiple rows at least along the first direction, and the plurality of memory cells arranged along the first direction share the same bit line; the plurality of memory cells located in different layers of the same row share the same word line. Since the design area of the memory cells can be fully utilized, the design area of the memory array can be reduced.
[0026] In one embodiment, a plurality of memory cells located in the same layer are arranged in a plurality of rows and columns along the first direction and the second direction, and a plurality of memory cells located in the same layer and the same column share the same bit line.
[0027] In a fourth aspect, the present application also provides another storage array, characterized in that it includes multiple storage structures as described in the above embodiments and multiple word lines; wherein the multiple storage structures are arranged in multiple layers, each layer includes multiple storage structures, and the multiple storage structures located in the same layer are arranged in multiple rows at least along the first direction, and the multiple storage structures arranged along the first direction share the same bit line; among the multiple storage structures located in different layers of the same row, the first storage cells share the same word line, and the second storage cells share the same word line.
[0028] The above-mentioned storage array includes multiple storage structures and multiple word lines as in the above-mentioned embodiments; wherein the multiple storage structures are arranged in multiple layers, each layer includes multiple storage structures, and the multiple storage structures located in the same layer are arranged in multiple rows at least along the first direction, and the multiple storage structures arranged along the first direction share the same bit line; in the multiple storage structures located in different layers of the same row, each of the first storage cells shares the same word line, and each of the second storage cells shares the same word line. Since the design area of the storage cell can be fully utilized, the design area of the storage array can be reduced. At the same time, since the first storage cell and the second storage cell share the same bit line, the design area of the storage structure can be further reduced.
[0029] In one embodiment, a plurality of storage structures located in the same layer are arranged in multiple rows and columns along the first direction and the second direction, and the plurality of storage structures located in the same column in the same layer share the same bit line.
[0030] In a fifth aspect, the present application also provides an electronic device, which includes a storage unit as described in any of the previous embodiments.
[0031] The electronic device mentioned above includes the storage unit as described in any of the previous embodiments. Since the design area of the storage unit can be fully utilized, the design area of the storage array can be reduced. BRIEF DESCRIPTION OF THE DRAWINGS
[0032] In order to more clearly illustrate the technical solutions in the embodiments of the present application or the conventional technology, the drawings required for use in the embodiments or the conventional technology descriptions are briefly introduced below. Obviously, the drawings described below are only some embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without creative work.
[0033] Figure 1 A schematic diagram of a 3D structure of a storage unit provided in an embodiment of the present application;
[0034] Figure 2In one embodiment of this application Figure 1 A schematic diagram of a cross-sectional structure of a storage unit along AA';
[0035] Figure 3 In one embodiment of this application Figure 1 A schematic diagram of the cross-sectional structure of a storage unit along BB';
[0036] Figure 4 In one embodiment of this application Figure 1 A schematic diagram of a cross-sectional structure of a storage unit along CC';
[0037] Figure 5 A schematic diagram of a 3D structure of a storage unit provided in another embodiment of the present application;
[0038] Figure 6 A schematic diagram of a 3D structure of a storage unit provided in another embodiment of the present application;
[0039] Figure 7 In one embodiment of this application Figure 6 A schematic diagram of a cross-sectional structure of a storage unit along AA';
[0040] Figure 8 In one embodiment of this application Figure 6 A schematic diagram of the cross-sectional structure of a storage unit along BB';
[0041] Fig. 9 In one embodiment of this application Figure 6 A schematic diagram of a cross-sectional structure of a storage unit along CC';
[0042] Fig.10 In another embodiment of the present application Figure 1 A schematic diagram of the cross-sectional structure of a storage unit along BB';
[0043] Fig.11 In another embodiment of the present application Figure 1 A schematic diagram of a cross-sectional structure of a storage unit along CC';
[0044] Fig.12 A 3D structural schematic diagram of a storage structure provided in an embodiment of the present application;
[0045] Fig.13 A 3D structural schematic diagram of a storage structure provided in another embodiment of the present application;
[0046] Fig.14 A 3D structural schematic diagram of a storage structure provided in another embodiment of the present application;
[0047] Fig.15 A 3D structural diagram of a storage array provided in an embodiment of the present application;
[0048] Fig.16 A 3D structural schematic diagram of a storage array provided in another embodiment of the present application;
[0049] Fig.17 A 3D structural schematic diagram of a storage array provided in another embodiment of the present application;
[0050] Fig.18 This is a schematic diagram of the 3D structure of a storage array provided in yet another embodiment of the present application.
[0051] Description of the reference numerals: 10 - bit line, 20 - transistor, 201 - gate, 202 - gate insulating layer, 203 - active layer, 30 - capacitor, 301 - first electrode, 302 - dielectric layer, 303 - second electrode, 40 - isolation dielectric layer. DETAILED DESCRIPTION
[0052] In order to facilitate understanding of the present application, the present application will be described more fully below with reference to the relevant drawings. Embodiments of the present application are provided in the drawings. However, the present application can be implemented in many different forms and is not limited to the embodiments described herein. On the contrary, the purpose of providing these embodiments is to make the disclosure of the present application more thorough and comprehensive.
[0053] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as those commonly understood by those skilled in the art to which this application belongs. The terms used herein in the specification of this application are only for the purpose of describing specific embodiments and are not intended to limit this application.
[0054] It should be understood that when an element or layer is referred to as "on ...", "adjacent to ...", "connected to" or "coupled to" other elements or layers, it can be directly on, adjacent to, connected to or coupled to other elements or layers, or there can be intervening elements or layers. On the contrary, when an element is referred to as "directly on ...", "directly adjacent to ...", "directly connected to" or "directly coupled to" other elements or layers, there are no intervening elements or layers. It should be understood that although the terms first, second, third, etc. can be used to describe various elements, components, regions, layers, doping types and / or parts, these elements, components, regions, layers, doping types and / or parts should not be limited by these terms. These terms are only used to distinguish one element, component, region, layer, doping type or part from another element, component, region, layer, doping type or part. Therefore, without departing from the teachings of the present application, the first element, component, region, layer, doping type or portion discussed below may be represented as a second element, component, region, layer or portion; for example, the first doping type may be P-type and the second doping type may be N-type, or the first doping type may be N-type and the second doping type may be P-type.
[0055] Spatially relative terms such as "under," "beneath," "below," "under," "above," "above," and the like may be used herein to describe the relationship of an element or feature shown in the figures to other elements or features. It should be understood that, in addition to the orientations shown in the figures, spatially relative terms also include different orientations of the device in use and operation. For example, if the device in the accompanying drawings is flipped, an element or feature described as "under other elements" or "under it" or "under it" will be oriented as being "above" the other elements or features. Thus, the exemplary terms "under" and "under" may include both upper and lower orientations. In addition, the device may also include additional orientations (e.g., rotated 90 degrees or other orientations), and the spatial descriptors used herein are interpreted accordingly.
[0056] When used herein, the singular forms "a", "an", and "said / the" may also include plural forms, unless the context clearly indicates otherwise. It should also be understood that the terms "include / comprise" or "have" and the like specify the presence of stated features, wholes, steps, operations, components, parts, or combinations thereof, but do not exclude the possibility of the presence or addition of one or more other features, wholes, steps, operations, components, parts, or combinations thereof. At the same time, in this specification, the term "and / or" includes any and all combinations of the relevant listed items.
[0057] Embodiments of the invention are described herein with reference to cross-sectional views which are schematic diagrams of preferred embodiments (and intermediate structures) of the present application, so that variations in the shapes shown due to, for example, manufacturing techniques and / or tolerances can be expected. Therefore, embodiments of the present application should not be limited to the specific shapes of the zones shown herein, but rather include deviations in shapes due to, for example, manufacturing techniques. For example, an implanted region shown as a rectangle typically has rounded or curved features and / or an implant concentration gradient at its edges, rather than a binary change from an implanted region to a non-implanted region. Similarly, a buried region formed by implantation may result in some implantation in the region between the buried region and the surface through which the implantation is performed. Therefore, the regions shown in the figures are schematic in nature, their shapes do not represent the actual shape of the region of the device, and do not limit the scope of the present application.
[0058] In order to facilitate understanding of the specific structure of the storage unit, storage structure and storage array of the present application, three directions are defined in the drawings of the present application, namely, direction a, direction b and direction c, wherein direction a can be the first direction hereinafter, direction b can be the second direction hereinafter, and direction c can be the third direction hereinafter. It should be noted that the various directions in the drawings of the present application are only for the convenience of explaining the structure of the present solution, and do not constitute any limitation on the present solution. Moreover, in other suitable application scenarios, the first direction, the second direction and the third direction can also have other suitable definitions, for example, in other suitable application scenarios, direction a can be the second direction, direction b can be the third direction, and direction c can be the first direction, and it is only necessary to ensure that the solution of the present application is reasonable. In addition, the angle between the first direction, the second direction and the third direction can also be appropriately adjusted according to the application scenario, and this embodiment is not limited here.
[0059] See also Figure 1-Figure 4 The present application provides a storage unit, including a bit line 10, a transistor 20 and a capacitor 30. The bit line 10 extends along a first direction. The transistor 20 includes a first electrode, a second electrode and a gate 201, wherein the first electrode and the second electrode of the transistor 20 are arranged at intervals along a second direction, the first electrode of the transistor 20 is connected to the bit line 10, and the first direction intersects with the second direction. The capacitor 30 is connected to the second electrode of the transistor 20, and the ratio of the length of the capacitor 30 along the second direction to the width along the first direction is 1.05 to 1.55.
[0060] in, Figure 1 Schematic diagram of the 3D structure of the storage unit. Figure 2 for Figure 1 Schematic diagram of the cross-section structure along AA', Figure 3 for Figure 1 Schematic diagram of the cross-sectional structure along BB', Figure 4 for Figure 1 Schematic diagram of the cross-sectional structure along CC'.
[0061] The material of the bit line 10 may include a metal material, for example, at least one of tungsten (W), cobalt (Co), molybdenum (Mo), ruthenium (Ru), copper (Cu), aluminum (Al), titanium (Ti), and tantalum (Ta). The cross-sectional shape of the bit line 10 along the second direction and the third direction may be as follows: Figure 2 Of course, in other suitable application scenarios, the cross-sectional shape of the bit line 10 may also be a square, a circle or other suitable shapes, and the present embodiment does not limit the specific cross-sectional shape of the bit line 10.
[0062] It should be noted that the storage density of a memory is closely related to the design area of a single memory cell. The smaller the design area of a single memory cell, the more memory cells can be accommodated in the memory under the same area conditions, so the storage density of the memory is higher. The design area of a memory cell can be defined by the width of the memory cell along the a direction and the length of the memory cell along the b direction, that is, the area obtained by multiplying the width of a single memory cell along the a direction by the length of a single memory cell along the b direction can be regarded as the design area of the memory cell. In other words, when designing a memory cell, the width of the memory cell in the a direction and the length in the b direction should be reasonably designed to minimize the design area of the memory cell.
[0063] Furthermore, in a memory cell, the main components are the transistor 20 and the capacitor 30, and the ratio of the length of the capacitor 30 along the second direction to the width of the capacitor 30 along the first direction will affect the cross-sectional shape of the capacitor 30 along the first direction (or along the second direction), and the cross-sectional shape of the capacitor 30 will further affect the shape of a single memory cell. Since the memory usually includes multiple memory cells, it is also necessary to ensure that the shape of each memory cell is relatively regular, so that the memory can accommodate as many memory cells as possible. In the related art, the ratio of the length of the capacitor 30 along the second direction to the width of the capacitor 30 along the first direction is usually greater than 5, so that the length of the capacitor 30 along the second direction is much greater than the width of the capacitor 30 along the first direction. Although such a capacitor 30 can also work normally, the cross-sectional shape of the entire capacitor 30 along the first direction and the second direction will be designed to be quite narrow and long. When the memory cell composed of such a narrow and long capacitor 30 is arranged to form a memory, a considerable part of the design area will be wasted. When calculating, the wasted design area will be evenly distributed among the design areas of each memory cell, resulting in a single memory cell The design area is too large. In this embodiment, through theoretical calculation and simulation results, the ratio of the length of the capacitor 30 along the second direction to the width of the capacitor 30 along the first direction is designed to be between 1.05 and 1.55, which can make the design area of the capacitor 30 better. In other words, the storage unit designed within this ratio range can not only ensure the normal operation of the capacitor 30, but also make the design area of the capacitor 30 smaller, and at the same time avoid wasting more design area. Compared with the related art, the design area of the storage unit in this embodiment is smaller.
[0064] Furthermore, through theoretical calculation and simulation results, it is found that the ratio of the length of the capacitor 30 along the second direction to the width along the first direction can be any value between 1.05 and 1.55, for example, it can be 1.05, 1.1, 1.2, 1.3, 1.4, 1.5 or 1.55.
[0065] The above-mentioned memory cell includes: a bit line 10, a transistor 20 and a capacitor 30. The bit line 10 extends along a first direction. The transistor 20 includes a first electrode, a second electrode and a gate 201, wherein the first electrode and the second electrode of the transistor 20 are arranged at intervals along a second direction, the first electrode of the transistor 20 is connected to the bit line 10, and the first direction intersects with the second direction. The capacitor 30 is connected to the second electrode of the transistor 20. According to the results of theoretical calculation and simulation, the ratio of the length of the capacitor 30 along the second direction to the width along the first direction is designed to be 1.05-1.55, so that the design area of the memory cell can be fully utilized, thereby reducing the design area of the memory cell.
[0066] In addition, it can be seen from the definition of the above storage unit that the thickness of the capacitor 30 along the third direction does not affect the design area of the storage unit, so there is no strict limit relationship between the thickness of the capacitor 30 along the third direction and the length of the capacitor 30 along the second direction and the width of the capacitor 30 along the first direction. However, in actual process production, the thickness of the capacitor 30 along the third direction should not be too thin or too thick, but should be selected according to the actual application environment.
[0067] In some embodiments, the ratio of the length of the capacitor 30 along the second direction to the width along the first direction is 1.05-1.35, so that the design area of the memory cell can be more optimally utilized, thereby further reducing the design area of the memory cell.
[0068] The results of theoretical calculation and simulation also show that in the actual production process, the above ratio can also allow a certain range of errors, and the allowable error ratio can be adaptively adjusted according to the actual production process. Optionally, the allowable error ratio can be any suitable ratio within 20%, for example, 1%, 5%, 10%, 15% or 20%. For example, in a certain production process, assuming that the target ratio of the length of the capacitor 30 along the second direction to the width along the first direction is 1.2, and the allowable error ratio is 15%, then in this production process, the ratio of the length of the capacitor 30 along the second direction to the width along the first direction is within the range of 1.05-1.35 to meet the process requirements of this production process.
[0069] In some embodiments, the ratio of the length of the capacitor 30 along the second direction to the width along the first direction is 1.2, so that the design area of the memory cell can be fully utilized, thereby reducing the design area of the memory cell.
[0070] In some embodiments, Figure 1-Figure 4As shown, the transistor 20 includes a gate 201 and a gate insulating layer 202 and an active layer 203 that surround the outer surface of the gate 201 from the inside to the outside; the first electrode and the second electrode of the transistor 20 are both located in the active layer 203 and are respectively located on both sides of the gate 201.
[0071] The material of the gate 201 may include any suitable gate material known in the art, such as polysilicon, or other suitable metal gate materials, etc., which are not limited in this embodiment. Further, the conductivity type of polysilicon may be P-type or N-type, which are not limited in this embodiment.
[0072] The material of the gate insulating layer 202 may include a high-dielectric (High-K) material, such as silicon oxide, aluminum oxide, hafnium oxide, etc.
[0073] The material of the active layer 203 may include a metal oxide material. When the metal oxide material is IGZO, the leakage current of the transistor is small (the leakage current is less than or equal to 10-15A), thereby ensuring a low refresh rate of the dynamic memory. It should be noted that the material of the metal oxide can also be ITO, IWO, ZnOx, InOx, In2O3, InWO, SnO2, TiOx, InSnOx, ZnxOyNz, MgxZnyOz, InxZnyOz, InxGayZnzOa, ZrxInyZnzOa, HfxInyZnzOa, SnxInyZnzOa, AlxSnyInzZnaOd, SixInyZnzOa, ZnxSnyOz, AlxZnySnzOa, GaxZnySnzOa, ZrxZnySnzOa, InGaSiO, IAZO, IGO, IZO (indium-zinc-oxide), IZOx and other materials, as long as the leakage current of the transistor can meet the requirements, and the specific adjustment can be made according to the actual situation.
[0074] The active layer 203 surrounds the outer surface of the gate 201, and the cross-sectional shape of the gate 201 along the first direction and the second direction can be as follows: Figure 3 Of course, in other suitable application scenarios, the cross-sectional shape of the gate 201 may also be a suitable shape such as a rectangle or a circle, and this embodiment does not limit the specific cross-sectional shape of the channel.
[0075] In some embodiments, the gate 201 extends along a third direction, and the first direction, the second direction and the third direction intersect each other.
[0076] Since the main components of a memory cell are the transistor 20 and the capacitor 30, the main factors affecting the design area of the memory cell are the design area of the transistor 20 and the design area of the capacitor 30 (the definitions of the design area of the transistor 20 and the design area of the capacitor 30 are similar to the definitions of the design area of the memory cell described above, and will not be repeated here). In the above embodiment, the design area of the capacitor 30 can be made smaller by reasonably controlling the ratio of the length of the capacitor 30 along the second direction to the width along the first direction. In the present embodiment, since the gate 201 of the transistor 20 mainly extends along the third direction, the length of the transistor 20 along the first direction and the length along the second direction can be designed to be very small, thereby further reducing the design area of the memory cell.
[0077] Optionally, the first direction, the second direction and the third direction are perpendicular to each other.
[0078] Optionally, the transistor 20 may include a Channel-All-Around (CAA) transistor 20 .
[0079] In some embodiments, Figure 2-Figure 4 As shown, the capacitor 30 includes a first electrode 301, a dielectric layer 302 and a second electrode 303. The first electrode 301 is in contact with the second electrode of the transistor 20. The dielectric layer 302 covers the surface of the first electrode. The second electrode 303 covers the surface of the dielectric layer 302 and is arranged around the dielectric layer 302.
[0080] The dielectric layer 302 is disposed between the first electrode 301 and the second electrode 303 . In addition, since the dielectric layer 302 covers the surface of the first electrode and the second electrode 303 covers the surface of the dielectric layer 302 , the shape of the second electrode 303 is defined by the shape of the first electrode 301 .
[0081] Furthermore, since the dielectric layer 302 and the second electrode 303 are generally thinner than the first electrode 301, specifically, the thickness of the dielectric layer 302 along the third direction and the thickness of the second electrode 303 along the third direction are generally smaller than the thickness of the first electrode 301 along the third direction, the shape of the capacitor 30 is generally also determined by the shape of the first electrode 301, that is, the shape of the capacitor 30 is generally also defined by the shape of the first electrode 301.
[0082] In some embodiments, Figure 1-Figure 5 As shown, the memory cell further includes an isolation dielectric layer 40 , which is located at least between the capacitor 30 and the bit line 10 and surrounds the transistor 20 .
[0083] Among them, the isolation dielectric layer 40 can play the role of insulation and support, and the material of the isolation dielectric layer 40 may include a low-K dielectric material. For example, silicon oxide, silicon oxynitride, silicon nitride, silicon carbide, etc. The isolation dielectric layer 40 can also cover the exposed surface of the second electrode 303 of the capacitor 30. In addition, the isolation dielectric layer 40 may include multiple layers of sub-isolation dielectric layers 40, and each layer of the sub-isolation dielectric layer 40 may be formed in a different process step. For example, the sub-isolation dielectric layer 40 covering the exposed surface of the second electrode 303 of the capacitor 30 and the sub-isolation dielectric layer 40 located between the capacitor 30 and the bit line 10 may be formed in different process steps.
[0084] It should be noted that, in general, the exposed surface of the second electrode 303 of the capacitor 30 should also be covered by the isolation dielectric layer 40, and the morphology of the formed storage unit is as follows: Figure 5 However, in order to better illustrate the 3D morphology of the capacitor 30 of the storage unit, some of the drawings in the present application do not illustrate the partial isolation dielectric layer 40 covering the exposed surface of the second electrode 303 of the capacitor 30. However, it should be noted that in actual application scenarios, the exposed surface of the second electrode 303 of the capacitor 30 should also be covered by the isolation dielectric layer 40.
[0085] In one embodiment, Figure 1-Figure 4 As shown, the first electrode 301 includes a plate-shaped electrode plate, one end of which is in contact with the second electrode of the transistor 20. The three-dimensional shape of the plate-shaped electrode plate may be a rectangular parallelepiped.
[0086] Can be compared Figure 1 as well as Figure 5 , they can actually be 3D topography images of the memory cell when the first electrode 301 is a plate-shaped electrode plate, except that Figure 1 In order to show the morphology of the plate-shaped electrode plate, only a portion of the isolation dielectric layer 40 is shown. Figure 5 FIG. 4 shows a structure obtained after the isolation dielectric layer 40 completely covers or fills the exposed surface of the memory cell and the gap in the memory cell.
[0087] In one embodiment, Figure 6-Figure 9 As shown, the first electrode 301 includes a first sub-electrode plate, a second sub-electrode plate and a connecting portion; the first sub-electrode plate and the second sub-electrode plate are arranged at intervals along the third direction; the connecting portion is integrally connected to the first sub-electrode plate and the second sub-electrode plate, and the connecting portion is away from the surfaces of the first sub-electrode plate and the second sub-electrode plate and contacts the second pole of the transistor 20.
[0088] in, Figure 6 Schematic diagram of the 3D structure of the storage unit. Figure 7 for Figure 6Schematic diagram of the cross-section structure along AA', Figure 8 for Figure 6 The cross-sectional structure along BB' is shown in Figure 1. Fig. 9 for Figure 6 Schematic diagram of the cross-sectional structure along CC'.
[0089] like Figure 7-Figure 9 As shown, the dielectric layer 302 can still cover the exposed surface of the first sub-electrode plate, the second sub-electrode plate and the connecting portion. The second electrode 303 can still cover the surface of the dielectric layer 302 and be arranged around the dielectric layer 302. The gap between the first sub-electrode plate and the second sub-electrode plate can also be filled with the isolation dielectric layer 40. In this way, the relative area between the first electrode 301 and the second electrode 303 in the capacitor 30 is also increased. Under the condition of the same occupied space volume, the relative area between the first electrode 301 and the second electrode 303 in this embodiment is larger. Therefore, under the condition of the same design requirements for the relative area between the first electrode 301 and the second electrode 303, the design area of the capacitor 30 in this embodiment can be smaller, thereby further reducing the design area of the storage unit.
[0090] In one embodiment, Figure 1 , Figure 7 , Fig.10 as well as Fig.11 As shown, the first electrode 301 includes an annular sub-electrode plate and a connecting portion, the connecting portion is integrally connected to the annular sub-electrode plate, and the connecting portion is away from the surface of the annular sub-electrode plate and contacts the second pole of the transistor 20 .
[0091] in, Figure 1 It can also be regarded as a schematic diagram of the 3D structure of the storage unit when the first electrode 301 is a ring-shaped sub-electrode plate. Figure 7 for Figure 1 Schematic diagram of the cross-section structure along AA', Fig.10 for Figure 1 Schematic diagram of the cross-sectional structure along BB', Fig.11 for Figure 1 Schematic diagram of the cross-sectional structure along CC'.
[0092] The cross-sectional shape of the annular sub-electrode plate along the third direction may be a rectangular ring, or may be a suitable shape such as a circular ring or a square ring. Figure 1 , Figure 7 , Fig.10 as well as Fig.11 In the example, the cross-sectional shape of the annular sub-electrode plate along the third direction is a rectangular ring. However, in other application scenarios, the annular sub-electrode plate may also be other suitable shapes, which is not limited in this embodiment.
[0093] like Figure 7 , Fig.10 as well as Fig.11 As shown, the dielectric layer 302 can still cover the exposed surface of the annular sub-electrode plate. The second electrode 303 can still cover the surface of the dielectric layer 302 and be arranged around the dielectric layer 302. The gap portion in the annular sub-electrode plate can also be filled with the isolation dielectric layer 40. In this way, the relative area between the first electrode 301 and the second electrode 303 in the capacitor 30 is also increased. Under the condition of the same occupied space volume, the relative area between the first electrode 301 and the second electrode 303 in this embodiment is larger. Therefore, under the condition of the same design requirements for the relative area between the first electrode 301 and the second electrode 303, the design area of the capacitor 30 in this embodiment can be smaller, thereby further reducing the design area of the storage unit.
[0094] In some embodiments, the annular sub-electrode plate includes an inner surface located inside the annular shape and an outer surface located outside the annular shape, and both the inner surface and the outer surface are covered with a dielectric layer 302 and a second electrode 303 .
[0095] In addition, in the present application, the storage unit composed of the plate-shaped electrode plate of the above-mentioned first electrode 301 can be called a single-plate storage unit; the storage unit composed of the first sub-electrode plate, the second sub-electrode plate and the connecting portion of the above-mentioned first electrode 301 can be called a double-plate storage unit; the storage unit composed of the annular sub-electrode plate and the connecting portion of the above-mentioned first electrode 301 can be called a cup-type storage unit. Of course, the above-mentioned name definitions are only for the convenience of concise description of the above-mentioned three schemes, and do not constitute any limitation on the above-mentioned three schemes. In addition, the types of storage units of the present application can also include other suitable types. Here are only a few examples. Other suitable types of storage units obtained according to the spirit of the scheme of the present application will also fall within the scope of protection of the present application.
[0096] In some embodiments, the width of capacitor 30 along the first direction is greater than the width of transistor 20 along the first direction.
[0097] The present application also provides a storage structure, such as Figure 12-14 As shown, the storage structure includes a first storage unit and a second storage unit, the first storage unit and the second storage unit are both storage units in any of the above embodiments, the first storage unit and the second storage unit share the same bit line 10, and the first storage unit and the second storage unit are respectively located on two opposite sides of the bit line 10.
[0098] Optionally, the first storage unit and the second storage unit may be of the same type, for example, both may be single-board storage units.
[0099] Optionally, the first storage unit and the second storage unit may be of different types. For example, the first storage unit may be a single-board storage unit, and the second storage unit may be a dual-board storage unit.
[0100] For example, when the first storage unit and the second storage unit are both single-board storage units, the 3D topography diagram of the storage structure is as follows: Fig.12 When the first storage unit and the second storage unit are both double-plate storage units, the 3D morphology diagram of the storage structure is as shown in Fig.13 When the first storage unit and the second storage unit are both cup-shaped storage units, the 3D morphology diagram of the storage structure is as shown in Fig.14 shown.
[0101] Among them, the first storage unit and the second storage unit share the same bit line 10, that is, the first storage unit and the second storage unit can be connected through the same bit line without designing two bit lines, thereby further reducing the design area of the storage unit and further reducing the design area of the storage structure.
[0102] The above storage structure includes a first storage unit and a second storage unit, the first storage unit and the second storage unit are the storage units in any of the above embodiments, the first storage unit and the second storage unit share the same bit line 10, and the first storage unit and the second storage unit are respectively located on two opposite sides of the bit line 10. Since the design area of the storage unit can be fully utilized, the design area of the storage structure can be reduced. At the same time, since the first storage unit and the second storage unit share the same bit line, the design area of the storage structure can be further reduced.
[0103] The present application also provides a storage array, which includes multiple storage cells as in any of the above embodiments and multiple word lines; wherein the multiple storage cells are arranged in multiple layers, each layer includes multiple storage cells, and the multiple storage cells located in the same layer are arranged in multiple rows at least along a first direction, and the multiple storage cells arranged along the first direction share the same bit line 10; multiple storage cells in different layers of the same row share the same word line.
[0104] like Fig.15 As shown, the present embodiment is described by taking a single-board storage unit as an example. The storage unit may be other types of storage units. Fig.15 It is derived by reasonable deduction. Fig.15 In the embodiment, direction a may be a first direction, direction b may be a second direction, and direction c may be a third direction.
[0105] The above-mentioned memory array includes a plurality of memory cells as in any of the above-mentioned embodiments and a plurality of word lines; wherein the plurality of memory cells are arranged in multiple layers, each layer includes a plurality of memory cells, the plurality of memory cells located in the same layer are arranged in multiple rows at least along a first direction, and the plurality of memory cells arranged along the first direction share the same bit line 10; the plurality of memory cells located in different layers of the same row share the same word line. Since the design area of the memory cells can be fully utilized, the design area of the memory array can be reduced.
[0106] In some embodiments, a plurality of memory cells in the same layer are arranged in a plurality of rows and columns along the first direction and the second direction, and a plurality of memory cells in the same layer and in the same column share a same bit line 10 .
[0107] like Fig.16 As shown, the present embodiment is described by taking a single-board storage unit as an example. The storage unit may be other types of storage units. Fig.16 It is derived by reasonable deduction.
[0108] The present application also provides another storage array, including multiple storage structures as in the above embodiments and multiple word lines; wherein the multiple storage structures are arranged in multiple layers, each layer includes multiple storage structures, and the multiple storage structures located in the same layer are arranged in multiple rows at least along a first direction, and the multiple storage structures arranged along the first direction share the same bit line 10; in the multiple storage structures located in different layers of the same row, the first storage units share the same word line, and the second storage units share the same word line.
[0109] like Fig.17 As shown, the present embodiment is described by taking the first storage unit and the second storage unit as single-board storage units as an example. The first storage unit and the second storage unit may be other types of storage units. Fig.17 The row extension direction may be the second direction, the column extension direction may be the first direction, and the layer stacking direction may be the third direction.
[0110] The above-mentioned storage array includes multiple storage structures and multiple word lines as in the above-mentioned embodiments; wherein the multiple storage structures are arranged in multiple layers, each layer includes multiple storage structures, and the multiple storage structures located in the same layer are arranged in multiple rows at least along the first direction, and the multiple storage structures arranged along the first direction share the same bit line 10; in the multiple storage structures located in different layers of the same row, each first storage unit shares the same word line, and each second storage unit shares the same word line. Since the design area of the storage unit can be fully utilized, the design area of the storage array can be reduced. At the same time, since the first storage unit and the second storage unit share the same bit line 10, the design area of the storage structure can be further reduced.
[0111] In some embodiments, a plurality of storage structures located in the same layer are arranged in a plurality of rows and columns along the first direction and the second direction, and a plurality of storage structures located in the same layer and in the same column share a same bit line 10 .
[0112] like Fig.18 As shown, the present embodiment is described by taking a single-board storage unit as an example. The storage unit may be other types of storage units. Fig.18 It is derived by reasonable deduction.
[0113] In addition, in order to better display the 3D morphology of each capacitor 30, Figure 15-18 The insulating dielectric layer 40 covering the exposed surface of the second electrode 303 of each capacitor 30 is not shown in the figure. However, it should be noted that in actual application scenarios, the outer surface of each capacitor 30 should also be completely covered by the insulating dielectric layer 40 (the specific structure formed in the actual application scenario can be similar to Figure 5 structure in ).
[0114] The present application also provides an electronic device, which includes a storage unit as in any of the previous embodiments.
[0115] The above-mentioned electronic device includes a storage unit as in any of the previous embodiments. Since the design area of the storage unit can be fully utilized, the design area of the storage array can be reduced; the electronic device may include computers, mobile phones, tablets, monitors, televisions, smart wearable devices, etc.
[0116] The technical features of the above embodiments may be combined arbitrarily. To make the description concise, not all possible combinations of the technical features of the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.
[0117] The above embodiments only express several implementation methods of the present application, and the descriptions thereof are relatively specific and detailed, but they cannot be understood as limiting the scope of the patent application. It should be pointed out that, for a person of ordinary skill in the art, several variations and improvements can be made without departing from the concept of the present application, and these all belong to the protection scope of the present application. Therefore, the protection scope of the patent application shall be subject to the attached claims.
Claims
1. A storage unit, characterized in that: include: A bit line extending along a first direction; A transistor, comprising a first electrode, a second electrode and a gate, wherein the first electrode and the second electrode of the transistor are arranged at intervals along a second direction, the first electrode of the transistor is connected to the bit line, and the first direction intersects with the second direction; A capacitor is connected to the second electrode of the transistor, and a ratio of a length of the capacitor along the second direction to a width of the capacitor along the first direction is 1.05-1.
55.
2. The storage unit according to claim 1, characterized in that The capacitor comprises: A first electrode, the first electrode is in contact with the second electrode of the transistor; a dielectric layer, covering a surface of the first electrode; The second electrode covers the surface of the dielectric layer and is arranged around the dielectric layer.
3. The storage unit according to claim 2, characterized in that The first electrode includes a plate-shaped electrode plate, one end of which is in contact with the second electrode of the transistor.
4. The storage unit according to claim 2, characterized in that The first electrode includes a first sub-electrode plate, a second sub-electrode plate and a connecting portion; the first sub-electrode plate and the second sub-electrode plate are arranged at intervals along a third direction; the connecting portion is integrally connected to the first sub-electrode plate and the second sub-electrode plate, and the surface of the connecting portion away from the first sub-electrode plate and the second sub-electrode plate is in contact with the second pole of the transistor; the first direction, the second direction and the third direction intersect each other.
5. The storage unit according to claim 2, characterized in that: The first electrode includes an annular sub-electrode plate and a connecting portion, wherein the connecting portion is integrally connected to the annular sub-electrode plate, and a surface of the connecting portion away from the annular sub-electrode plate is in contact with the second electrode of the transistor.
6. The storage unit according to claim 5, characterized in that The annular sub-electrode plate includes an inner surface located inside the annular shape and an outer surface located outside the annular shape, and both the inner surface and the outer surface are covered with the dielectric layer and the second electrode.
7. The storage unit according to claim 1, characterized in that A ratio of a length of the capacitor along the second direction to a width of the capacitor along the first direction is 1.05-1.
35.
8. The storage unit according to claim 1, characterized in that A width of the capacitor along the first direction is greater than a width of the transistor along the first direction.
9. The storage unit according to claim 1, characterized in that: The memory cell further includes an isolation dielectric layer located at least between the capacitor and the bit line and surrounding the transistor.
10. The storage unit according to claim 1, characterized in that The transistor comprises a gate, a gate insulating layer and an active layer which surround the outer surface of the gate in sequence from the inside to the outside; the first electrode and the second electrode of the transistor are both located in the active layer and are respectively located on both sides of the gate.
11. A storage structure, characterized in that: It includes a first storage unit and a second storage unit, the first storage unit and the second storage unit are the storage units described in any one of claims 1 to 10, the first storage unit and the second storage unit share the same bit line, and the first storage unit and the second storage unit are respectively located on two opposite sides of the bit line.
12. A storage array, characterized in that: It comprises a plurality of memory cells as described in any one of claims 1 to 10 and a plurality of word lines; wherein the plurality of memory cells are arranged in multiple layers, each layer comprises a plurality of memory cells, the plurality of memory cells located in the same layer are arranged in multiple rows at least along the first direction, and the plurality of memory cells arranged along the first direction share the same bit line; the plurality of memory cells located in different layers of the same row share the same word line.
13. The storage array according to claim 12, characterized in that: The plurality of memory cells located in the same layer are arranged in a plurality of rows and columns along the first direction and the second direction, and the plurality of memory cells located in the same column in the same layer share the same bit line.
14. A storage array, characterized in that: It comprises a plurality of storage structures as claimed in claim 11 and a plurality of word lines; wherein the plurality of storage structures are arranged in multiple layers, each layer comprises a plurality of storage structures, the plurality of storage structures located in the same layer are arranged in multiple rows at least along the first direction, and the plurality of storage structures arranged along the first direction share the same bit line; in the plurality of storage structures located in different layers of the same row, the first storage cells share the same word line, and the second storage cells share the same word line.
15. The storage array according to claim 14, characterized in that: The plurality of storage structures located in the same layer are arranged in a plurality of rows and columns along the first direction and the second direction, and the plurality of storage structures located in the same column in the same layer share the same bit line.
16. An electronic device, characterized in that: The electronic device comprises the storage unit according to any one of claims 1-10.