Transistor and manufacturing method thereof
By introducing a superlattice structure composed of a P-type gallium nitride dielectric layer and an InAlxGaN insertion layer into the gate dielectric layer of the transistor, the problem of low voltage with the existing silicon-based gallium nitride high electron mobility transistor is solved, and higher voltage withstand performance and reliability are achieved.
Patent Information
- Application Number
- CN202411566637.7
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2024-11-05
- Publication Date
- 2025-03-28
AI Technical Summary
Existing silicon-based gallium nitride high-electron mobility transistors have the problem of low withstand voltage, which leads to problems with low breakdown risk and low reliability in practical applications.
By introducing a superlattice structure composed of a P-type gallium nitride dielectric layer and an InAlxGaN insertion layer into the gate dielectric layer of the transistor, the thickness and period number are adjusted to enhance the voltage resistance of the gate dielectric layer.
This technical solution enhances the voltage withstand performance of the gate dielectric layer, improves the reliability of the transistor when facing the spike voltage, and effectively solves the problem of low voltage withstand voltage.
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Figure CN119730293A_ABST
Abstract
Description
Technical Field
[0001] The present disclosure relates to the field of semiconductor devices, and in particular to a transistor and a method for manufacturing the same. Background Art
[0002] GaN-on-Si is widely used in semiconductors, such as transistors.
[0003] The related art provides a silicon-based gallium nitride transistor, which mainly includes a channel layer, a barrier layer, a gate dielectric layer and a gate, wherein the gate dielectric layer is a P-type gallium nitride layer.
[0004] The above-mentioned transistor is an enhanced gallium nitride high electron mobility transistor with a breakdown voltage of about 10V. It has the problem of low voltage resistance and a certain breakdown risk in actual application, and its reliability is low. Summary of the invention
[0005] The present disclosure provides a transistor and a method for manufacturing the same, which belongs to the field of semiconductors. The technical solution is as follows:
[0006] In one aspect, a transistor is provided, comprising:
[0007] A channel layer, a barrier layer, a gate dielectric layer and a gate layer stacked in sequence on the channel layer;
[0008] The gate dielectric layer includes a P-type gallium nitride dielectric layer and an InAl x The superlattice structure formed by the GaN insertion layer, x≥0, the thickness of the P-type gallium nitride dielectric layer is 20-30nm, the InAl x The thickness of the GaN insertion layer is 4 to 6 nm.
[0009] Optionally, the InAl x The GaN insertion layer is a non-doped InAlGaN layer, a non-doped InGaN layer, an N-type InAlGaN layer or an N-type InGaN layer.
[0010] Optionally, the thickness of the P-type gallium nitride dielectric layer is 25 nm, and the InAl x The thickness of the GaN insertion layer is 5 nm.
[0011] Optionally, the number of periods of the superlattice structure is 8-12.
[0012] Optionally, the transistor further includes a buffer layer, and the channel layer is located in the buffer layer;
[0013] The buffer layer includes a super lattice structure consisting of an AlN layer and an AlGaN layer.
[0014] In another aspect, a method for manufacturing a transistor is provided, the method comprising:
[0015] manufacturing a channel layer;
[0016] forming a barrier layer on the channel layer;
[0017] A gate dielectric layer is formed on the barrier layer, wherein the gate dielectric layer includes a P-type gallium nitride dielectric layer and an InAl x The superlattice structure formed by the GaN insertion layer, x≥0, the thickness of the P-type gallium nitride dielectric layer is 20-30nm, the InAl x The thickness of the GaN insertion layer is 4 to 6 nm;
[0018] A gate is fabricated on the gate dielectric layer.
[0019] Optionally, forming a gate dielectric layer on the barrier layer includes:
[0020] In an environment where the reaction chamber temperature is 890-910°C, the reaction chamber pressure is 190-210 mbar, the NH3 flow rate is 4900-5100 sccm, the TMIn flow rate is 790-810 sccm, and the TMGa flow rate is 190-210 sccm, multiple cycles of P-type gallium nitride dielectric layers and non-doped InGaN layers are grown in sequence;
[0021] Alternatively, in an environment where the reaction chamber temperature is 890-910° C., the reaction chamber pressure is 190-210 mbar, the NH3 flow rate is 4900-5100 sccm, the TMIn flow rate is 790-810 sccm, the TMGa flow rate is 190-210 sccm, and the TMAl flow rate is 49-51 sccm, multiple cycles of P-type gallium nitride dielectric layers and non-doped InAlGaN layers are grown in sequence.
[0022] Optionally, forming a gate dielectric layer on the barrier layer includes:
[0023] In an environment where the reaction chamber temperature is 890-910°C, the reaction chamber pressure is 190-210 mbar, the SiH4 flow rate is 69-71 sccm, the NH3 flow rate is 4900-5100 sccm, the TMIn flow rate is 790-810 sccm, and the TMGa flow rate is 190-210 sccm, multiple cycles of P-type gallium nitride dielectric layers and N-type InGaN layers are grown in sequence;
[0024] Alternatively, in an environment where the reaction chamber temperature is 890-910°C, the reaction chamber pressure is 190-210 mbar, the SiH4 flow rate is 69-71 sccm, the NH3 flow rate is 4900-5100 sccm, the TMIn flow rate is 790-810 sccm, the TMGa flow rate is 190-210 sccm, and the TMAl flow rate is 49-51 sccm, multiple cycles of P-type gallium nitride dielectric layers and N-type InAlGaN layers are grown in sequence.
[0025] Optionally, the Mg doping concentration in the P-type gallium nitride dielectric layer is 0.5E19 to 2E19 / cm 3 .
[0026] Optionally, the thickness of the P-type gallium nitride dielectric layer is 25 nm, and the InAl x The thickness of the GaN insertion layer is 5 nm.
[0027] The technical solution provided by the embodiments of the present disclosure has the following beneficial effects:
[0028] The transistor includes a channel layer, the function of which is to form a two-dimensional electron gas between the channel layer and the barrier layer. The gate dielectric layer is composed of a P-type gallium nitride dielectric layer and an InAl x The GaN insertion layer superlattice consists of a P-type GaN dielectric layer with a thickness of 20 to 30 nm, which can consume the electrons of the two-dimensional electron gas, and an InAl2O3 layer with a thickness of 4 to 6 nm between adjacent P-type GaN dielectric layers. x The GaN insertion layer enables the entire gate dielectric layer structure to increase the breakdown voltage of the gate and channel layer, thereby enhancing the gate's voltage resistance, which is beneficial for coping with spike voltages during use and improving reliability. BRIEF DESCRIPTION OF THE DRAWINGS
[0029] In order to more clearly illustrate the technical solutions in the embodiments of the present disclosure, the drawings required for use in the description of the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present disclosure. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying any creative work.
[0030] Figure 1 is a schematic structural diagram of a transistor provided by an embodiment of the present disclosure;
[0031] Figure 2 is a schematic diagram of the structure of another transistor provided by an embodiment of the present disclosure;
[0032] Figure 3 is a flow chart of a method for manufacturing a transistor provided by an embodiment of the present disclosure;
[0033] Figure 4 It is a flow chart of another method for manufacturing a transistor provided in an embodiment of the present disclosure.
[0034] Reference numerals
[0035] 101: channel layer; 102: barrier layer; 103: gate dielectric layer; 131: P-type gallium nitride dielectric layer; 132: InAl x GaN insertion layer; 104: gate; 105: buffer layer; 106: substrate; 107: nucleation layer; 108: stress buffer layer; 109: cap layer; 110: source; 111: drain; 112: passivation layer. DETAILED DESCRIPTION
[0036] In order to make the objectives, technical solutions and advantages of the present disclosure more clear, the embodiments of the present disclosure will be further described in detail below with reference to the accompanying drawings.
[0037] Figure 1 A schematic diagram of a transistor structure provided by an embodiment of the present disclosure. Figure 1 The transistor includes: a channel layer 101, a barrier layer 102, a gate dielectric layer 103 and a gate 104 sequentially stacked on the channel layer 101.
[0038] The gate dielectric layer 103 includes a P-type gallium nitride dielectric layer 131 and an InAl x The GaN insertion layer 132 forms a superlattice structure, x≥0, the thickness of the P-type gallium nitride dielectric layer 131 is 20-30 nm, and the InAl x The thickness of the GaN insertion layer 132 is 4-6 nm.
[0039] In the embodiment of the present disclosure, the transistor includes a channel layer, the function of the channel layer is to form a two-dimensional electron gas between the channel layer and the barrier layer, and the gate dielectric layer is composed of a P-type gallium nitride dielectric layer and an InAl x The GaN insertion layer superlattice consists of a P-type GaN dielectric layer with a thickness of 20 to 30 nm, which can consume the electrons of the two-dimensional electron gas, and an InAl2O3 layer with a thickness of 4 to 6 nm between adjacent P-type GaN dielectric layers. x The GaN insertion layer enables the entire gate dielectric layer structure to increase the breakdown voltage of the gate and channel layer, thereby enhancing the gate's voltage resistance, which is beneficial for coping with spike voltages during use and improving reliability.
[0040] In the embodiment of the present disclosure, the channel layer 101 is a GaN channel layer.
[0041] The channel layer 101 has a thickness of 250-350 nm, for example, 300 nm.
[0042] In the embodiment of the present disclosure, the barrier layer 102 may be a single layer or a composite layer.
[0043] For example, the barrier layer 102 is an AlGaN layer.
[0044] For another example, the barrier layer 102 is an AlN layer, an Al 0.25 Ga 0.75 A stack of N and GaN layers.
[0045] Among them, the thickness of the AlN layer is 0.5~1.5nm, and the Al 0.25 Ga 0.75 The thickness of the N layer is 20 to 30 nm, and the thickness of the GaN layer is 1 to 3 nm.
[0046] For example, the thickness of AlN layer is 1nm, and Al 0.25 Ga 0.75 The thickness of the N layer is 25nm and the thickness of the GaN layer is 2nm.
[0047] In the embodiment of the present disclosure, the P-type gallium nitride dielectric layer 131 may be a Mg-doped gallium nitride dielectric layer, or a Sn-doped gallium nitride dielectric layer, or a Fe-doped gallium nitride dielectric layer.
[0048] In the embodiment of the present disclosure, the Mg doping concentration in the P-type gallium nitride dielectric layer 131 is 0.5E19 to 2E19 / cm 3 .
[0049] For example, the Mg doping concentration in the P-type gallium nitride dielectric layer 131 is 1E19 / cm 3 .
[0050] In this implementation, the use of the above doping concentration can better increase the withstand voltage of the transistor.
[0051] In one implementation of the present disclosure, the InAl x The GaN insertion layer 132 is a non-doped InAlGaN layer or a non-doped InGaN layer.
[0052] In this implementation, the undoped InAlGaN layer or the undoped InGaN layer can increase the breakdown voltage of the gate and the gallium nitride structure, thereby enhancing the gate withstand voltage. The staggered stacking of the supercrystalline format multi-layer insertion layer can adjust the uniform distribution of the Mg doping ion concentration in the dielectric layer, better consume the electrons of the 2DEG (two-dimensional electron gas), so that the conductive channel is cut off under normal conditions, further enhancing the gate withstand voltage.
[0053] In another implementation of the embodiment of the present disclosure, the InAl x The GaN insertion layer 132 is an N-type InAlGaN layer or an N-type InGaN layer.
[0054] In this implementation, a PN junction is formed between the Mg-doped P-type GaN dielectric layer and the Si-doped InAlGaN or InGaN insertion layer, and multiple PN junctions are formed between multiple N-type InAlGaN or InGaN insertion layers and multiple P-type gallium nitride layers, and the PN junction can be equivalently regarded as a diode. At least one layer of N-type InAlGaN or InGaN insertion layer is located on the P-type GaN layer, that is, at least one PN junction equivalent to a diode is reversely connected in series between the gate and the gallium nitride channel layer structure, wherein the equivalent reverse series PN junction enhances the withstand voltage, which can increase the breakdown voltage between the gate and the gallium nitride channel layer structure, thereby further enhancing the gate withstand voltage performance.
[0055] In the embodiment of the present disclosure, the thickness of the P-type gallium nitride dielectric layer 131 is 25 nm. x The thickness of the GaN insertion layer 132 is 5 nm.
[0056] In this implementation, the P-type gallium nitride dielectric layer 131 and the InAl x The above-mentioned thickness of the GaN insertion layer can ensure the effect of increasing the withstand voltage without causing the transistor size to be too large.
[0057] In the disclosed embodiment, the number of periods of the superlattice structure in the gate dielectric layer 103 is 8-12.
[0058] Exemplarily, the number of periods of the superlattice structure in the gate dielectric layer 103 is ten.
[0059] In this implementation, the P-type gallium nitride dielectric layer uses a superlattice with the above-mentioned number of periods to ensure the effect of increasing the withstand voltage without causing the transistor size to be too large.
[0060] Figure 2 A schematic diagram of the structure of another transistor provided by an embodiment of the present disclosure. Figure 2 , the transistor and Figure 1 The difference compared with the transistor shown in FIG. 1 is that the transistor further includes a buffer layer 105 , and the channel layer 101 is located in the buffer layer 105 .
[0061] The buffer layer 105 includes a super lattice structure composed of an AlN layer and an AlGaN layer.
[0062] In this implementation, by providing a buffer layer of a superlattice structure composed of an AlN layer and an AlGaN layer, the growth quality of the channel layer of the transistor is improved.
[0063] In the disclosed embodiment, the thickness of the AlN layer is 4-6 nm, and the thickness of the AlGaN layer is 20-40 nm.
[0064] Exemplarily, the thickness of the AlN layer is 5 nm, and the thickness of the AlGaN layer is 30 nm.
[0065] In the embodiment of the present disclosure, the number of periods of the superlattice structure in the buffer layer 105 is 40-60.
[0066] Exemplarily, the number of periods of the superlattice structure in the buffer layer 105 is 50.
[0067] Optionally, the buffer layer 105 may further include a carbon-doped GaN layer, and the carbon-doped GaN layer is located between the superlattice structure in the buffer layer 105 and the channel layer 101 .
[0068] In the embodiment of the present disclosure, the thickness of the carbon-doped GaN layer is 1200-1800 nm.
[0069] Exemplarily, the thickness of the carbon-doped GaN layer is 1500 nm.
[0070] Optionally, the transistor further includes a substrate 106 , a nucleation layer 107 , a stress buffer layer 108 and a cap layer 109 , the nucleation layer 107 and the stress buffer layer 108 are sequentially stacked on the substrate 106 , the buffer layer 105 is located on the stress buffer layer 108 , and the cap layer 109 is located between the barrier layer 102 and the gate dielectric layer 103 .
[0071] By way of example, the substrate 106 is a Si substrate, a silicon carbide substrate or a sapphire substrate.
[0072] In the embodiment of the present disclosure, the nucleation layer 107 is an AlN nucleation layer.
[0073] In the embodiment of the present disclosure, the thickness of the nucleation layer 107 is 150-200 nm.
[0074] Exemplarily, the thickness of the nucleation layer 107 is 170 nm.
[0075] In the embodiment of the present disclosure, the stress buffer layer 108 is an AlGaN stress buffer layer.
[0076] In the disclosed embodiment, the thickness of the stress buffer layer 108 is 80-120 nm.
[0077] By way of example, the thickness of the stress buffer layer 108 is 100 nm.
[0078] In the embodiment of the present disclosure, the cap layer 109 is a GaN layer, a SiN layer or an AlN layer.
[0079] In this implementation, the cap layer 109 is mainly used to protect the barrier layer from the influence of moisture, oxygen, etc. in the environment.
[0080] In the disclosed embodiment, the thickness of the cap layer 109 is 3-5 nm.
[0081] Exemplarily, the thickness of the cap layer 109 is 4 nm.
[0082] Optionally, the transistor further includes a source 110 and a drain 111 .
[0083] The transistor is a high electron mobility transistor (HEMT). Current can be transmitted between the drain and the source through a conductive channel formed by a two-dimensional electron gas. The gate is connected to the gallium nitride structure through a gate dielectric layer. By controlling the gate voltage, the conduction and cutoff of the transistor conductive channel can be controlled.
[0084] In one example, the source 110 and the drain 111 pass through the cap layer 109 and the barrier layer 102 respectively, and are connected to the channel layer 101 .
[0085] In another example, the source 110 and the drain 111 respectively pass through the cap layer 109 and are connected to the barrier layer 102 .
[0086] Optionally, the transistor further includes a passivation layer 112 , which covers the gate dielectric layer 103 and the cap layer 109 and mainly protects the gate.
[0087] In the embodiment of the present disclosure, the gate 104 , the source 110 , and the drain 111 all pass through the passivation layer 112 .
[0088] By way of example, the passivation layer 112 may be a SiN passivation layer.
[0089] Figure 3 is a flow chart of a method for manufacturing a transistor provided by an embodiment of the present disclosure. Figure 3 The method steps include:
[0090] 301. Fabricate a channel layer.
[0091] 302. Fabricate a barrier layer on the channel layer.
[0092] 303. Fabricate a gate dielectric layer on the barrier layer.
[0093] Wherein, the gate dielectric layer includes a P-type gallium nitride dielectric layer and an InAl x The superlattice structure formed by the GaN insertion layer, x≥0, the thickness of the P-type gallium nitride dielectric layer is 20-30nm, the InAl x The thickness of the GaN insertion layer is 4 to 6 nm.
[0094] 304. Fabricate a gate on the gate dielectric layer.
[0095] In the embodiment of the present disclosure, the transistor includes a channel layer, the function of the channel layer is to form a two-dimensional electron gas between the channel layer and the barrier layer, and the gate dielectric layer is composed of a P-type gallium nitride dielectric layer and an InAl x The GaN insertion layer superlattice consists of a P-type GaN dielectric layer with a thickness of 20 to 30 nm, which can consume the electrons of the two-dimensional electron gas, and an InAl2O3 layer with a thickness of 4 to 6 nm between adjacent P-type GaN dielectric layers. x The GaN insertion layer enables the entire gate dielectric layer structure to increase the breakdown voltage of the gate and channel layer, thereby enhancing the gate's voltage resistance, which is beneficial for coping with spike voltages during use and improving reliability.
[0096] Figure 4 A flow chart of a method for manufacturing a transistor provided in an embodiment of the present disclosure, see Figure 4 , the method flow chart includes:
[0097] 401. Provide a substrate.
[0098] Exemplarily, the substrate is a Si substrate, a silicon carbide substrate or a sapphire substrate.
[0099] Optionally, the method may further include:
[0100] The substrate is placed in a metal-organic chemical vapor deposition (MOCVD) reaction chamber for nitride epitaxy, hydrogen is introduced as a carrier gas and the substrate temperature is raised to 1000° C. to 1110° C. to decompose the oxide on the substrate surface at high temperature to obtain a clean surface.
[0101] For example, a silicon substrate is placed in MOCVD, the substrate temperature is raised to 1050°C, and treated in a H2 atmosphere for 10 minutes to obtain a clean silicon surface.
[0102] 402. A nucleation layer, a stress buffer layer, a buffer layer, a channel layer and a barrier layer are sequentially fabricated on the substrate.
[0103] In the embodiment of the present disclosure, the nucleation layer is an AlN nucleation layer.
[0104] In the embodiment of the present disclosure, the thickness of the nucleation layer is 150-200 nm.
[0105] Exemplarily, the thickness of the nucleation layer is 170 nm.
[0106] In the embodiment of the present disclosure, the stress buffer layer is an AlGaN stress buffer layer.
[0107] In the disclosed embodiment, the thickness of the stress buffer layer is 80-120 nm.
[0108] Exemplarily, the thickness of the stress buffer layer is 100 nm.
[0109] In the embodiment of the present disclosure, the buffer layer includes a super lattice structure consisting of an AlN layer and an AlGaN layer.
[0110] In this implementation, by providing a buffer layer of a superlattice structure composed of an AlN layer and an AlGaN layer, the growth quality of the channel layer of the transistor is improved.
[0111] In the disclosed embodiment, the thickness of the AlN layer is 4-6 nm, and the thickness of the AlGaN layer is 20-40 nm.
[0112] Exemplarily, the thickness of the AlN layer is 5 nm, and the thickness of the AlGaN layer is 30 nm.
[0113] In the disclosed embodiment, the number of periods of the superlattice structure in the buffer layer is 40-60.
[0114] Exemplarily, the number of periods of the superlattice structure in the buffer layer is 50.
[0115] Optionally, the buffer layer may further include a carbon-doped GaN layer, and the carbon-doped GaN layer is located between the superlattice structure and the channel layer in the buffer layer.
[0116] In the embodiment of the present disclosure, the thickness of the carbon-doped GaN layer is 1200-1800 nm.
[0117] Exemplarily, the thickness of the carbon-doped GaN layer is 1500 nm.
[0118] In the embodiment of the present disclosure, the channel layer is a GaN channel layer.
[0119] The thickness of the channel layer is 250-350 nm, for example, 300 nm.
[0120] In the embodiment of the present disclosure, the barrier layer can be a single layer or a composite layer.
[0121] For example, the barrier layer is an AlGaN layer.
[0122] For another example, the barrier layer is an AlN layer, an Al 0.25 Ga 0.75 A stack of N and GaN layers.
[0123] Among them, the thickness of the AlN layer is 0.5~1.5nm, and the Al 0.25 Ga 0.75 The thickness of the N layer is 20 to 30 nm, and the thickness of the GaN layer is 1 to 3 nm.
[0124] For example, the thickness of AlN layer is 1nm, and Al0.25 Ga 0.75 The thickness of the N layer is 25nm and the thickness of the GaN layer is 2nm.
[0125] In the embodiment of the present disclosure, step 402 may include:
[0126] In the first step, the temperature of the reaction chamber is increased to 1190-1210° C., the TMAl flow rate is 390-410 sccm, and the growth time is 15-25 minutes to grow an AlN nucleation layer with a thickness of 150-200 nm.
[0127] For example, the temperature of the reaction chamber is raised to 1200° C., the TMAl flow rate is 400 sccm, and the growth time is 20 min to grow an AlN nucleation layer with a thickness of 170 nm.
[0128] In the second step, the reaction chamber temperature is adjusted to 1170-1190°C, the reaction chamber pressure is 45-55mbar, the NH3 flow rate is 3900-4100sccm, the TMGa flow rate is 440-460sccm, the TMAl flow rate is 140-160sccm, and a 40-60nm AlGaN stress buffer layer is grown; then, the TMAl flow rate is increased to continue growing a 40-60nm AlGaN stress buffer layer, and a total of 80-120nm AlGaN stress buffer layer is grown.
[0129] For example, the reaction chamber temperature is adjusted to 1180°C, the reaction chamber pressure is 50mbar, the NH3 flow rate is 4000sccm, the TMGa flow rate is 450sccm, the TMAl flow rate is 150sccm, and a 50nm AlGaN stress buffer layer is grown; then, the TMAl flow rate is increased to continue growing a 50nm AlGaN stress buffer layer, and a total of 100nm AlGaN stress buffer layer is grown.
[0130] The third step is to adjust the reaction chamber temperature to 1130-1150°C, the reaction chamber pressure to 45-55mbar, the NH3 flow rate to 4900-5100sccm, the TMGa flow rate to 190-210sccm, the TMAl flow rate to 40-60sccm, and repeat the cycle to grow 40-60 cycles of AlN / AlGaN superlattice buffer layer; adjust the reaction chamber temperature to 1040-1060°C, the reaction chamber pressure to 190-210mbar, the TMGa flow rate to 390-410sccm, the carbon doping source C2H4 flow rate to 190-210sccm, the growth time to 15-25min, and grow a 1200-1800nm carbon-doped GaN layer. The AlN / AlGaN superlattice buffer layer and the carbon-doped GaN layer constitute a buffer layer.
[0131] For example, the reaction chamber temperature is adjusted to 1140°C, the reaction chamber pressure is 50mbar, the NH3 flow rate is 5000sccm, the TMGa flow rate is 200sccm, and the TMAl flow rate is 50sccm, and the AlN / AlGaN superlattice buffer layer is grown repeatedly for 50 cycles; the reaction chamber temperature is adjusted to 1050°C, the reaction chamber pressure is 200mbar, the TMGa flow rate is 400sccm, the carbon doping source C2H4 flow rate is 200sccm, and the growth time is 20min to grow a 1500nm carbon-doped GaN layer. The AlN / AlGaN superlattice buffer layer and the carbon-doped GaN layer constitute a buffer layer.
[0132] The fourth step is to adjust the reaction chamber temperature to 1040-1060°C, the reaction chamber pressure to 190-210 mbar, the NH3 flow rate to 9500-10500 sccm, the TMGa flow rate to 190-210 sccm, and grow a GaN channel layer with a thickness of 250-350 nm.
[0133] For example, the reaction chamber temperature is adjusted to 1050° C., the reaction chamber pressure is 200 mbar, the NH 3 flow rate is 10000 sccm, the TMGa flow rate is 200 sccm, and a GaN channel layer with a thickness of 300 nm is grown.
[0134] The fifth step is to adjust the temperature of the reaction chamber to 1040-1060°C and grow an AlN layer with a thickness of 0.5-1.5 nm and an Al layer with a thickness of 20-30 nm. 0.25 Ga 0.75 The barrier layer consists of an N layer and a GaN layer with a thickness of 1 to 3 nm.
[0135] For example, the reaction chamber temperature is adjusted to 1050°C to grow an AlN layer with a thickness of 1 nm and an AlN layer with a thickness of 25 nm. 0.25 Ga 0.75 The barrier layer consists of an N layer and a GaN layer with a thickness of 2nm.
[0136] 403. A cap layer is fabricated on the surface of the barrier layer.
[0137] In the embodiment of the present disclosure, the cap layer is a GaN layer, a SiN layer or an AlN layer.
[0138] In this implementation, the cap layer mainly protects the barrier layer from the influence of moisture, oxygen, etc. in the environment.
[0139] In the disclosed embodiment, the thickness of the cap layer is 3-5 nm.
[0140] Exemplarily, the thickness of the cap layer is 4 nm.
[0141] In the embodiment of the present disclosure, step 403 may include:
[0142] The temperature of the reaction chamber is adjusted to 1040-1060° C., and a cap layer with a thickness of 3-5 nm is grown.
[0143] For example, the temperature of the reaction chamber is adjusted to 1050° C. to grow a cap layer with a thickness of 4 nm.
[0144] 404. Fabricate a gate dielectric layer on the cap layer.
[0145] Wherein, the gate dielectric layer includes a P-type gallium nitride dielectric layer and an InAl x The superlattice structure formed by the GaN insertion layer, x≥0, the thickness of the P-type gallium nitride dielectric layer is 20-30nm, the InAl x The thickness of the GaN insertion layer is 4 to 6 nm.
[0146] In the embodiment of the present disclosure, the P-type gallium nitride dielectric layer may be a Mg-doped gallium nitride dielectric layer, or a Sn-doped gallium nitride dielectric layer, or a Fe-doped gallium nitride dielectric layer.
[0147] In the embodiment of the present disclosure, the Mg doping concentration in the P-type gallium nitride dielectric layer is 0.5E19 to 2E19 / cm 3 .
[0148] For example, the Mg doping concentration in the P-type gallium nitride dielectric layer is 1E19 / cm 3 .
[0149] In this implementation, the use of the above doping concentration can better increase the withstand voltage of the transistor.
[0150] In one implementation of the present disclosure, the InAl x The GaN insertion layer is a non-doped InAlGaN layer or a non-doped InGaN layer.
[0151] In this implementation, the undoped InAlGaN layer or the undoped InGaN layer can increase the breakdown voltage of the gate and the gallium nitride structure, thereby enhancing the gate withstand voltage. The staggered stacking of the supercrystalline format multi-layer insertion layer can adjust the uniform distribution of the Mg doping ion concentration in the dielectric layer, better consume the electrons of the 2DEG (two-dimensional electron gas), so that the conductive channel is cut off under normal conditions, further enhancing the gate withstand voltage.
[0152] In another implementation of the embodiment of the present disclosure, the InAl x The GaN insertion layer is an N-type InAlGaN layer or an N-type InGaN layer.
[0153] In this implementation, a PN junction is formed between the Mg-doped P-type GaN dielectric layer and the Si-doped InAlGaN or InGaN insertion layer, and multiple PN junctions are formed between multiple N-type InAlGaN or InGaN insertion layers and multiple P-type gallium nitride layers, and the PN junction can be equivalently regarded as a diode. At least one layer of N-type InAlGaN or InGaN insertion layer is located on the P-type GaN layer, that is, at least one PN junction equivalent to a diode is reversely connected in series between the gate and the gallium nitride channel layer structure, wherein the equivalent reverse series PN junction enhances the withstand voltage, which can increase the breakdown voltage between the gate and the gallium nitride channel layer structure, thereby further enhancing the gate withstand voltage performance.
[0154] In the embodiment of the present disclosure, the thickness of the P-type gallium nitride dielectric layer is 25 nm. x The thickness of the GaN insertion layer is 5 nm.
[0155] In this implementation, the P-type GaN dielectric layer and InAl x The above-mentioned thickness of the GaN insertion layer can ensure the effect of increasing the withstand voltage without causing the transistor size to be too large.
[0156] In the disclosed embodiment, the number of periods of the superlattice structure in the gate dielectric layer is 8-12.
[0157] Exemplarily, the number of periods of the superlattice structure in the gate dielectric layer is 10.
[0158] In this implementation, the P-type gallium nitride dielectric layer uses a superlattice with the above-mentioned number of periods to ensure the effect of increasing the withstand voltage without causing the transistor size to be too large.
[0159] In some examples, step 404 may include:
[0160] In an environment where the reaction chamber temperature is 890-910°C, the reaction chamber pressure is 190-210 mbar, the NH3 flow rate is 4900-5100 sccm, the TMIn flow rate is 790-810 sccm, and the TMGa flow rate is 190-210 sccm, multiple cycles of P-type gallium nitride dielectric layers and non-doped InGaN layers are grown in sequence;
[0161] Alternatively, in an environment where the reaction chamber temperature is 890-910° C., the reaction chamber pressure is 190-210 mbar, the NH3 flow rate is 4900-5100 sccm, the TMIn flow rate is 790-810 sccm, the TMGa flow rate is 190-210 sccm, and the TMAl flow rate is 49-51 sccm, multiple cycles of P-type gallium nitride dielectric layers and non-doped InAlGaN layers are grown in sequence.
[0162] For example, in an environment where the reaction chamber temperature is 900°C, the reaction chamber pressure is 200 mbar, the NH3 flow rate is 5000 sccm, the TMIn flow rate is 800 sccm, and the TMGa flow rate is 200 sccm, multiple cycles of P-type gallium nitride dielectric layers and non-doped InGaN layers are grown in sequence;
[0163] Alternatively, multiple cycles of P-type gallium nitride dielectric layers and undoped InAlGaN layers are grown in sequence under an environment of a reaction chamber temperature of 900° C., a reaction chamber pressure of 200 mbar, an NH3 flow rate of 5000 sccm, a TMIn flow rate of 800 sccm, a TMGa flow rate of 200 sccm, and a TMAl flow rate of 50 sccm.
[0164] In other examples, step 404 may include:
[0165] In an environment where the reaction chamber temperature is 890-910°C, the reaction chamber pressure is 190-210 mbar, the SiH4 flow rate is 69-71 sccm, the NH3 flow rate is 4900-5100 sccm, the TMIn flow rate is 790-810 sccm, and the TMGa flow rate is 190-210 sccm, multiple cycles of P-type gallium nitride dielectric layers and N-type InGaN layers are grown in sequence;
[0166] Alternatively, in an environment where the reaction chamber temperature is 890-910°C, the reaction chamber pressure is 190-210 mbar, the SiH4 flow rate is 69-71 sccm, the NH3 flow rate is 4900-5100 sccm, the TMIn flow rate is 790-810 sccm, the TMGa flow rate is 190-210 sccm, and the TMAl flow rate is 49-51 sccm, multiple cycles of P-type gallium nitride dielectric layers and N-type InAlGaN layers are grown in sequence.
[0167] For example, in an environment where the reaction chamber temperature is 900°C, the reaction chamber pressure is 200 mbar, the SiH4 flow rate is 70 sccm, the NH3 flow rate is 5000 sccm, the TMIn flow rate is 800 sccm, and the TMGa flow rate is 200 sccm, multiple cycles of P-type gallium nitride dielectric layers and N-type InGaN layers are grown in sequence;
[0168] Alternatively, in an environment where the reaction chamber temperature is 900° C., the reaction chamber pressure is 200 mbar, the SiH4 flow rate is 70 sccm, the NH3 flow rate is 5000 sccm, the TMIn flow rate is 800 sccm, the TMGa flow rate is 200 sccm, and the TMAl flow rate is 50 sccm, multiple cycles of P-type gallium nitride dielectric layers and N-type InAlGaN layers are grown in sequence.
[0169] In the disclosed embodiment, the gate dielectric layer does not cover the entire cap layer. During fabrication, a superlattice film layer is first fabricated and then patterned to obtain a final gate dielectric layer.
[0170] 405. Fabricate a gate on the surface of the gate dielectric layer.
[0171] Exemplarily, step 405 may include:
[0172] A gate metal layer is formed on the surface of the gate dielectric layer; and the gate metal layer is patterned to obtain a gate.
[0173] 406. Make a passivation layer.
[0174] Among them, the passivation layer covers the gate dielectric layer and the cap layer, and mainly protects the gate.
[0175] Exemplarily, the passivation layer may be a SiN passivation layer.
[0176] Exemplarily, step 406 may include:
[0177] A SiN passivation layer is manufactured; and the SiN passivation layer is patterned to expose the gate.
[0178] 407. Make source, drain and drain.
[0179] In one example, the source and the drain pass through the cap layer and the barrier layer respectively and are connected to the channel layer.
[0180] Exemplarily, step 407 may include:
[0181] A source groove and a drain groove are respectively formed on the passivation layer, the cap layer and the barrier layer, and both the source groove and the drain groove are connected to the channel layer; a source and a drain are respectively formed in the source groove and the drain groove.
[0182] In another example, the source and the drain pass through the cap layer and are connected to the barrier layer respectively.
[0183] Exemplarily, step 407 may include:
[0184] A source groove and a drain groove are respectively formed on the passivation layer and the cap layer, and both the source groove and the drain groove are connected to the barrier layer; a source and a drain are respectively formed in the source groove and the drain groove.
[0185] The above description is only an optional embodiment of the present disclosure and is not intended to limit the present disclosure. Any modifications, equivalent substitutions, improvements, etc. made within the spirit and principles of the present disclosure shall be included in the protection scope of the present disclosure.
Claims
1. A transistor, characterized in that: The transistor comprises: A channel layer (101), a barrier layer (102), a gate dielectric layer (103) and a gate (104) sequentially stacked on the channel layer (101); The gate dielectric layer (103) comprises a P-type gallium nitride dielectric layer (131) and an InAl x The GaN insertion layer (132) forms a superlattice structure, x≥0, the thickness of the P-type gallium nitride dielectric layer (131) is 20-30 nm, and the InAl x The thickness of the GaN insertion layer (132) is 4-6 nm.
2. The transistor according to claim 1, characterized in that The InAl x The GaN insertion layer (132) is a non-doped InAlGaN layer, a non-doped InGaN layer, an N-type InAlGaN layer or an N-type InGaN layer.
3. The transistor according to claim 1, characterized in that The thickness of the P-type gallium nitride dielectric layer (131) is 25 nm. x The thickness of the GaN insertion layer (132) is 5 nm.
4. The transistor according to any one of claims 1 to 3, characterized in that: The period number of the superlattice structure is 8-12.
5. The transistor according to any one of claims 1 to 3, characterized in that: The transistor further comprises a buffer layer (105), and the channel layer (101) is located on the buffer layer (105); The buffer layer (105) comprises a super lattice structure consisting of an AlN layer and an AlGaN layer.
6. A method for manufacturing a transistor, characterized in that: The method comprises: manufacturing a channel layer; forming a barrier layer on the channel layer; A gate dielectric layer is formed on the barrier layer, wherein the gate dielectric layer includes a P-type gallium nitride dielectric layer and an InAl x The superlattice structure formed by the GaN insertion layer, x≥0, the thickness of the P-type gallium nitride dielectric layer is 20-30nm, the InAl x The thickness of the GaN insertion layer is 4 to 6 nm; A gate is fabricated on the gate dielectric layer.
7. The method according to claim 6, characterized in that The step of forming a gate dielectric layer on the barrier layer comprises: In an environment where the reaction chamber temperature is 890-910°C, the reaction chamber pressure is 190-210 mbar, the NH3 flow rate is 4900-5100 sccm, the TMIn flow rate is 790-810 sccm, and the TMGa flow rate is 190-210 sccm, multiple cycles of P-type gallium nitride dielectric layers and non-doped InGaN layers are grown in sequence; Alternatively, in an environment where the reaction chamber temperature is 890-910° C., the reaction chamber pressure is 190-210 mbar, the NH3 flow rate is 4900-5100 sccm, the TMIn flow rate is 790-810 sccm, the TMGa flow rate is 190-210 sccm, and the TMAl flow rate is 49-51 sccm, multiple cycles of P-type gallium nitride dielectric layers and non-doped InAlGaN layers are grown in sequence.
8. The method according to claim 6, characterized in that The step of forming a gate dielectric layer on the barrier layer comprises: In an environment where the reaction chamber temperature is 890-910°C, the reaction chamber pressure is 190-210 mbar, the SiH4 flow rate is 69-71 sccm, the NH3 flow rate is 4900-5100 sccm, the TMIn flow rate is 790-810 sccm, and the TMGa flow rate is 190-210 sccm, multiple cycles of P-type gallium nitride dielectric layers and N-type InGaN layers are grown in sequence; Alternatively, in an environment where the reaction chamber temperature is 890-910°C, the reaction chamber pressure is 190-210 mbar, the SiH4 flow rate is 69-71 sccm, the NH3 flow rate is 4900-5100 sccm, the TMIn flow rate is 790-810 sccm, the TMGa flow rate is 190-210 sccm, and the TMAl flow rate is 49-51 sccm, multiple cycles of P-type gallium nitride dielectric layers and N-type InAlGaN layers are grown in sequence.
9. The method according to any one of claims 6 to 8, characterized in that: The Mg doping concentration in the P-type gallium nitride dielectric layer is 0.5E19 to 2E19 / cm 3 .
10. The method according to any one of claims 6 to 8, characterized in that: The thickness of the P-type gallium nitride dielectric layer is 25 nm. x The thickness of the GaN insertion layer is 5 nm.