Metal oxide semiconductor field effect transistor, preparation method thereof and electronic equipment

Abstract

According to the metal oxide semiconductor field effect transistor, the preparation method thereof and the electronic equipment disclosed by the embodiment of the invention, the N + substrate and the N-type low-doped semiconductor layer are both provided with the grooves to expose the N-type drift layer, the N + drain region doped with high-concentration N-type impurities is formed on one side, close to the N + substrate, of the N-type drift layer, and the grooves are filled with the drain conducting layer, so that the N-type drift layer is exposed out of the N-type drift layer. The resistance of the N + substrate can be greatly reduced, the N + substrate does not need to be thinned, the thicker N + substrate can still be kept, and compared with a method for thinning the N + substrate in the prior art, the method has the advantages that the fragment risk is reduced, and the mechanical strength of the wafer can be kept. The drain conducting layer is in direct contact with the N-type low-doped semiconductor layer, so that holes can be extracted from the contact surface of the drain conducting layer and the N-type low-doped semiconductor layer when a body diode of the metal oxide semiconductor field effect transistor is conducted, and the hole density in the N-type drift layer is reduced; reverse recovery charge of the device is reduced, and reverse recovery current is reduced.

Description

Technical Field

[0001] The present disclosure relates to the field of semiconductor technology, and in particular to a metal oxide semiconductor field effect transistor, a preparation method thereof, and an electronic device. Background Art

[0002] Bridge circuits such as half-bridge circuits and full-bridge circuits are widely used due to their simple circuit structure and simple drive. In bridge circuits, diodes are often required or the body diode of MOSFET is used to freewheel the current in the inductive load. Since the body diode in the MOSFET is a PiN diode, there are a large number of free carriers in the drift region when the body diode is turned on. Although this is beneficial to reducing the conduction voltage drop of the body diode, it will lead to higher reverse recovery charge and reverse recovery current, which not only leads to higher power consumption and limits the increase in device frequency, but also affects the long-term reliability of the device. In addition, in SiC-based MOSFETs, holes when the body diode is turned on will produce a bipolar degradation effect. Therefore, it is necessary to reduce the reverse recovery charge of the body diode of the MOSFET and improve the reverse recovery characteristics.

[0003] MOSFET is generally a vertical structure. For vertical power devices, a thicker substrate leads to a higher substrate resistance. Reducing the substrate thickness can reduce the substrate resistance and is more conducive to heat dissipation. Usually, the substrate can be ground to a specified thickness through substrate thinning technology, but a too thin substrate not only means longer processing time and higher process costs, but also easily leads to fragmentation. Summary of the invention

[0004] The embodiments of the present disclosure provide a metal oxide semiconductor field effect transistor, a method for preparing the same, and an electronic device, which are used to reduce the reverse recovery charge of the device and reduce the reverse recovery current. The device can also maintain a thicker substrate while reducing the on-resistance of the device, and the device is not prone to fragmentation.

[0005] The embodiments of the present disclosure provide a metal oxide semiconductor field effect transistor, a method for manufacturing the same, and an electronic device, the specific scheme of which is as follows:

[0006] In one aspect, an embodiment of the present disclosure provides a metal oxide semiconductor field effect transistor, comprising:

[0007] An N+ substrate including a first trench extending through a thickness thereof;

[0008] An N-type low-doped semiconductor layer, located on one side of the N+ substrate, the N-type low-doped semiconductor layer comprising a second trench running through the thickness thereof, the first trench and the second trench overlapping;

[0009] An N-type drift layer, located on a side of the N-type low-doped semiconductor layer away from the N+ substrate;

[0010] An N+ drain region, located in the N-type drift layer and on a side of the N-type drift layer close to the N+ substrate, the N+ drain region covering the second trench;

[0011] The drain conductive layer covers the side of the N+ substrate away from the N-type drift layer and fills the first trench and the second trench until they are in contact with the N+ drain region.

[0012] In some embodiments, in the above-mentioned metal oxide semiconductor field effect transistor provided by the embodiments of the present disclosure, the N+ drain region also covers a portion of the N-type low-doped semiconductor layer.

[0013] In some embodiments, in the metal oxide semiconductor field effect transistor provided in the embodiments of the present disclosure, the N-type low-doped semiconductor layer is an N-type buffer layer.

[0014] In some embodiments, in the above-mentioned metal oxide semiconductor field effect transistor provided by the embodiments of the present disclosure, a side of the N+ drain region close to the N+ substrate is in contact with a side of the N-type buffer layer away from the N+ substrate.

[0015] In some embodiments, in the above-mentioned metal oxide semiconductor field effect transistor provided in the embodiments of the present disclosure, the N-type drift layer has a groove that runs through part of its thickness on a side close to the N+ substrate and corresponding to the second trench, the groove overlaps with the second trench, and the N-type drift layer is provided between the N+ drain region and the N-type buffer layer.

[0016] In some embodiments, in the above-mentioned metal oxide semiconductor field effect transistor provided by the embodiments of the present disclosure, the N-type low-doped semiconductor layer and the N-type drift layer are an integrated structure.

[0017] In some embodiments, the above-mentioned metal oxide semiconductor field effect transistor provided in the embodiments of the present disclosure further includes: two P-type well regions located in the N-type drift layer and close to the side of the N-type drift layer away from the N+ substrate, and an N+ source region and a P+ source region located in the P-type well region and close to the side of the N-type drift layer away from the N+ substrate; wherein the N+ source region and the P+ source region are arranged laterally and contact each other, and the P+ source region is arranged close to the side of the N-type drift layer, and the P-type well region covers the side of the P+ source region and the N+ source region close to the N+ substrate and covers the side of the N+ source region away from the P+ source region;

[0018] It also includes: a gate dielectric layer located on a side of the N-type drift layer away from the N+ substrate, a gate conductive layer located on a side of the gate dielectric layer away from the N+ substrate, and an isolation dielectric layer located on a side of the gate conductive layer away from the N+ substrate; wherein the gate dielectric layer contacts the N-type drift layer, the P-type well region and the N+ source region, and the isolation dielectric layer wraps the gate conductive layer and contacts the gate dielectric layer;

[0019] It also includes a source conductive layer located on the side of the isolation dielectric layer, the N+ source region and the P+ source region away from the N+ substrate, and the source conductive layer wraps the isolation dielectric layer and contacts the N+ source region and the P+ source region.

[0020] On the other hand, the present disclosure also provides a method for preparing a metal oxide semiconductor field effect transistor, which is used to prepare the metal oxide semiconductor field effect transistor provided in the present disclosure, and the preparation method comprises:

[0021] Epitaxially forming an N-type low-doped semiconductor layer and an N-type drift layer on one side of the N+ substrate;

[0022] Etching the N+ substrate and the N-type low-doped semiconductor layer to form a first trench penetrating the thickness of the N+ substrate and a second trench penetrating the thickness of the N-type low-doped semiconductor layer to expose the N-type drift layer;

[0023] Implanting N-type impurities into the exposed side of the N-type drift layer close to the N+ substrate to form an N+ drain region;

[0024] A drain conductive layer is formed on a side of the N+ substrate away from the N-type drift layer, and the drain conductive layer fills the first trench and the second trench until it contacts the N+ drain region.

[0025] In some embodiments, in the above-mentioned preparation method provided in the embodiments of the present disclosure, when etching the N+ substrate and the N-type low-doped semiconductor layer to form a first trench penetrating the thickness of the N+ substrate and a second trench penetrating the thickness of the N-type low-doped semiconductor layer, the method further includes:

[0026] A groove is formed by over-etching into the inside of the N-type drift layer.

[0027] In some embodiments, in the above-mentioned preparation method provided by the embodiments of the present disclosure, after the N-type low-doped semiconductor layer and the N-type drift layer are epitaxially formed on one side of the N+ substrate, and before the N+ substrate and the N-type low-doped semiconductor layer are etched, it also includes: forming a P-type well region, an N+ source region and a P+ source region on a side of the N-type drift layer away from the N+ substrate by injecting corresponding N-type or P-type impurities;

[0028] After N-type impurities are implanted into the exposed N-type drift layer on a side close to the N+ substrate to form an N+ drain region, and before a drain conductive layer is formed on a side of the N+ substrate away from the N-type drift layer, the method further includes:

[0029] forming a gate dielectric layer on a side of the N-type drift layer away from the N+ substrate;

[0030] forming a gate conductive layer on a side of the gate dielectric layer away from the N+ substrate;

[0031] forming an isolation dielectric layer on a side of the gate conductive layer away from the N+ substrate;

[0032] A source conductive layer is formed on a side of the isolation dielectric layer, the N+ source region and the P+ source region away from the N+ substrate.

[0033] On the other hand, an embodiment of the present disclosure further provides an electronic device, comprising the above-mentioned metal oxide semiconductor field effect transistor provided by an embodiment of the present disclosure.

[0034] The beneficial effects of the present disclosure are as follows:

[0035] The embodiment of the present disclosure provides a metal oxide semiconductor field effect transistor, a preparation method thereof, and an electronic device. Since grooves are dug in both the N+ substrate and the N-type low-doped semiconductor layer, the N-type drift layer can be exposed. By forming an N+ drain region doped with high concentration N-type impurities on the side of the exposed N-type drift layer close to the N+ substrate, the N+ drain region can reduce the on-resistance and improve the withstand voltage performance, and the drain conductive layer fills the groove, so that the drain conductive layer is in contact with the side of the N+ substrate at the first groove position, the side of the N-type low-doped semiconductor layer at the second groove position, and the side of the N+ drain region close to the N+ substrate. Therefore, the metal oxide semiconductor field effect transistor provided by the present disclosure can greatly reduce the resistance of the N+ substrate, and there is no need to thin the N+ substrate, and a relatively thick N+ substrate can still be maintained. Compared with the method of thinning the N+ substrate in the prior art, the present disclosure reduces the risk of fragmentation and can maintain the mechanical strength of the wafer. At the same time, the drain conductive layer disclosed in the present invention can be in direct contact with the N-type low-doped semiconductor layer, which is beneficial for the holes to be extracted from the contact surface between the drain conductive layer and the N-type low-doped semiconductor layer when the body diode of the metal oxide semiconductor field effect transistor is turned on, thereby reducing the hole density in the N-type drift layer, and is beneficial for reducing the reverse recovery charge of the metal oxide semiconductor field effect transistor and reducing the reverse recovery current. BRIEF DESCRIPTION OF THE DRAWINGS

[0036] Figure 1 A schematic diagram of a structure of a metal oxide semiconductor field effect transistor provided in an embodiment of the present disclosure;

[0037] Figure 2 A schematic diagram of another structure of a metal oxide semiconductor field effect transistor provided in an embodiment of the present disclosure;

[0038] Figure 3 A schematic diagram of another structure of a metal oxide semiconductor field effect transistor provided in an embodiment of the present disclosure;

[0039] Figure 4A A schematic diagram of the forward current distribution of the metal oxide semiconductor field effect transistor provided in an embodiment of the present disclosure;

[0040] Figure 4B A schematic diagram of the forward current distribution of a conventional metal oxide semiconductor field effect transistor;

[0041] Figure 5A A schematic diagram of reverse conduction current distribution of a metal oxide semiconductor field effect transistor provided in an embodiment of the present disclosure;

[0042] Figure 5B A schematic diagram of reverse conduction current distribution of a conventional metal oxide semiconductor field effect transistor;

[0043] Figure 6 A flow chart of a method for preparing a metal oxide semiconductor field effect transistor provided in an embodiment of the present disclosure;

[0044] Figure 7 A flow chart of another method for preparing a metal oxide semiconductor field effect transistor provided in an embodiment of the present disclosure;

[0045] Fig. 8A for Figure 1 A schematic diagram of the structure of a metal oxide semiconductor field effect transistor during the preparation process shown;

[0046] Figure 8B for Figure 1 Another structural schematic diagram of a metal oxide semiconductor field effect transistor during the preparation process is shown;

[0047] Figure 8C for Figure 1 Another structural schematic diagram of a metal oxide semiconductor field effect transistor during the preparation process is shown;

[0048] Fig.8D for Figure 1 Another structural schematic diagram of a metal oxide semiconductor field effect transistor during the preparation process is shown;

[0049] Fig. 8E for Figure 1 Another structural schematic diagram of a metal oxide semiconductor field effect transistor during the preparation process is shown. DETAILED DESCRIPTION

[0050] In order to make the purpose, technical solution and advantages of the embodiments of the present disclosure clearer, the technical solution of the embodiments of the present disclosure will be clearly and completely described in conjunction with the drawings of the embodiments of the present disclosure. It should be noted that in the drawings, the thickness of the layers, films, panels, regions, etc. is magnified for clarity. In the present disclosure, exemplary embodiments are described with reference to cross-sectional views of schematic diagrams of idealized embodiments. In this way, deviations from the shapes of the figures as a result of, for example, manufacturing technology and / or tolerances will be expected. Therefore, the embodiments described in the present disclosure should not be interpreted as being limited to the specific shapes of the regions shown in the present disclosure, but include deviations in shape caused by, for example, manufacturing. For example, an area illustrated or described as flat may typically have rough and / or nonlinear features; the illustrated sharp corners may be rounded, etc. Therefore, the areas shown in the figures are schematic in nature, and their sizes and shapes do not represent the exact shapes of the illustrated areas, do not reflect the true proportions, and the purpose is only to illustrate the contents of the present disclosure. And the same or similar reference numerals throughout represent the same or similar elements or elements with the same or similar functions. In order to keep the following description of the embodiments of the present disclosure clear and concise, the present disclosure omits detailed descriptions of well-known functions and well-known components.

[0051] Unless otherwise defined, the technical terms or scientific terms used herein shall have the usual meanings understood by persons of ordinary skill in the field to which the present disclosure belongs. The words "first", "second" and similar words used in the present disclosure specification and claims do not indicate any order, quantity or importance, but are only used to distinguish different components. Words such as "include" or "comprise" and the like mean that the elements or objects appearing before the word include the elements or objects listed after the word and their equivalents, without excluding other elements or objects. Words such as "connect" or "connected" and the like are not limited to physical or mechanical connections, but may include electrical connections, whether direct or indirect. "Inside", "outside", "upper", "lower", etc. are only used to indicate relative positional relationships. When the absolute position of the described object changes, the relative positional relationship may also change accordingly.

[0052] In the following description, when an element or layer is referred to as being "on" or "connected to" another element or layer, the element or layer may be directly on, directly connected to, or there may be an intermediate element or intermediate layer. When an element or layer is referred to as being "disposed on one side of" another element or layer, the element or layer may be directly on one side of, directly connected to, or there may be an intermediate element or intermediate layer. However, when an element or layer is referred to as being "directly on" or "directly connected to" another element or layer, there are no intermediate elements or intermediate layers. The term "and / or" includes any and all combinations of one or more of the associated listed items.

[0053] The present disclosure provides a metal oxide semiconductor field effect transistor, such as Figure 1 As shown, including:

[0054] N+ substrate 1, N+ substrate 1 includes a first trench U1 running through the thickness thereof;

[0055] An N-type low-doped semiconductor layer 2 is located on one side of the N+ substrate 1, and the N-type low-doped semiconductor layer 2 includes a second trench U2 running through the thickness thereof, and the first trench U1 and the second trench U2 overlap;

[0056] An N-type drift layer 3 is located on a side of the N-type low-doped semiconductor layer 2 away from the N+ substrate 1;

[0057] An N+ drain region 4 is located in the N-type drift layer 3 and on a side of the N-type drift layer 3 close to the N+ substrate 1 , and the N+ drain region 4 covers the second trench U2 ;

[0058] The drain conductive layer 5 covers the side of the N+ substrate 1 away from the N-type drift layer 3 , and fills the first trench U1 and the second trench U2 until they are in contact with the N+ drain region 4 .

[0059] The above-mentioned metal oxide semiconductor field effect transistor provided by the embodiment of the present disclosure, because the N+ substrate and the N-type low-doped semiconductor layer are both grooved, the N-type drift layer can be exposed, and the N+ drain region doped with high concentration N-type impurities is formed on the side of the exposed N-type drift layer close to the N+ substrate, the N+ drain region can reduce the on-resistance and improve the withstand voltage performance, and the drain conductive layer fills the groove, so that the drain conductive layer is in contact with the side of the N+ substrate at the first groove position, the side of the N-type low-doped semiconductor layer at the second groove position, and the side of the N+ drain region close to the N+ substrate. Therefore, the metal oxide semiconductor field effect transistor provided by the present disclosure can greatly reduce the resistance of the N+ substrate, and there is no need to thin the N+ substrate, and a relatively thick N+ substrate can still be maintained. Compared with the method of thinning the N+ substrate in the prior art, the present disclosure reduces the risk of fragmentation and can maintain the mechanical strength of the wafer. At the same time, the drain conductive layer disclosed in the present invention is directly in contact with the N-type low-doped semiconductor layer, which is beneficial for holes to be extracted from the contact surface between the drain conductive layer and the N-type low-doped semiconductor layer when the body diode of the metal oxide semiconductor field effect transistor is turned on, thereby reducing the hole density in the N-type drift layer, and is beneficial for reducing the reverse recovery charge of the metal oxide semiconductor field effect transistor and reducing the reverse recovery current.

[0060] In some embodiments, in the above-mentioned metal oxide semiconductor field effect transistor provided in the embodiments of the present disclosure, as Figure 1-Figure 3 As shown, the N+ drain region 4 can be formed by ion implantation of high-concentration N-type impurities in the N-type drift layer exposed in the first trench U1 and the second trench U2. Due to the influence of the ion implantation process, the N+ drain region 4 will also cover part of the N-type low-doped semiconductor layer 2, that is, the N+ drain region 4 cannot completely cover the N-type low-doped semiconductor layer 2, and the side of the N-type drift layer 3 close to the N+ substrate 1 needs to be in contact with the side of the N-type low-doped semiconductor layer 2 away from the N+ substrate 1.

[0061] In some embodiments, in the above-mentioned metal oxide semiconductor field effect transistor provided in the embodiments of the present disclosure, as Figure 1-Figure 3 As shown, the first trench U1 and the second trench U2 can be formed by one etching process, and the cross-sectional shape of the entire trench formed by the first trench U1 and the second trench U2 along the thickness direction of the N+ substrate 1 can be a rectangle, but it is certainly not limited thereto.

[0062] In some embodiments, in the above-mentioned metal oxide semiconductor field effect transistor provided in the embodiments of the present disclosure, as Figure 1 As shown, the N-type low-doped semiconductor layer 2 may be an N-type buffer layer, and the side of the N+ drain region 4 close to the N+ substrate 1 is in contact with the side of the N-type buffer layer (i.e., the N-type low-doped semiconductor layer 2) away from the N+ substrate 1. That is, when etching the N+ substrate and the N-type low-doped semiconductor layer 2, the etching is just performed to the interface between the N-type buffer layer and the N-type drift layer 3.

[0063] In some embodiments, in the above-mentioned metal oxide semiconductor field effect transistor provided in the embodiments of the present disclosure, as Figure 1 As shown, it also includes: two P-type well regions 6 located in the N-type drift layer 3 and close to the side of the N-type drift layer 3 away from the N+ substrate 1, and an N+ source region 7 and a P+ source region 8 located in the P-type well region 6 and close to the side of the N-type drift layer 3 away from the N+ substrate 1; wherein the N+ source region 7 and the P+ source region 8 are arranged laterally and contact each other, and the P+ source region 8 is arranged close to the side of the N-type drift layer 3, and the P-type well region 6 covers the side of the P+ source region 8 and the N+ source region 7 close to the N+ substrate 1 and covers the side of the N+ source region 7 away from the P+ source region 8; specifically, as Figure 1 As shown, the P-type well region 6 , the N+ source region 7 and the P+ source region 8 are all formed by ion implantation on a side of the N-type drift layer 3 away from the N+ substrate 1 .

[0064] In some embodiments, in the above-mentioned metal oxide semiconductor field effect transistor provided in the embodiments of the present disclosure, as Figure 1 As shown, it also includes: a gate dielectric layer 9 located on the side of the N-type drift layer 3 away from the N+ substrate 1, a gate conductive layer 10 located on the side of the gate dielectric layer 9 away from the N+ substrate 1, and an isolation dielectric layer 11 located on the side of the gate conductive layer 10 away from the N+ substrate 1; wherein the gate dielectric layer 9 is in contact with the N-type drift layer 3, the P-type well region 6 and the N+ source region 7, and the isolation dielectric layer 11 wraps the gate conductive layer 10 and is in contact with the gate dielectric layer 9; specifically, the materials of the gate dielectric layer 9 and the isolation dielectric layer 11 can be SiO 2 , HfO 2 、Al 2 O 3 、Si 3 N 4 wait.

[0065] In some embodiments, in the above-mentioned metal oxide semiconductor field effect transistor provided in the embodiments of the present disclosure, as Figure 1 As shown, the gate structure composed of the gate dielectric layer 9, the gate conductive layer 10 and the isolation dielectric layer 11 is a planar gate, and of course it can also be a trench gate, which is not limited in the present disclosure.

[0066] In some embodiments, in the above-mentioned metal oxide semiconductor field effect transistor provided in the embodiments of the present disclosure, as Figure 1 As shown, it also includes a source conductive layer 12 located on the side of the isolation dielectric layer 11, the N+ source region 7 and the P+ source region 8 away from the N+ substrate 1. The source conductive layer 12 wraps the isolation dielectric layer 11 and contacts the N+ source region 7 and the P+ source region 8.

[0067] In some embodiments, in the above-mentioned metal oxide semiconductor field effect transistor provided in the embodiments of the present disclosure, as Figure 1 As shown, the side of the source conductive layer 12 away from the N+ substrate 1 is a flat surface, and the side of the drain conductive layer 5 away from the N+ substrate 1 is a flat surface, which is beneficial to improving device performance.

[0068] Specifically, Figure 1 As shown, the P-type well region 6, N+ source region 7, P+ source region 8 and source conductive layer 12 constitute the source region of the device, the gate dielectric layer 9, the gate conductive layer 10 and the isolation dielectric layer 11 constitute the gate region of the device, the N-type drift layer 3 is the drift region of the device, and the N+ substrate 1, the N-type buffer layer (i.e., the N-type low-doped semiconductor layer 2), the N+ drain region 4 and the drain conductive layer 5 constitute the drain region of the device. The cell structure of the device includes the above-mentioned source region, gate region, drift region and drain region, and a cell may include multiple P-type well regions 6, N+ source regions 7, P+ source regions 8 and source conductive layers 12.

[0069] In some embodiments, in the above-mentioned metal oxide semiconductor field effect transistor provided in the embodiments of the present disclosure, the source conductive layer and the drain conductive layer can be made of materials such as metal; the gate conductive layer can be made of one or more materials such as doped polysilicon, metal, etc.

[0070] by Figure 1 Taking the metal oxide semiconductor field effect transistor shown in the figure as an example, the forward conduction and reverse conduction current distributions of the metal oxide semiconductor field effect transistor of the present invention and the conventional metal oxide semiconductor field effect transistor are compared. The difference between the conventional structure and the structure of the present invention is that the N+ substrate 1 and the N-type buffer layer (i.e., the N-type low-doped semiconductor layer 2) in the conventional structure are not grooved, and the N+ drain region 4 is not formed in the N-type drift layer 3. Figure 4A and Figure 4B As shown, Figure 4A is a schematic diagram of the forward conduction current distribution of the structure disclosed in the present invention, Figure 4B This is a schematic diagram of the forward conduction current distribution of a conventional structure. The arrows indicate the current path. It can be seen from the figure that the forward current of the conventional structure needs to completely pass through the substrate N+ substrate 1 and the N-type buffer layer from the drain conductive layer 5. Therefore, the device on-resistance is closely related to the resistance of the N+ substrate 1 and the N-type buffer layer. Reducing this resistance is often achieved by thinning the thickness of the N+ substrate 1. However, if the N+ substrate 1 is too thin, it is easy to cause fragmentation. However, most of the forward current of the structure disclosed in the present invention is from the drain conductive layer 5 through the N+ drain region 4 to the N-type drift layer 3. Since the doping concentration of the N+ drain region 4 is high and at least 2 orders of magnitude thinner than the N+ substrate 1, the high parasitic resistance caused by the thick N+ substrate 1 and the N-type buffer layer is greatly reduced, thereby reducing the on-resistance of the device. Figure 5A and Figure 5B As shown, Figure 5A is a schematic diagram of reverse conduction current distribution of the structure disclosed in the present invention, Figure 5B The reverse conduction current distribution diagram of the conventional structure is shown in the figure. The arrows indicate the current path. It can be seen from the figure that the hole current conduction path of the conventional structure must pass through the N+ substrate 1. Since the doping concentration of the N+ substrate 1 is high and thick, it is difficult for holes to pass through the N+ substrate 1 to reach the drain conductive layer 5. A large number of holes are stored in the N-type drift layer 3, resulting in a higher hole concentration in the N-type drift layer 3, thereby causing a larger reverse recovery charge during the reverse recovery process. For the structure disclosed in the present invention, the N+ drain region 4 is thinner, so holes can easily pass through it to enter the drain conductive layer 5. In addition, holes can also enter the drain conductive layer 5 through the N-type buffer layer with a lower doping concentration. Therefore, the hole concentration in the N-type drift layer 3 of the structure disclosed in the present invention is lower, which can reduce the reverse recovery charge during the reverse recovery process.

[0071] In some embodiments, in the above-mentioned metal oxide semiconductor field effect transistor provided in the embodiments of the present disclosure, as Figure 2 As shown, the N-type low-doped semiconductor layer 2 can be an N-type buffer layer, and the N-type drift layer 3 has a groove U3 that runs through part of its thickness on the side close to the N+ substrate 1 and corresponding to the second groove U2, the groove U3 overlaps with the second groove U2, and there is an N-type drift layer 3 between the N+ drain region 4 and the N-type buffer layer (i.e., the N-type low-doped semiconductor layer 2). Figure 2 When etching the N+ substrate 1 and the N-type buffer layer, the structure shown in the figure can be overetched to the inside of the N-type drift layer 3 to form a groove U3, and then ion implantation is performed on the side of the N-type drift layer 3 exposed at the groove U3 near the N+ substrate 1 to form an N+ drain region 4, which is consistent with the present disclosure. Figure 1 Compared to the structure shown, Figure 2 The structure shown in FIG. 1 is overetched to the inside of the N-type drift layer 3, so that the drain conductive layer 5 is directly in contact with the lower-doped N-type drift layer 3. Therefore, when the body diode of the device is turned on, the hole concentration stored in the N-type drift layer 3 is lower than that in the N-type drift layer 3. Figure 1 The structure shown can be lowered further to reduce the reverse recovery charge during the reverse recovery process.

[0072] It should be noted that Figure 2 The structure shown and Figure 1 Compared with the structure shown in FIG. 1 , except that when etching the N+ substrate 1 and the N-type buffer layer, the N-type drift layer 3 is overetched to form a groove U3, the rest of the structure is the same. For details, please refer to the above description of FIG. Figure 1 Description of the structure shown.

[0073] In some embodiments, in the above-mentioned metal oxide semiconductor field effect transistor provided in the embodiments of the present disclosure, as Figure 3As shown, the N-type low-doped semiconductor layer 2 and the N-type drift layer 3 can be an integrated structure, that is, the N-type drift layer 3 is directly epitaxially formed on one side of the N+ substrate 1, and when the N+ substrate 1 is etched, the second groove U2 is formed inside the N-type drift layer 3, and then ion implantation is performed on the side of the N-type drift layer 3 exposed at the position of the second groove U2 close to the N+ substrate 1 to form an N+ drain region 4, that is, Figure 3 The structure shown is Figure 1 Compared to the structure shown, Figure 3 The structure shown in FIG. 1 removes the N-type buffer layer, which can reduce one epitaxy. Moreover, since the drain conductive layer 5 is directly in contact with the lower-doped N-type drift layer 3, the hole concentration stored in the N-type drift layer 3 when the body diode of the device is turned on is lower than that in FIG. 1 . Figure 1 The structure shown can be lowered further to reduce the reverse recovery charge during the reverse recovery process.

[0074] It should be noted that Figure 3 The structure shown and Figure 1 Compared with the structure shown in FIG. 1 , except for removing the N-type buffer layer and directly etching the N+ substrate 1 to form the second trench U2 inside the N-type drift layer 3, the rest of the structure is the same. For details, please refer to the above description of FIG. Figure 1 Description of the structure shown.

[0075] In some embodiments, the material of the N+ substrate in the present disclosure can be single crystal silicon, silicon carbide or gallium nitride, that is, the metal oxide semiconductor field effect transistor provided in the embodiment of the present disclosure can be based on semiconductor materials such as single crystal silicon, silicon carbide or gallium nitride, and can be prepared through processes such as epitaxy and ion implantation.

[0076] In some embodiments, in the above-mentioned metal oxide semiconductor field effect transistor provided in the embodiments of the present disclosure, as Figure 1-Figure 3 As shown, the gate structure and the source conductive layer 12 can be called the front structure of the metal oxide semiconductor field effect transistor, and the drain conductive layer 5 can be called the back structure of the metal oxide semiconductor field effect transistor. The front structure of the device and the drain conductive layer 5 may not be in a one-to-one correspondence. For example, one drain conductive layer 5 may correspond to multiple repeated front structures.

[0077] It should be noted that the thickness of each region, the type of doped ions, and the ion doping concentration in the metal oxide semiconductor field effect transistor provided in the embodiment of the present disclosure can be designed as needed.

[0078] Based on the same inventive concept, an embodiment of the present disclosure provides a method for preparing the above-mentioned metal oxide semiconductor field effect transistor. Since the principle of solving the problem by the preparation method is similar to the principle of solving the problem by the above-mentioned metal oxide semiconductor field effect transistor, the implementation of the preparation method provided by the embodiment of the present disclosure can refer to the implementation of the above-mentioned metal oxide semiconductor field effect transistor provided by the embodiment of the present disclosure, and the repeated parts will not be repeated.

[0079] In some embodiments, the method for preparing the metal oxide semiconductor field effect transistor provided in the embodiments of the present disclosure is as follows: Figure 6 As shown, this may include:

[0080] S601, epitaxially forming an N-type low-doped semiconductor layer and an N-type drift layer on one side of an N+ substrate;

[0081] S602, etching the N+ substrate and the N-type low-doped semiconductor layer to form a first trench penetrating the N+ substrate and a second trench penetrating the N-type low-doped semiconductor layer to expose the N-type drift layer;

[0082] S603, injecting N-type impurities into the exposed N-type drift layer on a side close to the N+ substrate to form an N+ drain region;

[0083] S604 , forming a drain conductive layer on a side of the N+ substrate away from the N-type drift layer, wherein the drain conductive layer fills the first trench and the second trench until it contacts the N+ drain region.

[0084] The method for preparing the above-mentioned metal oxide semiconductor field effect transistor provided in the embodiment of the present disclosure is to expose the N-type drift layer by digging grooves in the N+ substrate and the N-type low-doped semiconductor layer, and then ion-implant high-concentration N-type impurities into the exposed N-type drift layer to form an N+ drain region, and then form a drain conductive layer on the side of the N+ substrate away from the N-type drift layer. Through this method, the resistance of the N+ substrate can be completely eliminated, and the thicker N+ substrate is still maintained to maintain the mechanical strength of the wafer. At the same time, the contact between the drain conductive layer and the lower-doped N-type low-doped semiconductor layer is conducive to the extraction of holes from here when the body diode of the device is turned on, reducing the hole density in the N-type drift layer and reducing the reverse recovery charge.

[0085] In some embodiments, in the above-mentioned preparation method provided by the embodiment of the present disclosure, after performing step S601 to epitaxially form an N-type low-doped semiconductor layer and an N-type drift layer on one side of the N+ substrate, and before performing step S602 to etch the N+ substrate and the N-type low-doped semiconductor layer, as shown in FIG. Figure 7 As shown, it also includes: S701, forming a P-type well region, an N+ source region and a P+ source region by injecting corresponding N-type or P-type impurities on a side of the N-type drift layer away from the N+ substrate;

[0086] After performing step S603 to implant N-type impurities into the exposed N-type drift layer near the N+ substrate to form an N+ drain region, and before performing step S604 to form a drain conductive layer on the side of the N+ substrate away from the N-type drift layer, Figure 7 As shown, it also includes:

[0087] S702, forming a gate dielectric layer on a side of the N-type drift layer away from the N+ substrate;

[0088] S703, forming a gate conductive layer on a side of the gate dielectric layer away from the N+ substrate;

[0089] S704, forming an isolation dielectric layer on a side of the gate conductive layer away from the N+ substrate;

[0090] S705 , forming a source conductive layer on a side of the isolation dielectric layer, the N+ source region, and the P+ source region away from the N+ substrate.

[0091] In order to better understand the above preparation method provided in the embodiments of the present disclosure, Figure 1 Taking the metal oxide semiconductor field effect transistor shown in the figure as an example, the preparation process of the metal oxide semiconductor field effect transistor is described in detail.

[0092] In some embodiments, Figure 1 The preparation process of the metal oxide semiconductor field effect transistor may specifically include the following steps:

[0093] (1) Fig. 8A As shown, an N+ substrate 1 is provided, and an N-type low-doped semiconductor layer 2 (ie, an N-type buffer layer) and an N-type drift layer 3 are epitaxially formed on one side of the N+ substrate 1 .

[0094] (2) Figure 8B As shown, a P-type well region 6, an N+ source region 7 and a P+ source region 8 are formed on a side of the N-type drift layer 3 away from the N+ substrate 1 by injecting corresponding N-type or P-type impurities.

[0095] (3) Figure 8C As shown, a hard mask 20 is formed on a side of the N+ substrate 1 away from the N-type drift layer 3, and then selective etching is performed. The N+ substrate 1 and the N-type low-doped semiconductor layer 2 (i.e., the N-type buffer layer) are etched using dry etching, and the etching is stopped at the interface between the N-type low-doped semiconductor layer 2 (i.e., the N-type buffer layer) and the N-type drift layer 3 to form a first trench U1 penetrating the N+ substrate 1 and a second trench U2 penetrating the N-type buffer layer 2 to expose the N-type drift layer 3.

[0096] (4) Fig.8DAs shown, the hard mask state is maintained, and N-type impurities (as shown by arrows) are implanted into the exposed N-type drift layer 3 near the N+ substrate 1 to form an N+ drain region 4. Subsequently, the hard mask 20 is stripped off. Then, annealing is performed to activate the implanted ions and repair lattice damage.

[0097] (5) Fig. 8E As shown, a gate dielectric layer 9 is formed on the side of the N-type drift layer 3 away from the N+ substrate 1, a gate conductive layer 10 is formed on the side of the gate dielectric layer 9 away from the N+ substrate 1, an isolation dielectric layer 11 is formed on the side of the gate conductive layer 10 away from the N+ substrate 1, and a source conductive layer 12 is formed on the side of the isolation dielectric 11, the N+ source region 7 and the P+ source region 8 away from the N+ substrate 1.

[0098] (6) Figure 1 As shown, a drain conductive layer 5 is formed on a layer of the N+ substrate 1 away from the N-type drift layer 3 by sputtering, and the drain conductive layer 5 fills the first trench U1 and the second trench U2 until it contacts the N+ drain region 4 .

[0099] Through the above steps (1)-(6), Figure 1 The metal oxide semiconductor field effect transistor is shown.

[0100] Need to explain yes, Figure 2 The preparation method of the metal oxide semiconductor field effect transistor shown in Figure 1 The preparation methods of the structures shown are basically the same, except that: Figure 2 When the structure shown in the figure is formed, in executing the above step (3), when etching the N+ substrate 1 and the N-type low-doped semiconductor layer 2 to form a first trench U1 penetrating the N+ substrate 1 and a second trench U2 penetrating the N-type low-doped semiconductor layer 2, the groove U3 is formed by over-etching to the inside of the N-type drift layer 3.

[0101] Need to explain yes, Figure 3 The preparation method of the metal oxide semiconductor field effect transistor shown in Figure 1 The preparation methods of the structures shown are basically the same, except that: Figure 3 In the structure shown, when performing the above step (1), the N-type drift layer 3 is epitaxially formed only on one side of the N+ substrate 1, and when performing the above step (3), the N-type drift layer 3 is also etched when etching the N+ substrate 1 to form the second trench U2.

[0102] It should be noted that in the above-mentioned preparation method provided in the embodiment of the present disclosure, the patterning process involved in forming each layer structure may include not only part or all of the process such as deposition, photoresist coating, mask masking, exposure, development, etching, photoresist stripping, etc., but also other process, which is subject to the graphics of the required composition formed in the actual production process, and is not limited here. For example, a post-baking process may also be included after development and before etching. Among them, the deposition process may be chemical vapor deposition, plasma enhanced chemical vapor deposition or physical vapor deposition, which is not limited here; the mask used in the mask process may be a half-tone mask (Half Tone Mask), a single slit diffraction mask (Single Slit Mask) or a gray tone mask (Gray Tone Mask), which is not limited here; etching may be dry etching or wet etching, which is not limited here.

[0103] Based on the same inventive concept, an embodiment of the present disclosure provides an electronic device, including the metal oxide semiconductor field effect transistor provided in the embodiment of the present disclosure. Since the principle of solving the problem by the electronic device is similar to the principle of solving the problem by the metal oxide semiconductor field effect transistor, the implementation of the electronic device provided in the embodiment of the present disclosure can refer to the implementation of the metal oxide semiconductor field effect transistor provided in the embodiment of the present disclosure, and the repeated parts will not be repeated.

[0104] In some embodiments, the electronic devices provided by the embodiments of the present disclosure may include, but are not limited to: radio frequency amplifiers, mixers, radars, satellites, power supplies, automotive electronics, energy-saving lamps, household appliances, etc. Of course, in addition to metal oxide semiconductor field effect transistors, the electronic devices provided by the present disclosure may also include other structures, for example, when the electronic device is a radar, it also includes: transmitters, antennas, receivers, etc.; when the electronic device is a mixer, it also includes: input ports, output ports, etc.

[0105] The embodiment of the present disclosure provides a metal oxide semiconductor field effect transistor, a preparation method thereof, and an electronic device. Since grooves are dug in both the N+ substrate and the N-type low-doped semiconductor layer, the N-type drift layer can be exposed. By forming an N+ drain region doped with high concentration N-type impurities on the side of the exposed N-type drift layer close to the N+ substrate, the N+ drain region can reduce the on-resistance and improve the withstand voltage performance, and the drain conductive layer fills the groove, so that the drain conductive layer is in contact with the side of the N+ substrate at the first groove position, the side of the N-type low-doped semiconductor layer at the second groove position, and the side of the N+ drain region close to the N+ substrate. Therefore, the metal oxide semiconductor field effect transistor provided by the present disclosure can greatly reduce the resistance of the N+ substrate, and there is no need to thin the N+ substrate, and a relatively thick N+ substrate can still be maintained. Compared with the method of thinning the N+ substrate in the prior art, the present disclosure reduces the risk of fragmentation and can maintain the mechanical strength of the wafer. At the same time, the drain conductive layer disclosed in the present invention is directly in contact with the N-type low-doped semiconductor layer, which is beneficial for holes to be extracted from the contact surface between the drain conductive layer and the N-type low-doped semiconductor layer when the body diode of the metal oxide semiconductor field effect transistor is turned on, thereby reducing the hole density in the N-type drift layer, and is beneficial for reducing the reverse recovery charge of the metal oxide semiconductor field effect transistor and reducing the reverse recovery current.

[0106] Although the preferred embodiments of the present disclosure have been described, those skilled in the art may make additional changes and modifications to these embodiments once they have learned the basic creative concept. Therefore, the appended claims are intended to be interpreted as including the preferred embodiments and all changes and modifications falling within the scope of the present disclosure.

[0107] Obviously, those skilled in the art can make various changes and modifications to the present disclosure without departing from the spirit and scope of the present disclosure. Thus, if these modifications and variations of the present disclosure fall within the scope of the claims of the present disclosure and their equivalents, the present disclosure is also intended to include these modifications and variations.

Claims

1. A metal oxide semiconductor field effect transistor, characterized in that: include: An N+ substrate including a first trench extending through a thickness thereof; An N-type low-doped semiconductor layer, located on one side of the N+ substrate, the N-type low-doped semiconductor layer comprising a second trench running through the thickness thereof, the first trench and the second trench overlapping; An N-type drift layer, located on a side of the N-type low-doped semiconductor layer away from the N+ substrate; An N+ drain region, located in the N-type drift layer and on a side of the N-type drift layer close to the N+ substrate, the N+ drain region covering the second trench; The drain conductive layer covers the side of the N+ substrate away from the N-type drift layer and fills the first trench and the second trench until they are in contact with the N+ drain region.

2. The metal oxide semiconductor field effect transistor according to claim 1, characterized in that The N+ drain region also covers a portion of the N-type low-doped semiconductor layer.

3. The metal oxide semiconductor field effect transistor according to claim 2, characterized in that: The N-type low-doped semiconductor layer is an N-type buffer layer.

4. The metal oxide semiconductor field effect transistor according to claim 3, characterized in that: A side of the N+ drain region close to the N+ substrate contacts a side of the N-type buffer layer away from the N+ substrate.

5. The metal oxide semiconductor field effect transistor according to claim 3, characterized in that: The N-type drift layer has a groove that runs through part of its thickness on a side close to the N+ substrate and corresponding to the second trench. The groove overlaps with the second trench. The N-type drift layer is provided between the N+ drain region and the N-type buffer layer.

6. The metal oxide semiconductor field effect transistor according to claim 2, characterized in that: The N-type low-doped semiconductor layer and the N-type drift layer are an integrated structure.

7. The metal oxide semiconductor field effect transistor according to any one of claims 1 to 6, characterized in that: Also includes: Two P-type well regions located in the N-type drift layer and close to the side of the N-type drift layer away from the N+ substrate, and an N+ source region and a P+ source region located in the P-type well region and close to the side of the N-type drift layer away from the N+ substrate; wherein the N+ source region and the P+ source region are arranged laterally and contact each other, and the P+ source region is arranged close to the side of the N-type drift layer, and the P-type well region covers the side of the P+ source region and the N+ source region close to the N+ substrate and covers the side of the N+ source region away from the P+ source region; It also includes: a gate dielectric layer located on a side of the N-type drift layer away from the N+ substrate, a gate conductive layer located on a side of the gate dielectric layer away from the N+ substrate, and an isolation dielectric layer located on a side of the gate conductive layer away from the N+ substrate; wherein the gate dielectric layer contacts the N-type drift layer, the P-type well region and the N+ source region, and the isolation dielectric layer wraps the gate conductive layer and contacts the gate dielectric layer; It also includes a source conductive layer located on the side of the isolation dielectric layer, the N+ source region and the P+ source region away from the N+ substrate, and the source conductive layer wraps the isolation dielectric layer and contacts the N+ source region and the P+ source region.

8. A method for preparing a metal oxide semiconductor field effect transistor, characterized in that: For preparing the metal oxide semiconductor field effect transistor according to any one of claims 1 to 7, the preparation method comprising: Epitaxially forming an N-type low-doped semiconductor layer and an N-type drift layer on one side of the N+ substrate; Etching the N+ substrate and the N-type low-doped semiconductor layer to form a first trench penetrating the thickness of the N+ substrate and a second trench penetrating the thickness of the N-type low-doped semiconductor layer to expose the N-type drift layer; Implanting N-type impurities into the exposed side of the N-type drift layer close to the N+ substrate to form an N+ drain region; A drain conductive layer is formed on a side of the N+ substrate away from the N-type drift layer, and the drain conductive layer fills the first trench and the second trench until it contacts the N+ drain region.

9. The preparation method according to claim 8, characterized in that: When the N+ substrate and the N-type low-doped semiconductor layer are etched to form a first trench penetrating the thickness of the N+ substrate and a second trench penetrating the thickness of the N-type low-doped semiconductor layer, the method further includes: A groove is formed by over-etching into the inside of the N-type drift layer.

10. The preparation method according to claim 8, characterized in that: After epitaxially forming an N-type low-doped semiconductor layer and an N-type drift layer on one side of the N+ substrate, and before etching the N+ substrate and the N-type low-doped semiconductor layer, the method further comprises: forming a P-type well region, an N+ source region and a P+ source region on a side of the N-type drift layer away from the N+ substrate by injecting corresponding N-type or P-type impurities; After N-type impurities are implanted into the exposed N-type drift layer on a side close to the N+ substrate to form an N+ drain region, and before a drain conductive layer is formed on a side of the N+ substrate away from the N-type drift layer, the method further includes: forming a gate dielectric layer on a side of the N-type drift layer away from the N+ substrate; forming a gate conductive layer on a side of the gate dielectric layer away from the N+ substrate; forming an isolation dielectric layer on a side of the gate conductive layer away from the N+ substrate; A source conductive layer is formed on a side of the isolation dielectric layer, the N+ source region and the P+ source region away from the N+ substrate.

11. An electronic device, characterized in that: Comprising the metal oxide semiconductor field effect transistor as described in any one of claims 1 to 7.

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