Semiconductor device, manufacturing method thereof and static random access memory unit

Abstract

The semiconductor device includes a semiconductor substrate, a gate structure on the semiconductor substrate, first and second source / drain regions, and first and second locally doped regions. First and second source / drain regions are in the semiconductor substrate. The first and second locally doped regions are located in the semiconductor substrate between the gate structure and the first and second source / drain regions, respectively. The conductive types of the first and second locally doped regions are different from those of the first and second source / drain regions. And the doping concentration of the first local doping region is greater than that of the second local doping region. Asymmetric gate and source threshold voltages are caused by the asymmetric local doped regions, and the difference between forward current and reverse current of the transistor is achieved. This design may increase read margins and write margins of the memory cells.

Description

Technical Field

[0001] The invention relates to a semiconductor device and a manufacturing method thereof and a static random access memory unit. Background Art

[0002] The semiconductor integrated circuit (IC) industry has experienced rapid growth. Technological advances in integrated circuit materials and design have produced several generations of integrated circuits, each generation of which is smaller and more complex than the previous generation. Static Random Access Memory (SRAM) is commonly used in integrated circuits. SRAM cells have the advantageous feature of retaining data without the need for refresh. As the demand for speed in integrated circuits increases, the read and write speeds of SRAM cells become more important. Summary of the invention

[0003] According to some embodiments of the present invention, a method for manufacturing a semiconductor device is provided, comprising forming a gate structure on a semiconductor substrate, the gate structure having a first side and a second side opposite to each other; forming a first mask, wherein the first mask covers the second side of the gate structure but does not cover the first side of the gate structure; using the first mask, performing a first ion implantation process to form a first local doped region in the semiconductor substrate adjacent to the first side of the gate structure, wherein the first local doped region has a first conductivity type; forming a second mask, wherein the second mask exposes the first side and the second side of the gate structure; using the second mask, performing a second ion implantation process to form a second local doped region in the semiconductor substrate adjacent to the second side of the gate structure and increase the doping concentration of the first local doped region, wherein the second local doped region has the first conductivity type; and after forming the second local doped region, forming source / drain regions in the semiconductor substrate on the first side and the second side of the gate structure, respectively, wherein the source / drain regions have a second conductivity type different from the first conductivity type.

[0004] According to some embodiments of the present invention, a semiconductor device includes a semiconductor substrate, a gate structure, a first source / drain region, a second source / drain region, a first local doping region, and a second local doping region. The gate structure is located on the semiconductor substrate. The first source / drain region and the second source / drain region are located in the semiconductor substrate. The first local doping region is located in the semiconductor substrate between the gate structure and the first source / drain region. The second local doping region is located in the semiconductor substrate between the gate structure and the second source / drain region, wherein the first local doping region and the second local doping region have a first conductivity type, the first source / drain region and the second source / drain region have a second conductivity type, which is different from the first conductivity type, and the doping concentration of the first local doping region is greater than the doping concentration of the second local doping region.

[0005] According to some embodiments of the present invention, a static random access memory cell includes a first pull-up transistor and a first pull-down transistor, a second pull-up transistor and a second pull-down transistor, a first channel gate transistor and a second channel gate transistor. The first pull-up transistor and the first pull-down transistor are coupled to each other to form a first inverter. The second pull-up transistor and the second pull-down transistor are coupled to each other to form a second inverter, wherein the first inverter and the second inverter are coupled to each other. The first channel gate transistor is coupled between the first inverter, the second inverter and the first bit line. The second channel gate transistor is coupled between the first inverter, the second inverter and the second bit line. Each of the first channel gate transistor and the second channel gate transistor includes a channel gate structure, a first source / drain region and a second source / drain region, a first local doping region and a second local doping region. The first local doping region is located between the channel gate structure and the first source / drain region. The second local doping region is located between the channel gate structure and the second source / drain region. The first local doping region and the second local doping region have a first conductivity type, the first source / drain region and the second source / drain region have a second conductivity type different from the first conductivity type, and the doping concentration of the first local doping region is greater than the doping concentration of the second local doping region. BRIEF DESCRIPTION OF THE DRAWINGS

[0006] Figure 1 Schematic cross-sectional view of a semiconductor device according to some embodiments of the present invention.

[0007] Figure 2 is a graph of current versus voltage for a semiconductor device according to some embodiments of the present invention.

[0008] Figure 3 is a circuit diagram of a static random access memory cell according to some embodiments of the present invention.

[0009] Figure 4is a graph of a Read Static Noise Margin (RSNM) of a memory cell according to some embodiments of the present invention.

[0010] Figure 5 is a graph of a Write Static Noise Margin (WSNM) of a memory cell according to some embodiments of the present invention.

[0011] FIG. 6A to FIG. 10 According to some embodiments of the present invention, the manufacturing method comprises Figure 3 Schematic diagram of the various stages of an integrated circuit of a static random access memory cell. DETAILED DESCRIPTION

[0012] The following disclosure provides many different embodiments or illustrations to implement the different features of the invention objectives provided. The specific examples of components and arrangements described below are intended to simplify the invention. These are of course only for illustration and are not intended to be limiting.

[0013] Furthermore, spatially relative terms, such as “beneath,” “below,” “lower,” “above,” “upper,” etc., are used to easily describe the relationship between elements or features shown in the drawings and other elements or features.

[0014] As used herein, "approximately," "about," "approximately," or "substantially" may mean within 20%, within 10%, or within 5% of a given value or range. However, those skilled in the art will recognize that the values ​​or ranges listed throughout the description are merely examples and may decrease as integrated circuits shrink.

[0015] Figure 1 1 is a cross-sectional schematic diagram of a semiconductor device PG according to some embodiments of the present invention. The semiconductor device PG is also called a pass-gate transistor and is used in a static random access memory cell. The semiconductor device PG includes a semiconductor substrate 110, a gate structure GS, source / drain regions 200S, 200D, and local doped regions 173', 174. In some embodiments, the semiconductor device PG may be an n-type transistor or a p-type transistor.

[0016] The gate structure GS is located on the channel region 110C of the semiconductor substrate 110. The gate structure GS may include a gate dielectric 132, a gate electrode 142, and a hard mask 152. The gate dielectric 132 may include a suitable dielectric material, such as silicon dioxide. The gate electrode 142 may include a suitable conductive material, such as polysilicon. The hard mask 152 may include a suitable dielectric material, such as silicon nitride, silicon carbide, etc.

[0017] The source / drain regions 200S and 200D are located in the semiconductor substrate 110 and are located on two opposite sides of the gate structure GS. For the n-type semiconductor device PG, the source / drain regions 200S and 200D may be doped with n-type dopants, such as phosphorus (P), arsenic (As), tellurium (Te), etc. In some embodiments, the doping concentrations of the source / drain regions 200S and 200D are substantially the same, and they may serve as the source region and the drain region of the transistor, or as the drain region and the source region, respectively.

[0018] The local doped regions 173', 174 may also be referred to as halo regions, which are counter-doped relative to the source / drain regions 200S, 200D. The local doped region 173' is located in the semiconductor substrate 110 between the gate structure GS and the source / drain region 200S, and is located between the channel region 110C and the source / drain region 200S. The local doped region 174 is located in the semiconductor substrate 110 between the gate structure GS and the source / drain region 200D, and is located between the channel region 110C and the source / drain region 200D. For the n-type semiconductor device PG, the local doped regions 173' and 174 may be doped with p-type dopants, such as boron (B), aluminum (Al), gallium (Ga), etc. In some embodiments, the doping concentration (e.g., p-type dopant concentration) of the local doped region 173' is greater than the doping concentration (e.g., p-type dopant concentration) of the local doped region 174. This doping concentration difference can regulate the forward current I of the semiconductor device PG. Forward and reverse current I Reverse , where the forward current I Forward Flowing from the source / drain region 200D to the source / drain region 200S, the reverse current I Reverse Flows from the source / drain region 200S to the source / drain region 200D.

[0019] In other embodiments, when the semiconductor device PG is a p-type transistor, the source / drain regions 200S and 200D may be doped with p-type dopants, the local doping regions 173' and 174 may be doped with n-type dopants, and the doping concentration of the local doping region 173' (e.g., the n-type dopant concentration) is greater than the doping concentration of the local doping region 174 (e.g., the n-type dopant concentration).

[0020] The semiconductor device PG further includes a lightly doped region 180 , a metal silicide layer SL, gate spacers 160 , 190 , a metal contact CT, etc. An interlayer dielectric layer 290 may surround the semiconductor device PG. These elements will be described in detail later.

[0021] Figure 2 is a current-to-voltage curve diagram of a semiconductor device PG according to some embodiments of the present invention. Figure 2 In FIG. 1 , the horizontal axis is the drain-source current (Ids), and the vertical axis is the gate-source voltage (Vgs). By controlling the difference in doping concentrations of the local doping regions 173 ′ and 174 , the forward current I of the semiconductor device PG is regulated. Forward and the reverse current I Reverse , which can make the forward current I Forward Greater than the reverse current I Reverse .

[0022] Figure 3 1 is a circuit diagram of a static random access memory cell SC according to some embodiments of the present invention. The static random access memory cell SC includes a pull-up transistor PU1, a pull-down transistor PD1, a pull-up transistor PU2, a pull-down transistor PD2, a pass gate transistor PG1, and a pass gate transistor PG2. Figure 3 Also shown in the figure is a working voltage Vdd and a low voltage Vss, where the low voltage Vss is, for example, a ground voltage or 0V.

[0023] The pull-up transistor PU1 and the pull-down transistor PD1 are coupled to each other to form a first inverter INV1. The pull-up transistor PU2 and the pull-down transistor PD2 are coupled to each other to form a second inverter INV2, wherein the first inverter INV1 and the second inverter INV2 are coupled to each other. For example, the output end of the first inverter INV1 is connected to the input end of the second inverter INV2, which is marked as terminal N2; the input end of the first inverter INV1 is connected to the output end of the second inverter INV2, which is marked as terminal N1.

[0024] The pass-gate transistor PG1 is coupled between the first inverter INV1, the second inverter INV2 and the bit line BL1. The pass-gate transistor PG2 is coupled between the first inverter INV1, the second inverter INV2 and the bit line BL2. Specifically, a source / drain terminal of the pass-gate transistor PG1 is connected to the output terminal of the first inverter INV1 and the input terminal of the second inverter INV2 (this connection point is marked as terminal N2), and the other source / drain terminal is connected to the bit line BL1. Specifically, a source / drain terminal of the pass-gate transistor PG2 is connected to the input terminal of the first inverter INV1 and the output terminal of the second inverter INV2 (this connection point is marked as terminal N1), and the other source / drain terminal is connected to the bit line BL2. The control terminals (i.e., gate terminals) of the pass-gate transistors PG1 and PG2 are connected to the word line WL.

[0025] Here, the structure of each of the pass gate transistors PG1 and PG2 may be as follows: Figure 1 Thus, different gate-source threshold voltages (V t ). As shown in the figure, a local doping region 174 with a smaller concentration is provided on the side of the channel gate transistor PG1 adjacent to the bit line BL1 and the side of the channel gate transistor PG2 adjacent to the bit line BL2 to provide a lower gate-source threshold voltage; a local doping region 173' with a larger concentration is provided on the other side of the channel gate transistor PG1 away from the bit line BL1 (or called the side adjacent to the first inverter INV1 and the second inverter INV2) and the other side of the channel gate transistor PG2 away from the bit line BL2 (or called the side adjacent to the first inverter INV1 and the second inverter INV2) to provide a higher gate-source threshold voltage. Thereby, the asymmetric local doping region causes an asymmetric gate-source threshold voltage, which in turn causes the forward current I Forward and the reverse current I Reverse difference.

[0026] Figure 4 1 is a graph showing a read static noise margin (RSNM) of a memory cell SC according to some embodiments of the present invention. Figure 4 In FIG. 1 , the dotted line indicates that the memory cell uses a channel gate transistor with a symmetrical local doping region, and the solid line indicates that the memory cell uses a channel gate transistor with an asymmetrical local doping region. Figure 4 and Figure 3 . Figure 4 In the figure, the horizontal axis represents the potential of the terminal N1 (marked as V N1 ), the vertical axis represents the potential of the terminal N2 (marked as V N2 ). Also refer to Figure 3 and Figure 4 . In the read state, the word line WL will become high to turn on the pass gate transistor PG1, and then the data in the device will be sensed on the bit line BL1. The read static noise margin refers to the maximum DC noise voltage that can be tolerated during the read operation without changing the stored data. When reading, the bit line BL1 will be pre-charged to the operating voltage Vdd, which will result in voltage division at the endpoints N1 and N2 where the data stored is 1, and there will be a problem of noise tolerance.

[0027] In various embodiments of the present invention, the read margin RB' of a memory cell using a channel gate transistor with an asymmetric local doping region is greater than the read margin RB of a memory cell using a channel gate transistor with a symmetric local doping region. It can be seen that the use of an asymmetric local doping region can increase the read margin of the memory cell SC, which can further improve noise tolerance.

[0028] Figure 5 1 is a graph showing a Write Static Noise Margin (WSNM) curve of a memory cell SC according to some embodiments of the present invention. Figure 5 In FIG. 1 , the dotted line indicates that the memory cell uses a channel gate transistor with a symmetrical local doping region, and the solid line indicates that the memory cell uses a channel gate transistor with an asymmetrical local doping region. Figure 5 and Figure 3 . Figure 5 In the figure, the horizontal axis represents the potential of the word line WL (marked as V WL ), the vertical axis represents the potential of the terminal N1 (marked as V N1 In the write state, the voltage level of the bit line BL2 is set to 0V, and the word line WL is changed to a high potential to turn on the pass gate transistor PG2, and the voltage of the storage terminal N1 will drop to 0V (for example, from the working voltage Vdd).

[0029] In various embodiments of the present invention, the write margin WB' of the channel gate transistor using the asymmetric local doping region of the memory cell is greater than the write margin WB of the channel gate transistor using the symmetric local doping region of the memory cell. It can be seen that the use of asymmetric local doping regions can increase the write margin of the memory cell SC.

[0030] Depend on Figure 4 and Figure 5 It can be found that the use of asymmetric local doping regions can increase the read margin and write margin of the memory cell SC without sacrificing chip area. In particular, when the voltage of the access circuit is low, the memory cell margin can be significantly improved without increasing the area of ​​the memory cell SC or design assistance.

[0031] FIG. 6A to FIG. 10 According to some embodiments of the present invention, the manufacturing method comprises Figure 3 Schematic diagram of the various stages of an integrated circuit of a static random access memory cell SC.

[0032] It may include a plurality of memory cells SC arranged repeatedly (see Figure 3), where the range of a memory cell SC is defined by a memory cell boundary SCB. Fig. 6A and Fig. 7A It can be seen as a top view schematic diagram of the manufacturing of an integrated circuit at various stages. Figure 6B , Figure 7B , Figure 8 , Fig. 9 , Fig.10 is a cross-sectional diagram of the various stages of integrated circuit manufacturing, including Fig. 6A , Fig. 7A The areas R_PD and R_PG along the line B1-B1 and the area R_PU along the line B2-B2.

[0033] In the schematic diagram above ( Fig. 6A , Fig. 7A ), pull-down transistors PD1, PD2, pass-gate transistors PG1, PG2, and pull-up transistors PU1, PU2 are disposed within the memory cell boundary SCB. For ease of explanation, in each cross-sectional diagram of this document, regions R_PD, R_PG, and R_PU represent regions where pull-down transistors PD1, PD2, pass-gate transistors PG1, PG2, and pull-up transistors PU1, PU2 are located, respectively.

[0034] First, refer to FIG. 6A to FIG. 6B A semiconductor substrate 110 is provided, which may include various elemental semiconductors, such as silicon and germanium; or compound semiconductors, such as silicon germanium. An isolation structure 120 is formed on the semiconductor substrate 110 to surround the active region 110A to define multiple boundaries of the active region 110A.

[0035] The active region 110A may have an appropriate width according to the transistor to be formed. For example, as shown in the figure, the width of the active region 110A of the pull-down transistors PD1 and PD2 (reference region R_PD) is greater than the width of the active region 110A of the pass-gate transistors PG1 and PG2 (reference region R_PG), and the width of the active region 110A of the pass-gate transistors PG1 and PG2 (reference region R_PG) is greater than the width of the active region 110A of the pull-up transistors PU1 and PU2 (reference region R_PU).

[0036] The active region 110A may be doped with an appropriate well according to the conductivity type of the transistor to be formed. Figure 3For example, the region R_PD and the region R_PG used to form the n-type transistor can be doped with a p-type dopant to have a p-type well PW, and the region R_PU used to form the p-type transistor can be doped with an n-type dopant to have an n-type well NW. The p-type dopant can be boron (Boron; B), aluminum (Aluminum; Al), gallium (Gallium; Ga), indium (Indium; In), and the n-type dopant can be phosphorus (Phosphorus; P), arsenic (Arsenic; As), antimony (Antimony; Sb). For example, the doping concentration of the wells NW and PW is about 1E15cm -3 To about 1E18cm -3 .

[0037] In some embodiments, the semiconductor substrate 110 may provide a flat active region 110A substantially flush with the upper surface of the isolation structure 120 for forming a planar field effect transistor. Alternatively, the semiconductor substrate 110 may be patterned to have an active region 110A of a specific shape, such as a fin of a fin field effect transistor (FinFET), as the active region 110A. Its upper surface may be higher than the upper surface of the isolation structure 120.

[0038] Next, a gate structure GS is formed across the active region 110A (see Figure 1 ).

[0039] Next, after forming the gate structure GS, a plurality of gate spacers 160 are formed on opposite sides S1 and S2 of the gate structure GS. The gate spacers 160 may include one or more layers. The gate spacers 160 may include one or more dielectric materials, such as silicon oxide, silicon nitride and / or silicon oxynitride.

[0040] Herein, along the gate extension direction, the gate structure can be cut into multiple independent and discontinuous gate structures to realize an integrated circuit. In this embodiment, a gate cutting process is performed on the polysilicon gate structure GS to form multiple independent and discontinuous polysilicon gate structures GS.

[0041] Next, after forming the gate spacer 160, a mask PR1 is first formed on the semiconductor substrate 110. The material of the mask PR1 can be an organic photoresist material, which is patterned by photolithography. The mask PR1 can also be called a photomask. The mask PR1 covers the pull-up transistors PU1 and PU2 (refer to the area R_PU) and exposes the pull-down transistors PD1 and PD2 (refer to the area R_PD). ​​The mask PR1 only partially covers the channel gate transistors PG1 and PG2 (refer to the area R_PG). Specifically, for the channel gate transistors PG1 and PG2 (refer to the area R_PG), the mask PR1 covers one side S2 of the gate structure GS but does not cover one side S1 of the gate structure GS. Thereafter, a first local ion implantation process is performed through the mask PR1, and the doping dose is approximately 1E12cm -2 to about 1E14 cm -2 The hard mask 152, the gate spacer 160 and the mask PR1 can serve as masks for the first local ion implantation to define the location of the local doping.

[0042] In the region R_PD, the first local ion implantation process forms first local doped regions 171 and 172 on the two sides S1 and S2 of the gate structure GS, respectively. In the region R_PG, the first local ion implantation process forms a first local doped region 173 in the semiconductor substrate 110 adjacent to the side S1 of the gate structure GS.

[0043] In some embodiments, the first local ion implantation process is a p-type doping process, and the first local doping regions 171, 172, and 173 in the regions R_PD and R_PG for forming n-type transistors are doped with p-type dopants. In some embodiments, the conductivity type of the first local doping regions 171, 172, and 173 is the same as that of the well PW. After the first local doping region 173 is formed, the mask PR1 can be removed by an appropriate removal process (e.g., ashing).

[0044] Next, refer to Fig. 7A as well as Figure 7B After removing the mask PR1, a mask PR2 is first formed on the semiconductor substrate 110. The material of the mask PR2 can be an organic photoresist material, which is patterned by photolithography. The mask PR2 can also be called a photomask. The mask PR2 covers the pull-up transistors PU1 and PU2 (refer to the area R_PU), and exposes the pull-down transistors PD1 and PD2 (area R_PD) and the channel gate transistors PG1 and PG2 (refer to the area R_PG). Specifically, for the channel gate transistors PG1 and PG2 (refer to the area R_PG), the mask PR2 does not cover the sides S1 and S2 of the gate structure GS. Thereafter, a second local ion implantation process is performed through the mask PR2, and the doping dose is approximately 1E12 cm -2to about 1E14 cm -2 In some embodiments, the doping dose of the second local ion implantation process is less than the doping dose of the first local ion implantation process. For example, the doping dose of the first local ion implantation process is 2E13 cm -2 The doping dose of the second local ion implantation process is 1E13 cm -2 In other embodiments, the doping dose of the second local ion implantation process may be greater than the doping dose of the first local ion implantation process. The hard mask 152, the gate spacer 160 and the mask PR2 may serve as masks for the second local ion implantation to limit the location of local doping.

[0045] In the region R_PD, this second local ion implantation process increases the doping concentration of the first local doping regions 171, 172 on the two sides S1 and S2 of the gate structure GS, hereinafter referred to as local doping regions 171', 172'. In the region R_PG, this second local ion implantation process increases the doping concentration of the first local doping region 173 on the side S1 of the gate structure GS, hereinafter referred to as local doping region 173', and forms a second local doping region 174 in the semiconductor substrate 110 adjacent to the side S2 of the gate structure GS. The local doping regions 171', 172' and 173' have undergone secondary local doping and have a higher concentration than the second local doping region 174. For example, the doping concentration of the well PW is approximately 1E15cm -3 To about 1E18cm -3 In the range of 1.5, the doping concentration of the local doping regions 171', 172', 173', 174 is about 1E17 cm -3 to about 1E19 cm -3 The doping concentration of the local doping regions 171', 172', 173' is greater than the doping concentration of the local doping region 174. In some embodiments, the doping concentrations of the local doping regions 171', 172', 173' may be substantially the same.

[0046] In some embodiments, the second local ion implantation process is a p-type doping process, and in the region R_PD and the region R_PG for forming the n-type transistor, the local doping regions 171', 172', 173' and the second local doping region 174 are doped with p-type dopants. In some embodiments, the conductivity type of the local doping regions 171', 172', 173' and the second local doping region 174 is the same as the well PW.

[0047] Next, refer to Figure 7B, on the semiconductor substrate 110, a lightly doped ion implantation process is performed using the same mask PR2 to form source / drain lightly doped regions 180, also referred to as source / drain extension regions (S / D extension regions), on the sides S1 and S2 of the gate structure GS, respectively. For example, in order to form an n-type transistor, n-type dopants may be implanted into the semiconductor substrate 110 through an appropriate ion implantation process to form source / drain lightly doped regions 180. The hard mask 152, the gate spacer 160, and the mask PR2 may serve as masks for ion implantation to limit the location of the source / drain lightly doped regions 180. For example, the doping concentration of the source / drain lightly doped regions 180 is approximately 1E19 cm -3 To about 1E21cm -3 In some embodiments, the doping concentrations of the plurality of source / drain lightly doped regions 180 may be substantially the same.

[0048] Next, refer to Figure 8 After forming the source / drain lightly doped region 180, the mask PR2 can be removed by an appropriate removal (e.g., ashing) process. Thereafter, through similar steps (e.g., photolithography process to form a mask and multiple ion implantation processes), n-type local doped regions 212 and 214 and p-type source / drain lightly doped regions 220 are formed in the region R_PU for forming a p-type transistor. Among them, the local doped regions 212 and 214 can also be called halo regions, and the source / drain lightly doped regions 220 can also be called source / drain extension regions. The doping concentrations of the local doped regions 212 and 214 can be substantially the same. Thereafter, a gate spacer 190 can be formed on both sides of the gate structure GS.

[0049] Next, the photoresist layer is patterned by photolithography to form a source / drain mask PR3, and the material of the source / drain mask PR3 can be an organic photoresist material. The source / drain mask PR3 covers the region R_PU and exposes the regions R_PD and R_PG. Then, using the source / drain mask PR3, a source / drain region 200S / 200D can be formed in the semiconductor substrate 110 by an appropriate ion implantation process. This ion implantation process can implant n-type dopants into the semiconductor substrate 110 to form the source / drain region 200S / 200D of the n-type transistor. The hard mask 152, the gate spacers 160, 190 and the source / drain mask PR3 can serve as masks for ion implantation to limit the position of the source / drain region 200S / 200D. The doping concentration of the source / drain region 200S / 200D is greater than the doping concentration of the source / drain lightly doped region 180. For example, the doping concentration of the source / drain regions 200S / 200D is about 5E19 cm -3 To about 5E21cm -3In some embodiments, the doping concentrations of the source / drain regions 200S / 200D may be substantially the same.

[0050] In various embodiments of the present invention, for the same transistor, the source / drain regions 200S, 200D and the lightly doped region 180 are doped with the same conductivity type (e.g., n-type), and the local doped regions 173' and 174 and the well PW are doped with the same other conductivity type (e.g., p-type). In other words, relative to the source / drain regions 200S, 200D and the lightly doped region 180, the local doped regions 173' and 174 and the well PW are counter-doped.

[0051] By this, FIG. 6A to FIG. 8 In the step of , multiple ion implantation processes are performed to form n-type pull-down transistors PD and n-type pass gate transistors PG in regions R_PD and R_PG. After forming the source / drain regions 200S / 200D, the source / drain mask PR3 can be removed by an appropriate removal process (eg, ashing).

[0052] Next, refer to Fig. 9 , in the region R_PU, a p-type dopant may then be implanted into the semiconductor substrate 110 by a p-type ion implantation process to form a source / drain region 240S / 240D of a p-type transistor. In some embodiments of the present invention, the source / drain region 240S / 240D may be used as the source region and drain region of the transistor, or may be used as the source region and drain region of the transistor, respectively.

[0053] In the process of forming the local doped regions 212 and 214, the source / drain lightly doped regions 220, and the source / drain regions 240S / 240D of the p-type pull-up transistor PU, the covered regions R_PD and R_PG can be appropriately masked to expose only the region R_PU so as not to affect the features within the regions R_PD and R_PG. In this embodiment, the p-type pull-up transistor PU is formed after the n-type pull-down transistor PD and the n-type channel gate transistor PG are formed. In other embodiments, this order can be reversed, and the p-type pull-up transistor PU can be formed first, and then the n-type pull-down transistor PD and the n-type channel gate transistor PG are formed.

[0054] Next, refer to Fig.10, an interlayer dielectric layer 290 is deposited on the gate structure GS. The interlayer dielectric layer 290 may include a suitable dielectric material, such as silicon dioxide. Thereafter, a metal contact CT is formed in the interlayer dielectric layer 290 to connect the source / drain region 200S / 200D or the source / drain region 240S / 240D of each transistor to the gate electrode 142. The metal contact includes a suitable conductive metal material, such as titanium, titanium nitride, tungsten, the like, or a combination thereof. Before forming the metal contact CT, a metal silicide layer SL may be formed on the source / drain region 200S / 200D and the source / drain region 240S / 240D to facilitate electrical connection between the semiconductor doped region (e.g., the source / drain region 200S / 200D or the source / drain region 240S / 240D) and the metal material (e.g., the metal contact CT).

[0055] For a plurality of semiconductor devices with static random access memory cells, the Fig. 9 After process and Fig.10 Before the process, a metal gate replacement process is performed to replace the polysilicon gate structure GS (refer to Fig.10 ) is replaced with a metal gate structure RG. The hard mask 152, the gate electrode 142 and the gate dielectric 132 are removed in sequence to leave a gate trench between the gate spacers 160, and then a high-k dielectric layer and a work function metal layer are conformally deposited in the gate trench and filled with a filling metal.

[0056] One of the advantages of the present invention is that the asymmetric local doping region is used to cause an asymmetric gate-source threshold voltage, thereby causing a difference in forward current and reverse current. When the channel gate transistor used in the memory cell adopts the asymmetric local doping region, the read margin and the write margin can be increased.

[0057]

Explanation of symbols

[0058] 110:Substrate

[0059] 110A: Active area

[0060] 110C: Channel area

[0061] 120: Isolation Structure

[0062] 132: Gate dielectric

[0063] 142: Gate electrode

[0064] 152:Hard mask

[0065] 160: Gate spacer

[0066] 171,172,173: Local doping area

[0067] 171', 172', 173': Local doping area

[0068] 174: Local doping region

[0069] 180: Lightly doped region

[0070] 190: Gate spacer

[0071] 212,214: Local doping area

[0072] 200S, 200D: Source / Drain Region

[0073] 220: Source / drain lightly doped region

[0074] 240S, 240D: Source / drain region

[0075] 290: Interlayer dielectric layer

[0076] GS: Gate Structure

[0077] S1, S2: Side

[0078] SL: Metal Silicide Layer

[0079] PR1,PR2,PR3:Mask

[0080] I Forward :Forward current

[0081] I Reverse :Reverse current

[0082] PG: Semiconductor device, pass-gate transistor

[0083] PU,PU1,PU2:Pull-up transistors

[0084] PG1,PG2: Pass-gate transistors

[0085] PD, PD1, PD2: Pull-down transistors

[0086] INV1: First inverter

[0087] INV2: Second inverter

[0088] N1: Endpoint

[0089] N2: Endpoint

[0090] BL1, BL2: bit lines

[0091] WL: Character Line

[0092] SC: Memory Cell

[0093] SCB: Cell Boundary

[0094] RB, RB': read margin

[0095] WB,WB': write margin

[0096] B1-B1: Line

[0097] B2-B2: Line

[0098] R_PD, R_PG, R_PU: Area

[0099] CT:Metal Contact

[0100] PW,NW: Well

[0101] Vdd: operating voltage

[0102] Vss: low voltage.

Claims

1. A method for manufacturing a semiconductor device, characterized in that: Include: On a semiconductor substrate, a gate structure is formed, the gate structure having a first side and a second side opposite to each other; forming a first mask, wherein the first mask covers the second side of the gate structure but does not cover the first side of the gate structure; Using the first mask, performing a first ion implantation process to form a first local doped region in the semiconductor substrate adjacent to the first side of the gate structure, wherein the first local doped region has a first conductivity type; forming a second mask, wherein the second mask exposes the first side and the second side of the gate structure; Using the second mask, performing a second ion implantation process to form a second local doped region in the semiconductor substrate adjacent to the second side of the gate structure and increase the doping concentration of the first local doped region, wherein the second local doped region has the first conductivity type; and After forming the second local doped region, source / drain regions are formed in the semiconductor substrate on the first side and the second side of the gate structure, respectively, wherein the source / drain regions have a second conductivity type different from the first conductivity type.

2. The method according to claim 1, characterized in that The first conductive type is p-type, and the second conductive type is n-type.

3. The method according to claim 1, characterized in that Also includes: Using the second mask, a third ion implantation process is performed to form a source / drain lightly doped region in the semiconductor substrate on the first side and the second side of the gate structure, respectively, wherein the source / drain lightly doped region has the second conductivity type, and the doping concentration of the source / drain lightly doped region is lower than the doping concentration of the source / drain region.

4. The method according to claim 1, characterized in that: The doping dose of the first ion implantation process is greater than the doping dose of the second ion implantation process.

5. A semiconductor device, characterized in that: Include: Semiconductor substrates; A gate structure is located on the semiconductor substrate; as well as A first source / drain region and a second source / drain region are located in the semiconductor substrate; A first local doped region is located in the semiconductor substrate between the gate structure and the first source / drain region; as well as A second local doped region is located in the semiconductor substrate between the gate structure and the second source / drain region, wherein the first local doped region and the second local doped region have a first conductivity type, the first source / drain region and the second source / drain region have a second conductivity type different from the first conductivity type, and the doping concentration of the first local doped region is greater than the doping concentration of the second local doped region.

6. The semiconductor device according to claim 5, wherein: The first conductive type is p-type, and the second conductive type is n-type.

7. The semiconductor device according to claim 5, wherein: The doping concentration of the first source / drain region and the doping concentration of the second source / drain region are substantially the same.

8. A static random access memory cell, characterized in that: Include: A first pull-up transistor and a first pull-down transistor are coupled to each other to form a first inverter; A second pull-up transistor and a second pull-down transistor are coupled to each other to form a second inverter, wherein the first inverter and the second inverter are coupled to each other; A first pass-gate transistor is coupled between the first inverter, the second inverter and the first bit line; as well as A second pass-gate transistor is coupled between the first inverter, the second inverter and the second bit line, wherein each of the first pass-gate transistor and the second pass-gate transistor comprises: Channel gate structure; a first source / drain region and a second source / drain region; A first local doped region is located between the channel gate structure and the first source / drain region; as well as A second local doped region is located between the channel gate structure and the second source / drain region, wherein the first local doped region and the second local doped region have a first conductivity type, the first source / drain region and the second source / drain region have a second conductivity type different from the first conductivity type, and the doping concentration of the first local doped region is greater than the doping concentration of the second local doped region.

9. The static random access memory cell according to claim 8, characterized in that: Each of the first pull-down transistor and the second pull-down transistor comprises: Pull-down gate structure; A third source / drain region and a fourth source / drain region, wherein the third source / drain region and the fourth source / drain region have the second conductivity type; a third local doped region located between the pull-down gate structure and the third source / drain region; and The fourth local doping region is located between the pull-down gate structure and the fourth source / drain region, wherein the third local doping region and the fourth local doping region have the first conductivity type, and the doping concentration of the third local doping region is substantially the same as the doping concentration of the fourth local doping region.

10. The static random access memory cell according to claim 8, wherein: The first conductive type is p-type, and the second conductive type is n-type.

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