Array substrate manufacturing method and low-temperature polycrystalline silicon array substrate

Abstract

The invention discloses an array substrate manufacturing method and a low-temperature polycrystalline silicon array substrate.The method comprises the steps that a polycrystalline silicon layer, a first insulating layer, a grid layer, an interlayer insulating layer and an SD layer are manufactured on a glass substrate in sequence, a plurality of TFT tube areas and a plurality of display areas are obtained, and the display areas are located between the TFT tube areas; manufacturing a first via hole and a second via hole, and respectively connecting the active region of the polycrystalline silicon layer with the SD layer and connecting the drain region with the SD layer by using the first via hole and the second via hole to obtain a source and a drain; a plurality of light holes are formed in the first insulating layer of the display area, and all the light holes are filled and leveled up through transparent photoresist. The plurality of light holes are formed in the inorganic film layer of the display area of the low-temperature polycrystalline silicon array substrate, namely the first insulating layer and the interlayer insulating layer, and then the light holes are filled and leveled up by the transparent photoresist, so that light is prevented from being reflected back to a backlight module, the light extraction efficiency is improved, and the overall transmittance of the product is improved.

Description

Technical Field

[0001] The present invention relates to the technical field of transmittance of low-temperature polysilicon displays, and in particular to an array substrate manufacturing method and a low-temperature polysilicon array substrate. Background Art

[0002] The liquid crystal panel includes a color filter substrate, a thin film transistor array substrate and a liquid crystal layer arranged between the two substrates. Its working principle is to control the rotation of the liquid crystal molecules in the liquid crystal layer by applying a driving voltage on the two glass substrates, thereby refracting the light from the backlight module to produce a picture.

[0003] Low Temperature Poly-silicon (LTPS) technology is a new generation of TFT substrate manufacturing technology. The biggest difference between it and traditional amorphous silicon (a-Si) technology is that low temperature poly-silicon displays have faster response speeds and have the advantages of high brightness, high resolution and low power consumption.

[0004] Currently, LTPS-LCD products have been widely used in the automotive field. In order to respond to the national call for energy conservation, higher requirements are placed on the transmittance of automotive LTPS-LCD products under the same backlight brightness. This has led to many LTPS-LCD products failing to meet customer requirements for transmittance and contrast, and have been unable to be mass-produced.

[0005] Commonly used methods to improve transmittance include increasing the aperture ratio, reducing the thickness of CF ink, etc. At present, the total thickness of the inorganic layer (SiNx+SiOx) in the pixel display area of ​​the TFT substrate of LTPS-LCD products is as high as about 1um, and the light output efficiency of the inorganic layer (SiNx+SiOx) itself is not very high, which seriously affects the improvement of LTPS transmittance. Summary of the invention

[0006] The inorganic layer thickness of the display area of ​​the TFT substrate of the existing low-temperature polysilicon display is relatively large, which affects the improvement of the transmittance of the display.

[0007] In view of the above problems, a method for manufacturing an array substrate and a low-temperature polycrystalline silicon array substrate are proposed. A plurality of light-transmitting holes are set on the inorganic film layer of the display area of ​​the low-temperature polycrystalline silicon array substrate, that is, on the first insulating layer and the interlayer insulating layer, and then filled with transparent photoresist to prevent light from being reflected back to the backlight module, thereby improving the light output efficiency and the overall transmittance of the product.

[0008] In a first aspect, a method for manufacturing an array substrate includes:

[0009] Step 100, obtaining a glass substrate, a polysilicon layer, a first insulating layer, a gate layer, an interlayer insulating layer and an SD layer, and sequentially manufacturing the polysilicon layer, the first insulating layer, the gate layer, the interlayer insulating layer and the SD layer on the glass substrate to obtain a plurality of TFT tube areas and a plurality of display areas, wherein the display area is located between the TFT tube areas;

[0010] Step 200, making a first via hole and a second via hole, using the first via hole and the second via hole to respectively connect the active area of ​​the polysilicon layer and the SD layer, and the drain area and the SD layer to obtain a source electrode and a drain electrode;

[0011] Step 300: making a plurality of light-transmitting holes on the first insulating layer in the display area, and filling all the light-transmitting holes with transparent photoresist.

[0012] In conjunction with the array substrate manufacturing method described in the first aspect of the present invention, in a first possible implementation manner, step 100 includes:

[0013] Step 110, forming an amorphous silicon thin film on the glass substrate;

[0014] Step 120 , scanning the amorphous silicon film by laser to convert the amorphous silicon film into a polycrystalline silicon film to obtain the polycrystalline silicon layer.

[0015] In combination with the first possible implementation of the first aspect of the present invention, in a second possible implementation, step 100 further includes:

[0016] Step 130, forming an active region in the polysilicon layer by ND ion implantation;

[0017] Step 140 : forming drain regions on the polysilicon layer adjacent to the active regions by LDD ion implantation.

[0018] In combination with the second possible implementation manner of the first aspect of the present invention, in a third possible implementation manner, step 100 further includes:

[0019] Step 150, forming the first insulating layer on the polysilicon layer;

[0020] Step 160, forming the gate layer in the first insulating layer;

[0021] Step 170, forming the interlayer insulating layer on the first insulating layer;

[0022] Step 180: fabricate the SD layer on the interlayer insulating layer.

[0023] In combination with the array substrate manufacturing method described in the first aspect of the present invention, in a fourth possible implementation manner, the array substrate manufacturing method further includes:

[0024] Step 400: Obtain a VITO layer, and manufacture the VITO layer on the interlayer insulating layer.

[0025] In combination with the fourth possible implementation manner of the first aspect of the present invention, in a fifth possible implementation manner, the array substrate manufacturing method further includes:

[0026] Step 500, obtaining a passivation layer, and manufacturing the passivation layer on the VITO layer;

[0027] Step 600: Obtain a PITO layer, and manufacture the PITO layer on the passivation layer.

[0028] In combination with the array substrate manufacturing method described in the first aspect of the present invention, in a sixth possible implementation manner, the first insulating layer is made of a composite material of SiNx material and SiOx material.

[0029] In a second aspect, a low-temperature polycrystalline silicon array substrate is provided, using the array substrate manufacturing method described in the first aspect, comprising:

[0030] A glass substrate, a polysilicon layer, a first insulating layer, a gate layer, an interlayer insulating layer, an SD layer and a plurality of light-transmitting holes;

[0031] The polysilicon layer, the first insulating layer, the gate layer, the interlayer insulating layer and the SD layer are sequentially fabricated on the glass substrate to obtain a plurality of TFT tube regions and a plurality of display regions, wherein the display region is located between the TFT tube regions;

[0032] The plurality of light-transmitting holes are formed on the first insulating layer and the interlayer insulating layer in the display area and are filled with transparent photoresist.

[0033] In conjunction with the low-temperature polysilicon array substrate described in the second aspect of the present invention, in a first possible implementation manner, the low-temperature polysilicon array substrate further includes:

[0034] a first via hole and a second via hole;

[0035] The first via hole and the second via hole are made on the polysilicon layer, and are used to overlap the active area of ​​the polysilicon layer and the SD layer, and the drain area and the SD layer, respectively, to obtain the source and the drain.

[0036] In combination with the low-temperature polysilicon array substrate described in the second aspect of the present invention, in a second possible implementation manner, the low-temperature polysilicon array substrate further includes:

[0037] VITO layer, passivation layer, PITO layer;

[0038] The VITO layer is formed on the interlayer insulating layer;

[0039] The passivation layer is formed on the VITO layer;

[0040] The PITO layer is formed on the passivation layer.

[0041] The array substrate manufacturing method and the low-temperature polysilicon array substrate in the present invention are implemented by setting a plurality of light-transmitting holes on the inorganic film layer of the display area of ​​the low-temperature polysilicon array substrate, that is, on the first insulating layer and the interlayer insulating layer, and then filling them with transparent photoresist to avoid light reflection back to the backlight module, thereby improving the light output efficiency and the overall transmittance of the product. BRIEF DESCRIPTION OF THE DRAWINGS

[0042] In order to more clearly illustrate the scheme in the present application, a brief introduction is given below to the drawings required for use in the description of the embodiments of the present application. Obviously, the drawings described below are some embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying any creative work.

[0043] Figure 1 is a flow chart of an embodiment of a method for manufacturing an array substrate of the present application;

[0044] Figure 2 yes Figure 1 A flowchart of a specific implementation of S100;

[0045] Figure 3 yes Figure 2 A flowchart of a specific implementation method after S120;

[0046] Figure 4 yes Figure 3 A flowchart of a specific implementation method after S140;

[0047] Figure 5 is a flow chart of another embodiment of a TFT substrate manufacturing method of the present application;

[0048] Figure 6 It is a structural schematic diagram of a low-temperature polysilicon array substrate in the present application. DETAILED DESCRIPTION

[0049] The following will be combined with the accompanying drawings in the invention to clearly and completely describe the technical solutions in the present invention. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments in the present invention, other embodiments obtained by ordinary technicians in this field without creative work are all within the scope of protection of the present invention.

[0050] Reference to "embodiments" herein means that a particular feature, structure, or characteristic described in conjunction with the embodiments may be included in at least one embodiment of the present application. The appearance of the phrase in various locations in the specification does not necessarily refer to the same embodiment, nor is it an independent or alternative embodiment that is mutually exclusive with other embodiments. It is explicitly and implicitly understood by those skilled in the art that the embodiments described herein may be combined with other embodiments.

[0051] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by technicians in the technical field to which this application belongs; the terms used in the specification of the application are only for the purpose of describing specific embodiments and are not intended to limit this application; the terms "including" and "having" in the specification and claims of this application and the above-mentioned figure descriptions and any variations thereof are intended to cover non-exclusive inclusions.

[0052] In addition, the terms "first" and "second" are used for descriptive purposes only and should not be understood as indicating or implying relative importance or implicitly indicating the number of the indicated technical features. Thus, a feature defined as "first" or "second" may explicitly or implicitly include one or more of the features. In the description of this application, the meaning of "plurality" is two or more, unless otherwise clearly and specifically defined.

[0053] The inorganic layer thickness of the TFT substrate display area 102 of the existing low-temperature polysilicon display is relatively large, which affects the improvement of the transmittance of the display.

[0054] In view of the above problems, a method for manufacturing an array substrate and a low-temperature polysilicon array substrate are proposed.

[0055] In a first aspect, a method for manufacturing an array substrate is provided. Figure 1 , Figure 1 It is a flow chart of an embodiment of an array substrate manufacturing method of the present application, including S100, obtaining a glass substrate 100, a polysilicon layer 200, a first insulating layer 300, a gate layer 400, an interlayer insulating layer 600 and an SD layer 500, and sequentially manufacturing the polysilicon layer 200, the first insulating layer 300, the gate layer 400, the interlayer insulating layer 600 and the SD layer 500 on the glass substrate 100 to obtain a plurality of TFT tube areas 101 and a plurality of display areas 102, wherein the display area 102 is located between the TFT tube areas 101.

[0056] In this embodiment, the polysilicon layer 200 in the array substrate is implanted with ND ions to form a heavily doped region, i.e., an active region, and implanted with LDD ions to form a lightly doped region, i.e., a drain region. The active region and the drain region are connected to the SD layer 500 through vias to form a source and a drain. The middle portion of the polysilicon layer 200 is implanted with ions to form a channel.

[0057] In this embodiment, the silicon source gas forms an amorphous silicon film by deposition, and then is crystallized by laser annealing to form a polysilicon layer 200 .

[0058] In a preferred embodiment, if Figure 2 , Figure 2 yes Figure 1 Flow chart of a specific implementation of S100; S100 includes: S110, forming an amorphous silicon film on a glass substrate 100; S120, converting the amorphous silicon film into a polycrystalline silicon film by laser scanning the amorphous silicon film to obtain a polycrystalline silicon layer 200.

[0059] In a preferred embodiment, if Figure 3 , Figure 3 yes Figure 2 Flow chart of a specific implementation method after S120; S100 also includes: S130, forming an active area in the polysilicon layer 200 through ND ion implantation; S140, forming a drain area on the polysilicon layer 200 adjacent to the active area through LDD ion implantation.

[0060] When performing ND ion implantation to form a heavily doped region, it is necessary to first make an ND photoresist pattern to shield the polysilicon layer 200 region that does not require ND ion implantation to avoid ND ion implantation. Similarly, when performing LDD ion implantation to form a lightly doped region, first remove the ND photoresist pattern, then make an LDD photoresist pattern to form two gap distances that can be used for LDD ion implantation, then perform LDD ion implantation, and then form a lightly doped region in the polysilicon layer 200.

[0061] In a preferred embodiment, Figure 4 , Figure 4 yes Figure 3 A flowchart of a specific implementation method after S140; S100 also includes: S150, making a first insulating layer 300 on the polysilicon layer 200; S160, making a gate layer 400 in the first insulating layer 300; S170, making an interlayer insulating layer 600 on the first insulating layer 300; S180, making an SD layer 500 on the interlayer insulating layer 600.

[0062] The first insulating layer 300 is used as a gate insulating layer, and its material may be a composite material of SiNx material and SiOx material.

[0063] In the prior art, since the thickness of the first insulating layer 300 (inorganic layer) is as high as 1 um and the light extraction efficiency of the inorganic layer (SiNx+SiOx) itself is not very high, the improvement of the LTPS transmittance is seriously affected.

[0064] S200 , making a first via hole and a second via hole, and using the first via hole and the second via hole to respectively connect the active area of ​​the polysilicon layer 200 and the SD layer 500 , and the drain area and the SD layer 500 , to obtain a source and a drain.

[0065] In this embodiment, the first via hole and the second via hole are used to connect the active region and the SD layer 500 , and the drain region and the SD layer 500 , so as to form the drain and source of the TFT region 101 .

[0066] S300, making a plurality of light-transmitting holes 103 on the first insulating layer 300 and the interlayer insulating layer 600 of the display area 102, and filling all the light-transmitting holes 103 with transparent photoresist. By setting a plurality of light-transmitting holes 103 on the inorganic film layer of the display area 102 of the low-temperature polycrystalline silicon array substrate, that is, on the first insulating layer 300 and the interlayer insulating layer 600, and then filling them with transparent photoresist, it is prevented that light is reflected back to the backlight module, thereby improving the light extraction efficiency and the overall transmittance of the product.

[0067] In a preferred embodiment, the array substrate manufacturing method further includes: S400 , obtaining a VITO layer 700 , and manufacturing the VITO layer 700 on the interlayer insulating layer 600 .

[0068] In a preferred embodiment, if Figure 5 , Figure 5 It is a flow chart of another embodiment of a TFT substrate manufacturing method of the present application; the array substrate manufacturing method also includes: S500, obtaining a passivation layer 800, and manufacturing the passivation layer 800 on the VITO layer 700; S600, obtaining a PITO layer 900, and manufacturing the PITO layer 900 on the passivation layer 800.

[0069] In a second aspect, a low temperature polysilicon array substrate, such as Figure 6 , Figure 6 This is a structural schematic diagram of a low-temperature polysilicon array substrate in the present application, which adopts the array substrate manufacturing method of the first aspect, including:

[0070] A glass substrate 100, a polysilicon layer 200, a first insulating layer 300, a gate layer 400, an interlayer insulating layer 600, a SD layer 500 and a plurality of light-transmitting holes 103;

[0071] A polysilicon layer 200, a first insulating layer 300, a gate layer 400, an interlayer insulating layer 600 and an SD layer 500 are sequentially fabricated on a glass substrate 100 to obtain a plurality of TFT tube regions 101 and a plurality of display regions 102, wherein the display regions 102 are located between the TFT tube regions 101;

[0072] A plurality of light-transmitting holes 103 are formed on the first insulating layer 300 and the interlayer insulating layer 600 in the display area 102 and are filled with transparent photoresist.

[0073] Furthermore, the low-temperature polysilicon array substrate also includes a first via and a second via. The first via and the second via are made on the polysilicon layer 200 and are used to overlap the active area of ​​the polysilicon layer 200 and the SD layer 500, and the drain area and the SD layer 500, respectively, to obtain the source and the drain.

[0074] Furthermore, the low-temperature polysilicon array substrate further includes a VITO layer 700 , a passivation layer 800 , and a PITO layer 900 ; the VITO layer 700 is formed on the interlayer insulating layer 600 ; the passivation layer 800 is formed on the VITO layer 700 ; and the PITO layer 900 is formed on the passivation layer 800 .

[0075] The array substrate manufacturing method and the low-temperature polycrystalline silicon array substrate in the present invention are implemented by setting a plurality of light-transmitting holes 103 on the inorganic film layer of the display area 102 of the low-temperature polycrystalline silicon array substrate, that is, on the first insulating layer 300 and the interlayer insulating layer 600, and then filling them with transparent photoresist to avoid light reflection back to the backlight module, thereby improving the light extraction efficiency and the overall transmittance of the product.

[0076] The above are only preferred embodiments of the present invention and are not intended to limit the present invention. Any modifications, equivalent substitutions, improvements, etc. made within the spirit and principles of the present invention should be included in the protection scope of the present invention.

Claims

1. A method for manufacturing an array substrate, used for manufacturing a low-temperature polycrystalline silicon array substrate, characterized in that: include: Step 100, obtaining a glass substrate, a polysilicon layer, a first insulating layer, a gate layer, an interlayer insulating layer and an SD layer, and sequentially manufacturing the polysilicon layer, the first insulating layer, the gate layer, the interlayer insulating layer and the SD layer on the glass substrate to obtain a plurality of TFT tube areas and a plurality of display areas, wherein the display area is located between the TFT tube areas; Step 200, making a first via hole and a second via hole, using the first via hole and the second via hole to respectively connect the active area of ​​the polysilicon layer and the SD layer, and the drain area and the SD layer to obtain a source electrode and a drain electrode; Step 300: making a plurality of light-transmitting holes on the first insulating layer in the display area, and filling all the light-transmitting holes with transparent photoresist.

2. The method for manufacturing an array substrate according to claim 1, characterized in that: The step 100 comprises: Step 110, forming an amorphous silicon thin film on the glass substrate; Step 120 , scanning the amorphous silicon film by laser to convert the amorphous silicon film into a polycrystalline silicon film to obtain the polycrystalline silicon layer.

3. The method for manufacturing an array substrate according to claim 2, characterized in that: The step 100 further includes: Step 130, forming an active region in the polysilicon layer by ND ion implantation; Step 140 : forming drain regions on the polysilicon layer adjacent to the active regions by LDD ion implantation.

4. The method for manufacturing an array substrate according to claim 3, characterized in that: The step 100 further includes: Step 150, forming the first insulating layer on the polysilicon layer; Step 160, forming the gate layer in the first insulating layer; Step 170, forming the interlayer insulating layer on the first insulating layer; Step 180: fabricate the SD layer on the interlayer insulating layer.

5. The method for manufacturing an array substrate according to claim 1, characterized in that: The array substrate manufacturing method further includes: Step 400: Obtain a VI TO layer, and manufacture the VI TO layer on the interlayer insulating layer.

6. The method for manufacturing an array substrate according to claim 5, characterized in that: The array substrate manufacturing method further includes: Step 500, obtaining a passivation layer, and manufacturing the passivation layer on the VI TO layer; Step 600: Obtain a PI TO layer, and manufacture the PI TO layer on the passivation layer.

7. The method for manufacturing an array substrate according to any one of claims 1 to 6, characterized in that: The first insulating layer is made of a composite material of SiNx material and SiOx material.

8. A low temperature polycrystalline silicon array substrate, using the array substrate manufacturing method according to claim 8, characterized in that: include: A glass substrate, a polysilicon layer, a first insulating layer, a gate layer, an interlayer insulating layer, an SD layer and a plurality of light-transmitting holes; The polysilicon layer, the first insulating layer, the gate layer, the interlayer insulating layer and the SD layer are sequentially fabricated on the glass substrate to obtain a plurality of TFT tube regions and a plurality of display regions, wherein the display region is located between the TFT tube regions; The plurality of light-transmitting holes are formed on the first insulating layer and the interlayer insulating layer in the display area and are filled with transparent photoresist.

9. The low-temperature polysilicon array substrate according to claim 8, characterized in that: The low temperature polysilicon array substrate further comprises: a first via hole and a second via hole; The first via hole and the second via hole are made on the polysilicon layer, and are used to overlap the active area of ​​the polysilicon layer and the SD layer, and the drain area and the SD layer, respectively, to obtain the source and the drain.

10. The low temperature polysilicon array substrate according to claim 9, characterized in that: The low temperature polysilicon array substrate further comprises: VI TO layer, passivation layer, PI TO layer; The VI TO layer is formed on the interlayer insulating layer; The passivation layer is formed on the VITO layer; The PI TO layer is formed on the passivation layer.

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