A back contact solar cell and a method of manufacturing the same

Abstract

The application provides a back contact type solar cell and a preparation method thereof, and relates to the technical field of solar cell manufacturing. The preparation method provides a preparation mode of a mask layer level, reduces the preparation and removal difficulty of the mask layer level, avoids the lateral etching problem existing in wet etching of the mask layer, further comprises a PN isolation region between the N region and the P region, and forms lateral physical isolation in the two times of mask processing, so that the effective isolation between the P region and the N region is ensured. Therefore, the back contact type solar cell prepared by using the preparation method has high conversion efficiency.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of solar cell manufacturing, in particular to a back contact type solar cell and a preparation method thereof. BACKGROUND

[0002] In the field of solar photovoltaic technology, the back contact type solar cell inevitably increases the preparation process steps because it needs to introduce photoresist or ink or SiNx, SiOx and other mask layers multiple times during the preparation process, and removes part of the mask layer through photolithography, chemical etching and other methods. The multi-step and complexity of the process cause the stability of the preparation process to deteriorate, the difficulty of process control increases, and the conversion efficiency of the prepared back contact type solar cells is uneven, which seriously affects the overall quality of the cell product. SUMMARY

[0003] The present application provides a back contact type solar cell and a preparation method thereof. In the preparation process, the thin film mask method is alternately used to realize the patterning of the P region, the N region and the PN isolation region, so that the entire preparation process is simple and easy to implement, and the subsequent process is facilitated, and the conversion efficiency of the obtained back contact type solar cell is high.

[0004] To achieve the above object, the technical scheme adopted by the embodiments of the present application is as follows:

[0005] In an aspect of the embodiments of the present application, a preparation method of a back contact type solar cell is provided, including: providing a pretreated N-type silicon wafer substrate, the N-type silicon wafer substrate including N regions and P regions crossing each other, and a PN isolation region between the N regions and the P regions; depositing a first passivation layer on a back surface of the N-type silicon wafer substrate; adhering a first mask pattern layer on the first passivation layer, the first mask pattern layer being formed by patterning a first mask layer by using a laser, the first mask pattern layer including a first region preset pattern formed in a first region, a layer formed by retaining material in the PN isolation region, and a hollow formed by removing material in a second region; solution cleaning to form the first region preset pattern of the first passivation layer in the first region, the hollow part in the first region preset pattern exposing the N-type silicon wafer substrate; depositing a first amorphous silicon composite layer, mechanically removing the first mask pattern layer to form an inverse pattern of the first mask pattern layer of the first region preset pattern of the first amorphous silicon composite layer in the first region; adhering a second mask pattern layer on the first passivation layer, the second mask pattern layer being formed by patterning a second mask layer by using a laser, the second mask pattern layer including a second region preset pattern formed in a second region, a layer formed by retaining material in the PN isolation region, and a hollow formed by removing material in the first region; solution cleaning to form the second region preset pattern of the first passivation layer in the second region, the hollow part in the second region preset pattern exposing the N-type silicon wafer substrate; depositing a second amorphous silicon composite layer, mechanically removing the second mask pattern layer to form an inverse pattern of the second mask pattern layer of the second amorphous silicon composite layer in the second region; annealing treatment, the annealing temperature being 800-950 DEG C; and performing positive and negative electrode metallization treatment on the back surface of the N-type silicon wafer substrate to obtain the back contact type solar cell.

[0006] In another aspect of the embodiments of the present application, a back contact type solar cell is provided, which is prepared by using the preparation method of the back contact type solar cell according to any one of the above aspects.

[0007] In still another aspect of the embodiments of the present application, another method for manufacturing a back contact solar cell is provided, including: providing a pretreated P-type silicon wafer substrate, the P-type silicon wafer substrate including N regions and P regions crossing each other, and a PN isolation region between the N regions and the P regions; depositing a second passivation layer on the back surface of the P-type silicon wafer substrate; adhering a third mask pattern layer on the second passivation layer, the third mask pattern layer being formed by patterning a third mask layer using a laser, the third mask pattern layer including N region preset patterns formed in the N regions, a layer formed by retaining material in the PN isolation region, and a hollow formed by removing material in the P regions; solution cleaning to form the N region preset patterns in the second passivation layer of the N regions, the hollow portions in the N region preset patterns exposing the P-type silicon wafer substrate; sequentially depositing a tunneling oxide layer and a second amorphous silicon layer using an in-situ doping method, the second amorphous silicon layer including at least one phosphorus-containing layer of an intrinsic amorphous silicon layer, a phosphorus-containing amorphous silicon layer, and a phosphorus-containing silicon oxide layer; removing the third mask pattern layer in a mechanical manner to form an inverse pattern of the third mask pattern layer in the tunneling oxide layer and the second amorphous silicon layer of the N regions; annealing to form an N+ polysilicon layer in the second amorphous silicon layer; depositing a first anti-reflection layer on the front surface of the P-type silicon wafer substrate, the first anti-reflection layer being formed by at least one layer of an aluminum oxide, a silicon nitride, or a silicon oxide material; depositing a second anti-reflection layer on the back surface of the P-type silicon wafer substrate, the second anti-reflection layer being formed by at least one layer of a silicon oxide, a silicon nitride, or a silicon oxynitride material; and performing positive and negative electrode metallization processing on the back surface of the P-type silicon wafer substrate to obtain the back contact solar cell.

[0008] In still another aspect of the embodiments of the present application, another back contact solar cell is provided, which is manufactured by the method for manufacturing a back contact solar cell described above.

[0009] The embodiments of the present application have the following beneficial effects:

[0010] The embodiment of the present application provides a preparation method of a back contact type solar cell, comprising the following steps: providing a pretreated N-type silicon wafer substrate, the N-type silicon wafer substrate comprising N regions and P regions crossing each other, and a PN isolation region between the N regions and the P regions; depositing a first passivation layer on the back surface of the N-type silicon wafer substrate; adhering a first mask pattern layer on the first passivation layer, the first mask pattern layer being formed by patterning the first mask layer by using a laser, the first mask pattern layer comprising a first region preset pattern formed in a first region, a layer formed by retaining material in the PN isolation region, and a hollow formed by removing material in a second region; solution cleaning to form the first region preset pattern of the first passivation layer in the first region, and the hollow part of the first region preset pattern exposing the N-type silicon wafer substrate; depositing a first amorphous silicon composite layer, and mechanically removing the first mask pattern layer to form an inverse pattern of the first mask pattern layer in the first region; adhering a second mask pattern layer on the first passivation layer, the second mask pattern layer being formed by patterning the second mask layer by using a laser, the second mask pattern layer comprising a second region preset pattern formed in a second region, a layer formed by retaining material in the PN isolation region, and a hollow formed by removing material in the first region; solution cleaning to form the second region preset pattern of the first passivation layer in the second region, and the hollow part of the second region preset pattern exposing the N-type silicon wafer substrate; depositing a second amorphous silicon composite layer, and mechanically removing the second mask pattern layer to form an inverse pattern of the second mask pattern layer in the second region; annealing treatment, the annealing temperature being 800-950 DEG C; and performing positive and negative electrode metallization treatment on the back surface of the N-type silicon wafer substrate to obtain the back contact type solar cell. In the preparation method, a mask layer level preparation method is provided, the preparation and removal difficulty of the mask layer level is reduced, the lateral etching problem existing in the mask layer wet etching is avoided, the PN isolation region is further included between the N region and the P region, lateral physical isolation is formed in the two alternating mask processing processes, the effective isolation between the P region and the N region is ensured, and therefore, the back contact type solar cell prepared by using the preparation method has high conversion efficiency. BRIEF DESCRIPTION OF DRAWINGS

[0011] In order to more clearly illustrate the technical solutions of the embodiments of the present application, the following will briefly introduce the drawings needed to be used in the embodiments. It should be understood that the following drawings only show some of the embodiments of the present application, and therefore should not be regarded as a limitation on the scope. For those skilled in the art, other related drawings can also be obtained without creative labor on the basis of these drawings.

[0012] Figure 1 One of the flowcharts of the preparation method of the back contact type solar cell provided by the embodiment of the present application;

[0013] Figure 2Flowchart II of a preparation method of a back contact type solar cell provided by an embodiment of the present application;

[0014] Figure 3 Preparation process schematic diagram I of a back contact type solar cell provided by an embodiment of the present application;

[0015] Figure 4 Preparation process schematic diagram II of a back contact type solar cell provided by an embodiment of the present application;

[0016] Figure 5 Preparation process schematic diagram III of a back contact type solar cell provided by an embodiment of the present application;

[0017] Figure 6 Preparation process schematic diagram IV of a back contact type solar cell provided by an embodiment of the present application;

[0018] Figure 7 Preparation process schematic diagram V of a back contact type solar cell provided by an embodiment of the present application;

[0019] Figure 8 Preparation process schematic diagram VI of a back contact type solar cell provided by an embodiment of the present application;

[0020] Figure 9 Preparation process schematic diagram VII of a back contact type solar cell provided by an embodiment of the present application;

[0021] Figure 10 Preparation process schematic diagram VIII of a back contact type solar cell provided by an embodiment of the present application;

[0022] Figure 11 Preparation process schematic diagram IX of a back contact type solar cell provided by an embodiment of the present application;

[0023] Figure 12 Flowchart III of a preparation method of a back contact type solar cell provided by an embodiment of the present application;

[0024] Figure 13 Flowchart IV of a preparation method of a back contact type solar cell provided by an embodiment of the present application;

[0025] Figure 14 Flowchart V of a preparation method of a back contact type solar cell provided by an embodiment of the present application;

[0026] Figure 15 Flowchart VI of a preparation method of a back contact type solar cell provided by an embodiment of the present application;

[0027] Figure 16A flowchart of a preparation method of a back contact type solar cell provided in an embodiment of the present application;

[0028] Figure 17 A flowchart of a preparation method of a back contact type solar cell provided in an embodiment of the present application;

[0029] Figure 18 A flowchart of a preparation method of a back contact type solar cell provided in an embodiment of the present application;

[0030] Figure 19 A flowchart of a preparation method of a back contact type solar cell provided in an embodiment of the present application;

[0031] Figure 20 A flowchart of a preparation method of a back contact type solar cell provided in an embodiment of the present application;

[0032] Figure 21 A flowchart of a preparation method of a back contact type solar cell provided in an embodiment of the present application;

[0033] Figure 22 A flowchart of a preparation method of a back contact type solar cell provided in another embodiment of the present application;

[0034] Figure 23 A structural schematic diagram of a laser mask patterning device provided in an embodiment of the present application;

[0035] Figure 24 A surface grid line pattern schematic diagram of a back contact type solar cell provided in an embodiment of the present application.

[0036] Icon: 100-N type silicon wafer substrate; 110-first passivation layer; 120-P type amorphous silicon composite layer; 130-N type amorphous silicon composite layer; 1-1-laser; 1-2-mirror; 1-3-beam expander; 1-4-vibrating mirror scanning module; 1-5-thin film layer; 1-6-ta; 200-first mask pattern layer; 300-second mask pattern layer; second passivation layer; third mask layer. DETAILED DESCRIPTION

[0037] In order to make the purpose, technical solutions and advantages of the embodiments of the present application clearer, the technical solutions in the embodiments of the present application will be described clearly and completely below with reference to the drawings in the embodiments of the present application. Obviously, the described embodiments are some embodiments of the present application, but not all the embodiments of the present application. It should be noted that, in the case of no conflict, each feature in the embodiments of the present application can be combined with each other, and the combined embodiments are still within the protection scope of the present application.

[0038] In the description of the present application, it should be noted that the terms "upper", "lower", "left", "right", "inner", "outer" and the like indicate the orientation or positional relationship shown in the drawings, and are only for the convenience of describing the present application and simplifying the description, and therefore cannot be understood as a limitation on the present application. In addition, the terms "first", "second", "third" and the like are only used for differentiation in description, and cannot be understood as indicating or implying relative importance.

[0039] In one aspect of the embodiments of the present application, a preparation method of a back contact type solar cell is provided, as shown in the accompanying drawings. Figure 1 The preparation method of the back contact type solar cell of the embodiments of the present application includes the following steps.

[0040] S001, a pretreated N-type silicon wafer substrate is provided, the N-type silicon wafer substrate includes N regions and P regions intersecting with each other, and a PN isolation region is further included between the N regions and the P regions.

[0041] S002, a first passivation layer is deposited on the back surface of the N-type silicon wafer substrate.

[0042] S003, a first mask pattern layer is formed by adhering on the first passivation layer, the first mask pattern layer is formed by patterning a first mask layer using a laser, the first mask pattern layer includes a first region preset pattern formed in a first region, a layer formed by retaining material in the PN isolation region, and a hollow formed by removing material in a second region.

[0043] S004, solution cleaning is performed to form a first region preset pattern in the first passivation layer of the first region, and the hollow part in the first region preset pattern exposes the N-type silicon wafer substrate.

[0044] S005, a first amorphous silicon composite layer is deposited, the first mask pattern layer is removed in a mechanical manner, and the first amorphous silicon composite layer in the first region forms an inverse pattern of the first mask pattern layer.

[0045] S006, a second mask pattern layer is formed by adhering on the first passivation layer, the second mask pattern layer is formed by patterning a second mask layer using a laser, the second mask pattern layer includes a second region preset pattern formed in a second region, a layer formed by retaining material in the PN isolation region, and a hollow formed by removing material in the first region.

[0046] S007, solution cleaning is performed to form a second region preset pattern in the first passivation layer of the second region, and the hollow part in the second region preset pattern exposes the N-type silicon wafer substrate.

[0047] S008, a second amorphous silicon composite layer is deposited, the second mask pattern layer is removed in a mechanical manner, and the second amorphous silicon composite layer in the second region forms an inverse pattern of the second mask pattern layer.

[0048] S009, annealing treatment, annealing temperature is 800-950℃.

[0049] S010, back surface of the N-type silicon wafer substrate is metalized to obtain a back contact solar cell.

[0050] Wherein, steps S003 to S005, and steps S006 to S008, are used to prepare mask patterns for P and N regions crossing each other on the N-type silicon wafer substrate. The first region in step S003 can be a P region. When the first region is a P region, the first region preset pattern is a P region preset pattern, and the first amorphous silicon composite layer deposited in step S005 is a P-type amorphous silicon composite layer. Conversely, the first region can also be an N region, which will not be described here.

[0051] In order to clearly describe the method steps, the following will take the first region as P region and the second region as N region as an example for specific description.

[0052] As shown in Figure 2 The preparation method of the back contact solar cell of the embodiment of the present application comprises:

[0053] S101, providing a pretreated N-type silicon wafer substrate 100, the N-type silicon wafer substrate 100 includes N and P regions crossing each other, and a PN isolation region between the N and P regions.

[0054] First, the N-type silicon wafer substrate 100 is pretreated, for example, texturing, polishing and other processes, so that the surface of the N-type silicon wafer substrate 100 is more conducive to the effective formation of subsequent process steps. Among them, the N-type silicon wafer substrate 100 includes N and P regions crossing each other, and a PN isolation region between the N and P regions. It should be noted that the N, P and PN isolation regions are preset divisions of the N-type silicon wafer substrate 100 according to the layout of the specific solar cell, so that in the subsequent steps, the N and P regions are prepared on the N-type silicon wafer substrate 100, and the main grid and the auxiliary grid are patterned according to the preset division. As shown in Figure 24 The N and P regions are preset divisions at different positions on the N-type silicon wafer substrate 100, and the PN isolation region is located at the adjacent region of the N and P regions, which is used to realize the mutual isolation between the N and P regions during the process. That is, during the specific preparation process, the PN isolation region is reserved for isolation when the N region is patterned, and the PN isolation region is still reserved to ensure the isolation effect when the P region is patterned.

[0055] S102, as shown in Figure 3 A first passivation layer 110 is deposited on the back surface of the N-type silicon wafer substrate 100.

[0056] The first passivation layer 110 is deposited on the back surface of the N-type silicon wafer substrate 100, thereby playing a whole layer protection role for the N-type silicon wafer substrate 100. Thus, when the layers above the first passivation layer 110 need to be removed in subsequent steps, even if the removed layers are adhered to the first passivation layer 110, the N-type silicon wafer substrate 100 can be effectively protected from being damaged or damaged in the tearing process due to the presence of the first passivation layer 110.

[0057] Similarly, in subsequent steps, in order to protect the lower layer before the layer to be removed is formed, a passivation layer can be provided in advance to protect the adverse effects that the tearing action may have on it. The material of the passivation layer provided can be the same as the first passivation layer 110, or it can be different, and the thickness can also be set as needed, as long as the passivation layer provided can protect the lower layer when the layer above it is removed.

[0058] S103, a first mask pattern layer 200 is attached to the first passivation layer 110. The first mask pattern layer 200 is formed by patterning the first mask layer using a laser. The first mask pattern layer 200 includes a P region pre-designed pattern formed in the P region, a layer formed by retaining the material in the PN isolation region, and a hollow formed by removing the material in the N region.

[0059] As shown in Figure 4 , the first mask pattern layer 200 is attached to the first passivation layer 110. The first mask pattern layer 200 is formed by patterning the first mask layer using a laser. The first mask pattern layer 200 includes a P region pre-designed pattern formed in the P region, a layer formed by retaining the material in the PN isolation region, and a hollow formed by removing the material in the N region.

[0060] Those skilled in the art will understand that the size of the first mask pattern layer 200 attached to the first passivation layer 110 should generally be substantially the same as the size of the N-type silicon wafer substrate 100. After the first mask pattern layer 200 is attached, the pattern of the first mask pattern layer 200 in the P region matches to cover the pre-designed pattern of the P region, and the material of the first mask layer is retained in the PN isolation region to form an isolation between the N region and the hollow of the N region.

[0061] For example, as shown in Figure 24 , the pre-designed patterns of the P region and the N region are both interdigital, and the PN isolation region is the position between the interdigital P region and the N region.

[0062] It should be noted that the first mask pattern layer 200 is attached on the first passivation layer 110. A person skilled in the art can select to attach the first mask layer on the first passivation layer 110 first and then pattern the first mask layer to obtain the first mask pattern layer 200 according to actual work needs, or select to pattern the first mask layer to form the first mask pattern layer 200 first and then attach on the first passivation layer 110. In the embodiment of the present application, the first mask layer is patterned to form the first mask pattern layer 200 first, and then the first mask pattern layer 200 is attached on the first passivation layer 110. In this way, on the one hand, the first mask layer is patterned on the external device, avoiding damage to the first passivation layer 110 or the N-type silicon wafer substrate 100 below the first passivation layer 110 in the patterning process; on the other hand, the patterning process is specially performed on the external device, which is also conducive to the accuracy of the pattern formed on the first mask pattern layer 200.

[0063] It should be further noted that the first mask layer is patterned by laser in the embodiment of the present application to obtain the first mask pattern layer 200. For example, the laser used for patterning in the embodiment of the present application adopts a laser beam with a wavelength of 0.3 μm-12 μm, which is selected according to needs in pulse mode, quasi-continuous mode or continuous mode, laser pulse width is ps (picosecond), ns (nanosecond), and light energy distribution is Gaussian distribution or flat-top distribution, and the light spot size is usually between 10-500 μm.

[0064] The laser mask patterning device can be selected, as shown in Figure 23 The laser mask patterning device includes an optical module and a stage module. The optical module includes a laser 1-1. The laser beam emitted by the laser 1-1 is reflected by a mirror 1-2, expanded by an expansion mirror 1-3, and then enters a galvanometer scanning module 1-4. The scanning beam is formed by the galvanometer scanning module 1-4 and then emitted.

[0065] The thin film layer 1-5 (such as the first passivation layer 110 or the N-type silicon wafer substrate 100 after the first passivation layer 110 is attached) to be patterned is adsorbed on the table 1-6. When the step method of first patterning the first mask layer and then attaching the N-type silicon wafer substrate 100 with the first passivation layer 110 is used, the attachment can be achieved by adding an adhesive layer. In this case, the side with the adhesive layer is upward, and the other side is adsorbed on the table 1-6. Then, the laser 1-1 is started, and the outgoing scanning beam is used to scan and process the thin film layer 1-5. When the pattern to be patterned includes intersecting main and auxiliary grid structures, the table 1-6 can be pre-provided with grooves corresponding to the main and auxiliary grid structures, so that when the scanning beam is scanned according to the pre-provided pattern, it corresponds to the main and auxiliary grid grooves on the table 1-6. In this way, it is more conducive to the accuracy of the patterned pattern. Similarly, in the process of patterning other layers by laser, the laser mask patterning device can also be used, which will not be described here.

[0066] S104, solution cleaning to form a P region pre-pattern in the first passivation layer 110 of the P region, and the hollow part in the P region pre-pattern exposes the N-type silicon wafer substrate 100.

[0067] As shown in Figure 5 , the N-type silicon wafer substrate 100 with the first mask pattern layer 200 is cleaned with an HF solution. The first passivation layer 110 exposed in the hollow part of the pattern in the P region reacts with the HF solution to be removed, so that the first passivation layer 110 in the P region is formed into a P region pre-pattern. After the first passivation layer 110 exposed in the first mask pattern layer 200 is removed by the HF solution, the hollow part in the P region pre-pattern directly exposes the N-type silicon wafer substrate 100.

[0068] S105, depositing a P-type amorphous silicon composite layer 120, removing the first mask pattern layer 200 in a mechanical way, so that the P-type amorphous silicon composite layer 120 in the P region forms an inverted pattern of the first mask pattern layer.

[0069] As shown in Figure 6 , the P-type amorphous silicon composite layer 120 is deposited on the N-type silicon wafer substrate 100 after solution cleaning. The P-type amorphous silicon composite layer 120 includes at least one layer. For example, the P-type amorphous silicon composite layer 120 can have three layers as shown in Figure 6 .

[0070] Then, as shown in Figure 7As shown, the first mask pattern layer 200 is removed in a mechanical manner. Since the physical material of the first mask pattern layer 200 is located in the P region and the PN isolation region, after the first mask pattern layer 200 is removed, the part of the P-type amorphous silicon composite layer 120 in the P region located on the first mask pattern layer 200 is removed, so that the P-type amorphous silicon composite layer 120 in the P region is formed into the inverse pattern of the first mask pattern layer 200. In this way, the mask patterning process of the P region is completed. Since the design of the first mask pattern layer 200 makes the PN isolation region exist between the P region and the N region before the first mask pattern layer 200 is removed, the P region and the N region are not conductive, and the problem of lateral etching of the P region and the N region in the wet etching process is solved.

[0071] It should be noted that, as an example, after the P-type amorphous silicon composite layer 120 is deposited, a passivation layer can be further deposited in order to facilitate the integrity and convenience of the mechanical removal of the first mask pattern layer 200. The passivation layer and the first passivation layer 110 are made of the same material. In this way, the deposited passivation layer can protect the P-type amorphous silicon composite layer 120 below and prevent the P-type amorphous silicon composite layer 120 from being left with substances such as colloids when the first mask pattern layer 200 is mechanically removed, so as to facilitate the complete and complete formation of the pattern. At the same time, the deposited passivation layer can increase the thickness of the PN isolation region and achieve better electrical isolation effect.

[0072] S106, the second mask pattern layer 300 is formed on the first passivation layer 110. The second mask pattern layer 300 is formed by patterning the second mask layer by laser. The second mask pattern layer 300 includes the N region preset pattern formed in the N region, the layer formed by retaining the material in the PN isolation region, and the hollow formed by removing the material in the P region.

[0073] As shown in Figure 8 After the mask patterning of the P region is completed, the second mask pattern layer 300 is attached again. The second mask pattern layer 300 includes the N region preset pattern formed in the N region and the layer formed by retaining the material in the PN isolation region. Through laser patterning, the material of the second mask pattern layer 300 corresponding to the P region is removed to present a hollow in the P region. In this way, during the mask patterning process in the N region, the PN isolation region still plays a role in isolating and protecting between the P region and the N region.

[0074] Similarly, the attachment of the second mask pattern layer 300 on the first passivation layer 110 and the laser patterning of the second mask pattern layer 300 can be prepared in any order according to the actual needs of the workers in the field.

[0075] It should be noted that the order of the first mask pattern layer 200 patterning the P region and the second mask pattern layer 300 patterning the N region is not limited to the order shown in the embodiments of the present application. The P region and the N region need to be prepared in turn, and the order is not limited.

[0076] S107, solution cleaning to form the N region preset pattern of the first passivation layer 110 in the N region, and the hollow part in the N region preset pattern exposes the N-type silicon wafer substrate 100.

[0077] As shown in Figure 9 , the N-type silicon wafer substrate 100 with the second mask pattern layer 300 is cleaned with HF solution, and the first passivation layer 110 exposed in the hollow part of the pattern of the second mask pattern layer 300 reacts with the HF solution to be removed, so that the first passivation layer 110 in the N region is formed into the N region preset pattern. After the first passivation layer 110 exposed in the second mask pattern layer 300 is removed by HF solution reaction, the hollow part in the N region preset pattern directly exposes the N-type silicon wafer substrate 100.

[0078] S108, depositing the N-type amorphous silicon composite layer 130, and removing the second mask pattern layer 300 in a mechanical manner, so that the N-type amorphous silicon composite layer 130 in the N region forms the inverse pattern of the second mask pattern layer 300.

[0079] As shown in Figure 10 , the N-type amorphous silicon composite layer 130 is deposited on the N-type silicon wafer substrate 100 after solution cleaning, wherein the N-type amorphous silicon composite layer 130 includes at least one layer, and the N-type amorphous silicon composite layer 130 can be three layers as shown in Figure 10 .

[0080] Then, as shown in Figure 11 , the second mask pattern layer 300 is removed in a mechanical manner. Since the solid material of the second mask pattern layer 300 is located in the N region and the PN isolation region, after the second mask pattern layer 300 is removed, the part of the N-type amorphous silicon composite layer 130 in the N region located on the second mask pattern layer 300 is removed, so that the N-type amorphous silicon composite layer 130 in the N region forms the inverse pattern of the second mask pattern layer 300. In this way, the mask patterning process of the N region is completed. During the whole mask patterning process, the PN isolation region is always located between the P region and the N region to ensure the isolation effect.

[0081] Similarly, after the deposition of the N-type amorphous silicon composite layer 130, in order to facilitate the integrity and convenience of the mechanical removal of the second mask pattern layer 300, a passivation layer can also be deposited, the passivation layer and the first passivation layer 110 are made of the same material, thus, the deposited passivation layer can protect the N-type amorphous silicon composite layer 130 below, protect the N-type amorphous silicon composite layer 130 from being contaminated or damaged during the preparation process, and can prevent the residual of substances such as colloids on the N-type amorphous silicon composite layer 130 when the second mask pattern layer 300 is mechanically removed, thereby more conducive to the thoroughness and integrity of the formed pattern.

[0082] S109, annealing treatment, the annealing temperature is between 800-950℃.

[0083] The sample after the above preparation steps is sent into a furnace tube for annealing treatment, the annealing temperature is set between 800-950℃, and the P-type amorphous silicon composite layer 120 and the N-type amorphous silicon composite layer 130 after the annealing treatment undergo corresponding annealing reactions.

[0084] S110, the back surface of the N-type silicon wafer substrate 100 is subjected to positive and negative electrode metallization treatment to obtain a back contact type solar cell.

[0085] Specifically, the positive and negative electrodes are printed in contact or non-contact and subjected to drying sintering and other treatments to realize the back surface positive and negative electrode metallization.

[0086] It should be further pointed out that in the preparation method of the back contact type solar cell of the embodiment of the present application, other steps such as cleaning, polishing, planarization, etc. can also be included, for example, after the annealing treatment step, a cleaning step for the formed sample can also be included, and the sample can also be cleaned by HF solution to remove the remaining material of the first passivation layer 110 on the surface of the sample, thereby more conducive to the realization of the process effect of the subsequent positive and negative electrode metallization.

[0087] This application provides a method for fabricating a back-contact solar cell, comprising: providing a pretreated N-type silicon substrate 100, the N-type silicon substrate 100 including intersecting N-regions and P-regions, and a PN isolation region between the N-regions and P-regions; depositing a first passivation layer 110 on the back side of the N-type silicon substrate 100; bonding and forming a first mask pattern layer 200 on the first passivation layer 110, the first mask pattern layer 200 being formed by patterning the first mask layer using a laser, the first mask pattern layer 200 including a preset P-region pattern formed in the P-region, a layer of material retained in the PN isolation region, and a cutout formed by material removal in the N-region; solution cleaning to form a preset P-region pattern in the first passivation layer 110 in the P-region, the cutout portion of the preset P-region pattern exposing the N-type silicon substrate 100; depositing a P-type amorphous silicon composite layer 120; and mechanically removing the first mask pattern layer 200 to allow the first passivation layer 110 to form a preset P-region pattern ... in the P-region, the cutout portion of the preset P-region pattern exposing the N-type silicon substrate 100; and depositing a P-type amorphous silicon composite layer 120; and mechanically removing the first mask pattern layer 200 to allow the first passivation layer 110 to form a preset P-region pattern in the P-region. The P-type amorphous silicon composite layer 120 in the P-region forms the inverted pattern of the first mask pattern layer 200; a second mask pattern layer 300 is formed by bonding, the second mask pattern layer 300 is formed by patterning the second mask layer with a laser, the second mask pattern layer 300 includes an N-region preset pattern formed in the N-region, a layer formed by retaining material in the PN isolation region, and a cutout formed by removing material in the P-region; solution cleaning is performed to form the N-region preset pattern in the first passivation layer 110 in the N-region, the cutout portion in the N-region preset pattern exposes the N-type silicon wafer substrate 100; an N-type amorphous silicon composite layer 130 is deposited, and the second mask pattern layer 300 is removed mechanically to form the inverted pattern of the second mask pattern layer 300 in the N-region N-type amorphous silicon composite layer 130; annealing is performed, the annealing temperature is 800℃-950℃; positive and negative electrode metallization is performed on the back side of the N-type silicon wafer substrate 100 to obtain a back contact solar cell. The fabrication method of this application provides a mask-level fabrication approach, which reduces the difficulty of mask-level fabrication and removal, and avoids the lateral drilling problem present in wet etching of the mask layer. A PN isolation region is also included between the N-region and the P-region, forming lateral physical isolation during the two alternating mask processing steps, ensuring effective isolation between the P-region and the N-region. Thus, the back-contact solar cell fabricated using the method of this application embodiment has high conversion efficiency.

[0088] Optional, such as Figure 12 As shown, S102, depositing a first passivation layer 110 on the back side of the N-type silicon substrate 100 includes:

[0089] S1021, the first passivation layer 110 is a silicon nitride layer or a silicon oxide layer, and the thickness of the first passivation layer 110 is between 20-80nm.

[0090] The first passivation layer 110 is formed by depositing silicon nitride (SiNx) or silicon oxide (SiOx), and the thickness of the first passivation layer 110 is controlled to be between 20-80 nm.

[0091] It should be noted that when a passivation layer is deposited after the deposition of the P-type amorphous silicon composite layer 120 and the deposition of the N-type amorphous silicon composite layer 130, the deposited passivation layer is made of the same material as the first passivation layer 110, and the deposition thickness can also be consistent with the first passivation layer 110. The deposited passivation layer can serve as a protective layer to buffer the film layer, and on the other hand, it can also avoid damage to the underlying amorphous silicon layer (P-type amorphous silicon composite layer 120 or N-type amorphous silicon composite layer 130) during mechanical removal or cause contamination of the functional layer due to residual glue.

[0092] Optionally, as shown in S103, the first passivation layer 110 is adhered to form a first mask pattern layer 200, which includes: Figure 13

[0093] S1031, the first mask pattern layer 200 includes a polymer film layer and an adhesive layer adhered to each other, and the polymer film layer is adhered to the first passivation layer 110 through the adhesive layer.

[0094] In order to make the first mask pattern layer 200 better adhere to the first passivation layer 110, the first mask pattern layer 200 includes a polymer film layer and an adhesive layer adhered to each other, and the polymer film layer is adhered to the first passivation layer 110 through the adhesive layer, which is equivalent to increasing the adhesive layer to ensure that the effective structure layer of the first mask pattern layer 200 is tightly adhered to the first passivation layer 110. Moreover, the effective structure layer of the first mask pattern layer 200 is selected as a polymer material film layer.

[0095] Optionally, the polymer film layer is made of a material with a temperature resistance greater than 350°C, the thickness of the polymer film layer is between 5-100 μm, preferably between 5-50 μm, and the thickness of the adhesive layer is between 3-10 μm.

[0096] The polymer film layer is made of a material with a temperature resistance greater than 350°C to ensure that the film layer is not adversely affected during laser patterning, and to effectively improve the accuracy of patterning to form the first mask pattern layer 200. Specifically, the temperature resistance generally refers to the glass transition temperature of the polymer film layer. The thickness of the polymer film layer is set to be between 5-100 μm, preferably between 5-50 μm, and the thickness of the adhesive layer is between 3-10 μm, to ensure that the polymer film layer has sufficient thickness to form a mask pattern, and to ensure the adhesive force of the adhesive layer and avoid the adverse effects of the adhesive layer being too thick on the accuracy of the mask pattern. At the same time, the polymer film is made of a material with a temperature resistance greater than 350°C, which is more friendly to the process of depositing the back amorphous silicon layer.​

[0097] Similarly, the second mask pattern layer 300 and the first mask pattern layer 200 are mask materials that pattern the P-region and N-region respectively. They act on different areas but have the same function. Therefore, the second mask pattern layer 300 can also use the same material and layer thickness as described above.

[0098] Optional, such as Figure 14 As shown, S103, the first mask pattern layer 200 is formed by patterning the first mask layer using a laser. The first mask pattern layer 200 includes a preset pattern formed in the P region, a layer formed by retaining material in the PN isolation region, and a cutout formed by removing material in the N region.

[0099] S1032, the P-region preset pattern includes the projection pattern of the main gate electrode and the sub-gate electrode arranged crosswise in the P-region on the N-type silicon substrate 100.

[0100] The P-region preset pattern should generally have feature points related to the mask pattern. For example, for the interdigitated main gate electrode and sub-gate electrode, the P-region preset pattern includes the projection pattern of the main gate electrode and sub-gate electrode intersecting in the P-region on the N-type silicon substrate 100. In addition, the P-region preset pattern may also include feature shapes such as solder joints and harpoons.

[0101] It should be noted that the PN isolation region is located between the P and N regions. Those skilled in the art should understand that, generally, to maximize the effective area of ​​the P and N regions, the PN isolation region should occupy as little area as possible while ensuring isolation effectiveness, thereby guaranteeing battery electrical performance. Using the method of this application, the width of the PN isolation region is between 20-60 μm, preferably 20-40 μm, and more preferably, between 20-30 μm.

[0102] Similarly, the preset pattern of the N region of the second mask pattern layer 300 also includes the projection pattern of the relevant structure of the N region. This will not be elaborated upon here.

[0103] Optional, such as Figure 15 As shown, S101, the pre-treated N-type silicon substrate 100 includes:

[0104] S1011 provides N-type silicon wafers.

[0105] S1012. The N-type silicon wafer is texturized and back-side polished to obtain the pre-treated N-type silicon wafer substrate 100.

[0106] The N-type silicon wafer undergoes pretreatment steps, such as dicing, edge passivation, texturing, and back-side polishing. The treated N-type silicon wafer can then be used as an N-type silicon substrate 100.

[0107] Optionally, as shown in Figure 16 S105, depositing a P-type amorphous silicon composite layer 120 includes:

[0108] S1051, sequentially depositing a tunneling oxide layer and a first amorphous silicon layer by in-situ doping, the first amorphous silicon layer including at least one boron-containing layer among an intrinsic amorphous silicon layer, a boron-containing amorphous silicon layer and a boron-containing silicon oxide layer.

[0109] Taking a TBC cell as an example, depositing the P-type amorphous silicon composite layer 120 includes sequentially depositing a tunneling oxide layer and a first amorphous silicon layer by in-situ doping, such as LPCVD, PECVD, HWCVD and other related equipment and technologies, wherein the first amorphous silicon layer includes at least one boron-containing layer among an intrinsic amorphous silicon layer, a boron-containing amorphous silicon layer and a boron-containing silicon oxide layer. For example, it can be to sequentially deposit a tunneling oxide layer and a boron-containing amorphous silicon layer, or it can be to sequentially deposit a tunneling oxide layer, an intrinsic amorphous silicon layer and a boron-containing amorphous silicon layer, or it can be to sequentially deposit a tunneling oxide layer, an intrinsic amorphous silicon layer and a boron-containing silicon oxide layer.

[0110] Optionally, as shown in Figure 17 S108, depositing an N-type amorphous silicon composite layer 130 includes:

[0111] S1081, sequentially depositing a tunneling oxide layer and a second amorphous silicon layer by in-situ doping, the second amorphous silicon layer including at least one phosphorus-containing layer among an intrinsic amorphous silicon layer, a phosphorus-containing amorphous silicon layer and a phosphorus-containing silicon oxide layer.

[0112] Still taking a TBC cell as an example, depositing the N-type amorphous silicon composite layer 130 includes sequentially depositing a tunneling oxide layer and a second amorphous silicon layer by in-situ doping, such as LPCVD, PECVD, HWCVD and other related equipment and technologies, wherein the second amorphous silicon layer includes at least one phosphorus-containing layer among an intrinsic amorphous silicon layer, a phosphorus-containing amorphous silicon layer and a phosphorus-containing silicon oxide layer. For example, it can be to sequentially deposit a tunneling oxide layer and a phosphorus-containing amorphous silicon layer, or it can be to sequentially deposit a tunneling oxide layer, an intrinsic amorphous silicon layer and a phosphorus-containing amorphous silicon layer, or it can be to sequentially deposit a tunneling oxide layer, an intrinsic amorphous silicon layer and a phosphorus-containing silicon oxide layer.

[0113] Optionally, as shown in Figure 18 S109, annealing treatment, the annealing temperature being 800-950°C, including:

[0114] S1091, annealing to form a P+ polysilicon layer and an N+ polysilicon layer from the P-type amorphous silicon composite layer 120 and the N-type amorphous silicon composite layer 130, respectively.

[0115] Still taking the TBC cell as an example, when the P-type amorphous silicon composite layer 120 comprises a boron-doped amorphous silicon layer, and when the N-type amorphous silicon composite layer 130 comprises a phosphorus-doped amorphous silicon layer, in the annealing process in the temperature range of 800-950°C, the P-type amorphous silicon composite layer 120 and the N-type amorphous silicon composite layer 130 form a P+ polysilicon layer and an N+ polysilicon layer, respectively.

[0116] Optionally, as shown in S105, the P-type amorphous silicon composite layer 120 is deposited by: Figure 19

[0117] S1052, the intrinsic amorphous silicon i-a Si layer and the P-type amorphous silicon Pa-Si layer or the microcrystalline silicon Pμ-Si layer are sequentially deposited by chemical vapor deposition.

[0118] Taking the preparation of the HBC cell as an example, when the P-type amorphous silicon composite layer 120 is deposited in the back P region, the intrinsic amorphous silicon i-a Si layer and the P-type amorphous silicon Pa-Si layer are sequentially deposited by chemical vapor deposition, or the intrinsic amorphous silicon i-a Si layer and the microcrystalline silicon Pμ-Si layer are sequentially deposited.

[0119] The chemical vapor deposition can be, for example, plasma-enhanced chemical vapor deposition (PECVD), hot-wire chemical vapor deposition (HWCVD), etc., which is not specifically limited in the embodiments of the present application.

[0120] Optionally, as shown in S108, the N-type amorphous silicon composite layer 130 is deposited by: Figure 20

[0121] S1082, the intrinsic amorphous silicon i-a Si layer and the N-type amorphous silicon Na-Si layer or the microcrystalline silicon Nμ-Si layer are sequentially deposited by chemical vapor deposition.

[0122] Taking the preparation of the HBC cell as an example, when the N-type amorphous silicon composite layer 130 is deposited in the back N region, the intrinsic amorphous silicon i-a Si layer and the N-type amorphous silicon Na-Si layer are sequentially deposited by chemical vapor deposition, or the intrinsic amorphous silicon i-a Si layer and the microcrystalline silicon Nμ-Si layer are sequentially deposited.

[0123] Similarly, the chemical vapor deposition can be, for example, plasma-enhanced chemical vapor deposition (PECVD), hot-wire chemical vapor deposition (HWCVD), etc.

[0124] Optionally, as shown in S108, the N-type amorphous silicon composite layer 130 is deposited by: Figure 21

[0125] S201, a first anti-reflection layer is deposited on the front surface of the N-type silicon wafer substrate 100, and the first anti-reflection layer is formed by at least one layer of aluminum oxide, silicon nitride or silicon oxide material.​​​

[0126] S202, depositing a second anti-reflective layer on the back surface of the N-type silicon wafer substrate 100, the second anti-reflective layer being formed by at least one layer of silicon oxide, silicon nitride or silicon oxynitride.

[0127] After the annealing process, a passivation anti-reflective layer can be further deposited, a first anti-reflective layer can be deposited on the front surface of the N-type silicon wafer substrate 100, or a second anti-reflective layer can be deposited on the back surface of the N-type silicon wafer substrate 100. The first anti-reflective layer is formed by at least one layer or a combination of multiple layers of aluminum oxide, silicon nitride or silicon oxide, and the second anti-reflective layer is formed by at least one layer or a combination of multiple layers of silicon oxide, silicon nitride or silicon oxynitride.

[0128] In another aspect of the embodiments of the present application, a back contact type solar cell is provided, which is prepared by using the preparation method of the back contact type solar cell according to any one of the preceding embodiments.

[0129] The above is a description of the scheme taking the N-type silicon wafer substrate 100 as an example, but the embodiments of the present application are not limited thereto, and the P-type silicon wafer substrate is also applicable to the technical scheme of the present application.

[0130] The back contact type solar cell provided by the embodiments of the present application includes but is not limited to the TBC cell and the HBC cell described above, and is prepared by using the preparation method of the back contact type solar cell according to any one of the preceding embodiments. Since the mask layer preparation process specific to the present application is used in the preparation method, the difficulty of preparation and removal of the mask layer is reduced, and the problem of lateral etching that may exist when the mask layer is etched by a wet method is avoided, thereby ensuring the effective isolation between the P region and the N region during the preparation process, so that the prepared back contact type solar cell has a high conversion efficiency. In still another aspect of the embodiments of the present application, another preparation method of a back contact type solar cell is provided, which is applied to the preparation of an HPBC cell. As shown in Figure 22 The method comprises the following steps:

[0131] S301, providing a pretreated P-type silicon wafer substrate, the P-type silicon wafer substrate comprising an N region and a P region intersecting with each other, and further comprising a PN isolation region between the N region and the P region.

[0132] The P-type silicon wafer substrate is used in the preparation of the HPBC cell, and the P-type silicon wafer substrate is pretreated, for example, by texturing, polishing and the like, so that the surface of the P-type silicon wafer substrate is more conducive to the effective formation of subsequent process steps.

[0133] S302, depositing a second passivation layer on the back surface of the P-type silicon wafer substrate.

[0134] S303, a third mask pattern layer is formed on the second passivation layer by laser patterning of the third mask layer, the third mask pattern layer including an N region preset pattern formed in the N region, a layer formed of the PN isolation region remaining material, and a hollow formed by removing the material in the P region.

[0135] The third mask pattern layer is arranged on the second passivation layer, and the third mask pattern layer is a pattern layer formed by laser patterning, the third mask pattern layer including an N region preset pattern formed in the N region, a layer formed of the PN isolation region remaining material, and a hollow formed by removing the material corresponding to the P region.

[0136] S304, the second passivation layer in the N region is cleaned to form an N region preset pattern, and the hollow part in the N region preset pattern exposes the P-type silicon substrate.

[0137] The P-type silicon substrate with the third mask pattern layer is cleaned with an HF solution, and in the third mask pattern layer, the second passivation layer exposed in the hollow part of the pattern reacts with the HF solution to be removed, so that the second passivation layer in the N region is formed into an N region preset pattern, and after the second passivation layer exposed in the third mask pattern layer is removed by the HF solution, the hollow part in the N region preset pattern directly exposes the P-type silicon substrate.

[0138] S305, a tunneling oxide layer and a second amorphous silicon layer are sequentially deposited by in-situ doping, and the second amorphous silicon layer includes at least one phosphorus-containing layer among an intrinsic amorphous silicon layer, a phosphorus-containing amorphous silicon layer, and a phosphorus-containing silicon oxide layer.

[0139] The tunneling oxide layer and the second amorphous silicon layer are sequentially deposited by in-situ doping, such as LPCVD, PECVD, HWCVD, and related equipment and technology, and the second amorphous silicon layer includes at least one phosphorus-containing layer among an intrinsic amorphous silicon layer, a phosphorus-containing amorphous silicon layer, and a phosphorus-containing silicon oxide layer. The tunneling oxide layer, the phosphorus-containing amorphous silicon layer, or the tunneling oxide layer, the intrinsic amorphous silicon layer, and the phosphorus-containing amorphous silicon layer, or the tunneling oxide layer, the intrinsic amorphous silicon layer, and the phosphorus-containing silicon oxide layer can be sequentially deposited.

[0140] S306, the third mask pattern layer is removed by a mechanical method, so that the tunneling oxide layer and the second amorphous silicon layer in the N region form an inverted pattern of the third mask pattern layer.

[0141] The third mask pattern layer is removed mechanically, for example, by tearing, and after the third mask pattern layer is removed, the part of the tunneling oxide layer and the second amorphous silicon layer in the N region on which the third mask pattern layer is located is removed, thereby forming an inverse pattern of the third mask pattern layer on the tunneling oxide layer and the second amorphous silicon layer in the N region. Due to the design of the third mask pattern layer, the material of the PN isolation region is reserved, so that the P region and the N region are not connected during the mask preparation process, and the problem of lateral etching between the P region and the N region in the wet etching process is solved.

[0142] S307, annealing to form an N+ polysilicon layer from the second amorphous silicon layer.

[0143] The annealing treatment is usually performed at a temperature of 800-950 DEG C, and the phosphorus-containing amorphous silicon layer in the second amorphous silicon layer forms an N+ polysilicon layer during the annealing treatment.

[0144] S308, depositing a first anti-reflection layer on the front surface of the P-type silicon wafer substrate, the first anti-reflection layer being formed of at least one layer of aluminum oxide, silicon nitride or silicon oxide material, and depositing a second anti-reflection layer on the back surface of the P-type silicon wafer substrate, the second anti-reflection layer being formed of at least one layer of silicon oxide, silicon nitride or silicon oxynitride material.

[0145] Further deposition of a passivation anti-reflection layer after the annealing treatment includes depositing a first anti-reflection layer on the front surface of the P-type silicon wafer substrate, or depositing a second anti-reflection layer on the back surface of the P-type silicon wafer substrate. The first anti-reflection layer is formed of at least one layer or a combination of multiple layers of aluminum oxide, silicon nitride or silicon oxide material, and the second anti-reflection layer is formed of at least one layer or a combination of multiple layers of silicon oxide, silicon nitride or silicon oxynitride material.

[0146] S309, performing positive and negative electrode metallization treatment on the back surface of the P-type silicon wafer substrate to obtain a back contact type solar cell.

[0147] Similar to the above-described method for preparing a back contact type solar cell, other steps such as cleaning, polishing and planarization can also be included in the above-described method steps. For example, a cleaning step can be further included after the annealing treatment step, and the sample can be cleaned by HF solution to remove the remaining material of the first passivation layer 110 on the surface of the sample, thereby facilitating the subsequent positive and negative electrode metallization process.

[0148] In another aspect of the embodiments, another back contact type solar cell is provided, which is prepared by the above-described method for preparing a back contact type solar cell.

[0149] The back contact type solar cell provided by the embodiments of the present application includes but is not limited to the HPBC cell exemplified above, and is prepared by the preparation method of any one of the back contact type solar cells described above. Since the mask layer preparation process specific to the present application is adopted in the preparation method, the difficulty of preparation and removal of the mask layer is reduced, and the lateral etching problem existing when the mask layer is etched by a wet method is avoided, so that effective isolation between the P region and the N region in the preparation process is ensured, and the prepared back contact type solar cell has high conversion efficiency.

[0150] The above merely provides preferred embodiments of the present application but is not intended to limit the present application. For those skilled in the art, the present application can have various modifications and changes. Any modification, equivalent replacement, improvement, etc. made within the spirit and principle of the present application shall be included in the protection scope of the present application.

Claims

1. A method for producing a back contact solar cell, characterized by, The method comprises the following steps: providing a pretreated N-type silicon wafer substrate, the N-type silicon wafer substrate comprising N and P regions crossing each other, and a PN isolation region between the N and P regions; depositing a first passivation layer on the back surface of the N-type silicon wafer substrate; attaching a first mask pattern layer on the first passivation layer, the first mask pattern layer being formed by patterning a first mask layer by laser, the first mask pattern layer comprising a first region preset pattern formed in a first region, a layer formed by retaining material in the PN isolation region, and a hollow formed by removing material in a second region; solution cleaning to form the first passivation layer in the first region into the first region preset pattern, the hollow part in the first region preset pattern exposing the N-type silicon wafer substrate; depositing a first amorphous silicon composite layer, and mechanically removing the first mask pattern layer so that the first amorphous silicon composite layer in the first region forms an inverse pattern of the first mask pattern layer; attaching a second mask pattern layer on the first passivation layer, the second mask pattern layer being formed by patterning a second mask layer by laser, the second mask pattern layer comprising a second region preset pattern formed in a second region, a layer formed by retaining material in the PN isolation region, and a hollow formed by removing material in the first region; solution cleaning to form the first passivation layer in the second region into the second region preset pattern, the hollow part in the second region preset pattern exposing the N-type silicon wafer substrate; depositing a second amorphous silicon composite layer, and mechanically removing the second mask pattern layer so that the second amorphous silicon composite layer in the second region forms an inverse pattern of the second mask pattern layer; annealing treatment, the annealing temperature being 800-950℃; subjecting the back surface of the N-type silicon wafer substrate to positive and negative electrode metallization treatment to obtain a back contact type solar cell.

2. The method of producing a back contact type solar cell according to claim 1, wherein The first region is a P region, the first region preset pattern is a P region preset pattern, the first amorphous silicon composite layer is a P-type amorphous silicon composite layer, the second region is an N region, the second region preset pattern is an N region preset pattern, and the second amorphous silicon composite layer is an N-type amorphous silicon composite layer. The method comprises the following steps: providing a pretreated N-type silicon wafer substrate, the N-type silicon wafer substrate comprising N and P regions crossing each other, and a PN isolation region between the N and P regions; depositing a first passivation layer on the back surface of the N-type silicon wafer substrate; attaching a first mask pattern layer on the first passivation layer, the first mask pattern layer being formed by patterning a first mask layer by laser, the first mask pattern layer comprising a P region preset pattern formed in a P region, a layer formed by retaining material in the PN isolation region, and a hollow formed by removing material in an N region; solution cleaning to form the first passivation layer in the P region into the P region preset pattern, the hollow part in the P region preset pattern exposing the N-type silicon wafer substrate; depositing a P-type amorphous silicon composite layer, and mechanically removing the first mask pattern layer so that the P-type amorphous silicon composite layer in the P region forms an inverse pattern of the first mask pattern layer; A second mask pattern layer is formed on the first passivation layer by lasing the second mask layer, the second mask pattern layer including a preset pattern in the N region, a layer of remaining material in the PN isolation region, and a hollow in the P region; The first passivation layer of the N region is dissolved to form the preset pattern in the N region, and the hollow part in the preset pattern in the N region exposes the N-type silicon substrate; An N-type amorphous silicon composite layer is deposited, and the second mask pattern layer is removed mechanically to form an inverse pattern of the second mask pattern layer in the N region; Annealing treatment is performed at a temperature of 800-950°C; The back surface of the N-type silicon substrate is subjected to positive and negative electrode metallization treatment to obtain a back contact type solar cell.

3. The method of producing a back contact type solar cell according to claim 2, wherein The deposition of the first passivation layer on the back surface of the N-type silicon substrate includes: The first passivation layer is a silicon nitride layer or a silicon oxide layer, and the thickness of the first passivation layer is between 20-80 nm.

4. The method for manufacturing a back contact type solar cell according to claim 2 or 3, wherein The first mask pattern layer is formed on the first passivation layer by lasing the first mask layer, the first mask pattern layer including a preset pattern in the P region, a layer of remaining material in the PN isolation region, and a hollow in the N region. The first mask pattern layer includes a polymer film layer and an adhesive layer, and the polymer film layer is attached to the first passivation layer through the adhesive layer.

5. The method of producing a back contact type solar cell according to claim 4, wherein The polymer film layer is made of a material with a temperature resistance greater than 350°C, the thickness of the polymer film layer is between 5-100 μm, and the thickness of the adhesive layer is between 3-10 μm.

6. The method of producing a back contact type solar cell according to claim 2, wherein The first mask pattern layer is formed by lasing the first mask layer, and the first mask pattern layer includes a preset pattern in the P region, a layer of remaining material in the PN isolation region, and a hollow in the N region. The preset pattern in the P region includes the projection pattern of the main grid electrode and the auxiliary grid electrode on the N-type silicon substrate. The second mask pattern layer is formed by lasing the second mask layer, and the second mask pattern layer includes a preset pattern in the N region, a layer of remaining material in the PN isolation region, and a hollow in the P region. The preset pattern in the N region includes the projection pattern of the main grid electrode and the auxiliary grid electrode on the N-type silicon substrate.

7. The method of producing a back contact type solar cell according to claim 2, wherein The deposition of the P-type amorphous silicon composite layer, the mechanical removal of the first mask pattern layer, and the formation of an inverse pattern of the first mask pattern layer in the P region of the P-type amorphous silicon composite layer include: Deposition of a P-type amorphous silicon composite layer; Deposition of a passivation layer; Mechanical removal of the first mask pattern layer to form an inverse pattern of the first mask pattern layer in the P region of the P-type amorphous silicon composite layer.

8. The method of producing a back contact type solar cell according to claim 2, wherein The width of the PN isolation region is between 20 μm-60 μm.

9. The method of producing a back contact type solar cell according to claim 2, wherein The provision of a pretreated N-type silicon substrate includes: Providing an N-type silicon wafer; The N-type silicon wafer is subjected to texturing treatment and back surface polishing treatment to obtain a pretreated N-type silicon substrate.

10. The method of producing a back contact type solar cell according to claim 2, wherein The deposition of the P-type amorphous silicon composite layer includes: The tunneling oxide layer and the first amorphous silicon layer are sequentially deposited by in-situ doping, and the first amorphous silicon layer comprises at least one boron-containing layer selected from the group consisting of intrinsic amorphous silicon layer, boron-containing amorphous silicon layer and boron-containing silicon oxide layer.

11. The method of producing a back contact solar cell according to claim 10, wherein The deposition of the N-type amorphous silicon composite layer comprises: The tunneling oxide layer and the second amorphous silicon layer are sequentially deposited by in-situ doping, and the second amorphous silicon layer comprises at least one phosphorus-containing layer selected from the group consisting of intrinsic amorphous silicon layer, phosphorus-containing amorphous silicon layer and phosphorus-containing silicon oxide layer.

12. The method of producing a back contact solar cell according to claim 10 or 11, wherein The annealing treatment is performed at an annealing temperature of 800-950 ℃. The annealing treatment is performed to form P+ polysilicon layer and N+ polysilicon layer from the P-type amorphous silicon composite layer and the N-type amorphous silicon composite layer, respectively.

13. The method of producing a back contact type solar cell according to claim 2, wherein The deposition of the P-type amorphous silicon composite layer comprises: The intrinsic amorphous silicon i-a Si layer and the P-type amorphous silicon Pa-Si layer or microcrystalline silicon Pμ-Si layer are sequentially deposited by chemical vapor deposition.

14. The method of producing a back contact solar cell according to claim 13, wherein The deposition of the N-type amorphous silicon composite layer comprises: The intrinsic amorphous silicon i-a Si layer and the N-type amorphous silicon Na-Si layer or microcrystalline silicon Nμ-Si layer are sequentially deposited by chemical vapor deposition.

15. The method of producing a back contact type solar cell according to claim 2, wherein After the annealing treatment, the method further comprises: A first anti-reflection layer is deposited on the front surface of the N-type silicon wafer substrate, and the first anti-reflection layer is formed by at least one layer of aluminum oxide, silicon nitride or silicon oxide material; A second anti-reflection layer is deposited on the back surface of the N-type silicon wafer substrate, and the second anti-reflection layer is formed by at least one layer of silicon oxide, silicon nitride or silicon oxynitride material.

16. A back contact solar cell, characterized by, The back contact type solar cell is prepared by the preparation method of any one of claims 1-15.

17. A method of manufacturing a back contact solar cell, characterized by, Comprise: A pretreated P-type silicon wafer substrate is provided, and the P-type silicon wafer substrate comprises N region and P region intersecting with each other, and PN isolation region between the N region and the P region; A second passivation layer is deposited on the back surface of the P-type silicon wafer substrate; A third mask pattern layer is formed by adhering on the second passivation layer, and the third mask pattern layer is formed by patterning a third mask layer by laser, and the third mask pattern layer comprises N region preset pattern formed in the N region, layer formed by retaining material in the PN isolation region, and hollow formed by removing material in the P region; Solution cleaning is performed to form the N region preset pattern in the second passivation layer of the N region, and the hollow part in the N region preset pattern exposes the P-type silicon wafer substrate; The tunneling oxide layer and the second amorphous silicon layer are sequentially deposited by in-situ doping, and the second amorphous silicon layer comprises at least one phosphorus-containing layer selected from the group consisting of intrinsic amorphous silicon layer, phosphorus-containing amorphous silicon layer and phosphorus-containing silicon oxide layer. The third mask pattern layer is removed by mechanical method to form an inverse pattern of the third mask pattern layer in the tunneling oxide layer and the second amorphous silicon layer of the N region; The second amorphous silicon layer is annealed to form N+ polysilicon layer; A first anti-reflection layer is deposited on the front surface of the P-type silicon wafer substrate, and the first anti-reflection layer is formed by at least one layer of aluminum oxide, silicon nitride or silicon oxide material, and a second anti-reflection layer is deposited on the back surface of the P-type silicon wafer substrate, and the second anti-reflection layer is formed by at least one layer of silicon oxide, silicon nitride or silicon oxynitride material; The back surface of the P-type silicon wafer substrate is subjected to positive and negative electrode metallization treatment to obtain a back contact type solar cell.

18. A back contact solar cell, characterized by, The back contact type solar cell is prepared by using the preparation method of claim 17.

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