Photoelectric sensor preparation process

Abstract

The invention discloses a photoelectric sensor preparation process, which comprises the following steps of: 1, preparing an isolation groove region pattern; step 2, etching to form an isolation groove; step 3, depositing SiO2 to form a spacer layer; 4, depositing Si3N4 (silicon nitride); step 5, preparing a trapezoidal groove area pattern; step 6, etching to form a trapezoidal groove; 7, removing SiO2 and Si3N4 on the upper surface and the lower surface; 8, phosphorus ions are injected to form a shielding layer; step 9, preparing an N-type semiconductor region pattern; 10, phosphorus ions are injected to form an N-type semiconductor; based on the design principle of a back contact solar cell, the PN junctions, the positive electrode and the negative electrode are designed on the back face of the substrate, the light sensing faces of different angles are machined on the front face of the substrate, and the incident angle of light is judged according to the difference of electric signals on the PN junctions under the light sensing faces of different angles. The manufacturing difficulty and the manufacturing cost are effectively reduced, and the functionality and the reliability are improved.

Description

Technical Field

[0001] The invention relates to the technical field of sensors, and in particular to a photoelectric sensor preparation process. Background Art

[0002] Photoelectric sensors can convert light signals into electrical signals, and mainly detect changes in light intensity, color, frequency and other characteristics to measure physical quantities and detect the existence, position and motion state of objects. However, when detecting the incident angle of light, existing photoelectric sensors need to accurately arrange and fix multiple photoelectric sensors in a specific array structure, which greatly increases the investment in production equipment and the complexity of the process, resulting in increased material costs and manufacturing process costs. In addition, since each photoelectric sensor has certain differences, it will have an adverse effect on the performance stability and accuracy of the sensor array, resulting in the need for complex calibration and testing processes to improve consistency, which further increases production costs. Therefore, a photoelectric sensor preparation process is proposed. Summary of the invention

[0003] The object of the present invention is to provide a photoelectric sensor preparation process to solve the problems raised in the above background technology.

[0004] To achieve the above-mentioned purpose, the present invention provides the following technical solutions: a photoelectric sensor preparation process, comprising step one, preparing an isolation groove area pattern; step two, etching to form an isolation groove; step three, depositing SiO2 to form a separation layer; step four, depositing Si3N4; step five, preparing a trapezoidal groove area pattern; step six, etching to form a trapezoidal groove; step seven, removing SiO2 and Si3N4 on the upper and lower surfaces; step eight, injecting phosphorus ions to form a shielding layer; step nine, preparing an N-type semiconductor area pattern; step ten, injecting phosphorus ions to form an N-type semiconductor; step eleven, preparing a P-type semiconductor area pattern; step twelve, injecting boron ions to form a P-type semiconductor; step thirteen, depositing Si3N4 to form an isolation layer; step fourteen, preparing positive and negative electrode area patterns; step fifteen, preparing positive and negative electrodes;

[0005] In the above step 1, a clean substrate is taken, a photoresist is coated on the lower surface of the substrate, and after exposure and development, a regional pattern of the isolation groove is obtained;

[0006] In the above step 2, the lower surface of the substrate is processed by directional ion reaction etching technology, and then the photoresist on the substrate is removed to obtain the isolation groove;

[0007] In the above step 3, SiO2 is deposited on the upper and lower surfaces of the substrate using a low-pressure chemical vapor deposition method, and SiO2 is filled in the isolation groove to form a separation layer;

[0008] In the above step 4, Si3N4 is deposited on the upper and lower surfaces of the substrate using a low pressure chemical vapor deposition method;

[0009] In the above step 5, a photoresist is coated on the upper surface of the substrate, and after exposure and development, a regional pattern of trapezoidal grooves is obtained;

[0010] In the above step 6, the SiO2 and Si3N4 in the trapezoidal groove area pattern are removed by reactive ion etching technology, and then the upper surface of the substrate is processed by reactive ion etching technology to obtain the trapezoidal groove;

[0011] In the above step 7, the SiO2 and Si3N4 on the upper and lower surfaces of the substrate are removed by reactive ion etching technology;

[0012] In the above step eight, phosphorus ions are implanted on the upper surface of the substrate using ion implantation technology to obtain a shielding layer;

[0013] In the above step nine, a photoresist is coated on the lower surface of the substrate, and after exposure and development, a regional pattern of an N-type semiconductor is obtained;

[0014] In the above step 10, phosphorus ions are implanted on the lower surface of the substrate using ion implantation technology to remove the photoresist on the substrate to obtain an N-type semiconductor;

[0015] In the above step 11, a photoresist is coated on the lower surface of the substrate, and after exposure and development, a regional pattern of a P-type semiconductor is obtained;

[0016] In the above step 12, boron ions are implanted on the lower surface of the substrate using ion implantation technology to remove the photoresist on the substrate to obtain a P-type semiconductor;

[0017] In the above step thirteen, Si3N4 is deposited on the lower surface of the substrate by plasma enhanced chemical vapor deposition to obtain an isolation layer;

[0018] In the above step 14, a photoresist is coated on the lower surface of the substrate, and after exposure and development, the regional patterns of the positive and negative electrodes are obtained;

[0019] In the above step fifteen, reactive ion etching technology is used to remove Si3N4 in the positive and negative electrode area patterns, and physical vapor deposition technology is used to sputter metal aluminum on the lower surface of the substrate. The positive and negative electrodes are obtained after stripping and removing the photoresist on the substrate.

[0020] Preferably, in step 2, the isolation groove has a depth of 70 μm and a width of 5 μm.

[0021] Preferably, in step three, the deposition conditions are: temperature 700° C., pressure 100 mTorr, deposition rate 5-10 nm / min, and time 3 h.

[0022] Preferably, in step 4, the deposition conditions are: temperature 800° C., pressure 100 mTorr, deposition rate 3-4.5 nm / min, and time 40 min.

[0023] Preferably, in step six, the depth of the trapezoidal groove is 250 μm, and the etching conditions are: the etching solution is a potassium hydroxide solution with a concentration of 33%, and the etching temperature is 80° C.

[0024] Preferably, in step eight, the thickness of the shielding layer is 1 μm, and the phosphorus ion doping concentration is 5×10 19 cm -3 The ion implantation conditions are as follows: the ion implantation energy is 30 keV, and after implantation, rapid thermal annealing is performed at 1050°C for 1 min.

[0025] Preferably, in step 10, the width of the N-type semiconductor is 10 μm, the thickness is 0.6 μm, and the doping concentration is 6.4×10 19 cm -3 The ion implantation conditions are as follows: the ion implantation energy is 30 keV, and after implantation, rapid thermal annealing is performed at 1050°C for 1 min.

[0026] Preferably, in step 12, the width of the P-type semiconductor is 110 μm, the thickness is 0.6 μm, and the doping concentration is 6.4×10 19 cm -3 The ion implantation conditions are as follows: the ion implantation energy is 30 keV, and after implantation, rapid thermal annealing is performed at 1050°C for 1 min.

[0027] Preferably, in step thirteen, the thickness of the isolation layer is 100 nm, and the deposition conditions are: temperature of 250° C., pressure of 2 Torr, deposition rate of 10 nm / min, and time of 10 min.

[0028] Preferably, in step fifteen, the voltage used for sputtering the metal aluminum is 500V.

[0029] Compared with the prior art, the beneficial effects of the present invention are as follows: the present invention is based on the design principle of back-contact solar cells, designs PN junctions and positive and negative electrodes on the back of the substrate, processes photosensitive surfaces of different angles on the front of the substrate, and uses the difference in electrical signals on the PN junctions under photosensitive surfaces of different angles to judge the incident angle of light. Compared with the existing array-type photoelectric sensors, the present invention effectively reduces the manufacturing difficulty and cost, and improves functionality and reliability. BRIEF DESCRIPTION OF THE DRAWINGS

[0030] Figure 1 is a flow chart of the steps of the present invention;

[0031] Figure 2 The figure is a flow chart of the method of the present invention. DETAILED DESCRIPTION

[0032] The following will be combined with the drawings in the embodiments of the present invention to clearly and completely describe the technical solutions in the embodiments of the present invention. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present invention.

[0033] Please see attached Figure 1 -Attached Figure 2 , an embodiment provided by the present invention: a photoelectric sensor preparation process, comprising step one, preparing an isolation groove area pattern; step two, etching to form an isolation groove; step three, depositing SiO2 to form a separation layer; step four, depositing Si3N4; step five, preparing a trapezoidal groove area pattern; step six, etching to form a trapezoidal groove; step seven, removing SiO2 and Si3N4 on the upper and lower surfaces; step eight, injecting phosphorus ions to form a shielding layer; step nine, preparing an N-type semiconductor area pattern; step ten, injecting phosphorus ions to form an N-type semiconductor; step eleven, preparing a P-type semiconductor area pattern; step twelve, injecting boron ions to form a P-type semiconductor; step thirteen, depositing Si3N4 to form an isolation layer; step fourteen, preparing positive and negative electrode area patterns; step fifteen, preparing positive and negative electrodes;

[0034] In the above step 1, a clean substrate is taken, a photoresist is coated on the lower surface of the substrate, and after exposure and development, a regional pattern of the isolation groove is obtained;

[0035] In the above step 2, the lower surface of the substrate is processed by directional ion reaction etching technology, and then the photoresist on the substrate is removed to obtain an isolation groove with a depth of 70 μm and a width of 5 μm;

[0036] In the above step 3, SiO2 is deposited on the upper and lower surfaces of the substrate using a low-pressure chemical vapor deposition method, and SiO2 is filled in the isolation groove to form a separation layer. The deposition conditions are: temperature 700°C, pressure 100mTorr, deposition rate 5-10nm / min, and time 3h;

[0037] In the above step 4, Si3N4 is deposited on the upper and lower surfaces of the substrate using a low-pressure chemical vapor deposition method, and the deposition conditions are: temperature 800°C, pressure 100mTorr, deposition rate 3-4.5nm / min, and time 40min;

[0038] In the above step 5, a photoresist is coated on the upper surface of the substrate, and after exposure and development, a regional pattern of trapezoidal grooves is obtained;

[0039] In the above step 6, the SiO2 and Si3N4 in the trapezoidal groove area pattern are removed by reactive ion etching technology, and then the upper surface of the substrate is processed by reactive ion etching technology to obtain a trapezoidal groove with a depth of 250 μm. The etching conditions are: the etching solution uses a potassium hydroxide solution with a concentration of 33% and the etching temperature is 80°C;

[0040] In the above step 7, the SiO2 and Si3N4 on the upper and lower surfaces of the substrate are removed by reactive ion etching technology;

[0041] In the above step eight, phosphorus ions are implanted on the upper surface of the substrate by ion implantation technology to obtain a shielding layer with a thickness of 1 μm and a phosphorus ion doping concentration of 5×10 19 cm -3 ,The ion implantation conditions are: the ion implantation energy is 30 keV, and after implantation, rapid thermal annealing is performed at 1050°C for 1 min;

[0042] In the above step nine, a photoresist is coated on the lower surface of the substrate, and after exposure and development, a regional pattern of an N-type semiconductor is obtained;

[0043] In the above step 10, phosphorus ions are implanted on the lower surface of the substrate by ion implantation technology, and the photoresist on the substrate is removed to obtain an N-type semiconductor. The width of the N-type semiconductor is 10 μm, the thickness is 0.6 μm, and the doping concentration is 6.4×10 19 cm -3 ,The ion implantation conditions are: the ion implantation energy is 30 keV, and after implantation, rapid thermal annealing is performed at 1050°C for 1 min;

[0044] In the above step 11, a photoresist is coated on the lower surface of the substrate, and after exposure and development, a regional pattern of a P-type semiconductor is obtained;

[0045] In the above step 12, boron ions are implanted on the lower surface of the substrate by ion implantation technology, and the photoresist on the substrate is removed to obtain a P-type semiconductor. The width of the P-type semiconductor is 110 μm, the thickness is 0.6 μm, and the doping concentration is 6.4×10 19 cm -3 ,The ion implantation conditions are: the ion implantation energy is 30 keV, and after implantation, rapid thermal annealing is performed at 1050°C for 1 min;

[0046] In the above step thirteen, Si3N4 is deposited on the lower surface of the substrate by plasma enhanced chemical vapor deposition to obtain an isolation layer, the thickness of the isolation layer is 100nm, and the deposition conditions are: temperature 250°C, pressure 2Torr, deposition rate 10nm / min, and time 10min;

[0047] In the above step 14, a photoresist is coated on the lower surface of the substrate, and after exposure and development, the regional patterns of the positive and negative electrodes are obtained;

[0048] In the above step fifteen, reactive ion etching technology is used to remove Si3N4 in the positive and negative electrode area patterns, and physical vapor deposition technology is used to sputter metal aluminum on the lower surface of the substrate. After stripping and removing the photoresist on the substrate, the positive and negative electrodes are obtained. The voltage used for sputtering metal aluminum is 500V.

[0049] Based on the above, the advantage of the present invention is that when the present invention is used, a PN junction and positive and negative electrodes are designed on the back of the substrate, and a trapezoidal groove is processed on the front of the substrate as a photosensitive surface. The difference in electrical signals on the PN junction under the photosensitive surface at different angles is used to judge the incident angle of light. Compared with the existing photoelectric sensor preparation process, the present invention has the advantages of simple manufacturing process and low manufacturing cost, and the manufactured photoelectric sensor has a smaller size, stronger functionality and higher reliability, can achieve high-precision light intensity and light angle detection, and is suitable for miniaturized high-precision electronic equipment.

[0050] It will be apparent to those skilled in the art that the invention is not limited to the details of the exemplary embodiments described above and that the invention can be implemented in other specific forms without departing from the spirit or essential features of the invention. Therefore, the embodiments should be considered exemplary and non-limiting in all respects, and the scope of the invention is defined by the appended claims rather than the foregoing description, and it is intended that all variations falling within the meaning and scope of the equivalent elements of the claims be included in the invention. Any reference numeral in a claim should not be considered as limiting the claim to which it relates.

Claims

1. A photoelectric sensor preparation process, comprising step 1, preparing an isolation groove area pattern; step 2, etching to form an isolation groove; step 3, depositing SiO2 to form a separation layer; step 4, depositing Si3N4; step 5, preparing a trapezoidal groove area pattern; step 6, etching to form a trapezoidal groove; step 7, removing SiO2 and Si3N4 on the upper and lower surfaces; step 8, injecting phosphorus ions to form a shielding layer; step 9, preparing an N-type semiconductor area pattern; Step 10, injecting phosphorus ions to form an N-type semiconductor; Step 11, preparing a P-type semiconductor region pattern; Step 12, injecting boron ions to form a P-type semiconductor; Step 13, depositing Si3N4 to form an isolation layer; Step 14, preparing positive and negative electrode region patterns; Step 15, preparing positive and negative electrodes; It is characterized in that: In the above step 1, a clean substrate is taken, a photoresist is coated on the lower surface of the substrate, and after exposure and development, a regional pattern of the isolation groove is obtained; In the above step 2, the lower surface of the substrate is processed by directional ion reaction etching technology, and then the photoresist on the substrate is removed to obtain the isolation groove; In the above step 3, SiO2 is deposited on the upper and lower surfaces of the substrate using a low-pressure chemical vapor deposition method, and SiO2 is filled in the isolation groove to form a separation layer; In the above step 4, Si3N4 is deposited on the upper and lower surfaces of the substrate using a low pressure chemical vapor deposition method; In the above step 5, a photoresist is coated on the upper surface of the substrate, and after exposure and development, a regional pattern of trapezoidal grooves is obtained; In the above step 6, the SiO2 and Si3N4 in the trapezoidal groove area pattern are removed by reactive ion etching technology, and then the upper surface of the substrate is processed by reactive ion etching technology to obtain the trapezoidal groove; In the above step 7, the SiO2 and Si3N4 on the upper and lower surfaces of the substrate are removed by reactive ion etching technology; In the above step eight, phosphorus ions are implanted on the upper surface of the substrate using ion implantation technology to obtain a shielding layer; In the above step nine, a photoresist is coated on the lower surface of the substrate, and after exposure and development, a regional pattern of an N-type semiconductor is obtained; In the above step 10, phosphorus ions are implanted on the lower surface of the substrate using ion implantation technology to remove the photoresist on the substrate to obtain an N-type semiconductor; In the above step 11, a photoresist is coated on the lower surface of the substrate, and after exposure and development, a regional pattern of a P-type semiconductor is obtained; In the above step 12, boron ions are implanted on the lower surface of the substrate using ion implantation technology to remove the photoresist on the substrate to obtain a P-type semiconductor; In the above step thirteen, Si3N4 is deposited on the lower surface of the substrate by plasma enhanced chemical vapor deposition to obtain an isolation layer; In the above step 14, a photoresist is coated on the lower surface of the substrate, and after exposure and development, the regional patterns of the positive and negative electrodes are obtained; In the above step fifteen, reactive ion etching technology is used to remove Si3N4 in the positive and negative electrode area patterns, and physical vapor deposition technology is used to sputter metal aluminum on the lower surface of the substrate. The positive and negative electrodes are obtained after stripping and removing the photoresist on the substrate.

2. A photoelectric sensor preparation process according to claim 1, characterized in that: In the step 2, the isolation groove has a depth of 70 μm and a width of 5 μm.

3. The photoelectric sensor preparation process according to claim 1, characterized in that: In the step three, the deposition conditions are: temperature 700° C., pressure 100 mTorr, deposition rate 5-10 nm / min, and time 3 h.

4. The photoelectric sensor preparation process according to claim 1, characterized in that: In the step 4, the deposition conditions are: temperature 800° C., pressure 100 mTorr, deposition rate 3-4.5 nm / min, and time 40 min.

5. The photoelectric sensor preparation process according to claim 1, characterized in that: In the step six, the depth of the trapezoidal groove is 250 μm, and the etching conditions are: the etching solution is a potassium hydroxide solution with a concentration of 33%, and the etching temperature is 80° C.

6. The photoelectric sensor preparation process according to claim 1, characterized in that: In step eight, the thickness of the shielding layer is 1 μm, and the phosphorus ion doping concentration is 5×10 19 cm -3 The ion implantation conditions are as follows: the ion implantation energy is 30 keV, and after implantation, rapid thermal annealing is performed at 1050°C for 1 min.

7. The photoelectric sensor preparation process according to claim 1, characterized in that: In step 10, the width of the N-type semiconductor is 10 μm, the thickness is 0.6 μm, and the doping concentration is 6.4×10 19 cm -3 The ion implantation conditions are as follows: the ion implantation energy is 30 keV, and after implantation, rapid thermal annealing is performed at 1050°C for 1 min.

8. The photoelectric sensor preparation process according to claim 1, characterized in that: In step 12, the width of the P-type semiconductor is 110 μm, the thickness is 0.6 μm, and the doping concentration is 6.4×10 19 cm -3 The ion implantation conditions are as follows: the ion implantation energy is 30 keV, and after implantation, rapid thermal annealing is performed at 1050°C for 1 min.

9. The photoelectric sensor preparation process according to claim 1, characterized in that: In the step thirteen, the thickness of the isolation layer is 100 nm, and the deposition conditions are: temperature is 250° C., pressure is 2 Torr, deposition rate is 10 nm / min, and time is 10 min.

10. The photoelectric sensor preparation process according to claim 1, characterized in that: In the step fifteen, the voltage used for sputtering the metal aluminum is 500V.

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