Display panel and display device

Abstract

The embodiment of the invention provides a display panel and a display device. The display panel comprises a device area and a peripheral area located on the side, facing the edge of the display panel, of the device area. The display panel further comprises a substrate, a transistor array layer, an organic planarization layer and a packaging layer, the organic planarization layer is located on the side, away from the substrate, of the transistor array layer, and the packaging layer is located on the side, away from the substrate, of the organic planarization layer; wherein the organic planarization layer and the packaging layer extend from the device area to the peripheral area, in the peripheral area, a clearance groove is formed in the organic planarization layer, and at least part of the clearance groove is filled with the packaging layer. According to the display panel, a path for transmitting external water vapor by the organic planarization layer can be cut off, and the external water vapor can be prevented from invading into the display panel through the organic planarization layer to damage devices in the display panel.

Description

Technical Field

[0001] The present application relates to the field of display technology, and in particular to a display panel and a display device. Background Art

[0002] Micro-LED display panels have the advantages of high brightness, long life, fast response and high resolution, and have become the focus of current research.

[0003] In existing Micro-LED display panels, external water vapor can easily enter the display panel along the organic film, corroding the components inside the display panel and causing component failure. Therefore, a solution is urgently needed. Summary of the invention

[0004] In view of this, embodiments of the present application provide a display panel and a display device to solve the above problems.

[0005] In a first aspect, an embodiment of the present application provides a display panel, comprising a device area and a peripheral area located on the side of the device area facing the edge of the display panel; the display panel also comprises a substrate, a transistor array layer, an organic planarization layer and an encapsulation layer, the organic planarization layer is located on the side of the transistor array layer away from the substrate, and the encapsulation layer is located on the side of the organic planarization layer away from the substrate; wherein the organic planarization layer and the encapsulation layer extend from the device area to the peripheral area, and in the peripheral area, a clearance groove is provided in the organic planarization layer, and the encapsulation layer fills at least part of the clearance groove.

[0006] In a second aspect, an embodiment of the present application provides a display device, comprising a display panel provided in the first aspect.

[0007] In the embodiment of the present application, a clearance groove is provided in the organic planarization layer, and the entity part of the organic planarization layer can be disconnected or cut off at the clearance groove. If the entity part of the organic planarization layer is disconnected at the clearance groove, and the encapsulation layer fills at least part of the clearance groove, the encapsulation layer can be located between the entity parts of the disconnected organic planarization layer, and the path for the organic planarization layer to transmit external water vapor is cut off, which is conducive to preventing external water vapor from invading the interior of the display panel through the organic planarization layer and damaging the devices inside the display panel.

[0008] If the physical part of the organic planarization layer ends at the clearance groove and the encapsulation layer fills at least part of the clearance groove, the encapsulation layer can more reliably cover the side wall of the physical part of the organic planarization layer facing the edge of the display panel, thereby preventing external water and oxygen from invading the organic planarization layer, thereby helping to prevent external water vapor from invading the interior of the display panel along the organic planarization layer and damaging the devices inside the display panel. BRIEF DESCRIPTION OF THE DRAWINGS

[0009] In order to more clearly illustrate the technical solutions of the embodiments of the present application, the drawings required for use in the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying creative labor.

[0010] Figure 1 A schematic diagram of a structure of a display panel in the prior art;

[0011] Figure 2 A schematic plan view of a display panel provided in an embodiment of the present application;

[0012] Figure 3 for Figure 2 A schematic cross-sectional view along the NN' tangent line;

[0013] Figure 4 for Figure 2 Another schematic cross-sectional view along the NN' tangent line;

[0014] Figure 5 A partially enlarged schematic diagram of a first peripheral area provided in an embodiment of the present application;

[0015] Figure 6 for Figure 5 A schematic cross-sectional view along the MM' tangent line;

[0016] Figure 7 for Figure 5 Another cross-sectional schematic diagram along the MM' tangent line;

[0017] Figure 8 for Figure 5 A schematic cross-sectional view along the CC' tangent line;

[0018] Fig. 9 A partial enlarged schematic diagram of another first peripheral area provided in an embodiment of the present application;

[0019] Fig.10 A partial enlarged schematic diagram of another first peripheral area provided in an embodiment of the present application;

[0020] Fig.11 for Figure 5 Another cross-sectional schematic diagram along the CC' tangent line;

[0021] Fig.12 A partial enlarged schematic diagram of another first peripheral area provided in an embodiment of the present application;

[0022] Fig.13 for Figure 5 Another cross-sectional schematic diagram along the MM' tangent line;

[0023] Fig.14 for Figure 5 Another cross-sectional schematic diagram along the MM' tangent line;

[0024] Fig.15 A partial enlarged schematic diagram of another first peripheral area provided in an embodiment of the present application;

[0025] Fig.16 for Fig.15 A schematic cross-sectional view along the DD' tangent line;

[0026] Fig.17 for Fig.15 A schematic cross-sectional view along the EE' tangent line;

[0027] Fig.18 A partial enlarged schematic diagram of another first peripheral area provided in an embodiment of the present application;

[0028] Fig.19 A partial enlarged schematic diagram of another first peripheral area provided in an embodiment of the present application;

[0029] Fig. 20 A partial enlarged schematic diagram of another first peripheral area provided in an embodiment of the present application;

[0030] Fig.21 A partial enlarged schematic diagram of another first peripheral area provided in an embodiment of the present application;

[0031] Fig. 22 for Fig.21 A schematic cross-sectional view along the FF' tangent line;

[0032] Fig.23 A partial enlarged schematic diagram of another first peripheral area provided in an embodiment of the present application;

[0033] Fig.24 A schematic plan view of another display panel provided in an embodiment of the present application;

[0034] Fig.25 A schematic diagram of a display device provided in an embodiment of the present application. DETAILED DESCRIPTION

[0035] In order to better understand the technical solution of the present application, the embodiments of the present application are described in detail below with reference to the accompanying drawings.

[0036] It should be clear that the described embodiments are only part of the embodiments of the present application, rather than all the embodiments. Based on the embodiments in the present application, all other embodiments obtained by ordinary technicians in the field without creative work are within the scope of protection of the present application.

[0037] The terms used in the embodiments of the present application are only for the purpose of describing specific embodiments, and are not intended to limit the present application. The singular forms "a", "said" and "the" used in the embodiments of the present application and the appended claims are also intended to include plural forms, unless the context clearly indicates other meanings.

[0038] It should be understood that the term "and / or" used in this article is only a description of the association relationship of associated objects, indicating that there can be three relationships. For example, A and / or B can represent: A exists alone, A and B exist at the same time, and B exists alone. In addition, the character " / " in this article generally indicates that the associated objects before and after are in an "or" relationship.

[0039] Figure 1 The figure is a schematic diagram of a structure of a display panel in the prior art.

[0040] In the prior art, Figure 1 As shown, the display panel 01 ′ includes a device area AA′ and a peripheral area NA′ located on a side of the device area AA′ facing an edge of the display panel 01 ′, and the peripheral area NA′ surrounds the device area AA′.

[0041] like Figure 1 As shown, the display panel 01' also includes a substrate 10' and a transistor array layer 20', an organic planarization layer 30' and a first inorganic layer 40' located on one side of the substrate 10', the organic planarization layer 30' is located on the side of the transistor array layer 20' away from the substrate 10', the first inorganic layer 40' is located on the side of the organic planarization layer 30' away from the substrate 10', and the organic planarization layer 30' and the first inorganic layer 40' both extend from the device area AA' to the outer ring area NA'.

[0042] In the peripheral area NA', the first inorganic layer 40' covers the sidewalls of the organic planarization layer 30' to prevent external water vapor from invading the device area AA' of the display panel 01' through the organic planarization layer 30'.

[0043] However, the inventor of the present application has found through research that in the existing display panel 01', the thickness of the organic planarization layer 30' is usually relatively large. In the peripheral area NA', the step difference at the side wall of the organic planarization layer 30' is usually relatively large, which results in a poor effect of the first inorganic layer 40' covering the side wall of the organic planarization layer 30', and the first inorganic layer 40' located at the side wall of the organic planarization layer 30' is relatively thin. In the subsequent manufacturing process, the first inorganic layer 40' at the side wall of the organic planarization layer 30' may be damaged, thereby causing external water vapor to intrude into the interior of the display panel 01' along the organic planarization layer 30', causing the device in the display panel 01' to fail.

[0044] In view of this, the inventor of the present application proposed a technical solution to solve the problems in the prior art.

[0045] Figure 2 A schematic plan view of a display panel provided in an embodiment of the present application, Figure 3 for Figure 2 A schematic cross-sectional view along the NN' tangent line.

[0046] The present application embodiment provides a display panel 01, such as Figure 2 As shown, the display panel 01 includes a device area AA and a peripheral area NA located on the side of the device area AA facing the edge of the display panel 01, and the peripheral area NA may surround the device area AA. Exemplarily, the device area AA may include electronic devices such as light-emitting devices, pixel circuits, shift registers, electrostatic discharge units, and demultiplexers in the display panel 01.

[0047] Combination Figure 3 As shown, the display panel 01 further includes a substrate 10 and a transistor array layer 20, an organic planarization layer 30 and an encapsulation layer 40 located on one side of the substrate 10. The organic planarization layer 30 is located on the side of the transistor array layer 20 away from the substrate 10, and the encapsulation layer 40 is located on the side of the organic planarization layer 30 away from the substrate 10. The organic planarization layer 30 can be a single-layer or multi-layer structure.

[0048] The organic planarization layer 30 and the encapsulation layer 40 both extend from the device area AA to the peripheral area NA. In the peripheral area NA, a clearance groove 31 is provided in the organic planarization layer 30, and the encapsulation layer 40 fills at least a portion of the clearance groove 31. The material of the encapsulation layer 40 is different from that of the organic planarization layer 30.

[0049] It can be understood that, in the display panel 01 , the encapsulation layer 40 is generally a continuous structure.

[0050] In the embodiment of the present application, a clearance groove 31 is provided in the organic planarization layer 30, and the solid part of the organic planarization layer 30 can be disconnected or cut off at the clearance groove 31. Figure 3 As shown, if the physical portion of the organic planarization layer 30 is disconnected at the clearance groove 31, so that the encapsulation layer 40 fills at least a portion of the clearance groove 31, the encapsulation layer 40 can be located between the physical portions of the disconnected organic planarization layer 20, thereby blocking the path for the organic planarization layer 30 to transmit external water vapor, which helps to prevent external water vapor from invading the interior of the display panel 01 through the organic planarization layer 30 and damaging the devices inside the display panel 01.

[0051] like Figure 4 As shown, Figure 4 for Figure 2Another cross-sectional schematic diagram along the NN' cut line in the figure shows that if the solid part of the organic planarization layer 30 ends at the clearance groove 31, and the encapsulation layer 40 fills at least part of the clearance groove 31, the encapsulation layer 40 can more reliably cover the side wall of the solid part of the organic planarization layer 30 facing the edge of the display panel 01, thereby preventing external water and oxygen from invading the organic planarization layer 30, thereby preventing external water vapor from invading the interior of the display panel 01 along the organic planarization layer 30 and damaging the devices inside the display panel 01.

[0052] Optionally, the encapsulation layer 40 is a water-blocking layer. That is, the encapsulation layer 40 has a water-blocking property. In this way, after the encapsulation layer 40 fills the clearance groove 31 , it can block external water vapor from invading the inside of the display panel 01 along the organic planarization layer 30 .

[0053] Furthermore, the encapsulation layer 40 is an organic water-blocking layer, so that the encapsulation layer 40 has a high water-blocking property and is easy to prepare thicker, thereby improving the water-blocking and encapsulation effects of the encapsulation layer 40 .

[0054] For example, the encapsulation layer 40 may be disposed on a side of the organic planarization layer 30 away from the substrate 10 by printing. In other embodiments, other methods may be used for preparation, which is not limited in the present application.

[0055] Optional, please continue to refer to Figure 3 and Figure 4 The display panel 01 further includes a first inorganic layer 50 , which extends from the device area AA to the peripheral area NA. The first inorganic layer 50 is located between the encapsulation layer 40 and the organic planarization layer 30 .

[0056] In the peripheral area NA, the first inorganic layer 50 is attached to the surface of the organic planarization layer 30. For example, Figure 3 and Figure 4 As shown, in the peripheral area NA, the first inorganic layer 50 is conformally attached to the surface of the organic planarization layer 30. Based on this configuration, the first inorganic layer 50 can cover the sidewall of the organic planarization layer 30.

[0057] Since inorganic layers generally have water-blocking properties, using the first inorganic layer 50 to cover the sidewalls of the organic planarization layer 30 is beneficial for further improving the ability to block external water and oxygen from invading the interior of the display panel 01 along the organic planarization layer 30 .

[0058] In one embodiment of the present application, Figure 3 As shown, in the peripheral area NA, the organic planarization layer 30 includes a first sub-portion 301 and a second sub-portion 302, and a clearance groove 31 is located between the first sub-portion 301 and the second sub-portion 302. That is, the first sub-portion 301 and the second sub-portion 302 are disconnected at the clearance groove 31.

[0059] In the embodiment of the present application, a clearance groove 31 is provided between the first sub-portion 301 and the second sub-portion 302. When the encapsulation layer 40 fills at least a portion of the clearance groove 31, the encapsulation layer 40 can be located between the disconnected first sub-portion 301 and the second sub-portion 302, thereby blocking the passage for the organic planarization layer 30 to transmit external water vapor, thereby facilitating preventing external water vapor from invading the interior of the display panel 01 through the organic planarization layer 30 and damaging the devices inside the display panel 01.

[0060] Moreover, setting the clearance groove 31 between the first sub-section 301 and the second sub-section 302 is conducive to allowing the encapsulation layer 40 to completely cover the clearance groove 31 in the direction Z perpendicular to the plane where the display panel 01 is located, thereby facilitating the encapsulation layer 40 to fill the clearance groove 31 and improve the ability to block the water vapor transmission path along the organic planarization layer 30.

[0061] For example, Figure 3 As shown, the second sub-section 302 is located on the side of the first sub-section 301 facing the edge of the display panel 01. The first sub-section 301 includes a first side 3011 facing the second sub-section 302, and the second sub-section 302 includes a second side 3021 facing the first sub-section 301, and the clearance groove 31 is located between the first side 3011 and the second side 3021. In the direction Z perpendicular to the plane where the display panel 01 is located, the encapsulation layer 40 covers the first side 3011 and the second side 3021. That is, the encapsulation layer 40 fills at least part of the clearance groove 31 and covers the first side 3011 and the second side 3021. In this way, it is beneficial to improve the ability of the encapsulation layer 40 to block the transmission of water vapor along the organic planarization layer 30, thereby further preventing external water and oxygen from invading the interior of the display panel 01 along the organic planarization layer 30.

[0062] Further, such as Figure 3 As shown, in the direction Z perpendicular to the plane where the display panel 01 is located, the encapsulation layer 40 protrudes from the clearance groove 30. That is, the encapsulation layer 40 can fill the clearance groove 30. Based on this arrangement, on the one hand, there can be more encapsulation materials between the first sub-section 301 and the second sub-section 302, thereby improving the ability of the encapsulation layer 40 to block the transmission of water vapor by the organic planarization layer 30; on the other hand, the encapsulation layer 40 can also play a planarization role, which is conducive to ensuring the continuity of the subsequent film layer preparation and avoiding the subsequent film layer from breaking at the clearance groove 31.

[0063] like Figure 4As shown, in one embodiment of the present application, the organic planarization layer 30 includes a solid portion 32, a clearance groove 31 is located on a side of the solid portion 32 facing the edge of the display panel 01, and the solid portion 32 includes a third side surface 321 facing the edge of the display panel 01. That is, the solid portion 32 of the organic planarization layer 30 is terminated at the clearance groove 31, and the clearance groove 31 is located between the third side surface 321 of the solid portion 32 and the edge of the display panel 01.

[0064] In the direction Z perpendicular to the plane where the display panel 01 is located, the encapsulation layer 40 covers the third side surface 321 .

[0065] In the embodiment of the present application, a clearance groove 31 is provided between the third side surface 321 of the entity portion 32 and the edge of the display panel 01, and the encapsulation layer 40 covers the third side surface 321 in the direction Z perpendicular to the plane where the display panel 01 is located. When the encapsulation layer 40 fills at least a portion of the clearance groove 31, the encapsulation layer 40 can better cover the third side surface 321 of the entity portion 32, thereby facilitating the prevention of external water vapor from invading the organic planarization layer 30, and further facilitating the prevention of external water vapor from invading the interior of the display panel 01 along the organic planarization layer 30.

[0066] In addition, disposing the clearance groove 31 on the edge side close to the display panel 01 is also beneficial to reducing the difficulty of preparing the clearance groove 31 in terms of process, and facilitating the encapsulation layer 40 to cover the third side surface 321 .

[0067] Optional, such as Figure 3 and Figure 4 As shown, in the direction Z perpendicular to the plane where the display panel 01 is located, the encapsulation layer 40 overlaps with the clearance groove 31, and the width of the overlap between the encapsulation layer 40 and the clearance groove 31 is W, W ≥ 10 μm. Here, W may refer to the width of the overlap between the encapsulation layer 40 and the bottom surface of the clearance groove 31 close to the substrate 10.

[0068] Based on this setting method, the encapsulation layer 40 at the third side surface 321 of the entity part 32 can be set thicker, which is conducive to ensuring that the encapsulation layer 40 more reliably covers the third side surface 321 of the entity part 32, thereby preventing external water vapor from invading the organic planarization layer 30 through the encapsulation layer 40, and then invading the interior of the display panel 01 along the organic planarization layer 30.

[0069] In addition, for the structure in which the clearance groove 31 is located between the first sub-section 301 and the second sub-section 302, the overlapping width of the encapsulation layer 40 and the clearance groove 31 is not less than 10 μm, so that the clearance groove 31 can ensure that the space separating the first sub-section 301 and the second sub-section 302 is larger, and the encapsulation layer 40 between the first sub-section 301 and the second sub-section 302 can be set thicker, which is beneficial to ensure the ability of the encapsulation layer 40 to block water vapor from invading the interior of the display panel 01 along the organic planarization layer 30, thereby helping to improve the reliability of the encapsulation layer 40 in blocking external water vapor from invading the interior of the display panel 01 along the organic planarization layer 30.

[0070] In one embodiment of the present application, Figure 4 As shown, the display panel 01 further includes a first power line PVDD and a second power line PVEE, and the first power line PVDD and the second power line PVEE may be located in different film layers.

[0071] Optionally, the organic planarization layer 30 includes a first sublayer 30A and a second sublayer 30B, the first sublayer 30A is located on a side of the second sublayer 30B close to the substrate 10, the first power line PVDD is located between the first sublayer 30A and the second sublayer 30B, and the second power line PVEE is located on a side of the second sublayer 30B away from the first sublayer 30A.

[0072] Exemplarily, the first power line PVDD is disposed on the surface of the first sub-layer 30A, and the second power line PVEE is disposed on the surface of the second sub-layer 30B.

[0073] Figure 5 A partially enlarged schematic diagram of a first peripheral area provided in an embodiment of the present application, Figure 6 for Figure 5 A schematic cross-sectional view along the MM' tangent line.

[0074] In one embodiment of the present application, Figure 2 As shown, the peripheral area NA includes a first peripheral area NA1 located on one side of the device area AA, the first peripheral area NA1 is electrically connected to a circuit board (not shown in the figure), and the circuit board can be used to transmit display signals. The first peripheral area NA1 can be the "lower" frame of the display panel 01.

[0075] Combination Figure 5 and Figure 6 As shown, the first peripheral area NA1 includes a power line transfer area DA, which can be used to receive power signals transmitted by the circuit board and transmit the power signals to the first power line PVDD and the second power line PVEE. The clearance groove 31 is located between the power line transfer area DA and the device area AA.

[0076] Optional, such as Figure 6As shown, in a direction Z perpendicular to the plane where the display panel 01 is located, the encapsulation layer 40 covers the clearance groove 31 , and the encapsulation layer 40 can fill the clearance groove 31 .

[0077] Optional, such as Figure 7 As shown, Figure 7 for Figure 5 In another cross-sectional schematic diagram along the MM' cut line, in the direction Z perpendicular to the plane where the display panel 01 is located, the encapsulation layer 40 partially overlaps with the clearance groove 31, and the encapsulation layer 40 can cover the side wall of the entity part of the organic planarization layer 30 close to the device area AA. Of course, a first inorganic layer 50 can be provided between the encapsulation layer 40 and the entity part of the organic planarization layer 30.

[0078] In the embodiment of the present application, the clearance groove 31 is arranged between the power line transfer area DA and the device area AA. On the one hand, the clearance groove 31 can be closer to the device area AA, which is conducive to facilitating the preparation of the encapsulation layer 40 filling the clearance groove 31, thereby using the encapsulation layer 40 to cut off the path for the organic planarization layer 30 to transmit external water vapor. On the other hand, since a large electrode is usually not arranged between the power line transfer area DA and the device area AA, it is conducive to avoiding the mutual influence between the clearance groove 31 and the large electrode in the first peripheral area NA1, thereby reducing the design difficulty of the display panel 01.

[0079] Figure 8 for Figure 5 A schematic cross-sectional view along the CC' tangent line.

[0080] In one embodiment of the present application, Figure 6 and Figure 8 As shown, the first peripheral area NA1 includes a first adapter line 61 and a second adapter line 62, the first adapter line 61 is electrically connected to the first power line PVDD, the second adapter line 62 is electrically connected to the second power line PVEE, and the first adapter line 61 and the second adapter line 62 are both extended to the power line transfer area DA. That is, the first power line PVDD can be extended to the power line transfer area DA through the first adapter line 61, and the second power line PVEE can be extended to the power line transfer area DA through the second adapter line 62.

[0081] In the direction Z perpendicular to the plane where the display panel 01 is located, at least one of the first adapter line 61 and the second adapter line 62 overlaps with the clearance groove 31 .

[0082] Optional, combined Figure 5 , Figure 6 and Figure 8As shown, in the direction Z perpendicular to the plane where the display panel 01 is located, the first adapter line 61 and the second adapter line 62 overlap with the clearance groove 31. Based on this arrangement, it is beneficial to make the clearance groove 31 a continuous structure, thereby facilitating the omni-directional isolation of the path for the organic planarization layer 30 to transmit water vapor to the inside of the display panel 01.

[0083] Exemplary, combined Figure 6 and Figure 8 As shown, the first transfer line 61 and the second transfer line 62 are both located on the side of the first sub-layer 30A close to the substrate 10. From the above analysis, it can be seen that the side of the first sub-layer 30A close to the substrate 10 is usually provided with transistors and their connecting wires. The first transfer line 61 and the second transfer line 62 are both located on the side of the first sub-layer 30A close to the substrate 10. Then, the first transfer line 61 and the second transfer line 62 can be prepared in the same layer as other wires on the side of the first sub-layer 30A close to the substrate 10, without adding additional processes, which is conducive to simplifying the preparation process of the display panel 01.

[0084] Exemplarily, the first adapter line 61 and the second adapter line 62 are in the same layer. This helps to simplify the structural complexity of the display panel 01 and reduce the difficulty of designing the display panel 01.

[0085] Optional, such as Fig. 9 As shown, Fig. 9 Another partial enlarged schematic diagram of the first peripheral area provided in the embodiment of the present application, in the direction perpendicular to the plane where the display panel 01 is located, the first adapter line 61 overlaps with the clearance groove 31, and the second adapter line 62 does not overlap with the clearance groove 31. Based on this setting, the clearance groove 31 can be a non-continuous structure that does not overlap with the second adapter line 62. While ensuring that the path for transmitting water vapor from the organic planarization layer 30 to the inside of the display panel 01 can be largely blocked, the connection between the second adapter line 62 and the second power line PVEE does not require punching and layer replacement, which is conducive to simplifying the manufacturing process of the display panel 01 and reducing the manufacturing cost.

[0086] Of course, if Fig.10 As shown, Fig.10 A partial enlarged schematic diagram of another first peripheral area provided in an embodiment of the present application shows that in a direction perpendicular to the plane where the display panel 01 is located, the first adapter line 61 and the clearance groove 31 may not overlap, and the second adapter line 62 and the clearance groove 31 may overlap.

[0087] Combination Figure 5 , Figure 6 and Figure 8As shown, in one embodiment of the present application, the power line transition area DA includes a first transition electrode DA1 and a second transition electrode DA2, and one end of the first transition line 61 is electrically connected to the first power line PVDD, and the other end is electrically connected to the first transition electrode DA1. One end of the second transition line 62 is electrically connected to the second power line PVEE, and the other end is electrically connected to the second transition electrode DA2. The first transition electrode DA1 and the second transition electrode DA2 can be located in different film layers.

[0088] The first transfer electrode DA1 can receive the first power signal transmitted by the circuit board, and transmit the first power signal to the first transfer line 61, and the first transfer line 61 transmits the received first power signal to the first power line PVDD. The second transfer electrode DA2 can receive the second power signal transmitted by the circuit board, and transmit the second power signal to the second power line 62, and the second power line 62 transmits the received second power signal to the second power line PVEE.

[0089] Optionally, the first transfer line 61 and the first transfer electrode DA1 are in the same layer, or the second transfer line 62 and the second transfer electrode DA2 are in the same layer. Figure 6 and Figure 8 As shown, the second transfer line 62 and the second transfer electrode DA2 are in the same layer, and the first transfer line 61 and the first transfer electrode DA1 are in different layers.

[0090] Based on this configuration, there is no need to punch holes to achieve electrical connection between the first adapter line 61 and the first adapter electrode DA1, or there is no need to punch holes to achieve electrical connection between the second adapter line 62 and the second adapter electrode DA2, which is beneficial to simplify the manufacturing process of the display panel 01 and save costs.

[0091] Optional, such as Figure 6 As shown, the first transfer line 61 is electrically connected to the first transfer electrode DA1 at least through the first via hole K1. Fig.11 As shown, Fig.11 for Figure 5 In another cross-sectional schematic diagram along the CC' cut line, the second transfer line 62 is electrically connected to the second transfer electrode DA2 at least through the second via K2. In this way, in the first peripheral area NA1, the first transfer electrode DA1 and the second transfer electrode DA2 can be set in a film layer with fewer wirings, which is conducive to reducing the setting interference between the first transfer electrode DA1 and the second transfer electrode DA2 and other wirings.

[0092] Fig.12 A partial enlarged schematic diagram of another first peripheral region provided in an embodiment of the present application.

[0093] In one embodiment of the present application, the first power line PVDD and the second power line PVEE both extend into the power line transition area DA, and in a direction perpendicular to the plane where the display panel 01 is located, at least one of the first power line PVDD and the second power line PVEE does not overlap with the clearance groove 31.

[0094] For example, Fig.12 As shown, in a direction perpendicular to the plane where the display panel 01 is located, the first power line PVDD and the second power line PVEE do not overlap with the clearance groove 31 .

[0095] In the embodiment of the present application, the clearance groove 31 can be a non-continuous structure. While ensuring that the path for transmitting water vapor from the organic planarization layer 30 to the interior of the display panel 01 can be largely blocked, it can also prevent the first power line PVDD and / or the second power line PVEE from extending through the heterolayer adapter line to the power line transfer area DA, which is beneficial to simplifying the preparation process of the display panel 01 and reducing the preparation cost.

[0096] Fig.13 for Figure 5 Another cross-sectional schematic diagram along the MM' tangent line.

[0097] In one embodiment of the present application, Fig.13 As shown, the first peripheral area NA1 includes a light shielding layer BM, which is located on a side of the encapsulation layer 40 away from the substrate 10 . Along a direction Z perpendicular to the plane where the display panel 01 is located, the light shielding layer BM overlaps the clearance groove 31 .

[0098] From the above analysis, it can be known that metal traces, such as the first adapter line 61 electrically connected to the first power line PVDD, are arranged on the side of the clearance groove 31 facing the substrate 10. In the embodiment of the present application, the light shielding layer BM is arranged to overlap with the clearance groove 31 in the direction Z perpendicular to the plane where the display panel 01 is located, which is conducive to the light shielding layer BM shielding the metal traces on the side of the clearance groove 31 facing the substrate 10, thereby helping to reduce the reflected light of these metal traces and improve the display effect of the display panel 01.

[0099] Fig.14 for Figure 5 Another cross-sectional schematic diagram along the MM' tangent line.

[0100] In one embodiment of the present application, Fig.14As shown, the first peripheral area NA1 includes a first inorganic layer 50 and a light shielding layer BM, the first inorganic layer 50 is attached to the surface of the organic planarization layer 30, and the first inorganic layer 50 can cover the side wall of the solid part of the organic planarization layer 30 facing the clearance groove 31. The light shielding layer BM is located between the encapsulation layer 40 and the first inorganic layer 50, and along the direction Z perpendicular to the plane where the display panel 01 is located, the light shielding layer BM overlaps the clearance groove 31. The light shielding layer BM can fill the clearance groove 31.

[0101] Since inorganic layers usually have a water-blocking effect, the embodiment of the present application sets a first inorganic layer 50 attached to the surface of the organic planarization layer 30. The first inorganic layer 50 can be used to isolate the organic planarization layer 30 and the light-shielding layer BM to prevent the organic planarization layer 30 from contacting the light-shielding layer BM, which is beneficial to prevent external water vapor from invading the interior of the display panel 01 along the organic planarization layer 30 and the light-shielding layer BM.

[0102] At the same time, it can be known from the above analysis that metal traces, such as the first adapter line 61 electrically connected to the first power line PVDD, will be arranged on the side of the clearance groove 31 facing the substrate 10. In the embodiment of the present application, the light shielding layer BM is arranged to overlap with the clearance groove 31 in the direction Z perpendicular to the plane where the display panel 01 is located, which is conducive to the light shielding layer BM shielding the metal traces on the side of the clearance groove 31 facing the substrate 10, thereby helping to reduce the reflected light of these metal traces and improve the display effect of the display panel 01.

[0103] Fig.15 A partial enlarged schematic diagram of another first peripheral area provided in an embodiment of the present application, Fig.16 for Fig.15 A schematic cross-sectional view along the DD' tangent line.

[0104] In one embodiment of the present application, Figure 2 , Fig.15 and Fig.16 As shown, the peripheral area NA includes a first peripheral area NA1 located on one side of the device area AA, the first peripheral area NA1 includes a power line transfer area DA and a pad area DB, the pad area DB is located on the side of the power line transfer area DA away from the device area AA, the pad area DB is electrically connected to a circuit board (not shown in the figure), and the circuit board can be used to transmit display signals. The first peripheral area NA1 can be the "lower" frame of the display panel 01.

[0105] The pad area DB can transmit the power signal transmitted by the circuit board to the power line transfer area DA, and the power line transfer area DA can be used to transmit the received power signal to the first power line PVDD and the second power line PVEE.

[0106] The clearance groove 31 is located between the power line transfer area DA and the pad area DB.

[0107] For example, Fig.16 As shown, in a direction Z perpendicular to the plane where the display panel 01 is located, the encapsulation layer 40 covers the clearance groove 31 .

[0108] The inventor of the present application has found through research that the number of connecting wires between the power line transfer area DA and the pad area DB is usually small, and the encapsulation layer 40 can extend from the device area AA to the area between the power line transfer area DA and the pad area DB. Therefore, the embodiment of the present application sets a clearance groove 31 between the power line transfer area DA and the pad area DB, which is conducive to reducing the number of line changes of the connecting wires between the power line transfer area DA and the pad area DB while ensuring that the encapsulation layer 40 can fill at least part of the clearance groove 31, thereby helping to reduce the manufacturing cost of the display panel 01.

[0109] Fig.17 for Fig.15 A schematic cross-sectional view along the EE' tangent line.

[0110] In one embodiment of the present application, Fig.15 , Fig.16 and Fig.17 As shown, the power line transfer area DA includes a first transfer electrode DA1 and a second transfer electrode DA2, and the pad area DB includes a first terminal DB1 and a second terminal DB2. A first connection line 71 and a second connection line 72 are provided between the power line transfer area DA and the pad area DB, one end of the first connection line 71 is electrically connected to the first transfer electrode DA1, and the other end is electrically connected to the first terminal DB1, and one end of the second connection line 72 is electrically connected to the second transfer electrode DA2, and the other end is electrically connected to the second terminal DB2.

[0111] The first terminal DB1 can receive a first power signal transmitted by the circuit board, and the first connecting line 71 can transmit the first power signal received by the first terminal DB1 to the first transfer electrode DA1, and the first transfer electrode DA1 can transmit the received first power signal to the first power line PVDD. The second terminal DB2 can receive a second power signal transmitted by the circuit board, and the second connecting line 72 can transmit the second power signal received by the second terminal DB2 to the second transfer electrode DA2, and the second transfer electrode DA2 can transmit the received second power signal to the second power line PVEE.

[0112] In the direction Z perpendicular to the plane where the display panel 01 is located, at least one of the first connection line 71 and the second connection line 72 overlaps with the clearance groove 31 .

[0113] Optional, combined Fig.15 , Fig.16 and Fig.17As shown, in the direction Z perpendicular to the plane where the display panel 01 is located, the first connection line 71 and the second connection line 72 overlap with the clearance groove 31. Based on this arrangement, it is beneficial to make the clearance groove 31 a continuous structure, thereby facilitating the omni-directional isolation of the path for the organic planarization layer 30 to transmit water vapor to the inside of the display panel 01.

[0114] Exemplary, combined Fig.16 and Fig.17 As shown, the first connection line 71 and the second connection line 72 are both located on the side of the first sub-layer 30A close to the substrate 10. Based on this arrangement, the first connection line 71 and the second connection line 72 can be prepared on the same layer as other wirings on the side of the first sub-layer 30A close to the substrate 10, without adding additional processes, which is conducive to simplifying the preparation process of the display panel 01.

[0115] Exemplary, combined Fig.16 and Fig.17 As shown, the first connection line 71 and the second connection line 72 are in the same layer. This is helpful to further simplify the structural complexity of the display panel 01 and reduce the design difficulty of the display panel 01.

[0116] Optional, such as Fig.18 As shown, Fig.18 Another partial enlarged schematic diagram of the first peripheral area provided in the embodiment of the present application, in the direction perpendicular to the plane where the display panel 01 is located, the first connection line 71 overlaps with the clearance groove 31, and the second connection line 72 does not overlap with the clearance groove 31. Based on this setting, the clearance groove 31 can be a non-continuous structure that does not overlap with the second connection line 72. While ensuring that the path for transmitting water vapor from the organic planarization layer 30 to the inside of the display panel 01 can be largely blocked, the connection between the second connection line 72 and the second transfer electrode DA2 does not require punching and layer replacement, which is conducive to simplifying the manufacturing process of the display panel 01 and reducing the manufacturing cost.

[0117] Of course, if Fig.19 As shown, Fig.19 A partial enlarged schematic diagram of another first peripheral area provided in an embodiment of the present application shows that in a direction perpendicular to the plane where the display panel 01 is located, the first connecting line 71 and the clearance groove 31 may not overlap, and the second connecting line 72 and the clearance groove 31 may overlap.

[0118] In one embodiment of the present application, the first connection line 71 and the first transfer electrode DA1 are in the same layer, or the second connection line 72 and the second transfer electrode DA2 are in the same layer.

[0119] For example, combining Fig.16 and Fig.17 As shown, the second connection line 72 and the second transfer electrode DA2 are in the same layer, and the first connection line 71 and the first transfer electrode DA1 are in different layers.

[0120] Based on this configuration, there is no need to punch holes to achieve electrical connection between the first connection line 71 and the first transfer electrode DA1, or there is no need to punch holes to achieve electrical connection between the second connection line 72 and the second transfer electrode DA2, which is beneficial to simplify the manufacturing process of the display panel 01 and save costs.

[0121] Fig. 20 A partial enlarged schematic diagram of another first peripheral region provided in an embodiment of the present application.

[0122] In one embodiment of the present application, Fig. 20 As shown, the power line transfer area DA includes a first transfer electrode DA1 and a second transfer electrode DA2, and the pad area DB includes a first terminal DB1 and a second terminal DB2. A first connection line 71 and a second connection line 72 are provided between the power line transfer area DA and the pad area DB, one end of the first connection line 71 is electrically connected to the first transfer electrode DA1, and the other end is electrically connected to the first terminal DB1, and one end of the second connection line 72 is electrically connected to the second transfer electrode DA2, and the other end is electrically connected to the second terminal DB2.

[0123] In a direction perpendicular to the plane where the display panel 01 is located, at least one of the first connection line 71 and the second connection line 72 does not overlap with the clearance groove 31 .

[0124] For example, Fig. 20 As shown, in a direction perpendicular to the plane where the display panel 01 is located, the first connecting line 71 and the second connecting line 72 do not overlap with the clearance groove 31 .

[0125] In the embodiment of the present application, the clearance groove 31 can be a non-continuous structure. While ensuring that the path for transmitting water vapor from the organic planarization layer 30 to the inside of the display panel 01 can be largely blocked, at least one of the first connecting line 71 and the second connecting line 72 does not need to be set across the clearance groove 31, which is beneficial to simplify the preparation process of the display panel 01 and reduce the preparation cost.

[0126] Fig.21 A partial enlarged schematic diagram of another first peripheral area provided in an embodiment of the present application, Fig. 22 for Fig.21 A schematic cross-sectional view along the FF' tangent line.

[0127] In one embodiment of the present application, Fig.21 and Fig. 22As shown, the peripheral area NA includes a first peripheral area NA1 located on one side of the device area AA, the first peripheral area NA1 includes a power line transfer area DA and a pad area DB, the pad area DB is located on the side of the power line transfer area DA away from the device area AA, the pad area DB is electrically connected to a circuit board (not shown in the figure), and the circuit board can be used to transmit display signals. The first peripheral area NA1 can be the "lower" frame of the display panel 01.

[0128] The pad area DB can transmit the power signal transmitted by the circuit board to the power line transfer area DA, and the power line transfer area DA can be used to transmit the received power signal to the first power line PVDD and the second power line PVEE.

[0129] The clearance groove 31 includes a first clearance groove 311 and a second clearance groove 312 . The first clearance groove 311 is located between the power line transfer area DA and the device area AA, and the second clearance groove 312 is located between the power line transfer area DA and the pad area DB.

[0130] In the embodiment of the present application, a first clearance groove 311 and a second clearance groove 312 are set in the first peripheral area NA1, and the first clearance groove 311 and the second clearance groove 312 can be arranged in the direction from the device area AA to the edge of the display panel 01, which is beneficial to improve the reliability of the clearance groove 31 in blocking the water vapor transmission path of the organic planarization layer 30, thereby helping to further prevent water vapor from being transmitted along the organic planarization layer 30 to the interior of the display panel 01 and damaging the devices inside the display panel 01.

[0131] Optional, such as Fig.21 As shown, the first clearance groove 311 and the second clearance groove 312 are both continuous structures. In this way, the first clearance groove 311 and the second clearance groove 312 can block the path of water vapor transmission from the organic planarization layer 30 to the inside of the display panel 01 in all directions, thereby improving the reliability of blocking the path of water vapor transmission from the organic planarization layer 30 to the inside of the display panel 01.

[0132] Optionally, at least one of the first clearance groove 311 and the second clearance groove 312 is a discontinuous structure. Fig.23 As shown, Fig.23 This is another partially enlarged schematic diagram of a first peripheral area provided in an embodiment of the present application, in which the first clearance groove 311 and the second clearance groove 312 are both non-continuous structures.

[0133] Based on this setting method, in the direction Z perpendicular to the plane where the display panel 01 is located, it is beneficial to ensure that at least one of the first clearance groove 311 and the second clearance groove 312 has no overlap with the wiring in the display panel 01, thereby helping to reduce the preparation of the wiring crossing the first clearance groove 311 or the second clearance groove 312, and further helping to reduce the difficulty of preparing the display panel 01 and save costs.

[0134] In one embodiment of the present application, along the arrangement direction of the first clearance groove 311 and the second clearance groove 312, the projection of the second clearance groove 312 and the first clearance groove 311 on the same plane is a connection structure. In this way, the first clearance groove 311 and the second clearance groove 312 complement each other and cooperate with each other to achieve all-round blocking of the path of water vapor transmission along the organic planarization layer 30 to the inside of the display panel 01.

[0135] For example, Fig.23 As shown, in the first peripheral area NA1, the first clearance groove 311 and the second clearance groove 312 are both non-continuous structures. In the direction where the second clearance groove 312 cannot block the transmission of water vapor by the organic planarization layer 30, the first clearance groove 311 can block. In the direction where the first clearance groove 311 cannot block the transmission of water vapor by the organic planarization layer 30, the second clearance groove 312 can block. While achieving all-round blocking of the transmission path of water vapor along the organic planarization layer 30, it is helpful to reduce the preparation of the wiring crossing the first clearance groove 311 or the second clearance groove 312, and reduce the difficulty of manufacturing the display panel 01.

[0136] Of course, in the first peripheral area NA1, at least one of the first clearance groove 311 and the second clearance groove 312 may also be a continuous structure. While achieving all-round blocking of the water vapor transmission path along the organic planarization layer 30, in at least part of the orientation, the first clearance groove 311 and the second clearance groove 312 may achieve double blocking of the water vapor transmission path of the organic planarization layer 30, which is beneficial to improving the reliability of blocking the water vapor transmission path along the organic planarization layer 30.

[0137] Fig.24 A schematic plan view of another display panel provided in an embodiment of the present application.

[0138] In one embodiment of the present application, Fig.24 As shown, in the peripheral area NA, at least two clearance grooves 31 are provided in the organic planarization layer, and the at least two clearance grooves 31 are arranged in the direction from the device area AA to the peripheral area NA. That is, in the direction from the device area AA to the edge of the display panel 01, the at least two clearance grooves 31 can sequentially block the path of external water vapor being transmitted along the organic planarization layer 30 to the inside of the display panel 01.

[0139] Along the direction from the device area AA to the peripheral area NA, the projections of at least two clearance grooves 31 on the same plane are a continuous structure.

[0140] For example, Fig.24As shown, at least two clearance grooves 31 include a clearance groove 31A and a clearance groove 31B, and the projection of the clearance groove 31B on the plane where the clearance groove 31A is located forms a continuous structure with the clearance groove 31A. The clearance groove 31A and the clearance groove 31B can both be continuous structures, or both be discontinuous structures, or one of them can be a continuous structure and the other a discontinuous structure. Fig.24 It is merely illustrated that both the clearance groove 31A and the clearance groove 31B are discontinuous structures.

[0141] In the embodiment of the present application, at least two clearance grooves 31 can complement each other and cooperate with each other to achieve all-round blocking of the path of water vapor transmission along the organic planarization layer 30 to the inside of the display panel 01. Moreover, the embodiment of the present application provides at least two clearance grooves 31, which is also conducive to increasing the structural diversity of the display panel 01.

[0142] Fig.25 A schematic diagram of a display device provided in an embodiment of the present application.

[0143] The present application embodiment provides a display device 02, such as Fig.25 As shown, the display device 02 includes the display panel 01 provided in the above embodiment. Exemplarily, the display device 02 is an electronic device such as a mobile phone, a computer, a television, a wearable display, a car display, etc., which is not specifically limited in this application.

[0144] In the display device 02, a clearance groove 31 is provided in the organic planarization layer 30, and the entity part of the organic planarization layer 30 can be disconnected or cut off at the clearance groove 31. If the entity part of the organic planarization layer 30 is disconnected at the clearance groove 31, and the encapsulation layer 40 fills at least part of the clearance groove 31, the encapsulation layer 40 can be located between the disconnected entity parts of the organic planarization layer 20, and the path for the organic planarization layer 30 to transmit external water vapor is blocked, which is conducive to preventing external water vapor from invading the interior of the display panel 01 through the organic planarization layer 30 and damaging the internal devices of the display panel 01.

[0145] If the solid part of the organic planarization layer 30 is terminated at the clearance groove 31, and the encapsulation layer 40 fills at least a portion of the clearance groove 31, the encapsulation layer 40 can more reliably cover the side wall of the solid part of the organic planarization layer 30 facing the edge of the display panel 01, thereby preventing external water and oxygen from invading the organic planarization layer 30, thereby preventing external water vapor from invading the interior of the display panel 01 along the organic planarization layer 30 and damaging the devices inside the display panel 01.

[0146] The above description is only a preferred embodiment of the present application and is not intended to limit the present application. Any modifications, equivalent substitutions, improvements, etc. made within the spirit and principles of the present application shall be included in the scope of protection of the present application.

Claims

1. A display panel, characterized in that: The display panel comprises a device area and a peripheral area located on a side of the device area facing the edge of the display panel; the display panel further comprises a substrate, a transistor array layer, an organic planarization layer and an encapsulation layer, the organic planarization layer is located on a side of the transistor array layer away from the substrate, and the encapsulation layer is located on a side of the organic planarization layer away from the substrate; The organic planarization layer and the encapsulation layer extend from the device region to the peripheral region. In the peripheral region, a clearance groove is provided in the organic planarization layer, and the encapsulation layer fills at least a portion of the clearance groove.

2. The display panel according to claim 1, characterized in that: The encapsulation layer is a water-blocking layer.

3. The display panel according to claim 1, characterized in that: The display panel comprises a first inorganic layer, the first inorganic layer extends from the device area to the peripheral area, and the first inorganic layer is located between the encapsulation layer and the organic planarization layer; In the peripheral region, the first inorganic layer is attached to a surface of the organic planarization layer.

4. The display panel according to claim 1, characterized in that: In the peripheral region, the organic planarization layer includes a first sub-portion and a second sub-portion, and the clearance groove is located between the first sub-portion and the second sub-portion.

5. The display panel according to claim 4, characterized in that: The second sub-section is located on a side of the first sub-section facing the edge of the display panel, the first sub-section includes a first side surface facing the second sub-section, and the second sub-section includes a second side surface facing the first sub-section; in a direction perpendicular to the plane where the display panel is located, the encapsulation layer covers the first side surface and the second side surface.

6. The display panel according to claim 5, characterized in that: In a direction perpendicular to the plane where the display panel is located, the encapsulation layer protrudes from the clearance groove.

7. The display panel according to claim 1, characterized in that: In the peripheral area, the organic planarization layer includes a solid portion, the clearance groove is located on a side of the solid portion facing the edge of the display panel, and the solid portion includes a third side facing the edge of the display panel; in a direction perpendicular to the plane where the display panel is located, the encapsulation layer covers the third side.

8. The display panel according to claim 1, characterized in that: In a direction perpendicular to the plane where the display panel is located, the encapsulation layer overlaps with the clearance groove, and the overlapping width of the encapsulation layer and the clearance groove is W, where W≥10 μm.

9. The display panel according to claim 1, characterized in that: The display panel also includes a first power line and a second power line, the organic planarization layer includes a first sublayer and a second sublayer, the first sublayer is located on a side of the second sublayer close to the substrate; the first power line is located between the first sublayer and the second sublayer, and the second power line is located on a side of the second sublayer away from the first sublayer.

10. The display panel according to claim 9, characterized in that: The peripheral area includes a first peripheral area located at one side of the device area, and the first peripheral area is electrically connected to the circuit board; The first peripheral region includes a power line transition region, and the clearance groove is located between the power line transition region and the device region.

11. The display panel according to claim 10, characterized in that: The first peripheral area includes a first adapter wire and a second adapter wire, the first adapter wire is electrically connected to the first power line, the second adapter wire is electrically connected to the second power line, and the first adapter wire and the second adapter wire both extend into the power line adapter area; in a direction perpendicular to the plane where the display panel is located, at least one of the first adapter wire and the second adapter wire overlaps with the clearance groove.

12. The display panel according to claim 11, characterized in that: In a direction perpendicular to the plane where the display panel is located, both the first adapter line and the second adapter line overlap with the clearance groove.

13. The display panel according to claim 12, characterized in that: The first patch cord and the second patch cord are on the same layer.

14. The display panel according to claim 12, characterized in that: The first connecting line and the second connecting line are both located on a side of the first sub-layer close to the substrate.

15. The display panel according to claim 12, characterized in that: The power line adapter area includes a first adapter electrode and a second adapter electrode, one end of the first adapter line is electrically connected to the first power line, and the other end is electrically connected to the first adapter electrode, one end of the second adapter line is electrically connected to the second power line, and the other end is electrically connected to the second adapter electrode.

16. The display panel according to claim 15, characterized in that: The first transfer line is electrically connected to the first transfer electrode at least through a first via hole, and the second transfer line is electrically connected to the second transfer electrode at least through a second via hole.

17. The display panel according to claim 15, characterized in that: The first switching wire and the first switching electrode are in the same layer, or the second switching wire and the second switching electrode are in the same layer.

18. The display panel according to claim 10, characterized in that: The first power line and the second power line both extend into the power line transition area, and in a direction perpendicular to the plane where the display panel is located, at least one of the first power line and the second power line does not overlap with the clearance groove.

19. The display panel according to claim 10, characterized in that: The first peripheral region includes a light shielding layer, which is located on a side of the encapsulation layer away from the substrate, and overlaps the clearance groove along a direction perpendicular to a plane where the display panel is located.

20. The display panel according to claim 10, characterized in that: The first peripheral area includes a first inorganic layer and a light-shielding layer, the first inorganic layer is attached to the surface of the organic planarization layer, and the light-shielding layer is located between the encapsulation layer and the first inorganic layer; along a thickness direction perpendicular to the display panel, the light-shielding layer overlaps with the clearance groove.

21. The display panel according to claim 9, characterized in that: The peripheral area includes a first peripheral area, the first peripheral area includes a power line transfer area and a pad area, the pad area is located on a side of the power line transfer area away from the device area, and the pad area is electrically connected to the circuit board; Wherein, the clearance groove is located between the power line transfer area and the pad area.

22. The display panel according to claim 21, characterized in that: The power line transition area includes a first transition electrode and a second transition electrode, the pad area includes a first terminal and a second terminal, a first connection line and a second connection line are provided between the power line transition area and the pad area, one end of the first connection line is electrically connected to the first transition electrode, and the other end is electrically connected to the first terminal, and one end of the second connection line is electrically connected to the second transition electrode, and the other end is electrically connected to the second terminal; In a direction perpendicular to a plane where the display panel is located, at least one of the first connection line and the second connection line overlaps with the clearance groove.

23. The display panel according to claim 22, characterized in that: In a direction perpendicular to the plane where the display panel is located, both the first connecting line and the second connecting line overlap with the clearance groove.

24. The display panel according to claim 23, characterized in that: The first connecting line and the first switching electrode are in the same layer, or the second connecting line and the second switching electrode are in the same layer.

25. The display panel according to claim 21, characterized in that: The power line transition area includes a first transition electrode and a second transition electrode, the pad area includes a first terminal and a second terminal, a first connection line and a second connection line are provided between the power line transition area and the pad area, one end of the first connection line is electrically connected to the first transition electrode, and the other end is electrically connected to the first terminal, and one end of the second connection line is electrically connected to the second transition electrode, and the other end is electrically connected to the second terminal; In a direction perpendicular to a plane where the display panel is located, at least one of the first connecting line and the second connecting line does not overlap with the clearance groove.

26. The display panel according to claim 1, characterized in that: The peripheral area includes a first peripheral area located at one side of the device area, the first peripheral area includes a power line transfer area and a pad area, the pad area is located at a side of the power line transfer area away from the device area, and the pad area is electrically connected to the circuit board; The clearance groove includes a first clearance groove and a second clearance groove, the first clearance groove is located between the power line transition area and the device area, and the second clearance groove is located between the power line transition area and the pad area.

27. The display panel according to claim 26, characterized in that: Along the arrangement direction of the first clearance grooves and the second clearance grooves, the projections of the second clearance grooves and the first clearance grooves on the same plane are a continuous structure.

28. The display panel according to claim 1, characterized in that: In the peripheral region, at least two clearance grooves are provided in the organic planarization layer, and the at least two clearance grooves are arranged in a direction from the device region to the peripheral region; Along the direction from the device region to the peripheral region, projections of the at least two clearance grooves on the same plane are a continuous structure.

29. A display device, characterized in that: Comprising a display panel as described in any one of claims 1-28.

Images