Laminated solar cell and preparation method thereof

Abstract

The invention discloses a laminated solar cell and a preparation method thereof, and relates to the technical field of solar cell manufacturing. The composite layer is laminated on the silicon-based battery, the composite layer comprises a transition layer and an oxide layer which are laminated from bottom to top, and the ratio of the components of the transition layer to the lattice coefficient of a silicon substrate of the silicon-based battery is 10%-20%; the perovskite top cell is stacked on the oxide layer, and the perovskite top cell comprises an electron transport layer, a perovskite layer and a hole transport layer which are sequentially arranged from bottom to top. According to the embodiment, the composite layer composed of the transition layer and the oxide layer is arranged, the interface embedding degree between the silicon substrate cell and the composite layer can be improved through the transition layer, generation of interface defects is reduced, meanwhile, resistance in the vertical direction is weakened through the oxide layer, downward transmission of electrons generated in the perovskite top cell is better facilitated, and the performance of the perovskite top cell is improved. And the overall photoelectric conversion efficiency of the laminated solar cell is improved.

Description

Technical Field

[0001] The present invention relates to the technical field of solar cell manufacturing, and in particular to a stacked solar cell and a preparation method thereof. Background Art

[0002] In the existing stacked solar cell structure, a composite layer is usually required between the silicon base cell and the perovskite top cell to achieve light transmittance and electron flow between the silicon base cell and the perovskite top cell. However, in the prior art, transparent conductive oxide (TCO) is usually selected as the composite layer, and the transparent conductive oxide is prepared by sputtering deposition. The plasma-induced substances formed on the silicon base cell will accelerate to move toward the substrate during the preparation process, thereby damaging the silicon base cell and reducing the overall performance of the stacked cell. At the same time, indium (In), as the main component of TCO, is expensive, which makes the overall cost of stacked solar cells high. Summary of the invention

[0003] In view of this, an embodiment of the present invention provides a stacked solar cell and a method for preparing the same. By setting a composite layer composed of a transition layer and an oxide layer, not only can the transition layer be used to improve the interface fit between the silicon base cell and the composite layer and reduce the generation of interface defects, but the oxide layer can also be used to weaken the vertical resistance, which is more conducive to the downward transmission of electrons generated in the perovskite top cell and improves the overall photoelectric conversion efficiency of the stacked solar cell.

[0004] In order to solve the above technical problems, the present invention provides the following technical solutions:

[0005] In a first aspect, the present invention provides a stacked solar cell, comprising: a silicon base cell; a composite layer stacked on the silicon base cell, wherein the composite layer comprises a transition layer and an oxide layer stacked from bottom to top, and the ratio of the component of the transition layer to the lattice coefficient of the silicon substrate of the silicon base cell is 10% to 20%; a perovskite top cell stacked on the oxide layer, wherein the perovskite top cell comprises an electron transport layer, a perovskite layer and a hole transport layer arranged in sequence from bottom to top.

[0006] Optionally, the transition layer, the oxide layer and the electron transport layer contain the same transition metal element.

[0007] Optionally, the transition layer, the oxide layer and the electron transport layer are formed simultaneously.

[0008] Optionally, the transition layer is TiSi2; and / or the thickness of the transition layer is 5nm to 10nm.

[0009] Optionally, the oxide layer is silicon oxide; and / or the oxide layer has a thickness of 1 nm to 2 nm.

[0010] Optionally, it also includes: a modification layer arranged between the electron transport layer and the perovskite layer; wherein the modification layer is at least one of 4′-(4-(diphenylamino)phenyl)-5′-phenyl[1,1′:2′,1″-terphenyl]-4-nitrile and 4′-(4-(9H-carbazole-9-yl)phenyl)-5′-phenyl-[1,1′:2′,1″-terphenyl]-4-nitrile; and the perovskite layer (4) is an organic-inorganic hybrid perovskite or an organic perovskite.

[0011] Optionally, the thickness of the modified layer is 5 nm to 9 nm.

[0012] Optionally, the silicon-based cell is a TOPCon cell; and / or, the first main surface of the silicon substrate in the silicon-based cell is provided with a doping layer containing a first doping element; the composite layer is stacked on the doping layer; and / or, the second main surface of the silicon substrate in the silicon-based cell is stacked with a multilayer tunneling oxide structure; wherein each layer of the tunneling oxide structure includes a tunneling oxide layer stacked from the inside to the outside and a doped polysilicon layer doped with a second doping element.

[0013] Optionally, in the case where a multi-layer tunneling oxide structure is stacked on the second main surface of the silicon substrate battery, the tunneling oxide structure is two layers; wherein, in the tunneling oxide structure located on the inner side, the thickness of the doped polysilicon layer is 50nm to 70nm; and / or, in the tunneling oxide structure located on the outer side, the thickness of the doped polysilicon layer is 80nm to 100nm.

[0014] Optionally, in the case of a multilayer tunneling oxide structure stacked on the second main surface of the silicon-based battery, the doped polysilicon layers in the outermost tunneling oxide structures are arranged at intervals; and the doped polysilicon layers arranged at intervals correspond one-to-one to the metal electrodes of the silicon-based battery.

[0015] In a second aspect, the present invention provides a method for preparing a stacked solar cell, comprising: step 1, preparing a composite layer and an electron transport layer from the inside to the outside on a silicon base cell; wherein the ratio of the components contained in the composite layer to the lattice coefficient of the silicon substrate of the silicon base cell is 10% to 20%; step 2, preparing a perovskite layer and a hole transport layer in sequence from the inside to the outside on the electron transport layer.

[0016] The technical solution of the first aspect of the above invention has the following advantages or beneficial effects: by setting a composite layer composed of a transition layer and an oxide layer, not only can the transition layer be used to improve the interface fit between the silicon base cell and the composite layer and reduce the generation of interface defects, but the oxide layer can also be used to weaken the vertical resistance, which is more conducive to the downward transmission of electrons generated in the perovskite top cell and improves the overall photoelectric conversion efficiency of the stacked solar cell. BRIEF DESCRIPTION OF THE DRAWINGS

[0017] The accompanying drawings are used to better understand the present invention and do not constitute an improper limitation of the present invention.

[0018] Figure 1 is a schematic cross-sectional structure diagram of a stacked solar cell according to an embodiment of the present invention;

[0019] Figure 2 is a molecular structure diagram of a modified layer according to an embodiment of the present invention;

[0020] Figure 3 is the absorption and emission spectra of the modified layer according to the embodiment of the present invention;

[0021] Figure 4 is a schematic diagram of the main process of a method for preparing a stacked solar cell according to an embodiment of the present invention;

[0022] Figure 5 is a schematic diagram of the main flow of step S401 according to an embodiment of the present invention;

[0023] Figure 6 is a schematic diagram of the main flow of step S402 according to an embodiment of the present invention;

[0024] Figure 7 It is a schematic diagram of the main process of the method for preparing a silicon substrate battery according to an embodiment of the present invention.

[0025] The reference numerals are as follows:

[0026] 1-silicon substrate cell; 11-silicon substrate; 12-doped layer; 13-tunneling oxide structure; 131-tunneling oxide layer; 132-doped polysilicon layer;

[0027] 2-composite layer; 21-transition layer; 22-oxide layer; 3-electron transport layer; 4-perovskite layer; 5-hole transport layer; 6-modification layer; 7-metal electrode; 8-conductive glass layer. DETAILED DESCRIPTION

[0028] A solar cell is a photoelectric semiconductor wafer that uses sunlight to generate electricity directly. It is also called a "solar chip" or "photovoltaic cell". As long as it is illuminated by light that meets certain illumination conditions, it can instantly output voltage and generate current in the presence of a circuit. In physics, it is called solar photovoltaic (PV), or photovoltaic for short. In order to conveniently and clearly describe the method for preparing a solar cell and the solar cell of the present invention, the following exemplary embodiments of the present invention are described in conjunction with the accompanying drawings, which include various details of the embodiments of the present invention to facilitate understanding, and they should be considered to be merely exemplary. Therefore, those of ordinary skill in the art should recognize that various changes and modifications can be made to the embodiments described herein without departing from the scope and spirit of the present invention. Similarly, for the sake of clarity and conciseness, the description of well-known functions and structures is omitted in the following description.

[0029] Figure 1 The cross-sectional structure diagram of the stacked solar cell provided by the embodiment of the present invention is shown as follows: Figure 1 As shown, the stacked solar cell provided by the present invention includes: a silicon substrate cell 1; a composite layer 2 stacked on the silicon substrate cell 1, wherein the composite layer 2 includes a transition layer 21 and an oxide layer 22 stacked from bottom to top, and the ratio of the component of the transition layer 21 to the lattice coefficient of the silicon substrate of the silicon substrate cell 1 is 10% to 20%; a perovskite top cell stacked on the oxide layer 22, wherein the perovskite top cell includes an electron transport layer 3, a perovskite layer 4 and a hole transport layer 5 arranged in sequence from bottom to top.

[0030] In the prior art, a transparent conductive oxide (TCO) is usually prepared as a composite layer by sputtering deposition. Although TCO has a high transmittance and a low vertical resistivity, it is limited by the preparation method and will damage the silicon substrate cell 1, thereby reducing the overall performance of the stacked solar cell. Therefore, the embodiment of the present invention selects a new composite layer 2 material and prepares it by a different preparation method, so as to avoid damage to the silicon substrate cell 1 while ensuring the overall performance of the stacked solar cell.

[0031] It should be noted that the composite layer 2 in the present invention is composed of a stacked transition layer 21 and an oxide layer 22, wherein the transition layer 21 and the oxide layer 22 play different roles. Specifically, the transition layer 21 in the embodiment of the present invention can ensure the matching degree between the silicon substrate 1 and the transition layer 21 because the ratio of the component to the lattice coefficient of the silicon substrate 1 is 10% to 20%, so that as few interface defects as possible are generated between the silicon base battery 1 and the transition layer 21, thereby ensuring the smooth transmission of electrons. The oxide layer 22 can play a tunneling role, further separating electrons from holes, so that electrons move downward and holes move upward, thereby reducing the recombination of electrons in the perovskite top battery. In a preferred embodiment, the ratio of the component of the transition layer 21 to the lattice coefficient of the silicon substrate 1 is 12.1%.

[0032] It is understandable that there may be interface defects between each two adjacent layers of structure. Therefore, it is necessary not only to ensure the interface fit between the transition layer 21 and the silicon substrate battery 1, but also to ensure the interface fit between the transition layer 21, the oxide layer 22 and the electron transport layer 3, so that electrons can be smoothly transmitted between the multilayer structures. In order to achieve the above purpose, in an optional embodiment, the transition layer 21, the oxide layer 22 and the electron transport layer 3 contain the same transition metal elements. It is understandable that when the transition layer 21, the oxide layer 22 and the electron transport layer 3 contain the same elements, the similarity between the multilayer structures will increase, and then the fit of the interface will also increase, which can achieve a slow transition between multiple layer structures and further avoid the generation of interface defects.

[0033] Specifically, the transition metal element is titanium; correspondingly, the transition layer 21 is TiSi2. It should be noted that since TiSi2 itself has a certain color and is not a transparent material, the thickness of the transition layer 21 needs to be specially set so that the interface transition effect can be achieved without affecting the light-shielding performance. That is, in an optional embodiment, the thickness of the transition layer 21 is 5nm to 10nm, preferably 7nm to 8nm, such as 7nm, 7.2nm, 7.5nm, 7.8nm, 8.0nm, etc. Among them, if the thickness of the transition layer 21 is too thin, the transition effect will be relatively poor, and the overall photoelectric conversion performance of the stacked solar cell cannot be guaranteed. If the thickness of the transition layer 21 is too thick, it will block part of the sunlight, thereby affecting the photoelectric conversion performance of the silicon substrate battery 1 located in the lower layer.

[0034] Regarding the material of the oxide layer 22, in an optional embodiment, the oxide layer 22 may be silicon oxide (SiO x), the thickness of the oxide layer 22 is 1 nm to 2 nm, for example, 1 nm, 1.2 nm, 1.5 nm, 1.8 nm, 2.0 nm, etc. The thickness of the oxide layer 22 is related to the initial deposition thickness of the transition element (Ti) in the preparation process of the transition layer 21, and increases with the increase of the initial deposition thickness of Ti, and stops increasing after reaching a certain thickness (≤3 nm).

[0035] In addition, not only can the overall performance of the stacked solar cell be greatly improved in terms of structure, but no additional process flow is added in the preparation process, that is, in the embodiment of the present invention, the transition layer 21, the oxide layer 22 and the electron transport layer 3 are formed synchronously through a single process, and even the stacked structure does not require an additional preparation process, which maintains the simplicity of the preparation process and is conducive to industrial production. The specific preparation process will be described in the subsequent preparation method and will not be repeated here.

[0036] In a further optional embodiment, the present invention also optimizes the interface transition between the electron transport layer 3 and the perovskite layer 4, that is, the stacked solar cell provided by the present invention also includes: a modification layer 6 arranged between the electron transport layer 3 and the perovskite layer 4; wherein the modification layer 6 is at least one of 4′-(4-(diphenylamino)phenyl)-5′-phenyl[1,1′:2′,1″-terphenyl]-4-nitrile and 4′-(4-(9H-carbazole-9-yl)phenyl)-5′-phenyl-[1,1′:2′,1″-terphenyl]-4-nitrile; the perovskite layer (4) is an organic-inorganic hybrid perovskite or an organic perovskite. It should be emphasized that compared with the traditional fluorescent materials used as modification layers, the materials of the modification layer 6 provided by the present invention are all AIE luminescent materials with solid state aggregation-induced emission (AIE) characteristics. The characteristic of this material is that it can show obvious luminescence performance in the solid state or in a high concentration aggregation state. Specifically, the molecular formulas of 4′-(4-(diphenylamino)phenyl)-5′-phenyl[1,1′:2′,1″-terphenyl]-4-carbonitrile (TPB-AC) and 4′-(4-(9H-carbazol-9-yl)phenyl)-5′-phenyl-[1,1′:2′,1″-terphenyl]-4-carbonitrile (Cz-2pbb) are as follows Figure 2 As shown, from Figure 2 It can be seen that the above two materials use carbazole or triphenyl as the donor unit and cyano-tetraphenylbenzene as the acceptor unit, that is, a donor-π-acceptor type molecule is formed in the molecular structure. This molecule has a higher ultraviolet absorption coefficient and photoluminescence yield. Therefore, the modified layer 6 selected in the embodiment of the present invention itself has luminescent properties. In addition, the absorption and emission spectra of the two materials are shown in FIG. Figure 3 As shown, through Figure 3It can be seen that the maximum absorption peak of TPB-AC is 258nm, the emission peak is 473nm, the maximum absorption peak of Cz-2pbb is 274nm, and the emission peak is 424nm. It can be seen that the above two materials can convert part of the ultraviolet light into visible light, thereby improving the light absorption of the silicon substrate battery 1, and further improving the overall photoelectric conversion efficiency of the stacked solar cell.

[0037] In addition, the perovskite layer 4 and the modified layer 6 selected in the embodiment of the present invention interact with each other. Specifically, both TPB-AC and Cz-2pbb contain cyanide groups, which can interact with the lead ions (Pb 2+ ) and tin ions (Sn 2+ ) are connected, thereby compensating for iodide vacancies. Exemplarily, when the perovskite layer 4 selects tin-lead alloy (Sn-Pb) perovskite, the use of toxic heavy metal lead can be effectively reduced through the interaction between the perovskite layer 4 and the modified layer 6, and the toxicity of the perovskite layer 4 is weakened. It can be seen that the modified layer 6 in the embodiment of the present invention can not only achieve a good interface transition with the stacked perovskite layer 4, reduce the generation of void defects, and facilitate the longitudinal transmission of electrons, but also reduce the toxicity of the perovskite layer 4. Moreover, TPB-AC and Cz-2pbb also include nitrile groups, and the carbon-nitrogen triple bond of the nitrile group is very stable, and the chemical properties are relatively inert, so that the modified layer 6 in the embodiment of the present invention will not react chemically with other stacked structures, and the stability of the stacked solar cell can be guaranteed.

[0038] In a further optional embodiment, the thickness of the modification layer 6 is 5nm to 9nm. This is because too thin a thickness is not conducive to forming an effective transition with the perovskite layer 4, and too thick a thickness will affect the transmission performance of electrons. Therefore, in the embodiment of the present invention, the thickness of the modification layer 6 is preferably set to 4nm to 6nm, such as 4nm, 5nm, 6nm, etc.

[0039] Regarding the selection of the silicon substrate battery 1, in an optional embodiment of the present invention, the silicon substrate battery 1 is a TOPCon battery. Regarding the specific structure of the silicon substrate battery 1, in a further optional embodiment, Figure 1 For example, in the silicon-based cell 1, a doping layer 12 containing a first doping element is disposed on the first main surface of the silicon substrate 11; the composite layer 2 is stacked on the doping layer 12. Exemplarily, when the silicon substrate is an n-type silicon substrate, the first main surface is a side of the silicon substrate 11 facing the perovskite top cell, and the first doping element may be boron.

[0040] In contrast, the second main surface of the silicon substrate 11 in the silicon-based battery 1 is stacked with a multilayer tunneling oxide structure 13; wherein each layer of the tunneling oxide structure 13 includes a tunneling oxide layer 131 stacked from the inside to the outside and a doped polysilicon layer 132 doped with a second doping element. The second main surface is the side of the silicon substrate 11 facing away from the perovskite top battery, and the second doping element can be phosphorus. It should be noted here that in a conventional TOPCon battery structure, usually only one layer of tunneling oxide structure is arranged on the back side of the silicon substrate, that is, only a stacked single-layer tunneling oxide layer and a doped polysilicon layer are arranged. The present application can help electrons to transmit downward while reducing recombination and parasitic absorption problems by setting a plurality of stacked tunneling oxide structures 13, thereby improving the photoelectric conversion efficiency of the silicon-based battery.

[0041] In an optional embodiment, the tunneling oxide structure 13 is two layers, and the thickness of the doped polysilicon layer 132 in the two tunneling oxide structures is different. Specifically, in the tunneling oxide structure located on the inner side, the thickness of the doped polysilicon layer 132 is 50nm to 70nm, such as 50nm, 55nm, 60nm, 65nm, 70nm, etc.; in the tunneling oxide structure located on the outer side, the thickness of the doped polysilicon layer 132 is 80nm to 100nm, such as 80nm, 85nm, 90nm, 95nm, 100nm, etc. The reason why the two layers of doped polysilicon layers 132 are set to two layers with different thicknesses is to ensure the passivation of the metal gate line area on the back side after printing while thinning the doped polysilicon layer in the non-metallic area on the back side as much as possible. Moreover, the thickness of the doped polysilicon layer located on the inner side is greater than the thickness of the doped polysilicon layer located on the outer side because =, the doping concentration of the doping element in the inner doped polysilicon layer is lower than the doping concentration of the doped element in the outer doped polysilicon layer (approximately one order of magnitude lower), which can reduce the recombination of photogenerated electrons in the doped polysilicon layers, thereby further improving the photoelectric conversion efficiency.

[0042] In addition, in a further optional embodiment, as Figure 1 As shown, in the case of the multi-layer tunneling oxide structure 13 stacked on the second main surface of the silicon substrate battery 1, the doped polysilicon layer 132 in the outermost tunneling oxide structure is arranged at intervals; and the doped polysilicon layer 132 arranged at intervals corresponds to the metal electrode 7 of the silicon substrate battery 1. It can be understood that, due to the stacked multi-layer tunneling oxide structure 13, the overall passivation performance of the stacked solar cell can be met, the part of the doped polysilicon layer 132 in the non-metallic area can be reduced, the parasitic absorption of the back doped polysilicon layer 132 can be effectively reduced, the open circuit voltage of the overall stacked solar cell is improved, and the short circuit current is enhanced.

[0043] In addition, in an optional embodiment, if Figure 1As shown, a conductive glass layer 8 for encapsulating the hole transport layer 5 is also provided on the hole transport layer 5, and a metal electrode 7 is provided on the conductive glass layer 8. The metal electrode 7 on the conductive glass layer 8 may be provided at the same position as the doped polysilicon layer 132 on the back side, or may be provided at a different position according to actual needs, which is not limited in the present invention.

[0044] In an optional embodiment, the conductive glass layer 8 may be an ITO conductive film with a thickness of 50 nm to 150 nm. In the embodiment of the present invention, if the conductive glass layer 8 is set too thin, there will be a problem that the metal electrode penetrates the conductive glass layer 8 during the sintering process, and if the conductive glass layer 8 is too thick, it will waste consumables and increase the material cost of the laminated solar cell.

[0045] In summary, the stacked solar cell provided in the embodiment of the present invention, by setting a composite layer composed of a transition layer and an oxide layer, can not only utilize the transition layer to improve the interface fit between the silicon base cell and the composite layer and reduce the generation of interface defects, but also utilize the oxide layer to weaken the vertical resistance, which is more conducive to the downward transmission of electrons generated in the perovskite top cell, thereby improving the overall photoelectric conversion efficiency of the stacked solar cell.

[0046] In one embodiment of the present invention, Figure 4 As shown, a method for preparing a stacked solar cell is provided, and the preparation method may include the following steps:

[0047] Step S401, preparing a composite layer 2 and an electron transport layer 3 from the inside to the outside on a silicon-based battery 1; wherein the composite layer 2 includes a transition layer 21 and an oxide layer 22 stacked from bottom to top, and the ratio of the components contained in the transition layer 21 to the lattice coefficient of the silicon substrate 1 of the silicon-based battery 1 is 10% to 20%;

[0048] Step S402 , preparing a perovskite layer 4 and a hole transport layer 5 on the electron transport layer 3 from the inside to the outside.

[0049] Among them, the transition layer 21, the oxide layer 22 and the electron transport layer 3 in the composite layer 2 are obtained simultaneously based on a single preparation process, and the multi-layer stacked structure does not require an additional preparation process, thereby simplifying the process and facilitating industrial preparation.

[0050] Specifically, for step S401, in an optional embodiment, as Figure 5 As shown, including:

[0051] Step S501, preparing a transition metal layer on the silicon substrate cell 1 by using a vacuum thermal evaporation method;

[0052] Step S502 , annealing the transition metal layer in an oxygen environment to simultaneously obtain the composite layer 2 and the electron transport layer 3 .

[0053] Among them, the thickness of the transition metal layer can be 20nm to 50nm, for example, 20nm, 30nm, 40nm, 50nm, etc. Through the reaction between the transition metal layer and the silicon substrate 11, a transition layer 21 corresponding to the transition metal layer element can be generated. Exemplarily, when the transition metal layer is a metal titanium layer, the transition layer 21 in the generated composite layer 2 is TiSi2. Compared with the sputtering deposition method used in the prior art to prepare the composite layer, the embodiment of the present invention adopts a vacuum thermal evaporation method to avoid the bombardment of high kinetic energy. At the same time, in an aerobic environment, an oxide layer 22 can be synchronously generated on the outside of the transition layer 21, effectively avoiding the problem of the transition layer 2 moving toward the silicon substrate.

[0054] Exemplarily, the annealing temperature in step S402 is 550°C to 650°C, preferably 590°C to 610°C, such as 590°C, 600°C, 610°C, etc., and the annealing time is 25min to 35min, such as 25min, 28min, 30min, 32min, 35min. By controlling the annealing time and the annealing temperature, the thickness of the transition layer 21 can be controlled, thereby obtaining the thickness of the transition layer 21 required by the embodiment of the present invention.

[0055] For step S402, in an optional embodiment, as Figure 6 As shown, including:

[0056] Step S601, preparing a modified layer 6 on the electron transport layer 3; wherein the modified layer 6 is at least one of 4′-(4-(diphenylamino)phenyl)-5′-phenyl[1,1′:2′,1″-terphenyl]-4-carbonitrile and 4′-(4-(9H-carbazole-9-yl)phenyl)-5′-phenyl-[1,1′:2′,1″-terphenyl]-4-carbonitrile;

[0057] Step S602 , preparing a perovskite layer 4 and a hole transport layer 5 by stacking on the modified layer 6 ; wherein the perovskite layer 4 is an organic-inorganic hybrid perovskite or an organic perovskite.

[0058] Specifically, the preparation process of the modified layer 6 is as follows: at room temperature, a modified solution with a concentration of 0.1 to 0.5 mg / mL is spin-coated on the electron transport layer 3 at a rotation speed of 3000 rpm and dried. The spin coating time is 20s to 40s, for example 20s, 30s, 40s, preferably 30s.

[0059] In the process of preparing the perovskite layer 4 in step S602, in an optional embodiment, the perovskite layer 4 can also be prepared by spin coating. x FA1-x Pb 1-y Sn y I3 or Cs x MA 1-x Pb 1-y Sn y I3, the specific process is: by spin coating and evaporating the precursor solution of DMSO / ACN / 2-ME=2:7:4 (DMSO: dimethyl sulfoxide; ACN: acetonitrile; 2-ME: 2-methoxyethanol), annealing at T1=67℃~72℃ for t1=9~12 minutes, and then annealing at T2=98℃~102℃ for t2=13~16 minutes to form a film. Among them, the time interval between the two annealings is 30 minutes, and the film forming conditions are the surrounding normal environment (temperature is 25℃, humidity is 25%).

[0060] For the process of preparing the hole transport layer 5 in step S602, in an optional embodiment, the preparation process is: 5 to 9 nm of PTAA or Spiro-OMeTAD (PTAA: bis(4-phenyl)(2,4,6-trimethylphenyl)amine) is spin-coated on the surface of the perovskite layer 4 by spin coating, and annealed at 40° C. to 60° C. for 1 to 2 minutes. In another optional embodiment, the oxidized nitrogen layer can also be prepared by magnetron sputtering, and the oxidized nitrogen layer is used as the hole transport layer 5.

[0061] Through the above process, a multilayer structure of a perovskite top cell can be prepared by stacking on a silicon base cell 1. In the actual preparation process, the preparation of the silicon base cell 1 needs to be completed first before the perovskite top cell can be prepared on the prepared silicon base cell 1. Specifically, the preparation process of the silicon base cell 1 is as follows: Figure 7 As shown, including:

[0062] Step S701, diffusing a first doping element on a first main surface of a silicon substrate 11 to prepare a doping layer 12;

[0063] Step S702 : preparing multiple layers of tunneling oxide structures 13 doped with a second doping element on the second main surface of the silicon substrate 11 in sequence.

[0064] Exemplarily, when the silicon substrate 11 is an n-type silicon substrate, the first doping element is boron, and step S701 specifically includes: using an alkaline solution to perform alkali texturing on the first main surface and the second main surface of the silicon substrate 11 to obtain a velvet structure with a pyramid height of 0.8μm to 1.5μm and a pyramid base of 0.5μm to 3μm. Then, a double insertion process is used to diffuse boron on the first main surface of the velvet structure to form a doping layer 12. In an optional embodiment, the doping element concentration of the doping layer 12 is 2.5E 18 ~2.8E 18The thickness of the doping layer 12 is 1.2 μm to 1.6 μm, preferably 1.4 μm.

[0065] It can be understood that while boron is diffused on the first main surface, a borosilicate glass layer will be simultaneously generated on the side of the silicon substrate 11 and the edge of the second main surface. Therefore, before step S602, it is necessary to first use a hydrofluoric acid solution to remove the borosilicate glass layer on the edge and the side of the silicon substrate 11, and then polish the second main surface to facilitate the preparation of the tunneling oxide structure 13 on the back.

[0066] For step S702, in an optional embodiment, a tunneling oxide layer 131 and a doped polysilicon layer 132 doped with phosphorus are sequentially deposited on the second main surface of the silicon substrate 11 through an LPCVD double insertion process. Among them, in the tunneling oxide structure located on the inner side, the thickness of the doped polysilicon layer 132 is 50nm to 70nm, such as 50nm, 55nm, 60nm, 65nm, 70nm, etc.; in the tunneling oxide structure located on the outer side, the thickness of the doped polysilicon layer 132 is 80nm to 100nm, such as 80nm, 85nm, 90nm, 95nm, 100nm, etc. The thickness of the tunneling oxide layer 131 in the multi-layer tunneling oxide structure 13 is the same, and can be set to 1nm to 2nm. It can be understood that, similar to the preparation process of the front side of the silicon substrate 11, while forming the doped polysilicon layer 132, a phosphosilicate glass layer will also be formed on the front and side of the silicon substrate 11. Therefore, after step S702, it is also necessary to use a hydrofluoric acid solution to remove the generated phosphosilicate glass layer.

[0067] After removing the phosphorus silicon glass layer, it is necessary to use a laser process in combination with alkaline solution cleaning to remove the doped polysilicon layer 132 in the non-metallic area, and only retain the doped polysilicon layer 132 in the metal area corresponding to the metal fine gate. The total thickness of the doped polysilicon layer 132 in the metal area is 45nm to 55nm, and the total thickness of the doped polysilicon layer 132 in the non-metallic area is 75nm to 80nm.

[0068] In an optional embodiment, a passivation layer and a metal electrode 7 are also required to be prepared on the second main surface of the silicon substrate 11. The ratio of SiH4 and NH3 (0.1-0.3) can be controlled to form a passivation layer with different refractive indices according to actual needs, and the thickness of the passivation layer can be 70nm to 90nm, preferably 77nm to 81nm. The metal electrode 7 can be a silver electrode or an aluminum electrode.

[0069] After the above steps S701 to S702, the TOPCon silicon substrate battery 1 required by the present invention can be obtained, and on the basis of the silicon substrate battery 1, further Figures 3 to 6 The process finally obtains the stacked solar cell according to the embodiment of the present invention.

[0070] In summary, the method for preparing the stacked solar cell provided in the embodiment of the present invention, by setting a composite layer composed of a transition layer and an oxide layer, can not only utilize the transition layer to improve the interface fit between the silicon base cell and the composite layer and reduce the generation of interface defects, but also utilize the oxide layer to weaken the vertical resistance, which is more conducive to the downward transmission of electrons generated in the perovskite top cell, thereby improving the overall photoelectric conversion efficiency of the stacked solar cell.

[0071] Example

[0072] Step a: using an alkaline solution to texture the silicon substrate on both sides; the pyramid height of the texture surface is 1 μm, and the size of the pyramid base is 1.5 μm;

[0073] Step b: Using the double insertion process, the front side of the silicon substrate is subjected to boron diffusion to form a doped layer. The boron concentration of the doped layer is 2.5E 18 , the thickness of the doped layer is 1.4 μm;

[0074] Step c: Using the LPCVD double insertion process, a first layer of SiO2 tunneling oxide layer with a thickness of 2nm, a first layer of intrinsic polysilicon layer with a thickness of 50nm, a second layer of SiO2 tunneling oxide layer with a thickness of 2nm, and a second layer of intrinsic polysilicon layer with a thickness of 80nm are deposited on the back of the silicon substrate in sequence.

[0075] Step d: Phosphorus is diffused on the back of the silicon substrate to obtain a two-layer tunneling oxide structure (tunneling oxide layer + doped polysilicon layer); wherein the phosphorus concentration in the doped polysilicon layer is 5E 20 ;

[0076] Step e: using laser to partially remove the outermost doped polysilicon layer to obtain a doped polysilicon layer with a thickness of 50 nm in the metal region and a thickness of 80 nm in the non-metal region;

[0077] Step f: using a PECVD process to deposit a passivation layer with a thickness of 80 nm on the back side of the silicon substrate;

[0078] Step g: A Ti layer with a thickness of 30 nm is prepared on the doped layer by vacuum thermal evaporation, and annealed in an O2 environment at 600°C for 30 min. The TiSi2 transition layer and SiO x The thickness of the TiSi2 transition layer is 8nm, the thickness of the TiO2 electron transport layer is 2nm, and the thickness of the SiO x The thickness of the oxide layer is 1 nm.

[0079] Step h: Spin coat 4′-(4-(diphenylamino)phenyl)-5′-phenyl[1,1′:2′,1″-terphenyl]-4-carbonitrile (TPB-AC) at 0.1-0.5 mg / mL and 3000 rpm on the TiO2 electron transport layer at room temperature.

[0080] 30s, to obtain the modified layer;

[0081] Step i: Depositing the perovskite layer Cs on the modified layer by spin coating x FA 1-x Pb 1-y Sn y I3, thickness is 400; wherein DMSO / ACN / 2-ME=2:7:4 is used as the precursor solution, annealing is performed at T1=70°C for t1=10 minutes, and then annealing is performed at T2=100°C for t2=14 minutes, the interval between the two annealings is 30 minutes, and the film forming conditions are the surrounding normal environment (temperature is 25°C, humidity is 25%);

[0082] Step j: Spin coating PTAA with a thickness of 7 nm on the surface of the perovskite layer by spin coating, and annealing at 50° C. for 1 minute to obtain a hole transport layer;

[0083] Step k: preparing an ITO transparent conductive film with a thickness of 100 nm on the hole transport layer by magnetron sputtering (In2O3 / SnO2);

[0084] Step 1: Prepare silver electrodes on the front ITO transparent conductive film and the back passivation layer using a thermal evaporation method.

[0085] Comparative Example 1

[0086] The only difference from the embodiment is that

[0087] Step g is: preparing an ITO layer with a thickness of 20 nm as a transition layer by magnetron sputtering, and preparing an electron transport layer with a thickness of 2 nm on the transition layer.

[0088] Comparative Example 2

[0089] The only difference from the embodiment is that

[0090] Step h is: at room temperature, spin-coat γ-mercaptopropyltrimethoxysilane at 0.1-0.5 mg / mL and 3000 rpm for 30 seconds on the TiO2 electron transport layer to obtain a modified layer.

[0091] Comparative Example 3

[0092] The only difference from the embodiment is that

[0093] Step d is: diffuse phosphorus on the back of the silicon substrate to obtain a single-layer tunneling oxide structure (tunneling oxide layer + doped polysilicon layer); wherein the phosphorus concentration in the doped polysilicon layer is 5E 20 ;

[0094] Step e is: using laser to partially remove the doped polysilicon layer to obtain a doped polysilicon layer with a thickness of 110 nm in the metal region and a thickness of 90 nm in the non-metal region;

[0095] The performance of the laminated solar cells prepared in the above embodiments and multiple comparative examples was tested, and the test results are as follows:

[0096] Group Voc(V) Jsc(mA / cm2) FF(%) PCE(%) Example 1.95 19.8 83.9 26.2 Comparative Example 1 1.82 19.2 74.4 25.9 Comparative Example 2 1.87 19.1 76.3 25.8 Comparative Example 3 1.92 19.4 80.5 26.0

[0097] According to the above test results, it can be seen that the opening voltage, short-circuit current, fill factor, and conversion efficiency of the stacked battery in the embodiment are all improved compared with the comparative example. Specifically, compared with comparative example 1, the introduction of the TiSi2 transition layer allows for a better transition of the interface, improves the interface crystallization fit of the two materials, reduces the generation of defects, and also weakens the vertical resistance, which is more conducive to the extraction and downward transmission of photogenerated electrons in the perovskite; compared with comparative example 2, the modified layer material used in the embodiment of the present invention also has ultraviolet absorption and self-luminous properties, which enhances the utilization rate of light by the underlying single-crystal silicon battery and reduces the damage of ultraviolet light to the device. In addition, the nitrile group of the organic matter can compensate for the iodide vacancies at the perovskite interface, plays a connecting role, and further strengthens the degree of interface connection; compared with comparative example 3, the setting of the back stacked doped polysilicon layer and the thinning of part of the doped polysilicon layer can also reduce the parasitic absorption of the back doped polysilicon layer on the premise of satisfying passivation.

[0098] The embodiment of the present invention also provides the following technical solutions:

[0099] Technical solution 1. A stacked solar cell, characterized in that it includes: a silicon base cell 1; a composite layer 2 stacked on the silicon base cell 1, wherein the composite layer 2 includes a transition layer 21 and an oxide layer 22 stacked from bottom to top, and the ratio of the component of the transition layer 21 to the lattice coefficient of the silicon substrate of the silicon base cell 1 is 10% to 20%; a perovskite top cell stacked on the oxide layer 22, wherein the perovskite top cell includes an electron transport layer 3, a perovskite layer 4 and a hole transport layer 5 arranged in sequence from bottom to top.

[0100] Technical Solution 2. The stacked solar cell according to Technical Solution 1 is characterized in that the transition layer 21, the oxide layer 22 and the electron transport layer 3 contain the same transition metal element; the transition layer 21, the oxide layer 22 and the electron transport layer 3 are formed synchronously.

[0101] Technical Solution 3. The stacked solar cell according to Technical Solution 2 is characterized in that the transition layer 21 is TiSi2; and / or the thickness of the transition layer 21 is 5nm to 10nm.

[0102] Technical Solution 4. The stacked solar cell according to Technical Solution 2 is characterized in that the oxide layer 22 is silicon oxide; and / or the thickness of the oxide layer 22 is 1 nm to 2 nm.

[0103] Technical Solution 5. The stacked solar cell according to Technical Solution 1 is characterized in that it also includes: a modification layer 6 arranged between the electron transport layer 3 and the perovskite layer 4; wherein the modification layer 6 is at least one of 4′-(4-(diphenylamino)phenyl)-5′-phenyl[1,1′:2′,1″-terphenyl]-4-nitrile and 4′-(4-(9H-carbazole-9-yl)phenyl)-5′-phenyl-[1,1′:2′,1″-terphenyl]-4-nitrile; and the perovskite layer (4) is an organic-inorganic hybrid perovskite or an organic perovskite.

[0104] Technical Solution 6. The stacked solar cell according to Technical Solution 5 is characterized in that:

[0105] The thickness of the modification layer 6 is 5 nm to 9 nm.

[0106] Technical Solution 7. The stacked solar cell according to Technical Solution 1 is characterized in that:

[0107] The silicon-based battery 1 is a TOPCon battery; and / or, the first main surface of the silicon substrate 11 in the silicon-based battery 1 is provided with a doping layer 12 containing a first doping element; the composite layer 2 is stacked on the doping layer 12; and / or, the second main surface of the silicon substrate 11 in the silicon-based battery 1 is stacked with a multi-layer tunneling oxide structure 13; wherein each layer of the tunneling oxide structure 13 includes a tunneling oxide layer 131 stacked from the inside to the outside and a doped polysilicon layer 132 doped with a second doping element.

[0108] Technical Solution 8. The stacked solar cell according to Technical Solution 7 is characterized in that, when a multi-layer tunneling oxide structure 13 is stacked on the second main surface of the silicon substrate cell 1, the tunneling oxide structure 13 is two layers; wherein, in the tunneling oxide structure located on the inner side, the thickness of the doped polysilicon layer 132 is 50nm~70nm; and / or, in the tunneling oxide structure located on the outer side, the thickness of the doped polysilicon layer 132 is 80nm~100nm.

[0109] Technical Solution 9. The stacked solar cell according to Technical Solution 6 or 7 is characterized in that, in the case of a multilayer tunneling oxide structure 13 stacked on the second main surface of the silicon substrate battery 1, the doped polysilicon layer 132 located in the outermost tunneling oxide structure is arranged at intervals; and the doped polysilicon layer 132 arranged at intervals corresponds one-to-one to the metal electrode 7 of the silicon substrate battery 1.

[0110] Technical Solution 10. A method for preparing a stacked solar cell, characterized by comprising:

[0111] Step 1, preparing a composite layer 2 and an electron transport layer 3 from the inside to the outside on a silicon-based battery 1; wherein the composite layer 2 comprises a transition layer 21 and an oxide layer 22 stacked from bottom to top, and the ratio of the components contained in the transition layer 21 to the lattice coefficient of the silicon substrate 1 of the silicon-based battery 1 is 10% to 20%;

[0112] Step 2, preparing a perovskite layer 4 and a hole transport layer 5 on the electron transport layer 3 from the inside to the outside.

[0113] Technical solution 11. The preparation method according to technical solution 10 is characterized in that step 1 comprises:

[0114] Step 11, using vacuum thermal evaporation method to prepare a transition metal layer on the silicon substrate battery 1;

[0115] Step 12: annealing the metal titanium layer in an oxygen environment to simultaneously obtain the composite layer 2 and the electron transport layer 3.

[0116] Technical solution 12. The preparation method according to technical solution 10 is characterized in that step 2 comprises:

[0117] Step 21, preparing a modified layer 6 on the electron transport layer 3; wherein the modified layer 6 is at least one of 4′-(4-(diphenylamino)phenyl)-5′-phenyl[1,1′:2′,1″-terphenyl]-4-carbonitrile and 4′-(4-(9H-carbazol-9-yl)phenyl)-5′-phenyl-[1,1′:2′,1″-terphenyl]-4-carbonitrile;

[0118] Step 22, preparing the perovskite layer 4 and the hole transport layer 5 by stacking on the modified layer 6; wherein the perovskite layer 4 is an organic-inorganic hybrid perovskite or an organic perovskite.

[0119] Technical solution 13. The preparation method according to technical solution 10 is characterized in that the silicon substrate battery 1 is prepared by the following method:

[0120] Diffusion of a first doping element is performed on a first main surface of the silicon substrate 11 to prepare a doping layer 12;

[0121] A plurality of tunneling oxide structures 13 doped with a second doping element are sequentially prepared on the second main surface of the silicon substrate 11 .

[0122] The introduction provided in the above steps is only used to help understand the structure, method and core idea of ​​the present invention. For ordinary technicians in this technical field, without departing from the principle of the present invention, several improvements and modifications can be made to the present invention, and these improvements and modifications also belong to the scope of protection of the claims of the present invention.

Claims

1. A stacked solar cell, characterized in that: include: Silicon substrate battery (1); A composite layer (2) stacked on the silicon-based battery (1), wherein the composite layer (2) comprises a transition layer (21) and an oxide layer (22) stacked from bottom to top, and the ratio of the lattice coefficient of the component of the transition layer (21) to the silicon substrate of the silicon-based battery (1) is 10% to 20%; A perovskite top cell stacked on the oxide layer (22), wherein the perovskite top cell comprises an electron transport layer (3), a perovskite layer (4) and a hole transport layer (5) arranged in sequence from bottom to top.

2. The tandem solar cell according to claim 1, characterized in that: The transition layer (21), the oxide layer (22) and the electron transport layer (3) contain the same transition metal element; The transition layer (21), the oxide layer (22) and the electron transport layer (3) are formed simultaneously.

3. The tandem solar cell according to claim 2, characterized in that: The transition layer (21) is TiSi2; and / or, The thickness of the transition layer (21) is 5 nm to 10 nm.

4. The stacked solar cell according to claim 2, characterized in that: The oxide layer (22) is silicon oxide; and / or, The thickness of the oxide layer (22) is 1 nm to 2 nm.

5. The tandem solar cell according to claim 1, characterized in that: Also includes: A modification layer (6) disposed between the electron transport layer (3) and the perovskite layer (4); Wherein, the modified layer (6) is at least one of 4′-(4-(diphenylamino)phenyl)-5′-phenyl[1,1′:2′,1″-terphenyl]-4-carbonitrile and 4′-(4-(9H-carbazole-9-yl)phenyl)-5′-phenyl-[1,1′:2′,1″-terphenyl]-4-carbonitrile; The perovskite layer (4) is an organic-inorganic hybrid perovskite or an organic perovskite.

6. The tandem solar cell according to claim 5, characterized in that: The thickness of the modified layer (6) is 5 nm to 9 nm.

7. The tandem solar cell according to claim 1, characterized in that: The silicon substrate cell (1) is a TOPCon cell; and / or, The first main surface of the silicon substrate (11) in the silicon-based battery (1) is provided with a doping layer (12) containing a first doping element; The composite layer (2) is stacked on the doping layer (12); and / or, The second main surface of the silicon substrate (11) in the silicon-based battery (1) is stacked with a multi-layer tunneling oxidation structure (13); wherein: Each layer of the tunneling oxide structure (13) comprises a tunneling oxide layer (131) and a doped polysilicon layer (132) doped with a second doping element, which are stacked from the inside to the outside.

8. The tandem solar cell according to claim 7, characterized in that: In the case where a multi-layer tunneling oxide structure (13) is stacked on the second main surface of the silicon substrate battery (1), the tunneling oxide structure (13) is two layers; wherein: In the tunneling oxide structure located on the inner side, the thickness of the doped polysilicon layer (132) is 50nm to 70nm; and / or, In the tunneling oxide structure located on the outside, the thickness of the doped polysilicon layer (132) is 80nm-100nm.

9. The tandem solar cell according to claim 6 or 7, characterized in that: In the case of a multilayer tunneling oxide structure (13) stacked on the second main surface of the silicon substrate battery (1), the doped polysilicon layer (132) in the outermost tunneling oxide structure is arranged at intervals; The doped polysilicon layers (132) arranged at intervals correspond one to one with the metal electrodes (7) of the silicon-based battery (1).

10. A method for preparing a stacked solar cell, characterized in that: include: Step 1, preparing a composite layer (2) and an electron transport layer (3) from the inside out on a silicon-based battery (1); wherein the composite layer (2) comprises a transition layer (21) and an oxide layer (22) stacked from bottom to top, and the ratio of the lattice coefficient of the component contained in the transition layer (21) to the silicon substrate (1) of the silicon-based battery (1) is 10% to 20%; Step 2, preparing a perovskite layer (4) and a hole transport layer (5) on the electron transport layer (3) from the inside to the outside.

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