Turbo code design method, Turbo code design device, and storage medium for storing Turbo code design program

Abstract

The invention provides a Turbo code design method, which is used for designing a Turbo code using a high-performance interleaver. The Turbo encoder comprises a first convolution encoder, an interleaver and a second convolution encoder. A first convolutional encoder generates a first parity stream of input data using a predetermined recursive systematic convolutional RSC code. And an interleaver that rearranges the order of the internal sequence of the input data on the basis of a first rule and generates permutation data. And a second convolutional encoder that generates a second parity stream of the permutation data using the RSC code. A Turbo code design method includes selecting a polynomial representing an RSC code from a Galois field of the polynomial, and designing a first rule of an interleaver based on the RSC code.

Description

Technical Field

[0001] The invention relates to a Turbo code design method, a Turbo code design device, and a storage medium for storing a Turbo code design program. Background Art

[0002] Turbo codes, which are error-correcting codes, have performance close to the so-called Shannon limit. In Turbo codes, output data is generated by combining input data, a parity stream of the input data, and a parity stream of permuted data obtained by rearranging the order of the internal sequence of the input data.

[0003] A circuit that rearranges the order of the internal sequence of input data is called an interleaver. As interleavers, an S-random (Semi-Random) interleaver and a QPP (Quadratic Permutation Polynomial) interleaver are known. However, in the case of the S-random interleaver, there is a problem that the memory capacity required during encoding and / or decoding is relatively large and parallel decoding processing cannot be performed. In addition, in the case of the QPP interleaver, when the bit length is relatively long (for example, 1024 bits), the performance is worse than that of the S-random interleaver.

[0004] Regarding the above, non-patent document 1 (“LTE Envolved Universal Terrestrial Radio Access (E-UTRA): Multiplexing and Channel Coding”, Third Generation Partnership Project (3GPP) Std. published in January 2011) discloses that LTE (Long-Term Evolution) adopts Turbo codes using QPP interleavers (“3GPP” is a registered trademark).

[0005] Prior Art Literature

[0006] Non-patent literature

[0007] Non-patent document 1: “LTE Envolved Universal Terrestrial Radio Access (E-UTRA): Multiplexing and Channel Coding”, Third Generation Partnership Project (3GPP) Std. Published, January 2011 Summary of the invention

[0008] Problem that the invention aims to solve

[0009] In view of the above, one of the purposes of the present disclosure is to provide a Turbo code design method, a Turbo code design device and a storage medium storing a Turbo code design program for designing a Turbo code using a high-performance interleaver. Other purposes and novel features will be apparent from the description and drawings of this specification.

[0010] Technical means of solving problems

[0011] According to one embodiment, a turbo code design method is a turbo code design method for designing turbo codes. A turbo coder for executing turbo codes includes: a first convolutional encoder, an interleaver, and a second convolutional encoder. The first convolutional encoder generates a parity check stream of input data as a first parity check stream using a predetermined recursive systematic convolutional RSC code. The interleaver rearranges the order of the internal sequence of the input data based on a first rule to generate permuted data. The second convolutional encoder generates a parity check stream of permuted data using the RSC code as a second parity check stream. The turbo code design method includes: selecting a polynomial representing the RSC code from elements of a Galois field generated using a generating polynomial; designing a first rule of an interleaver based on the RSC code; and outputting information representing the designed turbo code to the outside. The polynomial representing the RSC code includes a feedforward polynomial representing a feedforward connection and a feedback polynomial representing a feedback connection, and the feedforward polynomial and the feedback polynomial are respectively a polynomial selected from elements of the Galois field, or a product of multiple polynomials selected from elements of the Galois field.

[0012] According to one embodiment, a Turbo code design device is a Turbo code design device for designing a Turbo code. A Turbo encoder for executing a Turbo code includes: a first convolutional encoder, which generates a parity check stream of input data as a first parity check stream using a predetermined recursive systematic convolutional RSC code; an interleaver, which rearranges the order of an internal sequence of the input data based on a first rule to generate permuted data; and a second convolutional encoder, which generates a parity check stream of permuted data using an RSC code as a second parity check stream. The Turbo code design device includes: an RSC code selection unit, which selects a polynomial representing an RSC code from elements of a Galois field generated using a generating polynomial; a PM design unit, which designs a permutation matrix PM based on a period of the RSC code, wherein PM represents the corresponding relationship between the order of the internal sequence of the input data and the permuted data. a coset design unit for designing a second rule, the second rule being used to divide the input data based on the period of the RSC code to generate multiple non-overlapping sets as multiple cosets; and an output unit for externally outputting information representing the designed Turbo code, the polynomial representing the RSC code includes a feedforward polynomial representing a feedforward connection and a feedback polynomial representing a feedback connection, the feedforward polynomial and the feedback polynomial are respectively a polynomial selected from the elements of the Galois field, or the product of multiple polynomials selected from the elements of the Galois field, when the RSC code is input with input data in which the first bit is 1 and the second bit and thereafter are 0, when the output data thereof is circulated with a predetermined period after a predetermined bit, the bit length of the cyclic part is the period of the RSC code.

[0013] According to one embodiment, a storage medium storing a Turbo code design program stores a program executed by a computing device to implement a process for designing a Turbo code. A Turbo encoder that executes a Turbo code includes a first convolutional encoder, an interleaver, and a second convolutional encoder. The first convolutional encoder generates a parity check stream of input data as a first parity check stream using a predetermined recursive systematic convolutional RSC code. The interleaver rearranges the order of an internal sequence of the input data based on a first rule to generate permuted data. The second convolutional encoder generates a parity check stream of permuted data using an RSC code as a second parity check stream. The process for designing a Turbo code includes: selecting a polynomial representing an RSC code from elements of a Galois field generated using a generating polynomial; designing a first rule of an interleaver based on the RSC code; and outputting information representing the designed Turbo code to the outside. The polynomial representing the RSC code includes a feedforward polynomial representing a feedforward connection and a feedback polynomial representing a feedback connection. The feedforward polynomial and the feedback polynomial are respectively one polynomial selected from the elements of the Galois field or the product of a plurality of polynomials selected from the elements of the Galois field.

[0014] According to one embodiment, a Turbo code using a high performance interleaver can be designed. BRIEF DESCRIPTION OF THE DRAWINGS

[0015] Figure 1A : is a circuit block diagram showing a configuration example of a turbo encoder according to an embodiment.

[0016] Figure 1B This is a circuit block diagram showing a structural example of a convolutional encoder according to one embodiment.

[0017] Figure 2 : is a circuit block diagram showing a configuration example of a turbo code design device according to an embodiment.

[0018] Figure 3 1 is a flowchart showing a configuration example of a process of a turbo code design method according to an embodiment.

[0019] Figure 4 : is a table showing examples of the orders of roots corresponding to a plurality of polynomials and the period of the RSC code, respectively.

[0020] Figure 5 : is a table showing an example of the correspondence relationship between the generator polynomial of the RSC code and each power expression of the element of the Galois field generated by using the generator polynomial.

[0021] Figure 6 This is a table showing an example of a combination of the Hamming weight of a code word, a common polynomial, an input bit sequence as permutation data, and an output bit sequence as a parity check stream when (37 / 21)8 is selected as the RSC code.

[0022] Figure 7 : is a table showing examples of combinations of parameters used in a general formula representing a conversion bit sequence when the Hamming weight of an input bit sequence is 4.

[0023] Figure 8 is a graph showing an example of the results of a computer simulation performed to verify the effectiveness of the RSC code of an embodiment.

[0024] Fig. 9 : is a graph showing an example of a computer simulation result of the performance of a turbo code designed by a turbo code design method according to an embodiment.

[0025] Fig.10 : is a graph showing an example of a computer simulation result of the performance of a turbo code designed by a turbo code design method according to an embodiment.

[0026] Fig.11: is a graph showing an example of a computer simulation result of the performance of a turbo code designed by a turbo code design method according to an embodiment.

[0027] Fig.12 : is a graph showing an example of a computer simulation result of the performance of a turbo code designed by a turbo code design method according to an embodiment.

[0028] Fig.13 : is a circuit block diagram showing a configuration example of a turbo encoder according to an embodiment. DETAILED DESCRIPTION

[0029] The following will describe the manner for implementing the Turbo code design method, Turbo code design device, and storage medium storing the Turbo code design program of the present disclosure with reference to the accompanying drawings.

[0030] (Implementation Method)

[0031] like Figure 1A As shown, a turbo encoder 1 for executing turbo code includes an interleaver 3, a first convolutional encoder 41, and a second convolutional encoder 42. The turbo encoder 1 may further include a connector which is not shown in the figure.

[0032] The first convolutional encoder 41 generates a parity stream 410 of the input data 2 by performing RSC (Recursive System Convolutional) encoding processing on the input data 2. The interleaver 3 rearranges the order of the internal sequence of the input data 2 based on a predetermined rule to generate the permuted data 30. The second convolutional encoder 42 performs RSC encoding processing on the permuted data 30 to generate a parity stream 420 of the permuted data 30.

[0033] The connector not shown in the figure generates output data by turbo encoding the input data 2 based on the input data 2, the parity stream 410 of the input data 2, and the parity stream 420 of the permuted data 30. The connector can generate intermediate data by partially puncturing and multiplexing the parity streams 410 and 420, and multiplexing the intermediate data and the input data 2 to generate output data.

[0034] like Figure 1BAs shown, the convolutional encoders 41 and 42 include delayers 431, 432, 433 and adders. The delayers 431, 432, 433 are connected in series. One part of the adders adds the output of one of the delayers 431, 432, 433 to the input data 2 or the permuted data 30. In addition, another part of the adders generates a parity stream 410 or 420 by adding the input data 2 or the permuted data 30 to the output of one of the delayers 431, 432, 433. The structure of the convolutional encoders 41 and 42 corresponds to the RSC encoding process performed by the convolutional encoders 41 and 42. More specifically, the total number of delayers 431, 432, 433, the total number of adders, and the connection relationship between the delayers 431, 432, 433 and the adders are determined corresponding to the polynomial representing the RSC code implemented by the convolutional encoders 41 and 42. The structures of the convolutional encoders 41 and 42 are the same. The delayers 431 , 432 , and 433 may be shift registers.

[0035] The design of the turbo code executed by the turbo encoder 1 includes designing convolutional encoders 41, 42 and designing an interleaver 3. The design of the convolutional encoders 41, 42 includes selecting a polynomial representing an RSC code from elements of a Galois field generated using a generating polynomial. Here, the polynomial representing the RSC code includes a feedforward polynomial representing a feedforward connection and a feedback polynomial representing a feedback connection. The feedforward polynomial and the feedback polynomial are respectively a polynomial selected from elements of the Galois field, or a product obtained by multiplying multiple polynomials in the elements of the Galois field. The design of the interleaver 3 includes designing a PM (Permutation Matrix) based on the RSC code represented by the selected polynomial, and designing a coset based on the designed PM. PM and coset will be described in detail later.

[0036] Turbo codes can be Figure 2 The turbo code design device 5 shown in the figure is designed. The turbo code design device 5 of this embodiment can be configured as a computer. The turbo code design device 5 includes a bus 51, a computing device 52, a storage device 53, a communication device 54, and an input / output device 55. The bus 51 connects the computing device 52, the storage device 53, the communication device 54, and the input / output device 55 so that they can communicate with each other.

[0037] The operation device 52 includes an RSC code selection unit 521, a PM design unit 522, a coset design unit 523, and an output unit 524. The storage device 53 stores a Turbo code design program in a readable manner. The Turbo code design program can be read from a storage medium 530 storing the Turbo code design program and stored in the storage device 53. The operation device 52 and the storage device 53 cooperate to implement the processing of the Turbo code design program. More specifically, the operation device 52 reads out the Turbo code design program and executes the Turbo code design program using the storage area of ​​the storage device 53, thereby implementing the processing of the RSC code selection unit 521, the PM design unit 522, the coset design unit 523, and the output unit 524. The RSC code selection unit 521, the PM design unit 522, the coset design unit 523, and the output unit 524 are virtual function blocks that implement the processing of the Turbo code design device 5.

[0038] The RSC code selection unit 521 selects an RSC code in step S01 described later. The PM design unit 522 designs a PM in step S02 described later. The coset design unit 523 designs a coset in step S03 described later. The output unit 524 outputs information indicating the designed turbo code to the outside in step S04 described later. The specific operations of these functional blocks will be described later.

[0039] The communication device 54 sends information to the outside via a network not shown in the figure, and receives information from the outside. As an example, the output unit 524 controls the communication device 54 to output information to the outside. The turbo code design program can be received from the outside by the communication device 54 through the network and stored in the storage device 53.

[0040] The input / output device 55 outputs information to the user and receives an operation input by the user. As an example, the input / output device 55 includes a display device for outputting an image, a keyboard and / or a mouse for receiving an input, and the like.

[0041] Reference Figure 3 The flowchart of the present embodiment describes the processing of the turbo code design method. For example, the turbo code design device 5 can be started when it is started. Figure 3 Flowchart of the process.

[0042] exist Figure 3 When the process of the flowchart of starts, step S01 is executed. In step S01, Figure 2 The RSC code selection unit 521 in selects the RSC code. More specifically, the RSC code selection unit 521 selects a polynomial representing the RSC code from the elements of the Galois field of the polynomial. The coefficients of each term of the polynomial as an element included in the Galois field are 0 or 1.

[0043] like Figure 1B As shown in the example of , in the convolution encoders 41 and 42 that execute the RSC code, a part of the adder feed-forwards a part of the output of the delayers 431, 432, and 433 to the output of the convolution encoders 41 and 42. The configuration of this feed-forward connection is represented by a polynomial f(x). Figure 1B In the example of FIG. 1 , the inputs of the convolutional encoders 41 and 42, the output of the first-stage delay 431, and the output of the third-stage delay 433 are feed-forwarded to the output of the convolutional encoder 41. Here, the inputs of the convolutional encoders 41 and 42 are the outputs of the virtual 0th-stage delay. The polynomial representing this configuration is f(x) equals x 0 +x 1 +x 3 , the configuration of this feed-forward connection is represented by the polynomial f(x)=1+x+x 3 .

[0044] Similarly, in Figure 1B In the convolution encoders 41 and 42 that perform the RSC code, a part of the adder feeds back a part of the output of the delayers 431, 432, and 433 to the input of the convolution encoders 41 and 42. The configuration of this feedback connection is represented by a polynomial g(x). Figure 1B In the example of , the output of the second stage delay 432 and the output of the third stage delay 433 are fed back to the input of the convolution encoder 41. The polynomial g(x) representing this configuration is equal to x 2 +x 3 , the configuration of this feedback connection is represented by the polynomial g(x)=x 2 +x 3 At this time, the generation function G of the RSC code is expressed as the following formula 1.

[0045] (Formula 1)

[0046] Here, "G" is a 1×2 matrix representing a generating function of an RSC code. "f(x)" is a polynomial representing a configuration of a feedforward connection. "g(x)" is a polynomial representing a configuration of a feedback connection.

[0047] The input bit sequence input to the input of the convolutional encoders 41 and 42 through the feedback connection is expressed as a polynomial b(x). Furthermore, the output bit sequence output to the output of the convolutional encoders 41 and 42 through the feedforward connection is expressed as a polynomial h(x). At this time, the output c(x) of the RSC code is expressed as the following formula 2.

[0048] (Formula 2)

[0049] Furthermore, the output bit sequence h(x) is expressed as the following formula 3.

[0050] (Formula 3)

[0051] From the above formula 2, we can see that the Hamming weight w of the output c(x) of the RSC code is H (c(x)) is the Hamming weight w based on the input bit sequence b(x) H (b(x)) and the Hamming weight w of the output bit sequence h(x) H (h(x)) is calculated by the following formula 4.

[0052] (Formula 4)

[0053] The Hamming weight of a polynomial is the total number of terms whose coefficients are not 0 among the terms included in the polynomial. In this embodiment, in order to simplify the design of the interleaver 3 of the Turbo code, a polynomial g(x) is selected to represent the configuration of the feedback connection, which makes the Hamming weight of the parity stream 420 (or parity stream 410) output by the convolutional encoder 42 (or the convolutional encoder 41) less than a predetermined first threshold only when the permuted data 30 (or the input data 2) input to the convolutional encoder 42 (or the convolutional encoder 41) meets the predetermined condition. The first threshold can be, for example, the free distance expected to be achieved by the Turbo code, which can be, for example, 42. Alternatively, the first threshold can also be a value calculated based on the desired free distance. As an example, the value obtained by subtracting the Hamming weight of the input bit sequence b(x) and the minimum Hamming weight of the output bit sequence h(x) from the desired free distance is divided by the weight within the period determined by the selected polynomial f(x), for example, 3, and is used as the first threshold. Furthermore, when the distance between bits with a value of "1" in the replacement data 30 (or input data 2) represented in binary is an integer multiple of the period τ of the RSC code, or when the replacement data 30 (or input data 2) can be represented as the sum of these values, the predetermined condition is satisfied. Here, the polynomial g(x) is divisible by a predetermined generating polynomial, and the predetermined generating polynomial satisfies the following condition, that is, there is no combination of at least three polynomials that are different from each other and whose sum is 0 among the elements contained in the Galois field generated by the predetermined generating polynomial.

[0054] Then, a polynomial f(x) representing the configuration of the feedforward connection is selected according to the selected polynomial g(x). As an example, once the polynomial g(x) is determined, polynomials f(x) satisfying the condition are listed, and a polynomial f(x) is selected from the listed polynomials f(x) which makes the polynomial h(x) the maximum for a specific mode.

[0055] Further, in the present embodiment, after the feedback polynomial g(x) is selected in such a way that the Hamming weight of the parity check stream 410, 420 is less than the first threshold value only when the input bit sequence (input data 2 or permuted data 30) satisfies the above conditions, and the feedforward polynomial f(x) is selected in such a way that the Hamming weight of the parity check stream 410, 420 is greater than the second threshold value only when the input bit sequence (input data 2 or permuted data 30) satisfies the above conditions, it is appropriate to refer to the set of factors corresponding to both the selected polynomial g(x) and the polynomial f(x), i.e., the polynomial a(x), as the common polynomial for designing the turbo code of the present embodiment. This correspondence means that the product of the polynomial g(x) and a(x) satisfies the condition of being the input bit sequence b(x), and the product of the polynomial f(x) and a(x) satisfies the condition of being the output bit sequence h(x). The inventors confirmed that when the bit error rate is evaluated using only the codewords included in the set determined in this way, it matches the result of computer simulation with sufficient accuracy. This means that the main codeword modes that play a role in the bit error rate calculation are not missed.

[0056] exist Figure 3 After step S01 in the above, step S02 is performed. In step S02, Figure 2 The PM design unit 522 in the embodiment designs a PM. More specifically, the PM design unit 522 designs a PM (Permutation Matrix) that represents the correspondence between the order of the internal sequence of the input data 2 and the permutation data 30 based on the period of the RSC code. This process is part of the rule design process, and the interleaver 3 rearranges the order of the internal sequence of the input data 2 according to the rule to generate the permutation data 30.

[0057] When input data 2 with the first bit being 1 and the second bit and thereafter being 0 is input to a convolutional encoder 41 that executes an RSC code, when a predetermined bit is predetermined in the output data output from the convolutional encoder 41 and circulates at a predetermined period, the bit length of the cyclic part is the period of the RSC code.

[0058] Figure 4 : is a table showing examples of the orders of roots corresponding to a plurality of polynomials, respectively, and the period of the RSC code. Figure 5 : is a table showing an example of the correspondence relationship between the generator polynomial of the RSC code and the vector expression of the elements expressed by the respective powers of the elements of the Galois Field generated by the generator polynomial. More specifically, the elements of the Galois Field are generated based on the remainder of the generator polynomial.

[0059] In this embodiment, based on Figure 4 and Figure 5, the case where (37 / 21)8 is selected as the RSC code is explained. (37 / 21)8 means that the polynomial representing the configuration of the feedforward connection is 37 in octal, that is, 1+x+x represented by 11111 in binary. 2 +x 3 +x 4 , and the polynomial representing the configuration of the feedback connection is 21 in octal, that is, 1+x represented by 10001 in binary 4 .

[0060] Reference Figure 5 , the case where the polynomial g(x) is divisible by the following generator polynomial is described, wherein the Galois field generated by the generator polynomial contains no combination of at least three polynomials that are different from each other and whose sum is 0. Figure 5 The elements of the Galois field (more precisely, the extended Galois field) generated by the generator polynomial in, for example, from 1+x+x 2 The generated elements include 1, x, and 1+x. Here, since 1, x, and 1+x add up to 0, the above condition of the polynomial g(x) is not satisfied. Similarly, from 1+x+x 4 The generated elements also include 1, x, and 1+x. Here, since the sum of 1, x, and 1+x is 0, the above conditions of the polynomial g(x) are not satisfied. 2 +x 3 The generated elements include 1, x 2 and 1+x 2 , the sum of these three elements is 0, so the above condition of the polynomial g(x) is not satisfied. On the other hand, from 1+x+x 2 +x 3 +x 4 No matter which three elements are selected from the generated elements and added together, the result will not be 0, so the above condition of the polynomial g(x) is satisfied. In addition, since there is only one element generated from 1+x, three different elements cannot be selected, so the above condition of the polynomial g(x) is satisfied.

[0061] Figure 6 is a diagram showing the Hamming weight w of the code word c(x) when (37 / 21)8 is selected as the RSC code. H (c(x)), the common polynomial a(x), the input bit sequence b(x) as the permuted data 30, and the output bit sequence h(x) as an example of the parity stream 420 (also referred to as "parity bit stream"). Figure 6 In the first row of , “b(x)” represents the input bit sequence, “h(x)” represents the output bit sequence, and “w H"(c(x))" represents the Hamming weight of the output c(x) of the RSC code. In addition, "a(x)" simultaneously satisfies "b(x) = a(x)g(x)" and "h(x) = a(x)f(x)". Here, "f(x)" is the function corresponding to the feedforward connection of the delay devices 431, 432, and 433 in the convolution encoders 41 and 42, and "g(x)" is the function corresponding to the feedback connection of the delay devices 431, 432, and 433 in the convolution encoders 41 and 42. Figure 6 In the cells after the second row and the second column of the polynomial, the integer in parentheses indicates the order of the terms in the polynomial whose coefficients are equal to 1. For example, "(0,1)" means "x 0 +x 1 ” or “1+x”, “(0,1,4,5)” means “x 0 +x 1 +x 4 +x 5 ” or “1+x+x 4 +x 5 ”.

[0062] An example of a method of selecting a polynomial f(x) representing a configuration of a feedforward connection is described using a specific example. Here, consider a case where there are two candidates for the polynomial g(x) representing a configuration of a feedback connection. The first candidate is g1(x)=1+x+x 2 , the second candidate is g2(x)=1+x 4 In this case, the second candidate g2(x) that makes the design of the interleaver 3 simpler is selected as the polynomial g(x) representing the configuration of the feedback connection. At this time, there are four candidates for the polynomial f(x) that satisfies the condition. Here, the first candidate is f1(x)=1+x+x 4 The second candidate is f2(x)=1+x 2 +x 4 The third candidate is f3(x)=1+x 3 +x 4 The fourth candidate is f4(x)=1+x+x 2 +x 3 +x 4 Among these candidates, f4(x) is selected as the most suitable candidate. The reason is that the following formula 5 holds.

[0063] [Formula 5]

[0064]

[0065] When the length of the input data 2 is N and the period of the RSC code is τ, the intermediate matrix Π with τ rows and τ columns is connected in the column direction by N / τ 2As an example, when N=32 and τ=4, PM is generated as shown in the following formula 6.

[0066] [Formula 6]

[0067]

[0068] Here, each element of the intermediate matrix Π is an integer between 0 and τ-1. Furthermore, each column of the intermediate matrix Π includes an integer between 0 and τ-1. For example, the intermediate matrix Π is generated as shown in the following formula 7 or formula 8.

[0069] [Formula 7]

[0070]

[0071] [Formula 8]

[0072]

[0073] exist Figure 3 After step S02 in the above, step S03 is executed. In step S03, by Figure 2 The coset design unit 523 in the RSC code is used to design the coset. More specifically, the coset design unit 523 divides the input data 2 into non-overlapping intermediate sets of the same number as the period τ of the RSC code. At this time, the elements with the same remainder after the order of the internal sequence of the input data 2 is divided by the period τ are assigned to the same intermediate set. When the length of the input data 2 is a multiple of the period τ, the number of elements in each intermediate set is the same. Then, integers that are coprime to the period τ are appropriately selected, and the elements of each intermediate set are rearranged in an order equal to the remainder after the selected integer is multiplied by a coefficient increasing from 1 and divided by the number of elements in the intermediate set, generating the same number of cosets as the period τ.

[0074] As an example, when the length of the input data 2 is 32 bits and the period τ of the RSC code is equal to 4, a total of 4 intermediate sets are generated. When the input data 2 is represented as {0, 1, ..., 31} using the order of its internal sequence, the four generated intermediate sets M can be represented as follows using the order of the internal sequence of the input data 2: 0 ,M 1 ,M 2 ,M 3 .

[0075] M 0 ={0,4,8,12,16,20,24,28}

[0076] M 1 ={1,5,9,13,17,21,25,29}

[0077] M2={2,6,10,14,18,22,26,30}

[0078] M 3 ={3,7,11,15,19,23,27,31}

[0079] When "3" is selected as an integer coprime with the period τ, the intermediate set M 0 、M 1 、M 2 、M 3 By performing the above rearrangement, the following four cosets C can be generated: 0 , C 1 , C 2 , C 3 .

[0080] C 0 ={0,12,24,4,16,28,8,20}

[0081] C 1 ={1,13,25,5,17,29,9,21}

[0082] C 2 ={2,14,26,6,18,30,10,22}

[0083] C 3 ={3,15,27,7,19,31,11,23}

[0084] For convenience, the interleaver 3 designed as described above is called a coset interleaver. 0 , C 1 , C 2 and C 3 The order of the internal sequence of the input data 2 is rearranged using a coset interleaver designed as shown in the above "Formula 6" and "Formula 7" to obtain the following permuted data 30.

[0085] Replacement data 30 = {0,1,2,3,13,14,15,12,26,27,24,25,7,4,5,6,16,17,18,19,29,30,31,28,10,11,8,9,23,20,21,22}

[0086] As an example, the inventors have confirmed through calculation that when the Hamming weight of the input bit sequence b(x) is 2, the Hamming weight of the input data 2 input to the interleaver 3 is greater than 14, and the Hamming weight of the permuted data 30 output by the interleaver 3 is also greater than 14. As a result, the Hamming weight of the output c(x) of the RSC code is greater than 30.

[0087] As another example, when the Hamming weight of the input bit sequence b(x) is 4, an interleaver 3 with one of the following three modes is obtained.

[0088] In the first mode, the first bit and the second bit of the input data 2 are rearranged to the same coset. In the first mode, the input bit sequence b4(x) with a Hamming weight of 4 and the permuted bit sequence b'4(x) output by the interleaver 3 inputting the input bit sequence b4(x) can be expressed as the following formula 9.

[0089] [Formula 9]

[0090]

[0091] In the second mode, the first bit and the third bit of the input data 2 are rearranged to the same coset. In the second mode, the input bit sequence b4(x) with a Hamming weight of 4 and the permuted bit sequence b'4(x) output by the interleaver 3 to which the input bit sequence b4(x) is input can be expressed as the following formula 10.

[0092] [Formula 10]

[0093]

[0094] In the third mode, the first bit and the last bit of the input data 2 are rearranged to the same coset. In the third mode, the input bit sequence b4(x) with a Hamming weight of 4 and the permuted bit sequence b'4(x) output by the interleaver 3 inputting the input bit sequence b4(x) can be expressed as the following formula 11.

[0095] [Formula 11]

[0096]

[0097] The permuted bit sequences b'4(x) in the first to third modes described above can be summarized as shown in the following formula 12.

[0098] [Formula 12]

[0099]

[0100] Here, the parameters "p'", "q'", and "v'" are defined as follows Figure 7 “R” indicates the deviation of the coset.

[0101] exist Figure 3 After step S03 in step S04 is executed. In step S04, by Figure 2The output unit 524 in the output unit 524 outputs the Turbo code. More specifically, the information indicating the Turbo code is output, the Turbo code is designed based on the RSC code and the coset interleaver, the RSC code is the RSC code selected in step S01, the coset interleaver is designed based on the PM and the coset, the PM is the PM designed in step S02, and the coset is the coset designed in step S03. Figure 2 The output unit 524 in can output information representing the designed Turbo code to the outside by controlling the communication device 54.

[0102] Figure 3 Step S04 ends, that is, Figure 3 The processing of the flowchart is completed.

[0103] Thus, in the present invention, Figure 3 After designing the convolutional encoders 41 and 42 in step S01, Figure 3 The interleaver 3 is designed in steps S02 and S03. It is worth noting that this order is opposite to the related art.

[0104] (Computer simulation, part 1)

[0105] Figure 8 : is a graph showing an example of the result of a computer simulation performed to verify the effectiveness of the RSC code of the present embodiment. Figure 8 The curve graph in includes a total of five curves G11, G12, G13, G14 and G15. Curve G11 shows the performance of the Turbo code using the RSC code according to the present embodiment. The generating polynomial of the RSC code in curve G11 is (37 / 21) 8. Curve G12 shows the error rate limit of the RSC code of the transfer function of the prior art. Curve G13 shows the performance of the Turbo code using the conversion function of the related art when k=1 in the following formula 13. Curve G14 shows the performance of the Turbo code using the conversion function of the related art when k=2 in the following formula 9. Curve G15 shows the performance of the Turbo code using the conversion function of the related art when k=3 in the following formula 9. The horizontal axes of curves G11 to G15 are all the energy-to-noise density ratio per bit expressed in dB (decibel), and the vertical axis represents BER (Bit Error Ratio). In addition, the bit length N of the input data 2 in curves G11 to G15 is 1024 bits.

[0106] [Formula 13]

[0107]

[0108] The above formula 13 represents the evaluation of the error rate. In formula 13, "N" represents the bit length of each frame of the input data 2 before encoding using the RSC code. "Pb(k)" represents the average bit error rate in the received signal before decoding when the input data 2 of N bits is transmitted using the RSC code. Strictly speaking, the upper limit of the range of "d" should be infinite, but here it is practically approximated to "d" in order to control the amount of calculation. free + k". The function "Q" represents the probability of an error. In addition, the set of common polynomials a(x) "A' c (d)" is a set of common polynomials a(x) that satisfy the condition that the Hamming weight of the output bit sequence h(x) and the Hamming weight of the input bit sequence b(x) are included in a predetermined range.

[0109] from Figure 8 It can be seen from the curve graph that although there is a certain difference between the RSC code according to the present embodiment and the conversion function according to the related art, when the energy-to-noise density ratio per bit increases, the two converge to the same value. This means that the approximation adopted by the RSC code according to the present embodiment has sufficient accuracy.

[0110] (Computer simulation, part 2)

[0111] Fig. 9 : is a graph showing an example of the result of a computer simulation on the performance of the turbo code designed by the turbo code design method according to the present embodiment. Fig. 9 The curve graph in FIG. 1 includes a total of three curves G21, G22 and G23. Curve G21 shows an example of the performance of a Turbo code using the coset interleaver of the present embodiment. Curve G22 shows an example of the performance of a Turbo code using an S-random interleaver. Curve G23 shows an example of the performance of a Turbo code using a QPP interleaver. The horizontal axes of the curves G21, G22 and G23 all represent the energy-to-noise density ratio per bit in dB, and the vertical axes represent BER. In addition, the bit length N of the input data 2 in the curves G21, G22 and G23 is 1024 bits.

[0112] from Fig. 9 It can be seen from the curve graph that when the bit length N of the input data 2 is a relatively long 1024 bits and the energy-to-noise density ratio per bit is above 1.2 dB, the BER of the Turbo code using the coset interleaver of this embodiment is significantly lower than the BER of the Turbo code using the S-random interleaver or the QPP interleaver. This confirms that, at least under the above conditions, the performance of the Turbo code using the coset interleaver of this embodiment is significantly higher than the performance of the Turbo code using the S-random interleaver or the QPP interleaver.

[0113] Fig.10: is a graph showing an example of the result of computer simulation of the performance of the turbo code designed by the turbo code design method according to the present embodiment. Fig.10 The graph in FIG. 3 includes two curves G31 and G32 in total. Curve G31 shows an example of the performance of a Turbo code using the coset interleaver of the present embodiment. Curve G32 shows an example of the performance of a Turbo code using an S-random interleaver. The horizontal axis of curves G31 and G32 both represent the energy-to-noise density ratio per bit in dB, and the vertical axis represents BER. In addition, the bit length N of the input data 2 in curves G31 and G32 is 2048 bits.

[0114] from Fig.10 As can be seen from the curve diagram, when the bit length N of the input data 2 is Fig. 9 When the length of the code is longer than 2048 bits and the energy-to-noise density ratio per bit is above 0.6 dB, the BER of the Turbo code using the coset interleaver of this embodiment is significantly lower than the BER of the Turbo code using the S-random interleaver. This confirms that, at least under the above conditions, the performance of the Turbo code using the coset interleaver of this embodiment is significantly higher than the performance of the Turbo code using the S-random interleaver.

[0115] Fig.11 : is a graph showing an example of the result of computer simulation of the performance of the turbo code designed by the turbo code design method according to the present embodiment. Fig.11 The graph in FIG. 4 includes two curves G41 and G42 in total. Curve G41 shows an example of the performance of a Turbo code using the coset interleaver of the present embodiment. Curve G42 shows an example of the performance of a Turbo code using an S-random interleaver. The horizontal axis of curves G41 and G42 both represent the energy-to-noise density ratio per bit in dB, and the vertical axis represents BER. In addition, the bit length N of the input data 2 in curves G41 and G42 is 4096 bits.

[0116] from Fig.11 As can be seen from the curve diagram, when the bit length N of the input data 2 is Fig.10 When the length of the code is longer than 4096 bits and the energy-to-noise density ratio per bit is above 0.4 dB, the BER of the Turbo code using the coset interleaver of this embodiment is significantly lower than the BER of the Turbo code using the S-random interleaver. This confirms that, at least under the above conditions, the performance of the Turbo code using the coset interleaver of this embodiment is significantly higher than the performance of the Turbo code using the S-random interleaver.

[0117] Fig.12: is a graph showing an example of the result of computer simulation of the performance of the turbo code designed by the turbo code design method according to the present embodiment. Fig.12 The curve graph in FIG. 5 includes a total of three curves G51, G52 and G53. Curve G51 shows an example of the performance of a Turbo code using the coset interleaver of the present embodiment. Curve G52 shows an example of the performance of a Turbo code using an S-random interleaver. Curve G53 shows an example of the performance of a Turbo code using a QPP interleaver. The horizontal axes of the curves G51, G52 and G53 all represent the energy-to-noise density ratio per bit in dB, and the vertical axes represent BER. Again, the bit length N of the input data 2 in the curves G51, G52 and G53 is 8192 bits.

[0118] from Fig.12 As can be seen from the curve diagram, when the bit length N of the input data 2 is Fig.11 When the length of the code is longer than 8192 bits and the energy-to-noise density ratio per bit is above 0.4 dB, the BER of the Turbo code using the coset interleaver of this embodiment is significantly lower than the BER of the Turbo code using the S-random interleaver. This confirms that, at least under the above conditions, the performance of the Turbo code using the coset interleaver of this embodiment is significantly higher than the performance of the Turbo code using the S-random interleaver.

[0119] As described above, the Turbo code using the coset interleaver designed by the Turbo code design method, Turbo code design device 5 and Turbo code design program of the present invention has higher performance than the Turbo code using the S-random interleaver or the QPP interleaver at least under the above-mentioned computer simulation conditions. Further, the inventors confirmed through computer simulation that in the Turbo code of the present embodiment, when different values ​​of depth D and deviation R are set for each coset, even if the bit length N of the input data 2 is extended to 16832 bits, better performance than the Turbo code using the S-random interleaver can be obtained.

[0120] (Variation 1)

[0121] In the above embodiment, it is described as follows Figure 1A The turbo encoder 1 shown in FIG. 1 includes an interleaver 3 and two convolutional encoders 41 and 42. As a variation of the structure, Fig.13 As shown, the turbo encoder 1 may include two interleavers 3A, 3B and three convolutional encoders 41, 42A, 42B.

[0122] Fig.13 The configuration of the first convolutional encoder 41 in Figure 1A and Figure 1BThe first convolutional encoder 41 in is similarly provided with input data 2 and outputs a first parity stream 410 . Fig.13 The first parity stream 410 in Figure 1A and Figure 1B The first parity stream 410 in is the same.

[0123] Fig.13 The configuration of the first interleaver 3A in Figure 1A and Figure 1B The interleaver 3 in is similarly supplied with the input data 2 and outputs the first permuted data 30A. Fig.13 The first replacement data 30A in Figure 1A and Figure 1B The replacement data 30 in is the same. Fig.13 The configuration of the second convolutional encoder 42A in Figure 1A Similarly, the second convolutional encoder 42 in is provided with the first arranged data 30A and outputs a second parity stream 420. Fig.13 The second parity stream 420A in Figure 1A and Figure 1B The same as the second parity stream 420 in .

[0124] Fig.13 The second interleaver 3B in is provided with input data 2 and based on Fig.13 The first interleaver 3A outputs the second permuted data 30B according to a different rule. Fig.13 The second replacement data 30B in Fig.13 The first replacement data 30A in is different. Fig.13 The configuration of the third convolutional encoder 42B in Fig.13 The second convolutional encoder 42A in is similarly supplied with the second converted data 30B and outputs a third parity stream 420B. Fig.13 The third parity stream 420B in Fig.13 The second parity stream 420A in is different.

[0125] As with the Turbo encoder 1 in FIG1 , Fig.13 The turbo encoder 1 in the embodiment further includes a connector (not shown in the figure). The connector performs turbo encoding on the input data 2 based on the input data 2, the first parity stream 410, the second parity stream 420A, and the third parity stream 420B to generate output data. The connector can generate intermediate data by partially puncturing and multiplexing the parity streams 410, 420A, and 420B, and generate output data by multiplexing the intermediate data and the input data 2.

[0126] When not distinguishing Fig.13When the interleavers 3A and 3B in FIG. 1 are not distinguished, they are collectively referred to as interleavers 3. Fig.13 When the replacement data 30A and 30B are not distinguished, they are collectively referred to as replacement data 30. Fig.13 When the convolutional encoders 42A and 42B in FIG. 4 are referred to as convolutional encoders 42A and 42B, they are collectively referred to as convolutional encoders 42. Fig.13 When the parity check streams 420A and 420B in the data transmission unit are referred to as parity check streams 420, they are collectively referred to as parity check streams 420. Even in this generalization, the relationship between the interleaver 3, the permuted data 30, the convolutional encoder 42, and the parity check stream 420 is the same as that in the reference numeral 420. Figure 1B Just as described.

[0127] In addition, as Fig.13 A further variation of the structure may be to add a further combination of the interleaver 3 and the convolutional encoder 42 in parallel.

[0128] The invention of the present inventor has been specifically described above based on the embodiments, but the present invention is not limited to the above embodiments, and various changes can be made within the scope of the gist thereof. In addition, the various features described in the embodiments can be freely combined within the scope of technical non-contradiction.

[0129] The present invention claims priority based on Japanese Patent Application No. 2022-182371 filed on November 15, 2022, and incorporates the entire disclosure thereof herein.

Claims

1. A Turbo code design method for designing a Turbo code, characterized in that: A turbo encoder for executing the turbo code, comprising: A first convolutional encoder generates a parity check stream of input data as a first parity check stream using a predetermined recursive systematic convolutional (RSC) code; an interleaver that rearranges the order of the internal sequence of the input data based on a first rule to generate permuted data; and a second convolutional encoder that generates a parity stream of the permuted data as a second parity stream using the RSC code, The Turbo code design method comprises: Selecting a polynomial representing the RSC code from elements of a Galois field generated using a generating polynomial; Designing the first rule of the interleaver based on the RSC code; and Outputting information indicating the designed Turbo code to the outside, The polynomial representing the RSC code includes a feedforward polynomial representing a feedforward connection and a feedback polynomial representing a feedback connection, The feedforward polynomial and the feedback polynomial are respectively one polynomial selected from the elements of the Galois field or the product of a plurality of polynomials selected from the elements of the Galois field.

2. The Turbo code design method according to claim 1, wherein: The second convolutional encoder comprises: A plurality of delay devices connected in series; a first adder group feed-forward connecting outputs of a portion of the plurality of delays to an output of the second convolutional encoder; and a second adder group, wherein the output feedback of a part of the plurality of delay devices is connected to the input of the second convolutional encoder, Selecting the polynomial representing the RSC code comprises: Selecting a polynomial g(x) for representing the configuration of the feedback connection so that the Hamming weight of the parity check stream output by the second convolutional encoder is less than a predetermined first threshold only when the permuted data input to the second convolutional encoder satisfies a predetermined condition; and a polynomial f(x) for representing the configuration of the feed-forward connection is selected so that the Hamming weight of the parity check stream output by the second convolutional encoder is greater than a predetermined second threshold only when the permuted data input to the second convolutional encoder satisfies the predetermined condition, The predetermined condition refers to: The replacement data is a value in which the distance between bits with a value of "1" in the replacement data represented by binary is an integer multiple of the period of the RSC code, or a sum of multiple values ​​in which the distance between bits with a value of "1" in the replacement data represented by binary is an integer multiple of the period of the RSC code, and The feedback polynomial g(x) is divisible by a predetermined generator polynomial, and the predetermined generator polynomial satisfies the following condition: the Galois field generated by the predetermined generator polynomial contains no combination of at least three polynomials that are different from each other and whose sum is 0.

3. The Turbo code design method according to claim 2, characterized in that: The first threshold is a value calculated based on an expected free distance in the turbo code.

4. The Turbo code design method according to claim 3, characterized in that: The first threshold is 42.

5. The Turbo code design method according to any one of claims 2 to 4, characterized in that: The first convolutional encoder has the same structure as the second convolutional encoder.

6. The Turbo code design method according to claim 5, characterized in that: Designing the first rule of the interleaver includes: designing a permutation matrix PM based on the period of the RSC code, the PM representing a corresponding relationship in order of an internal sequence between the input data and the permutation data; and The input data is divided based on the period of the RSC code to generate a plurality of disjoint sets as a plurality of cosets, When the RSC code is input with the first bit being 1 and the second bit and thereafter being 0, and the output data cycles with a predetermined period after a predetermined bit, the bit length of the cycle portion is the period of the RSC code.

7. The Turbo code design method according to claim 6, characterized in that: The design of the PM includes: generating a first matrix having τ rows and τ columns, wherein when the period of the RSC code is τ, each element of the first matrix is ​​an integer between 0 and τ-1, and each column contains an integer between 0 and τ-1; and The first matrix is ​​repeatedly connected in the column direction based on the period and the length of the input data to generate a second matrix as the PM.

8. The Turbo code design method according to claim 7, characterized in that: The generating a plurality of sets as the plurality of cosets comprises: dividing the input data into disjoint intermediate sets equal in number to the periods of the RSC code; and generating the plurality of cosets by rearranging the order of a plurality of elements in each of the plurality of intermediate sets, The segmentation includes: assigning the elements included in the input data, which have the same remainder after the order of the internal sequence of the input data is divided by the period, to the same intermediate set among the multiple intermediate sets, The rearrangement includes: For each of the plurality of intermediate sets, preparing an integer that is relatively prime to the period; Prepare a coefficient that increases from 1; and The elements of each of the multiple intermediate sets are rearranged in an order equal to the remainder obtained by multiplying the selected integer by the coefficient and then dividing the remainder by the number of elements of each of the multiple intermediate sets.

9. The Turbo code design method according to claim 1, characterized in that: The bit length of the input data is less than 16384 bits.

10. The Turbo code design method according to claim 1, characterized in that: The bit length of the input data is less than 8192 bits.

11. The Turbo code design method according to claim 1, characterized in that: The bit length of the input data is less than 1024 bits.

12. The Turbo code design method according to claim 2, characterized in that: When the Hamming weight of the input bit sequence input to the second convolutional encoder through the feedback connection is 2, the Hamming weight of the input data input to the interleaver is greater than 14, and the Hamming weight of the permuted data output by the interleaver is greater than 14.

13. The Turbo code design method according to claim 1, characterized in that: The Turbo encoder comprises: a second interleaver, which is different from the interleaver as the first interleaver, rearranges the order of the internal sequence of the input data based on a second rule different from the first rule to generate second permuted data different from the permuted data as the first permuted data; and a third convolutional encoder that generates a parity stream of the second permuted data as a third parity stream using the RSC code, The Turbo code design method further includes: The second rule of the second interleaver is designed based on the RSC code.

14. A Turbo code design device for designing a Turbo code, wherein: A turbo encoder for executing the turbo code, comprising: A first convolutional encoder generates a parity check stream of input data as a first parity check stream using a predetermined recursive systematic convolutional (RSC) code; an interleaver that rearranges the order of the internal sequence of the input data based on a first rule to generate permuted data; and a second convolutional encoder that generates a parity stream of the permuted data as a second parity stream using the RSC code, The Turbo code design device comprises: An RSC code selection unit selects a polynomial representing the RSC code from elements of a Galois field generated using a generating polynomial; A PM design unit, which designs a permutation matrix PM based on the period of the RSC code, wherein the PM represents a corresponding relationship between the order of the internal sequence of the input data and the permutation data; a coset design unit, configured to design a second rule, wherein the second rule is used to divide the input data based on the period of the RSC code to generate a plurality of disjoint sets as a plurality of cosets; and an output unit, outputting information indicating the designed Turbo code to the outside, The polynomial representing the RSC code includes a feedforward polynomial representing a feedforward connection and a feedback polynomial representing a feedback connection, The feedforward polynomial and the feedback polynomial are respectively one polynomial selected from the elements of the Galois field, or the product of a plurality of polynomials selected from the elements of the Galois field, When the RSC code is input with the first bit being 1 and the second bit and thereafter being 0, and the output data cycles with a predetermined period after a predetermined bit, the bit length of the cycle portion is the period of the RSC code.

15. A storage medium storing a Turbo code design program, wherein the Turbo code design program is executed by a computing device to implement a process for designing a Turbo code, characterized in that: A turbo encoder for executing the turbo code, comprising: A first convolutional encoder generates a parity check stream of input data as a first parity check stream using a predetermined recursive systematic convolutional (RSC) code; an interleaver that rearranges the order of the internal sequence of the input data based on a first rule to generate permuted data; and a second convolutional encoder that generates a parity stream of the permuted data as a second parity stream using the RSC code, The processing includes: Selecting a polynomial representing the RSC code from elements of a Galois field generated using a generating polynomial; Designing the first rule of the interleaver based on the RSC code; and Outputting information indicating the designed Turbo code to the outside, The polynomial representing the RSC code includes a feedforward polynomial representing a feedforward connection and a feedback polynomial representing a feedback connection, The feedforward polynomial and the feedback polynomial are respectively one polynomial selected from the elements of the Galois field or the product of a plurality of polynomials selected from the elements of the Galois field.

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