SSD Data Clearing Method, Device, Computer Equipment and Storage Medium

Abstract

The present application relates to an SSD data clearing method, apparatus, computer device, and storage medium. The SSD data clearing method includes: receiving a plurality of data clearing requests, calculating the total information data volume of the plurality of data clearing requests, and detecting the available storage space of the SRAM; determining whether the available storage space is less than the total information data volume, and if the available storage space is less than the total information data volume, determining the priority of each data clearing request. The priority of the data clearing request includes a first priority and a second priority, and screening the data clearing requests according to the priority of the data clearing requests; performing a cache eviction algorithm on the SRAM so that the remaining storage space of the SRAM is not less than the total information data volume of the data clearing requests with the first priority; writing the data clearing requests with the first priority into the SRAM; and executing the data clearing requests. The present application has the effect of improving the data clearing efficiency of the SSD when the capacity of the SRAM is small or the number of data clearing requests is excessive.

Description

Technical Field

[0001] This application relates to the technical field of SSD storage management, and in particular, to an SSD data clearing method, device, computer device, and storage medium. Background Art

[0002] Currently, as a high-performance data storage device, SSDs are widely used in fields such as cloud computing, databases, and high-speed computing. Since SSDs use NAND flash as the main storage medium, their data storage management involves mechanisms such as cache management, data clearing, and garbage collection to ensure efficient storage and read performance.

[0003] Currently, SSD data clearing methods usually rely on sequential scheduling, that is, writing data clearing requests one by one into SRAM and performing data clearing operations. However, when the SRAM capacity is small or the number of data clearing requests is too large, it is necessary to wait for the SRAM to free up storage space before continuing to process new clearing requests, resulting in some data clearing requests that need to be processed in a timely manner cannot be processed, reducing the data clearing efficiency. Summary of the Invention

[0004] In order to solve the problem that when the SRAM capacity is small or the number of data clearing requests is too large, the data clearing requests that need to be processed in a timely manner cannot be processed in a timely manner, this application provides an SSD data clearing method, device, computer device, and storage medium.

[0005] The first object of the above invention of this application is achieved through the following technical solutions:

[0006] An SSD data clearing method, the SSD data clearing method is applicable to an SSD solid-state drive, the SSD solid-state drive has an SRAM and an auxiliary storage medium, and the SSD data clearing method includes:

[0007] Receiving multiple data clearing requests for a single data operation, calculating the total information data volume of the multiple data clearing requests, and detecting the available storage space of the SRAM;

[0008] Judging whether the available storage space is less than the total information data volume. If the available storage space is less than the total information data volume, determining the priority of each data clearing request. The priority of the data clearing request includes a first priority and a second priority, and screening the data clearing requests according to the priority of the data clearing request, where the first priority is higher than the second priority;

[0009] Performing a cache eviction algorithm on the SRAM so that the remaining storage space of the SRAM is not less than the total information data volume of the data clearing requests with the first priority;

[0010] Write the data clearing request with the first priority to the SRAM, and write the data clearing request with the second priority to the auxiliary storage medium;

[0011] Execute the data clearing request.

[0012] By adopting the above technical solutions, by receiving multiple data clearing requests for a single data operation and calculating the total information data volume of the multiple data clearing requests, it is possible to accurately evaluate the storage space required for the multiple data clearing requests before data clearing, so as to reasonably schedule the storage resources of the SRAM and avoid task blocking or delay caused by insufficient storage space; by detecting the available storage space of the SRAM and determining whether the available storage space is less than the total information data volume, it is possible to pre-evaluate the storage space status before writing the data clearing request, so as to avoid the backlog of data clearing requests and improve the overall efficiency of the write operation; by determining the priority of the data clearing request and screening the data clearing requests according to the priority, it is possible to ensure that the data clearing requests related to high time sensitivity or system stability are executed first, so as to improve the execution efficiency of the data clearing requests and reduce the performance degradation caused by system resource competition; by executing the cache eviction algorithm to free up enough space in the SRAM to ensure that the data clearing request with the first priority can be executed smoothly, it is possible to optimize the cache management while ensuring the normal execution of high-priority tasks, thereby improving the data clearing efficiency of the SSD.

[0013] In one example, the present application can be further configured as: the execution of the cache eviction algorithm on the SRAM includes:

[0014] Obtain the access frequency and access time of multiple written data blocks in the SRAM;

[0015] Determine the cache eviction coefficient of the corresponding written data block in the SRAM according to the access frequency and the access time;

[0016] Judge whether the cache eviction coefficient is not greater than a first preset cache eviction value;

[0017] If the cache eviction coefficient is not greater than the first preset cache eviction value, execute the cache eviction algorithm on the corresponding written data block in the SRAM, and the cache eviction algorithm includes the LRU algorithm and the LFU algorithm;

[0018] If the cache eviction coefficient is greater than the first preset cache eviction value, retain the data of the corresponding written data block in the SRAM.

[0019] By adopting the above technical solution, by obtaining the access frequencies and access times of multiple written data blocks in the SRAM, the usage conditions of the data blocks can be accurately grasped, thereby providing basic data support for the cache management strategy and improving the rationality of the cache replacement decision; by calculating the cache replacement coefficient and determining whether it is not greater than the first preset cache replacement value, data blocks with low priority or low-frequency access can be effectively screened, thereby freeing up more cache space without affecting the access to high-frequency data and improving the utilization rate of storage resources; by executing the cache replacement algorithm on the data blocks that meet the conditions and adopting a strategy that combines LRU and LFU, the access frequency and time factors can be taken into account, thereby ensuring that high-value data remains in the written data blocks as much as possible and clearing the written data blocks occupied by low-value data as much as possible, so as to free up sufficient SRAM space.

[0020] In one example, the present application can be further configured as: the determining the cache replacement coefficient of the corresponding written data block in the SRAM according to the access frequency and the access time includes:

[0021] Through the cache replacement coefficient calculation formula:

[0022]

[0023] Calculating the cache replacement coefficient, where C is the cache replacement coefficient, T is the access time, F is the access frequency, and α and β are weight coefficients.

[0024] By adopting the above technical solution, by calculating the cache replacement coefficient based on the access frequency and the access time, the cache replacement algorithm executed on the written data blocks can be intelligently adjusted according to the historical access conditions of the written data blocks, thereby optimizing the cache management of the SRAM and improving the data access and storage efficiency; by setting the weight parameters α and β to balance the access frequency and the access time, the cache replacement strategy can be flexibly adjusted in different application scenarios, so as to free up sufficient SRAM space as much as possible.

[0025] In one example, the present application can be further configured as: the executing the cache replacement algorithm on the corresponding written data block in the SRAM includes:

[0026] Judging whether the cache replacement coefficient is not greater than a second preset cache replacement value;

[0027] If the cache replacement coefficient is not greater than the second preset cache replacement value, then combining multiple corresponding written data blocks into a first data block group, and then executing the LRU algorithm on the first data block group;

[0028] If the cache eviction coefficient is greater than the second preset cache eviction value, then a plurality of corresponding write data blocks are merged into a second data block group, and then the LFU algorithm is executed on the second data block group.

[0029] By adopting the above technical solution, by determining whether the cache eviction coefficient is not greater than the second preset cache eviction value, the screening conditions can be further optimized before data block eviction, so as to preferentially evict low-value data blocks when storage resources are tight, and improve the utilization efficiency of the SRAM storage space.

[0030] In one example of the present application, it can be further configured as: determining the priority of each data clearing request, where the priority of the data clearing request includes a first priority and a second priority, and screening the data clearing requests according to the priority of the data clearing request, including:

[0031] Obtain the creation time and execution deadline of the data clearing request;

[0032] Determine the remaining execution time of the data clearing request according to the creation time and the execution deadline;

[0033] Judge whether the remaining execution time is greater than a preset time value;

[0034] If the remaining execution time is not greater than the preset time value, then determine the priority of the corresponding data clearing request as the first priority;

[0035] If the remaining execution time is greater than the preset time value, then determine the priority of the corresponding data clearing request as the second priority.

[0036] By adopting the above technical solution, by obtaining the creation time and execution deadline of the data clearing request and calculating the remaining execution time, the urgency of the data clearing request can be accurately evaluated, so as to ensure the rationality of task scheduling and improve the resource allocation efficiency; by comparing the remaining execution time with the preset time value and determining the priority of the data clearing request according to the calculation result, it can ensure that time-sensitive tasks are executed first, thereby reducing data consistency problems caused by delayed processing and improving the data clearing efficiency of the SSD.

[0037] In one example of the present application, it can be further configured as: before calculating the total information data volume of a plurality of the data clearing requests, it further includes:

[0038] Detect the addresses of the cleared data blocks pointed to by a plurality of the data clearing requests;

[0039] Judge whether the addresses of a plurality of the cleared data blocks coincide;

[0040] If the addresses of multiple said data clearing blocks coincide, the corresponding said data clearing requests are merged into a new data clearing request.

[0041] By adopting the above technical solution, by detecting the addresses of the data clearing blocks pointed to by multiple data clearing requests and determining whether there is a coincidence, duplicate clearing operations can be avoided, thereby reducing the unnecessary data reading and writing burden and improving the data clearing efficiency of the SSD; by merging multiple data clearing requests pointing to the same data block into a new data clearing request, redundant requests can be reduced, thereby optimizing task scheduling and improving the execution efficiency of the data clearing task.

[0042] The second inventive object of the present application is achieved by the following technical solution:

[0043] An SSD data device, the SSD data device comprising:

[0044] A request processing module, configured to receive multiple data clearing requests for a single data operation and calculate the total information data volume of the multiple said data clearing requests;

[0045] A storage space management module, configured to detect the available storage space of the SRAM and determine whether the available storage space is less than the total information data volume;

[0046] A priority allocation module, configured to determine the priority of each said data clearing request when the available storage space is less than the total information data volume and screen the data clearing requests according to the priority of the data clearing requests;

[0047] A cache management module, configured to perform a cache eviction algorithm on the SRAM so that the remaining storage space of the SRAM is not less than the total information data volume of the data clearing requests of the first priority;

[0048] A data writing module, configured to write the data clearing requests of the first priority into the SRAM and write the data clearing requests of the second priority into an auxiliary storage medium;

[0049] A data clearing execution module, configured to execute the data clearing requests.

[0050] By adopting the above technical solution, by receiving multiple data clearing requests for a single data operation and calculating the total information data volume of the multiple data clearing requests, it is possible to accurately evaluate the storage space required for the multiple data clearing requests before data clearing, so as to reasonably schedule the storage resources of the SRAM and avoid task blocking or delay caused by insufficient storage space; by detecting the available storage space of the SRAM and determining whether the available storage space is less than the total information data volume, it is possible to evaluate the storage space status in advance before the data clearing request is written, so as to avoid the backlog of data clearing requests and improve the overall efficiency of the write operation; by determining the priority of the data clearing requests and screening the data clearing requests according to the priority, it is possible to ensure that the data clearing requests related to high time sensitivity or system stability are executed first, so as to improve the execution efficiency of the data clearing requests and reduce the performance degradation caused by system resource competition; by executing the cache eviction algorithm to free up enough SRAM space to ensure that the data clearing requests with the first priority can be executed smoothly, it is possible to optimize the cache management while ensuring the normal execution of high-priority tasks, so as to improve the data clearing efficiency of the SSD.

[0051] The above object three of the present application is achieved by the following technical solution:

[0052] A computer device includes a memory, a processor, and a computer program stored in the memory and executable on the processor. When the processor executes the computer program, the steps of the above SSD data clearing method are implemented.

[0053] The above object four of the present application is achieved by the following technical solution:

[0054] A computer-readable storage medium stores a computer program. When the computer program is executed by a processor, the steps of the above SSD data clearing method are implemented.

[0055] In summary, the present application includes the following beneficial technical effects:

[0056] 1. By receiving multiple data clearing requests for a single data operation and calculating the total information data volume of multiple data clearing requests, the storage space required for multiple data clearing requests can be accurately evaluated before data clearing, thereby reasonably scheduling the storage resources of SRAM and avoiding task blocking or delay caused by insufficient storage space; by detecting the available storage space of SRAM and judging whether the available storage space is less than the total information data volume, the storage space status can be evaluated in advance before the data clearing request is written, thereby avoiding the backlog of data clearing requests and improving the overall efficiency of write operations; by determining the priority of data clearing requests and screening data clearing requests according to the priority, it can ensure that data clearing requests with high time sensitivity or related to system stability are executed first, thereby improving the execution efficiency of data clearing requests and reducing the performance degradation caused by system resource competition; by executing the cache elimination algorithm, sufficient SRAM space is freed up to ensure that the first priority data clearing request can be executed smoothly, and the cache management can be optimized while ensuring the normal execution of high-priority tasks, thereby improving the data clearing efficiency of SSD;

[0057] 2. By obtaining the access frequency and access time of multiple write data blocks in SRAM, the usage of data blocks can be accurately grasped, thereby providing basic data support for cache management strategies and improving the rationality of cache elimination decisions; by calculating the cache elimination coefficient and judging whether it is not greater than the first preset cache elimination value, low-priority or low-frequency access data blocks can be effectively screened, thereby freeing up more cache space without affecting high-frequency data access, thereby improving the utilization rate of storage resources; by executing the cache elimination algorithm for qualified data blocks and adopting a strategy combining LRU and LFU, the access frequency and time factors can be taken into account, thereby ensuring that high-value data is retained in the write data blocks as much as possible, and clearing the write data blocks occupied by low-value data as much as possible, thereby freeing up sufficient SRAM space;

[0058] 3. By judging whether the cache elimination coefficient is not greater than the second preset cache elimination value, the screening conditions can be further optimized before the data block is eliminated, so that low-value data blocks are eliminated first when storage resources are tight, thereby improving the utilization efficiency of the SRAM storage space. BRIEF DESCRIPTION OF THE DRAWINGS

[0059] Figure 1 is a flow chart of a method for clearing SSD data in one embodiment of the present application;

[0060] Figure 2 is a flowchart for implementing step S3 in the SSD data clearing method in one embodiment of the present application;

[0061] Figure 3 is a flowchart for implementing step S32 in the SSD data clearing method in one embodiment of the present application;

[0062] Figure 4 It is a flowchart of implementing step S34 in the SSD data clearing method according to an embodiment of the present application;

[0063] Figure 5 It is a flowchart of implementing step S2 in the SSD data clearing method according to an embodiment of the present application;

[0064] Figure 6 It is another flowchart of the SSD data clearing method according to an embodiment of the present application;

[0065] Figure 7 It is a principle block diagram of an SSD data clearing device according to an embodiment of the present application;

[0066] Figure 8 It is a schematic diagram of a device according to an embodiment of the present application. Detailed implementation manners

[0067] The present application will be further described in detail below with reference to the accompanying drawings.

[0068] In one embodiment, as Figure 1 shown, the present application discloses an SSD (Solid State Disk) data clearing method, which specifically includes the following steps:

[0069] S1: Receive multiple data clearing requests for a single data operation, calculate the total information data volume of the multiple data clearing requests, and detect the available storage space of the SRAM.

[0070] Specifically, after receiving multiple data clearing requests, each data clearing request is parsed to extract the information data volume of the data clearing request, and then the total information data volume of the multiple data clearing requests is calculated. When detecting the available storage space of the SRAM (Static Random-Access Memory), the current usage status of the SRAM is obtained, the total size of the stored data blocks is checked, and the available storage space of the SRAM is calculated.

[0071] In this embodiment, the information data volume of the data clearing request is the space size occupied by the data clearing request in the SRAM after the data clearing request is written into the SRAM.

[0072] S2: Determine whether the available storage space is less than the total information data volume. If the available storage space is less than the total information data volume, determine the priority of each data clearing request. The priority of the data clearing request includes a first priority and a second priority, and the data clearing requests are screened according to the priority of the data clearing request, where the first priority is higher than the second priority.

[0073] Specifically, the available storage space is compared with the total amount of information data. If the available storage space is less than the total amount of information data, priorities are assigned according to the importance of the data clearing requests. During the process of determining priorities, multiple factors are considered, including the timeliness of the requests, the impact of data clearing on system performance, the historical execution frequency of the requests, etc. The first-priority data clearing requests include requests that are time-sensitive, affect data integrity or system stability, while the second-priority data clearing requests are usually non-critical clearing operations or tasks that can be deferred.

[0074] S3: Execute a cache eviction algorithm on the SRAM so that the remaining storage space of the SRAM is not less than the total amount of information data of the first-priority data clearing requests.

[0075] Specifically, calculate the amount of information data of all the first-priority data clearing requests, and then execute a cache eviction algorithm on the SRAM to free up the storage space of the SRAM. During the process of executing the cache eviction algorithm on the SRAM, select data blocks with low access frequency or long unaccessed time in the SRAM as the priority objects to be cleared, and at the same time avoid clearing data blocks that still have access requirements recently to reduce the impact on subsequent system operations. Also, when executing the cache eviction algorithm on the SRAM, record the meta-information of the cleared data blocks to ensure data consistency, and reserve some SRAM space to handle sudden data write requests.

[0076] Further, after executing the cache eviction algorithm on the SRAM, detect the available storage space of the SRAM again, and determine whether the available storage space of the SRAM is less than the total amount of information data. If the available storage space of the SRAM is less than the amount of information data of all the first-priority data clearing requests, execute the cache eviction algorithm on the SRAM again, and loop like this so that the remaining storage space of the SRAM is not less than the total amount of information data of the first-priority data clearing requests.

[0077] S4: Write the first-priority data clearing requests into the SRAM, and write the second-priority data clearing requests into the auxiliary storage medium.

[0078] Specifically, when writing the data clearing requests, perform the writing operation in the order of the priorities of the data clearing requests, first ensure the storage requirements of the first-priority data clearing requests, write the first-priority data clearing requests into the SRAM, and at the same time ensure that the storage resources required for the first-priority data clearing requests have been locked to avoid being overwritten later, and write the second-priority data clearing requests into the auxiliary storage medium.

[0079] Further, mark the execution status of the data clearing request with the second priority, and ensure that after the data clearing request with the first priority and when the storage space of the SRAM is sufficient, write the data clearing request with the second priority into the SRAM, thereby improving the execution efficiency of the data clearing request with the second priority.

[0080] In some specific embodiments, the execution status of the data clearing request with the second priority can be marked according to the timeliness of the data clearing request with the second priority. Mark the execution status of the data clearing request with the second priority having lower timeliness as postponed execution, and mark the execution status of the data clearing request with the second priority having higher timeliness as immediate execution. After the data clearing request with the first priority and when the storage space of the SRAM is sufficient, write the data clearing request with the second priority having lower timeliness into the SRAM, thereby improving the execution efficiency of the data clearing request with the second priority having lower timeliness.

[0081] In this embodiment, the auxiliary storage medium can be DRAM.

[0082] S5: Execute the data clearing request.

[0083] Specifically, execute the data clearing request according to the storage location of the data clearing request. Give priority to executing the data clearing request stored in the SRAM, directly call the data clearing operation, release the data storage space after the data clearing request is executed, and update the data management table. During the execution of the data clearing request, check and ensure that the relevant data blocks are not locked by other tasks to prevent data competition. Finally, after completing the clearing operation, update the system log to record the detailed information of this data clearing for subsequent tracking.

[0084] By receiving multiple data clearing requests for a single data operation and calculating the total information data volume of the multiple data clearing requests, it is possible to accurately evaluate the storage space required for the multiple data clearing requests before data clearing, thereby reasonably scheduling the storage resources of the SRAM and avoiding task blocking or delay caused by insufficient storage space; by detecting the available storage space of the SRAM and determining whether the available storage space is less than the total information data volume, it is possible to evaluate the storage space status in advance before the data clearing request is written, thereby avoiding the backlog of data clearing requests and improving the overall efficiency of the write operation; by determining the priority of the data clearing request and screening the data clearing requests according to the priority, it is possible to ensure that the data clearing requests related to high time sensitivity or system stability are executed first, thereby improving the execution efficiency of the data clearing requests and reducing the performance degradation caused by system resource competition; by executing the cache eviction algorithm to free up enough SRAM space to ensure that the data clearing request with the first priority can be executed smoothly, it is possible to optimize the cache management while ensuring the normal execution of high-priority tasks, thereby improving the data clearing efficiency of the SSD.

[0085] In one embodiment, as Figure 2 shown, in step S3, that is, performing a cache eviction algorithm on the SRAM, specifically including:

[0086] S31: Obtain the access frequencies and access times of multiple written data blocks in the SRAM.

[0087] Specifically, traverse multiple written data blocks in the SRAM, record the most recent access time and access frequency of each written data block. The access time refers to the time when the written data block was last read or written, and the access frequency represents the cumulative number of accesses of the written data block within a certain time window. To ensure the data accuracy of the access frequency and access time, a sliding window mechanism can be adopted to regularly refresh the data access status, ensuring that the cache eviction decision is based on the latest access frequency and access time.

[0088] S32: Determine the cache eviction coefficient of the corresponding written data block in the SRAM according to the access frequency and access time.

[0089] Specifically, before executing the cache eviction algorithm, first calculate the cache eviction coefficient of each written data block. The calculation of the cache eviction coefficient depends on the access frequency and access time of the data block. To ensure the accuracy of the calculation, the access records of each written data block need to be updated in real time to reflect the latest access situation. In practical applications, a sliding time window mechanism can be adopted to only retain the data access records within the most recent period of time, thereby avoiding the interference of historical access data on the current decision. During the calculation process, if the access frequency of the data block is zero, that is, it has not been accessed within the current time window, directly set its cache eviction coefficient to the maximum value so that it can be evicted as soon as possible, thereby releasing more SRAM space.

[0090] Furthermore, for some special written data blocks, such as those storing critical metadata or system logs, a minimum eviction threshold can be set to ensure that these written data blocks will not be accidentally deleted due to the adjustment of the cache eviction policy. In addition, for some written data blocks with unstable access patterns, such as those with a sharp increase in access frequency in a short period of time but then a decrease in access volume, a dynamic cache policy can be adopted, that is, when it is detected that the access frequency of the written data block has increased significantly in a short period of time, temporarily increase the cache eviction coefficient of the written data block to avoid the content in the written data block from being accidentally deleted, but if the access frequency decreases in the subsequent time period, appropriately reduce the cache eviction coefficient of the written data block, thereby ensuring the reasonable utilization of SRAM resources and improving the continuity of data access and the system response speed.

[0091] S33: Determine whether the cache eviction coefficient is not greater than the first preset cache eviction value.

[0092] Specifically, compare the calculated cache eviction coefficient with the first preset cache eviction value. If the cache eviction coefficient is less than or equal to the first preset cache eviction value, it indicates that the importance of the written data block remaining in the SRAM is relatively low and it can be used as a candidate for eviction. If the cache eviction coefficient is higher than the first preset cache eviction value, the data block still has a high access demand and should continue to be retained in the SRAM to reduce unnecessary cache data migration. In addition, the preset cache eviction value can be adaptively adjusted to adapt to different storage load conditions and improve the flexibility of cache management.

[0093] In some specific embodiments, the setting of the first preset cache eviction value can comprehensively consider factors such as access frequency, access time, cache space utilization rate, and system I / O load, and be optimized using a static base value and a dynamic adjustment strategy. The setting of the first preset cache eviction value ensures that frequently accessed written data blocks are not mis-evicted, while evicting low-priority written data blocks, improving the SSD data cleaning efficiency and storage management performance. The static base value can set a first preset cache eviction value through historical access pattern analysis to ensure that in typical load conditions, the SRAM can efficiently store high-priority data cleaning requests without affecting performance due to cache fullness. Then, use the dynamic adjustment strategy to adjust the first preset cache eviction value. If data with a high access frequency occupies a large amount of SRAM storage space, appropriately increase the first preset cache eviction value. If the overall access frequency is relatively low, then decrease the first preset cache eviction value to reduce unnecessary eviction of written data blocks and improve the cache hit rate.

[0094] Furthermore, a sliding time window can be used to record the past N cache eviction events. If the cache eviction coefficients of most of the evicted written data blocks are higher than the current first preset cache eviction value, it indicates that the first preset cache eviction value is too low and needs to be increased. Conversely, appropriately decrease the first preset cache eviction value to achieve dynamic optimization.

[0095] S34: If the cache eviction coefficient is not greater than the first preset cache eviction value, perform a cache eviction algorithm on the corresponding written data block in the SRAM. The cache eviction algorithm includes the LRU algorithm and the LFU algorithm.

[0096] Specifically, when the cache eviction coefficient is not greater than the preset cache eviction value, data is evicted according to the LRU algorithm or the LFU algorithm. When using the LRU algorithm, the least recently used written data block is cleared to ensure that data with high access timeliness can remain in the SRAM. When using the LFU algorithm, the written data block with the lowest access frequency is cleared to ensure that storage resources serve high-frequency access data as much as possible. To improve the adaptability of the eviction strategy, the advantages of the two algorithms can be combined to adaptively select the optimal strategy to optimize storage resource management.

[0097] S35: If the cache eviction coefficient is greater than the first preset cache eviction value, then retain the data of the corresponding written data block in the SRAM.

[0098] Specifically, for a cache eviction coefficient higher than the first preset cache eviction value, the corresponding data block is continuously retained in the SRAM to ensure that high-priority data can be continuously stored in the cache, improving the data access efficiency. At the same time, by periodically updating the cache eviction coefficient, it is avoided that high-priority data blocks reduce the overall system performance due to long-term occupation of the cache space.

[0099] By obtaining the access frequency and access time of multiple written data blocks in the SRAM, the usage situation of the data blocks can be accurately grasped, thereby providing basic data support for the cache management strategy and improving the rationality of the cache eviction decision; by calculating the cache eviction coefficient and determining whether it is not greater than the first preset cache eviction value, low-priority or low-frequency accessed data blocks can be effectively screened, thereby freeing up more cache space without affecting the access to high-frequency data and improving the utilization rate of storage resources; by performing a cache eviction algorithm on the eligible data blocks and adopting a strategy combining LRU and LFU, the access frequency and time factors can be taken into account, so as to ensure that high-value data remains in the written data blocks as much as possible and to clear the written data blocks occupied by low-value data as much as possible, thereby freeing up enough SRAM space.

[0100] In one embodiment, as Figure 3 shown, in step S32, that is, determining the cache eviction coefficient of the corresponding written data block in the SRAM according to the access frequency and access time, specifically includes:

[0101] S321: Through the cache eviction coefficient calculation formula:

[0102]

[0103] Calculate the cache eviction coefficient, where C is the cache eviction coefficient, T is the access time, F is the access frequency, and α and β are weight coefficients.

[0104] Specifically, when performing the cache eviction decision, use the cache eviction coefficient calculation formula to determine the eviction priority of each written data block, where F represents the access frequency of the data block, that is, the number of times the written data block is read or written within a specified time window, T represents the time interval of the last access of the written data block, that is, the time length from the last access to the current moment, and α and β are adjustable weight parameters used to balance the influence of the access frequency and access time on the cache eviction coefficient. When α takes a larger value, the cache eviction algorithm is more inclined to retain high-frequency accessed data blocks, and when β takes a larger value, the cache eviction algorithm is more inclined to evict data blocks that have not been accessed for a long time.

[0105] In this embodiment, the setting of α and β can comprehensively consider factors such as access time, access frequency, system I / O load, and SRAM space utilization, and adopt a static base value and a dynamic adjustment strategy for optimization. The setting of α and β ensures that the cache replacement algorithm can dynamically adjust between the LRU algorithm and the LFU algorithm, ensuring that the written data blocks with high access frequencies are preferentially retained, while reducing the residence of data that has not been accessed for a long time, thereby optimizing the data cleaning efficiency and storage management performance of the SSD.

[0106] The static base value can be set by analyzing the historical access pattern, and the initial values of α and β are set to adapt to different typical storage load scenarios. For example, in read-intensive applications such as database queries, a higher β is set to increase the influence weight of the LFU, ensuring that data blocks with high access frequencies have higher priorities, while α is relatively low to avoid premature elimination of data that has not been recently used but may still be needed. In write-intensive applications such as log storage, a higher α is set to strengthen the LRU strategy, preferentially eliminating data blocks that have not been accessed for a long time, while β is low to reduce the dependence on access frequency. In balanced load applications, α and β need to maintain an appropriate balance to ensure that the cache can retain both high-frequency access data and clean up long-unaccessed data in a timely manner.

[0107] The dynamic adjustment strategy can be used to further optimize the values of α and β. When the storage space of the SRAM is relatively sufficient, β is increased to reduce the frequent data loading of the SSD, while when the storage space of the SRAM is tight, α is increased to free up space for new requests. When the I / O load is high, β is increased to reduce the read / write burden of the SSD and improve the cache hit rate, while when the I / O load is low, α is increased to eliminate recently unaccessed data to ensure the efficient utilization of the storage space.

[0108] By adopting the above technical solution, by calculating the cache replacement coefficient based on the access frequency and access time, the cache replacement algorithm executed on the written data block can be intelligently adjusted according to the historical access situation of the written data block, thereby optimizing the cache management of the SRAM and improving the data access efficiency; by setting the weight parameters α and β to balance the access frequency and access time, the cache replacement strategy can be flexibly adjusted in different application scenarios, thereby freeing up enough SRAM space as much as possible.

[0109] In one embodiment, as Figure 4 shown, in step S34, that is, executing the cache replacement algorithm on the corresponding written data block in the SRAM, specifically including:

[0110] S341: Determine whether the cache replacement coefficient is not greater than the second preset cache replacement value.

[0111] Specifically, after calculating the cache eviction coefficient for each written data block, compare the cache eviction coefficient with a second preset cache eviction value, which is a threshold dynamically set by the system based on the current storage load, access pattern, and performance requirements.

[0112] In this embodiment, the setting of the second preset cache eviction value can comprehensively consider factors such as access frequency, access time, cache space occupancy ratio, and system I / O load, and adopt a combination of static setting and dynamic adjustment strategies for optimization. The setting of the second preset cache eviction value ensures that during the cache eviction process, it is possible to reasonably distinguish between written data blocks with high access frequencies and those with low access frequencies, ensuring the effective utilization of the SRAM storage space, improving the SSD data clearing efficiency and storage management performance.

[0113] The static setting method can analyze based on the system's historical access pattern and initially set the second preset cache eviction value to adapt to different storage load scenarios. For example, in application scenarios with a high access frequency, such as database queries, a lower second preset cache eviction value will be set to ensure that only written data blocks with extremely low access frequencies are evicted, guaranteeing that data with high access frequencies is retained. In application scenarios with a low access frequency, such as log storage, a higher second preset cache eviction value will be set to improve the cache utilization rate and promptly evict written data blocks that occupy space but are rarely accessed.

[0114] The dynamic adjustment strategy can adjust the second preset cache eviction value based on the system I / O load situation. When the I / O load is high, increase the second preset cache eviction value to reduce the additional storage operations caused by cache eviction; when the I / O load is low, decrease the second preset cache eviction value to improve the cache storage efficiency.

[0115] S342: If the cache eviction coefficient is not greater than the second preset cache eviction value, then merge multiple corresponding written data blocks into a first data block group, and then perform the LRU algorithm on the first data block group.

[0116] Specifically, after determining that the cache eviction coefficients of multiple written data blocks are not greater than the second preset cache eviction value, in order to improve the cache eviction efficiency, these written data blocks are merged to form a first data block group. The principle of merging the written data blocks can be based on the address continuity, storage relevance, or business logic relevance of the data blocks to reduce the fragmentation problem of data clearing operations. The LRU algorithm is executed on the first data block group. Under the LRU algorithm, the system will preferentially evict the least recently used data blocks to free up cache space. This method is particularly suitable for data blocks that are frequently accessed in a short time because their access patterns are relatively unstable and are likely to lose their access value in a short time. Adopting the LRU strategy can effectively improve the cache utilization rate, reduce the occupation of unnecessary written data blocks, and thus free up the storage space of SRAM as much as possible.

[0117] S343: If the cache eviction coefficient is greater than the second preset cache eviction value, then multiple corresponding written data blocks are merged into a second data block group, and then the LFU algorithm is executed on the second data block group.

[0118] Specifically, for the written data blocks with cache eviction coefficients greater than the second preset cache eviction value, these written data blocks are merged to form a second data block group. The data merging method can be based on the logical relevance or storage access pattern of the data blocks to reduce the complexity of data management. Subsequently, the LFU algorithm is executed on the second data block group. Under the LFU algorithm, the system preferentially evicts the data blocks with the lowest access frequency to ensure that the data blocks with high access frequency can be retained in the cache for a long time. This strategy is particularly suitable for data blocks that are stably accessed for a long time, such as operating system caches, index tables, etc. Through the LFU mechanism, high-value data can be prevented from being accidentally deleted due to short-term access fluctuations, improving the storage stability and access efficiency of the SSD.

[0119] By determining whether the cache eviction coefficient is not greater than the second preset cache eviction value, the screening conditions can be further optimized before data block eviction, so as to preferentially evict low-value data blocks when storage resources are scarce, improving the utilization efficiency of the SRAM storage space.

[0120] In one embodiment, as Figure 5 shown, in step S2, that is, determining the priority of each data clearing request, the priority of the data clearing request includes the first priority and the second priority. The data clearing requests are screened according to the priority of the data clearing request, specifically including:

[0121] S21: Obtain the creation time and execution deadline of the data clearing request.

[0122] Specifically, after receiving multiple data clearing requests, record the creation time and execution deadline of each data clearing request. The creation time refers to the time when the data clearing request is generated in the system, and the execution deadline refers to the latest time when the data clearing request must be completed. To ensure the data accuracy of the creation time and execution deadline, the creation time can be automatically recorded based on the system clock, and the execution deadline can be set by external control logic. For example, it can be configured by the task scheduling module according to the importance of the data clearing request or business rules. When the data clearing request enters the queue, the creation time and execution deadline will be synchronously stored in the management table for subsequent priority determination.

[0123] S22: Determine the remaining execution time of the data clearing request according to the creation time and execution deadline.

[0124] Specifically, before the data clearing task is executed, calculate the remaining execution time of each data clearing request. The calculation formula for the remaining execution time is , where is the remaining execution time, is the execution deadline, is the creation time. Through the calculation formula of the remaining execution time, the data clearing request closest to the execution deadline can be determined to ensure that urgent data clearing requests can be executed first. And during the process of calculating the remaining execution time, consider the accuracy of the system clock and standardize the timestamp to avoid incorrect calculations caused by clock drift or time zone issues. In the case of a large number of concurrent requests, the system can batch calculate the remaining execution time of multiple data clearing requests to optimize the calculation performance and improve the task scheduling efficiency.

[0125] S23: Determine whether the remaining execution time is greater than the preset time value.

[0126] Specifically, compare the calculated remaining execution time with the preset time value. The preset time value can be dynamically set according to the storage policy of the SSD device. For example, in a high-load state of the system, the preset time value can be appropriately reduced to ensure that high-priority tasks can be completed in time, while in a low-load state of the system, the preset time value can be appropriately extended to reduce unnecessary resource scheduling.

[0127] S24: If the remaining execution time is not greater than the preset time value, determine the priority of the corresponding data clearing request as the first priority.

[0128] Specifically, for a data clearing request with a remaining execution time not greater than a preset time value, the system marks the corresponding data clearing request as the first priority to ensure that the corresponding data clearing request can be executed preferentially. Such data clearing requests usually have high time sensitivity. For example, data blocks that are about to be full, system-level garbage collection tasks, or other data that must be cleared immediately. After the priorities are assigned, these data clearing requests will be put into the first-priority queue and preferentially written into the SRAM during the scheduling process to improve the execution efficiency of the data clearing requests.

[0129] Furthermore, to avoid system resource saturation caused by a large number of high-priority tasks, a maximum task quantity threshold can be set. Tasks exceeding the threshold will be temporarily stored in an auxiliary storage medium and scheduled again after the SRAM storage space is released.

[0130] S25: If the remaining execution time is greater than the preset time value, determine the priority of the corresponding data clearing request as the second priority.

[0131] Specifically, for a data clearing request with a remaining execution time greater than the preset time value, the system marks the corresponding data clearing request as the second priority and temporarily stores it in an auxiliary storage medium. The time requirements of these data clearing requests are relatively loose and do not need to be executed immediately. For example, some background data sorting, clearing of infrequently accessed data, etc. During the scheduling process, the data clearing requests with the second priority will not preempt the storage space of the data clearing requests with the first priority, but will be executed when the system load is low or the cache resources are sufficient. To avoid long-term backlog of low-priority tasks, a periodic check mechanism can be set to re-evaluate the execution requirements of the tasks after a certain time. If a change in the priority of the data clearing request is detected, the scheduling policy is adjusted to ensure the rationality of the execution of the data clearing request.

[0132] By obtaining the creation time and execution deadline of the data clearing request and calculating the remaining execution time, the urgency of the data clearing request can be accurately evaluated, thus ensuring the rationality of task scheduling and improving the resource allocation efficiency; by comparing the remaining execution time with the preset time value and determining the priority of the data clearing request according to the calculation result, it can ensure that time-sensitive tasks are executed first, thus reducing data consistency problems caused by delayed processing and improving the data clearing efficiency of the SSD.

[0133] In an embodiment, as Figure 6 shown, before calculating the total information data volume of multiple data clearing requests, the SSD data clearing method further includes:

[0134] S6: Detect the addresses of the cleared data blocks pointed to by multiple data clearing requests.

[0135] Specifically, traverse all data deletion requests, extract the address of the data block to be deleted corresponding to each data deletion request. The method of detecting the address of the data block to be deleted is usually based on the mapping table inside the SSD, such as the FTL mapping table, etc. And during the process of detecting the address of the data block to be deleted, the logical address and physical address of the data block to be deleted can be combined to ensure the accuracy of identifying the address of the data block to be deleted.

[0136] In this embodiment, the data block to be deleted refers to the data block for which the data deletion request needs to perform a data deletion operation on the SSD. One data deletion request can perform a data deletion operation on one data block to be deleted, or one data deletion request can perform a data deletion operation on multiple data blocks to be deleted.

[0137] S7: Determine whether the addresses of multiple data blocks to be deleted coincide.

[0138] Specifically, after completing the detection of the address of the data block to be deleted, the system will check whether multiple data deletion requests point to the same address of the data block to be deleted. The judgment logic of this step is based on an address matching algorithm. For example, a hash table is used to store the addresses of the data blocks to be deleted that have appeared, and when traversing new data deletion requests, the hash table is checked. If the same address of the data block to be deleted is found, the data deletion request is marked as a duplicate data deletion request. If the addresses of multiple data deletion requests coincide, the system will further merge these data deletion requests to reduce unnecessary data deletion operations.

[0139] S8: If the addresses of multiple data blocks to be deleted coincide, merge the corresponding data deletion requests into a new data deletion request.

[0140] Specifically, after detecting that multiple data deletion requests point to the same storage address, the system will merge the corresponding data deletion requests into a new data deletion request. The execution method of this new data deletion request is the same as that of a normal deletion request, but the execution result of the new data deletion request will overwrite the original multiple data deletion requests, thus avoiding the repeated execution of data deletion requests.

[0141] Furthermore, when merging requests, the priorities, execution times, and storage locations of the data blocks to be deleted of each data deletion request will be comprehensively considered to ensure that the merged data deletion request still conforms to the logic of task scheduling. For example, if the priorities of multiple data deletion requests are different, the merged data deletion request will be executed according to the higher priority to ensure the stability of system performance. In addition, to further optimize the merging process of data deletion requests, the system can adopt a batch merging strategy to improve the deletion efficiency and reduce the SSD load when processing a large number of requests.

[0142] Furthermore, if the addresses of multiple data blocks to be deleted do not coincide, calculate the total information data volume of multiple data deletion requests.

[0143] By detecting the addresses of the data clearing blocks pointed to by multiple data clearing requests and determining whether there is overlap, duplicate clearing operations can be avoided, thereby reducing unnecessary data read and write burdens and improving the data clearing efficiency of the SSD; by merging multiple data clearing requests pointing to the same data block into a new data clearing request, redundant requests can be reduced, thereby optimizing task scheduling and improving the execution efficiency of data clearing tasks.

[0144] It should be understood that the magnitudes of the sequence numbers of the steps in the above embodiments do not mean the order of execution. The order of execution of each process should be determined by its function and internal logic, and should not constitute any limitation to the implementation process of the embodiments of the present application.

[0145] In one embodiment, an SSD data clearing device is provided, and the SSD data clearing device corresponds one-to-one with the SSD data clearing method in the above embodiment. As Figure 7 shown, the SSD data clearing device includes a request processing module, a storage space management module, a priority allocation module, a cache management module, a data writing module, and a data clearing execution module. The detailed descriptions of each functional module are as follows:

[0146] The request processing module is configured to receive multiple data clearing requests for a single data operation and calculate the total information data volume of the multiple data clearing requests;

[0147] The storage space management module is configured to detect the available storage space of the SRAM and determine whether the available storage space is less than the total information data volume;

[0148] The priority allocation module is configured to determine the priority of each data clearing request when the available storage space is less than the total information data volume, and screen the data clearing requests according to the priority of the data clearing requests;

[0149] The cache management module is configured to perform a cache eviction algorithm on the SRAM so that the remaining storage space of the SRAM is not less than the total information data volume of the data clearing requests of the first priority;

[0150] The data writing module is configured to write the data clearing requests of the first priority into the SRAM and write the data clearing requests of the second priority into the auxiliary storage medium;

[0151] The data clearing execution module is configured to execute the data clearing requests.

[0152] Optionally, the cache management module includes:

[0153] A data access statistics module, configured to obtain the access frequencies and access times of multiple written data blocks in the SRAM;

[0154] A cache elimination coefficient determination module, configured to determine the cache elimination coefficients of the corresponding written data blocks in the SRAM according to the access frequencies and the access times;

[0155] A cache elimination judgment module, configured to judge whether the cache elimination coefficient is not greater than a first preset cache elimination value;

[0156] A cache optimization execution module, configured to, if the cache elimination coefficient is not greater than the first preset cache elimination value, execute the cache elimination algorithm on the corresponding written data blocks in the SRAM, where the cache elimination algorithm includes the LRU algorithm and the LFU algorithm, and if the cache elimination coefficient is greater than the first preset cache elimination value, retain the data of the corresponding written data blocks in the SRAM.

[0157] Optionally, the cache elimination coefficient determination module includes:

[0158] A cache elimination coefficient calculation module, configured to calculate the cache elimination coefficient through the cache elimination coefficient calculation formula: , where C is the cache elimination coefficient, T is the access time, F is the access frequency, and α and β are weight coefficients.

[0159] Optionally, the cache optimization execution module includes:

[0160] A cache elimination strategy judgment module, configured to judge whether the cache elimination coefficient is not greater than a second preset cache elimination value;

[0161] A data block merging and elimination module, configured to, if the cache elimination coefficient is not greater than the second preset cache elimination value, merge multiple corresponding written data blocks into a first data block group, and then execute the LRU algorithm on the first data block group; if the cache elimination coefficient is greater than the second preset cache elimination value, merge multiple corresponding written data blocks into a second data block group, and then execute the LFU algorithm on the second data block group.

[0162] Optionally: The priority assignment module includes:

[0163] A request time calculation module, configured to obtain the creation time and the execution deadline of the data clearing request;

[0164] A remaining execution time calculation module, configured to determine the remaining execution time of the data clearing request according to the creation time and the execution deadline;

[0165] A priority judgment module is used to determine the priority of the corresponding data deletion request as the first priority if the remaining execution time is not greater than a preset time value; and to determine the priority of the corresponding data deletion request as the second priority if the remaining execution time is greater than the preset time value.

[0166] Optionally, the SSD data deletion device further includes:

[0167] A cleared data block address detection module is used to detect the addresses of the cleared data blocks pointed to by multiple data deletion requests;

[0168] A data block coincidence judgment module is used to judge whether the addresses of multiple cleared data blocks coincide;

[0169] A data deletion request merging module is used to merge the corresponding data deletion requests into a new data deletion request if the addresses of multiple cleared data blocks coincide.

[0170] For the specific limitations of the SSD data deletion device, reference can be made to the limitations on the SSD data deletion method in the above text, which will not be elaborated here. Each module in the above SSD data deletion device can be implemented in whole or in part by software, hardware, and their combination. The above modules can be embedded in the processor of the computer device in hardware form or independent of it, or stored in the memory of the computer device in software form, so that the processor can call and execute the operations corresponding to the above modules.

[0171] In one embodiment, a computer device is provided. The computer device can be a server, and its internal structure diagram can be as Figure 8 shown. The computer device includes a processor, a memory, a network interface, and a database connected through a system bus. Among them, the processor of the computer device is used to provide computing and control capabilities. The memory of the computer device includes a non-volatile storage medium and an internal memory. The non-volatile storage medium stores an operating system, a computer program, and a database. The internal memory provides an environment for the operation of the operating system and the computer program in the non-volatile storage medium. The network interface of the computer device is used to communicate with an external terminal through a network connection. When the computer program is executed by the processor, it implements an SSD data deletion method.

[0172] In one embodiment, a computer device is provided, including a memory, a processor, and a computer program stored on the memory and executable on the processor. When the processor executes the computer program, the following steps are implemented:

[0173] Receive multiple data deletion requests for a single data operation, calculate the total information data volume of the multiple data deletion requests, and detect the available storage space of the SRAM;

[0174] Determine whether the available storage space is less than the total amount of information data. If the available storage space is less than the total amount of information data, determine the priority of each data deletion request. The priority of the data deletion request includes a first priority and a second priority. Screen the data deletion requests according to the priority of the data deletion request, where the first priority is higher than the second priority;

[0175] Execute a cache eviction algorithm on the SRAM so that the remaining storage space of the SRAM is not less than the total amount of information data of the data deletion requests with the first priority;

[0176] Write the data deletion requests with the first priority into the SRAM, and write the data deletion requests with the second priority into the auxiliary storage medium;

[0177] Execute the data deletion requests.

[0178] In one embodiment, a computer-readable storage medium is provided, on which a computer program is stored. When the computer program is executed by a processor, the following steps are implemented:

[0179] Receive multiple data deletion requests for a single data operation, calculate the total amount of information data of the multiple data deletion requests, and detect the available storage space of the SRAM;

[0180] Determine whether the available storage space is less than the total amount of information data. If the available storage space is less than the total amount of information data, determine the priority of each data deletion request. The priority of the data deletion request includes a first priority and a second priority. Screen the data deletion requests according to the priority of the data deletion request, where the first priority is higher than the second priority;

[0181] Execute a cache eviction algorithm on the SRAM so that the remaining storage space of the SRAM is not less than the total amount of information data of the data deletion requests with the first priority;

[0182] Write the data deletion requests with the first priority into the SRAM, and write the data deletion requests with the second priority into the auxiliary storage medium;

[0183] Execute the data deletion requests.

[0184] Those of ordinary skill in the art can understand that all or part of the processes in the methods of the above embodiments can be completed by instructing relevant hardware through a computer program. The computer program can be stored in a non-volatile computer-readable storage medium. When the computer program is executed, it can include the processes of the embodiments of the above methods. Among them, any reference to a memory, storage, database, or other medium used in the embodiments provided in the present application can include non-volatile and / or volatile memories. Non-volatile memories can include read-only memory (ROM), programmable ROM (PROM), electrically programmable ROM (EPROM), electrically erasable programmable ROM (EEPROM), or flash memory. Volatile memories can include random access memory (RAM) or external cache memory. By way of illustration and not limitation, RAM is available in many forms, such as static RAM (SRAM), dynamic RAM (DRAM), synchronous DRAM (SDRAM), double data rate SDRAM (DDR SDRAM), enhanced SDRAM (ESDRAM), synchronous link DRAM (SLDRAM), Rambus direct RAM (RDRAM), direct memory bus dynamic RAM (DRDRAM), and Rambus dynamic RAM (RDRAM), etc.

[0185] Those skilled in the art can clearly understand that for the convenience and brevity of description, only the above division of each functional unit and module is used as an example. In actual applications, the above functions can be allocated to different functional units and modules according to needs, that is, the internal structure of the device can be divided into different functional units or modules to complete all or part of the functions described above.

[0186] The above embodiments are only used to illustrate the technical solutions of the present application, rather than to limit them; although the present application has been described in detail with reference to the foregoing embodiments, those of ordinary skill in the art should understand that they can still modify the technical solutions recorded in the foregoing embodiments, or perform equivalent replacements for some of the technical features; and these modifications or replacements do not cause the essence of the corresponding technical solutions to deviate from the spirit and scope of the technical solutions of the embodiments of the present application, and should all be included in the protection scope of the present application.

Claims

1. A method for clearing SSD data, the method being applicable to an SSD solid state drive, the SSD solid state drive having an SRAM and an auxiliary storage medium, characterized in that: The SSD data clearing method comprises: Receiving multiple data clearing requests of a single data operation, calculating the total information data volume of the multiple data clearing requests, and detecting the available storage space of the SRAM; Determine whether the available storage space is less than the total amount of information data, if the available storage space is less than the total amount of information data, determine the priority of each of the data clearing requests, the priority of the data clearing request includes a first priority and a second priority, and screen the data clearing requests according to the priority of the data clearing request, wherein the first priority is higher than the second priority; Executing a cache elimination algorithm on the SRAM so that the remaining storage space of the SRAM is not less than the total information data volume of the data clearing request of the first priority; Writing the data clearing request of the first priority into the SRAM, and writing the data clearing request of the second priority into the auxiliary storage medium; executing the data clearing request; Wherein, executing the cache elimination algorithm on the SRAM includes: Obtaining access frequencies and access times of a plurality of write data blocks in the SRAM; Determine a cache elimination coefficient of a corresponding written data block in the SRAM according to the access frequency and the access time; Determining whether the cache elimination coefficient is not greater than a first preset cache elimination value; If the cache elimination coefficient is not greater than the first preset cache elimination value, executing the cache elimination algorithm on the corresponding write data block in the SRAM, the cache elimination algorithm including the LRU algorithm and the LFU algorithm; If the cache elimination coefficient is greater than the first preset cache elimination value, retaining the data of the corresponding written data block in the SRAM; Wherein, determining the cache elimination coefficient of the corresponding written data block in the SRAM according to the access frequency and the access time includes: The cache elimination coefficient is calculated by the formula: Calculate the cache elimination coefficient, where C is the cache elimination coefficient, T is the access time, F is the access frequency, and α and β are weight coefficients; The step of executing the cache elimination algorithm on the corresponding written data block in the SRAM includes: Determining whether the cache elimination coefficient is not greater than a second preset cache elimination value; If the cache elimination coefficient is not greater than the second preset cache elimination value, merging a plurality of corresponding written data blocks into a first data block group, and then executing the LRU algorithm on the first data block group; If the cache elimination coefficient is greater than the second preset cache elimination value, merging a plurality of corresponding written data blocks into a second data block group, and then executing the LFU algorithm on the second data block group; The step of determining the priority of each of the data clearing requests, wherein the priority of the data clearing requests includes a first priority and a second priority, and screening the data clearing requests according to the priority of the data clearing requests includes: Obtaining the creation time and execution deadline of the data clearing request; Determine the remaining execution time of the data clearing request according to the creation time and the execution deadline; Determine whether the remaining execution time is greater than a preset time value; If the remaining execution time is not greater than the preset time value, the priority of the corresponding data clearing request is determined as the first priority; If the remaining execution time is greater than the preset time value, the priority of the corresponding data clearing request is determined as the second priority.

2. The SSD data clearing method according to claim 1, characterized in that: Before calculating the total information data volume of the plurality of data clearing requests, the method further includes: Detecting addresses of cleared data blocks pointed to by a plurality of the data clearing requests; Determining whether addresses of a plurality of cleared data blocks overlap; If the addresses of the plurality of cleared data blocks overlap, the corresponding data clearing requests are merged into a new data clearing request.

3. An SSD data device, characterized in that: The SSD data device comprises: A request processing module, used for receiving multiple data clearing requests of a single data operation, and calculating the total information data volume of the multiple data clearing requests; A storage space management module, used to detect the available storage space of the SRAM and determine whether the available storage space is less than the total amount of information data; a priority allocation module, configured to determine the priority of each of the data clearing requests when the available storage space is less than the total amount of information data, and to screen the data clearing requests according to the priorities of the data clearing requests; A cache management module, used for executing a cache elimination algorithm on the SRAM so that the remaining storage space of the SRAM is not less than the total information data volume of the data clearing request of the first priority; A data writing module, used for writing the data clearing request of the first priority into the SRAM, and writing the data clearing request of the second priority into an auxiliary storage medium; A data clearing execution module, used for executing the data clearing request; A data access statistics module, used to obtain access frequencies and access times of multiple write data blocks in the SRAM; A cache elimination coefficient calculation module, used to determine the cache elimination coefficient of the corresponding write data block in the SRAM according to the access frequency and the access time; A cache elimination judgment module, used to judge whether the cache elimination coefficient is not greater than a first preset cache elimination value; A cache optimization execution module, configured to execute the cache elimination algorithm on the corresponding write data block in the SRAM if the cache elimination coefficient is not greater than the first preset cache elimination value, wherein the cache elimination algorithm includes an LRU algorithm and an LFU algorithm, and retain the data of the corresponding write data block in the SRAM if the cache elimination coefficient is greater than the first preset cache elimination value; The cache elimination coefficient calculation module is used to calculate the cache elimination coefficient through the formula , calculate the cache elimination coefficient, where C is the cache elimination coefficient, T is the access time, F is the access frequency, and α and β are weight coefficients; A cache elimination strategy judgment module, used to judge whether the cache elimination coefficient is not greater than a second preset cache elimination value; A data block merging and elimination module, configured to merge a plurality of corresponding written data blocks into a first data block group if the cache elimination coefficient is not greater than the second preset cache elimination value, and then execute the LRU algorithm on the first data block group; if the cache elimination coefficient is greater than the second preset cache elimination value, merge a plurality of corresponding written data blocks into a second data block group, and then execute the LFU algorithm on the second data block group; A request time calculation module, used to obtain the creation time and execution deadline of the data clearing request; a remaining execution time calculation module, configured to determine the remaining execution time of the data clearing request according to the creation time and the execution deadline; The priority judgment module is used to determine the priority of the corresponding data clearing request as the first priority if the remaining execution time is not greater than the preset time value; if the remaining execution time is greater than the preset time value, determine the priority of the corresponding data clearing request as the second priority.

4. A computer device comprising a memory, a processor, and a computer program stored in the memory and executable on the processor, characterized in that: When the processor executes the computer program, the steps of the SSD data clearing method according to any one of claims 1 to 2 are implemented.

5. A computer-readable storage medium storing a computer program, characterized in that: When the computer program is executed by a processor, the steps of the SSD data clearing method according to any one of claims 1 to 2 are implemented.

Images