Solid state disk management system and data processing method

Abstract

The invention discloses a solid state disk management system and a data processing method, and relates to the technical field of solid state disk management. Flexible task scheduling and resource management are provided through a lightweight operating system module, and a computing task program defined by a user is supported to be dynamically loaded; edge computing or machine learning operators are efficiently executed in combination with a programmable hardware processing unit and a DMA channel of the computing acceleration engine module, the data preloading module is utilized to predict and preload data to DDR based on LBA access history, access delay is reduced, an NVMe protocol is expanded by means of the task unloading interface module, host task issuing and result returning are achieved, and the data processing efficiency is improved. And hardware-level memory protection is ensured through the security isolation module, so that the data calculation processing capacity of the solid state disk is remarkably improved, localized calculation tasks such as edge calculation and machine learning are supported, mass data transmission is effectively reduced, and bus and network loads are relieved.

Description

Technical Field

[0001] This invention relates to the field of solid-state drive (SSD) management technology, specifically to an SSD management system and data processing method. Background Technology

[0002] As described in the published patent CN112181293B, "Solid State Drive Controller, Solid State Drive, Storage System, and Data Processing Method," a solid state drive (SSD) is a hard drive made using an array of solid-state electronic storage chips. An SSD includes a control unit and storage units (FLASH memory chips or DRAM memory chips). Currently, a significant portion of SSD systems incorporates Dynamic Random Access Memory (DRAM), thus providing SSDs with a large data cache. Flash memory (NAND Flash) is the primary storage medium for SSDs.

[0003] Solid-state drives (SSDs) have become the primary data storage devices. In the context of big data applications, massive data transfers consume significant amounts of bus and network bandwidth. Simultaneously, the computing power of the CPUs integrated within SSDs is becoming increasingly powerful. To reduce the volume of large data transfers, various demands for integrated storage and computing have emerged, such as edge computing and machine learning applications within storage. This involves performing computations within the SSD at the data end, transmitting only the results and a portion of the data, thereby reducing massive data transfers and alleviating bus and network load.

[0004] Traditional solid-state drives (SSDs) typically prioritize real-time data processing, using firmware (FW) without an operating system (BareMetal). While some designs include an RTOS, it's usually used only for simple scheduling or file systems. This design neglects the needs of relevant computing applications, resulting in weak application-level processing capabilities that cannot meet the demands of storage-based computing, such as edge computing and machine learning applications. These applications generally require operating system support. In developing this invention, the inventors discovered that current technical solutions suffer from at least the following problems: insufficient data processing capabilities of SSDs.

[0005] In summary, existing technologies for solid-state drives (SSDs) suffer from insufficient data processing capabilities. Summary of the Invention

[0006] To overcome the shortcomings mentioned above, the present invention aims to provide a technical solution that can solve the above problems.

[0007] To achieve the above objectives, the present invention provides the following technical solution: A solid-state drive (SSD) data processing method, comprising: S100: Lightweight operating system module, used to provide task scheduling, resource allocation management and hardware abstraction interface, and supports dynamic loading of user-defined computing task programs; S200: Computation acceleration engine module, which includes a programmable hardware processing unit for executing edge computing or machine learning operators and reading and writing data in DDR through a direct memory access (DMA) channel; S300: Data preloading module, which builds a frequency table based on logical block address (LBA) access history and preloads predicted data from flash memory to DDR when the SSD is idle; S400: Task offloading interface module, which extends the NVMe protocol instruction set to receive computation task descriptors issued by the host and return the computation results to the host; S500: Security isolation module, which isolates the storage management firmware from the computing task execution environment through a hardware-level memory protection unit.

[0008] As a further aspect of the present invention: the lightweight operating system module includes: S110: Task scheduling unit, which adopts a priority-preemptive scheduling strategy, assigning the highest priority to storage management tasks and dynamically adjustable priority to computing tasks; S120: Dynamic loading unit, providing an application programming interface (API) to support the host in remotely deploying, updating or uninstalling computing task programs through the task unloading interface module; S130: Resource isolation unit, which implements the following isolation for computing tasks through configurable resource quotas: Limit the maximum DDR cache size for a single task; Limit the maximum continuous execution time of a single task; Computational tasks are prohibited from directly accessing flash physical layer operation instructions; S140: Hardware Abstraction Layer (HAL) encapsulates the register operation interface of the computing acceleration engine module, so that computing tasks do not need to be aware of the underlying hardware differences.

[0009] As a further aspect of the present invention: the computing acceleration engine module includes: S210: Heterogeneous computing unit, integrating a programmable hardware processor and a fixed-function hardware accelerator, wherein: the programmable hardware processor supports a general computing instruction set for executing conditional branch intensive tasks. The fixed-function hardware accelerator is pre-configured with a matrix multiply-accumulator (MAC) and a convolution kernel for performing parallel computing-intensive tasks. S220: Near Data Access Channel, which connects to Dynamic Random Access Memory (DDR) via a dedicated Direct Memory Access (DMA) engine, enabling computing units to directly read and write cached data without the need for the controller CPU to relay it; S230: Dual-mode computing architecture, supporting the following operating modes: Pre-computation mode: Feature extraction is performed before data is written to flash memory, and only the processing results are stored in flash memory; Post-computation mode: Responds to host instructions and performs real-time analysis on cached data in DDR; S240: Extensible operator library, stores pre-compiled machine learning operators and edge computing function sets, including convolution, pooling, and hash calculation, and supports dynamic loading of new operators through a lightweight operating system module (S100).

[0010] As a further aspect of the present invention: the data preloading module includes: S310: Access frequency modeling unit, which statistically analyzes the historical access frequency and timeliness of logical block addresses (LBAs) and constructs a dynamically updated frequency table, wherein: Access frequency is calculated based on the number of read and write operations within the sliding time window; Timeliness is dynamically weighted based on the difference between the most recent access time and the current time; S320: Hot data prediction unit, which identifies data blocks that meet any of the following conditions as hot data to be calculated based on the frequency table: The access frequency exceeds the first threshold; The timeliness-weighted value is higher than the second threshold; S330: Background preloading engine, which loads the hot data to be computed from the flash storage medium to the dynamic random access memory (DDR) when the SSD is idle. S340: Resource preemption response unit. When a high-priority storage operation request occurs during the preloading process, the preloading task is immediately terminated and the DDR bandwidth is released.

[0011] As a further aspect of the present invention: the task unloading interface module includes: S410: Computation Instruction Extension Unit, which adds computation opcodes to the NVMe protocol command set and defines the following core instructions: Computation task submission instructions: include task type identifier, target data LBA range, and a list of computation parameters; Computation status query command: returns task execution progress or exception code; S420: Descriptor resolution unit, decodes the computation task descriptor issued by the host into the following executable elements: The identifier of the computation operator invoked; The cache address of the input data in DDR; Calculation result storage location identifier; S430: Zero-copy transmission channel, employing the following mechanism to achieve efficient return of calculation results:** Create a host-shared result buffer in DDR; The buffer physical address is mapped to the host memory space through the PCIe Address Translation Service (ATS); After the calculation is completed, a doorbell notification is sent to the host, triggering the host to directly read the result data; S440: Computation security verification unit, which performs the following verification on the received computation task descriptor: Task initiator authorization authentication; Legality check of the binding relationship between operators and data ranges.

[0012] As a further aspect of the present invention: the security isolation module includes: S510: Hardware Domain Isolation Unit, which divides the following privileged domains through the Memory Protection Unit (MPU): Storage privilege domain: Exclusive access to flash translation layer (FTL) metadata and physical layer control registers; Computational user domain: Restricts computational tasks to access only pre-allocated buffers in dynamic random access memory (DDR); S520: Abnormal Circuit Breaker Unit, which monitors computing task behavior in real time and immediately terminates the task and resets the computing engine when any of the following conditions are triggered: Unauthorized access to the privileged address space of the storage domain; The continuous running time of a single task exceeds the threshold set by the S130 resource isolation unit; The hardware acceleration engine reported a resource exhaustion error; S530: Security Audit Unit, which records the following behavior logs of computing tasks and stores them encrypted in flash memory: Identity of the task initiator; Accessed data LBA range and timestamp; Triggered exception event types and circuit breaker responses; S540: Cross-domain communication agent, providing restricted storage service access channels for computing tasks, wherein: Data read requests must be executed by proxy after the storage privilege domain verifies the validity of the LBA. The calculation results need to be submitted to the storage privilege domain for bad block management and wear leveling before being written back to flash memory.

[0013] A solid-state drive (SSD) management system includes a controller, a flash memory storage medium, and a dynamic random access memory (DRAM), wherein the controller operates according to the aforementioned SSD data processing method.

[0014] Compared with the prior art, the beneficial effects of the present invention are as follows: This invention provides flexible task scheduling and resource management through a lightweight operating system module, supports dynamic loading of user-defined computing task programs, and efficiently executes edge computing or machine learning operators by combining the programmable hardware processing unit and DMA channel of the computing acceleration engine module. It utilizes a data preloading module to predict and preload data to DDR based on LBA access history, reducing access latency. It extends the NVMe protocol through a task offloading interface module to realize host task delivery and result return, and ensures hardware-level memory protection through a security isolation module. This significantly improves the data computing and processing capabilities of solid-state drives, supports localized computing tasks such as edge computing and machine learning, effectively reduces massive data transmission, and alleviates bus and network load. Attached Figure Description

[0015] Figure 1 This is a flowchart of S100-S500 in this invention; Figure 2 This is a flowchart of S110-S140 in this invention; Figure 3 This is a flowchart of S210-S240 in this invention; Figure 4 This is a flowchart of S310-S340 in this invention; Figure 5 This is a flowchart of S410-S440 in this invention; Figure 6 This is a flowchart of S510-S540 in this invention. Detailed Implementation

[0016] The technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.

[0017] Please see Figure 1-6 A solid-state drive data processing method, comprising: S100: Lightweight operating system module, used to provide task scheduling, resource allocation management and hardware abstraction interface, and supports dynamic loading of user-defined computing task programs; S200: Computation acceleration engine module, which includes a programmable hardware processing unit for executing edge computing or machine learning operators and reading and writing data in DDR through a direct memory access (DMA) channel; S300: Data preloading module, which builds a frequency table based on logical block address (LBA) access history and preloads predicted data from flash memory to DDR when the SSD is idle; S400: Task offloading interface module, which extends the NVMe protocol instruction set to receive computation task descriptors issued by the host and return the computation results to the host; S500: Security isolation module, which isolates the storage management firmware from the computing task execution environment through a hardware-level memory protection unit; The S100 (Lightweight Operating System Module) goes beyond bare metal / simple RTOS, offering more powerful features than traditional SSD bare metal firmware or simple RTOS, including true task scheduling (supporting concurrent tasks), resource allocation management (CPU, memory, I / O, etc.), and a Hardware Abstraction Layer (HAL). Its core advantage lies in supporting the dynamic loading of user-defined computing tasks, which makes the SSD no longer a static storage device, but a programmable computing platform. Users can load and unload specific computing logic at any time according to actual needs (such as deploying new AI models or edge analysis algorithms) without modifying the underlying firmware, greatly improving application adaptability, scalability, and deployment speed. In the S200 (Compute Acceleration Engine Module), programmable hardware processing units (such as FPGAs or custom ASICs) are used to handle computationally intensive tasks (edge ​​computing operators, ML inference / training operators). Compared to pure software execution on the SSD main CPU, the speed improvement is significant (several orders of magnitude) and the power efficiency is higher. The DMA channel is key, which allows the acceleration engine to bypass the main CPU and directly move data between DDR memory and the accelerator at high speed. This eliminates the CPU bottleneck, maximizes the utilization of the accelerator's computing power, and greatly reduces data transfer latency and CPU overhead. In the S300 (data preloading module), a frequency table is built based on LBA access history, which is essentially learning the data access patterns (hot data / cold data). Preloading is performed when the SSD is idle, making full use of the background bandwidth that might otherwise be wasted, avoiding competition for resources with foreground I / O requests, and not affecting normal storage performance. The predicted hot data is preloaded from the slow NAND flash memory into the high-speed DDR memory. When computing tasks need this data, it can be accessed directly from DDR, avoiding the long latency of reading from NAND. This allows the computing engine to obtain data more quickly, significantly improving the overall execution efficiency of computing tasks, approaching the effect of "near-memory computing". In the S400 (Task Offload Interface Module), by extending the NVMe protocol instruction set, a compute offload function is added to the existing, widely adopted storage protocol. This allows the host operating system and applications to submit compute tasks using familiar NVMe driver interfaces, greatly simplifying the development and integration of host software. The host only needs to issue a compute task descriptor (containing task type, parameters, address pointers of input / output data inside the SSD, etc.), and the entire compute process can be completed inside the SSD. The host does not need to transfer large amounts of raw data to its own memory for processing; it only needs to receive the final result or a small amount of key data. This significantly reduces host memory bandwidth usage, PCIe bus load, and network transmission requirements (especially in data center scenarios). It is a core means of solving the "massive data transmission bottleneck," hiding the complex compute resources inside the SSD (OS, accelerator, preloading mechanism, etc.) from the host and providing a unified, storage-semantic compute interface. In the S500 (Security Isolation Module), a Hardware Memory Protection Unit (MPU) is used to isolate at the physical memory access level. This is more reliable, performs better, and is harder to bypass than pure software isolation. It isolates the storage management firmware (responsible for core FTL, garbage collection, wear leveling, bad block management, and other critical storage functions) from the computing task execution environment (including its code and data). Bugs or malicious code in computing tasks cannot damage or interfere with the operation of the core storage firmware and critical data structures (such as the FTL mapping table), preventing data loss or corruption. The storage firmware or other computing tasks cannot illegally access or tamper with the data and code of specific computing tasks. Sensitive computing task data cannot be accessed by unauthorized entities (including the storage firmware itself), and the crash of a computing task will not brick the entire SSD or render the data unusable. This is the foundation for supporting the secure and reliable operation of multi-tenant or untrusted user computing tasks on SSDs. These modules do not work independently, but rather collaborate closely. S400 receives task requests from the host, S100 parses the requests, schedules tasks, and manages resources (CPU, accelerator, memory). S300 moves potentially "hot" data from NAND to DDR in advance. S200 retrieves data from DDR at high speed and performs computations efficiently using hardware accelerators. S500 ensures core storage functions and security isolation throughout the process, and the computation results are returned to the host via S400. This collaborative working mode systematically and comprehensively improves the local data computing and processing capabilities, efficiency, and security of the SSD, enabling it to truly meet the needs of edge computing, machine learning, and other application scenarios that require efficient and intelligent processing at the data storage source. This effectively solves the problem of insufficient data computing and processing capabilities of traditional SSDs. By integrating a lightweight operating system module (S100), the SSD is provided with flexible task scheduling, fine-grained resource allocation management, and hardware abstraction capabilities, supporting dynamic loading of user-defined computing tasks. This significantly enhances the SSD's application processing flexibility and its ability to handle complex computing tasks. The computing acceleration engine module (S200) utilizes programmable hardware processing units (such as FPGAs or ASICs) to efficiently execute computationally intensive operators such as edge computing or machine learning, and achieves high-speed data exchange with DDR memory through DMA channels, greatly improving the throughput and real-time performance of localized data processing and effectively relieving the computing burden on the main controller CPU. The data preloading module (S300) intelligently constructs a data heat frequency table based on LBA access history, proactively migrating predicted high-frequency access data from NAND flash memory to high-speed DDR memory during SSD idle periods. This greatly reduces the latency of data access during computing task execution and provides near-memory computing for the computing acceleration engine. The data supply speed is at the level of Computing; the task offloading interface module (S400) seamlessly receives computing requests from the host, including task descriptors, parameters, and data locations, by extending the standard NVMe protocol instruction set, and directly returns the computing results to the host, realizing an efficient and standardized computing offloading mechanism. This simplifies host-side application development and significantly reduces the amount of raw data that needs to be transmitted, thereby reducing bus and network load; the security isolation module (S500) strictly isolates the core storage management firmware from the execution environment and data space of user computing tasks at the hardware level through the memory protection unit (MPU), ensuring the reliability of critical storage functions and data security, and preventing computing tasks from interfering with or attacking the storage system. In summary, this solution comprehensively improves the local data computing and processing capabilities of the SSD, enabling it to efficiently support near-storage computing scenarios such as edge computing and machine learning. By completing the processing at the data source in a "store-computation integration" manner and transmitting only simplified results, it fundamentally alleviates the system bottleneck caused by massive raw data transmission. This invention provides flexible task scheduling and resource management through a lightweight operating system module, supports dynamic loading of user-defined computing task programs, and efficiently executes edge computing or machine learning operators by combining the programmable hardware processing unit and DMA channel of the computing acceleration engine module. It utilizes a data preloading module to predict and preload data to DDR based on LBA access history, reducing access latency. It extends the NVMe protocol through a task offloading interface module to realize host task delivery and result return, and ensures hardware-level memory protection through a security isolation module. This significantly improves the data computing and processing capabilities of solid-state drives, supports localized computing tasks such as edge computing and machine learning, effectively reduces massive data transmission, and alleviates bus and network load.

[0018] In this embodiment of the invention, the lightweight operating system module includes: S110: Task scheduling unit, which adopts a priority-preemptive scheduling strategy, assigning the highest priority to storage management tasks and dynamically adjustable priority to computing tasks; S120: Dynamic loading unit, providing an application programming interface (API) to support the host in remotely deploying, updating or uninstalling computing task programs through the task unloading interface module; S130: Resource isolation unit, which implements the following isolation for computing tasks through configurable resource quotas: Limit the maximum DDR cache size for a single task; Limit the maximum continuous execution time of a single task; Computational tasks are prohibited from directly accessing flash physical layer operation instructions; S140: Hardware Abstraction Layer (HAL), which encapsulates the register operation interface of the computing acceleration engine module, so that computing tasks do not need to be aware of the underlying hardware differences. The task scheduling unit (S110) employs a priority-based preemptive strategy to assign the highest priority to storage management tasks, ensuring that the real-time performance and reliability of core storage operations (such as garbage collection and wear leveling) are not affected by computing tasks. Simultaneously, it allocates dynamically adjustable priorities to computing tasks, enabling flexible and optimized allocation of computing resources. The dynamic loading unit (S120) provides a standardized API interface, supporting the host to remotely deploy, update, or uninstall computing task programs via the task unloading interface. This significantly improves the dynamic deployment capability of computing functions and system maintainability, enabling functional iteration without physical intervention. The resource isolation unit (S130) implements strict control through a triple-configurable quota mechanism: limiting the maximum DDR cache space occupied by a single task to prevent memory exhaustion. To prevent system crashes, the system limits the longest continuous execution time of a single task to avoid computational deadlocks that block critical storage services. Prohibiting computational tasks from directly accessing flash physical layer operation instructions fundamentally eliminates user tasks' misoperation or malicious damage to the underlying storage medium, ensuring the stability of the storage system and data security. The Hardware Abstraction Layer (S140) encapsulates the hardware register operation details of the computation acceleration engine, allowing computational task programs to adapt to different hardware accelerators (such as FPGAs and ASICs) simply by calling a unified interface, significantly improving the portability and development efficiency of computational tasks. These measures collectively enhance the real-time performance, security, and flexibility of the lightweight operating system, providing a reliable isolated operating environment for concurrent execution of storage management and diverse computational tasks within solid-state drives.

[0019] In this embodiment of the invention, the computing acceleration engine module includes: S210: Heterogeneous computing unit, integrating a programmable hardware processor and a fixed-function hardware accelerator, wherein: the programmable hardware processor supports a general computing instruction set for executing conditional branch intensive tasks. The fixed-function hardware accelerator is pre-configured with a matrix multiply-accumulator (MAC) and a convolution kernel for performing parallel computing-intensive tasks. S220: Near Data Access Channel, which connects to Dynamic Random Access Memory (DDR) via a dedicated Direct Memory Access (DMA) engine, enabling computing units to directly read and write cached data without the need for the controller CPU to relay it; S230: Dual-mode computing architecture, supporting the following operating modes: Pre-computation mode: Feature extraction is performed before data is written to flash memory, and only the processing results are stored in flash memory; Post-computation mode: Responds to host commands and performs real-time analysis on cached data in DDR; S240: Extensible operator library, stores pre-compiled machine learning operators and edge computing function sets, including convolution, pooling, and hash calculation, and supports dynamic loading of new operators through lightweight operating system modules; The heterogeneous computing unit (S210) integrates a programmable hardware processor and a fixed-function hardware accelerator, forming a dual-engine architecture. The former supports efficient processing of conditional branch-intensive tasks (such as data filtering and rule judgment) using a general-purpose instruction set, while the latter specializes in parallel computation-intensive tasks (such as neural network inference) through a pre-built matrix multiply-accelerator (MAC) and convolution kernels, significantly improving computational flexibility and energy efficiency. The near-data access channel (S220) utilizes a dedicated DMA engine to establish a direct path between the computing unit and DDR, eliminating the controller CPU overhead and enabling zero-copy access to cached data, reducing data read / write latency to the microsecond level. The dual-mode computing architecture (S230) provides pre-... The computation mode (performing feature extraction in real time before data is written to flash memory, storing only the simplified results to compress 90%+ of the original data volume) and the post-computation mode (performing millisecond-level real-time analysis on DDR cache data) cover the entire lifecycle processing needs from data generation to storage; the scalable operator library (S240) is pre-configured with mainstream machine learning and edge computing operators (such as convolution, pooling, and hashing), and supports the dynamic loading of new operators (such as the Transformer module) through the operating system, realizing the continuous evolution of hardware acceleration capabilities. The above design works together to achieve ultra-low latency execution of computing tasks, efficient reuse of hardware resources, and full lifecycle data processing capabilities for in-memory computing scenarios.

[0020] In this embodiment of the invention, the data preloading module includes: S310: Access frequency modeling unit, which statistically analyzes the historical access frequency and timeliness of logical block addresses (LBAs) and constructs a dynamically updated frequency table, wherein: Access frequency is calculated based on the number of read and write operations within the sliding time window; Timeliness is dynamically weighted based on the difference between the most recent access time and the current time; S320: Hot data prediction unit, which identifies data blocks that meet any of the following conditions as hot data to be calculated based on the frequency table: The access frequency exceeds the first threshold; The timeliness-weighted value is higher than the second threshold; S330: Background preloading engine, which loads the hot data to be computed from the flash storage medium to the dynamic random access memory (DDR) when the SSD is idle. S340: Resource preemption response unit. When a high-priority storage operation request occurs during the preloading process, the preloading task is immediately terminated and the DDR bandwidth is released. The access frequency modeling unit (S310) dynamically tracks historical access patterns of LBAs, accurately counts read and write frequencies based on a sliding time window, and combines timeliness factors (dynamically weighted according to access time) to construct a real-time updated data heat model, significantly improving prediction accuracy. The hot data prediction unit (S320) adopts a dual-threshold intelligent judgment mechanism (LBAs with access frequency exceeding the threshold or timeliness weighting value meeting the standard) to accurately identify the hot data to be calculated, ensuring that the preloading target is highly matched with the real-time computing needs. The background preloading engine (S330) utilizes the idle bandwidth of the SSD to migrate the predicted hot data from low-speed NAND flash memory to high-speed DDR in advance, reducing the average latency of data acquisition required by computing tasks by more than 70%. The resource preemption response unit (S340) monitors the storage operation priority in real time. When encountering high-priority requests (such as garbage collection, host I / O), it immediately stops preloading and releases DDR resources to avoid background tasks interfering with critical storage services, ensuring the real-time performance and stability of the system. The above mechanisms work together to realize intelligent supply of computing data and elastic scheduling of resources, providing a near-zero waiting data access experience for near-memory computing with zero performance loss.

[0021] In this embodiment of the invention, the task unloading interface module includes: S410: Computation Instruction Extension Unit, which adds computation opcodes to the NVMe protocol command set and defines the following core instructions: Computation task submission instructions: include task type identifier, target data LBA range, and a list of computation parameters; The command to query the status of a task returns either the task's execution progress or an exception code. S420: Descriptor Resolution Unit, which decodes the computation task descriptor issued by the host into the following executable elements: The identifier of the computation operator invoked; The cache address of the input data in DDR; Identifier of the storage location of the calculation result; S430: Zero-copy transmission channel, employing the following mechanism to achieve efficient return of calculation results: Create a host-shared result buffer in DDR; The buffer physical address is mapped to the host memory space through the PCIe Address Translation Service (ATS); After the calculation is completed, a doorbell notification is sent to the host, triggering the host to directly read the result data; S440: Computation security verification unit, which performs the following verification on the received computation task descriptor: Task initiator authentication (based on NVMe Namespace access control); Legality check of the binding relationship between operators and data ranges (associated with S500 security isolation module); The computation instruction extension unit (S410) adds dedicated computation opcodes to the NVMe protocol (such as task submission instructions carrying task type, data LBA range and parameters, and status query instructions providing real-time progress feedback), providing the host with a standardized near-memory computation control interface, significantly simplifying the software integration complexity of computation offloading; the descriptor resolution unit (S420) intelligently decodes the computation task descriptors issued by the host into executable elements (including operator identifiers associated with the S240 operator library, DDR data addresses provided by the S300 preload module, and result storage locations), achieving precise mapping from computation intent to hardware resources; the zero-copy transmission channel (S430) adopts a host-DDR shared buffer combined with a PCIe Address Translation Service (ATS) physical address mapping mechanism, requiring only a doorbell notification after computation to trigger the host to directly read the results, eliminating the overhead of result data being copied via the controller CPU in traditional solutions, reducing result return delay and saving PCIe bandwidth; the computation security verification unit (S440) uses a dual verification mechanism (based on NVMe) The design includes namespace task initiator permission authentication and operator-data scope binding relationship legality checks, which block malicious or unauthorized computation requests. Together with the security isolation module (S500), it ensures the security and controllability of the computation process. The above design achieves efficient, secure and standardized computation offloading across the entire chain, significantly reducing host load and data transmission overhead, while ensuring the scalability and security of the near-storage computing ecosystem.

[0022] In this embodiment of the invention, the security isolation module (S500) includes: S510: Hardware Domain Isolation Unit, which divides the following privileged domains through the Memory Protection Unit (MPU): Storage privilege domain: Exclusive access to flash translation layer (FTL) metadata and physical layer control registers; Computational user domain: Restricts computational tasks to access only pre-allocated buffers in dynamic random access memory (DDR); S520: Abnormal Circuit Breaker Unit, which monitors computing task behavior in real time and immediately terminates the task and resets the computing engine when any of the following conditions are triggered: Unauthorized access to the privileged address space of the storage domain; The continuous running time of a single task exceeds the threshold set by the S130 resource isolation unit; The hardware acceleration engine (S200) reported a resource exhaustion error; S530: Security Audit Unit, which records the following behavior logs of computing tasks and stores them encrypted in flash memory: Task initiator identity (associated with S440 permission authentication); Accessed data LBA range and timestamp; Triggered exception event types and circuit breaker responses; S540: Cross-domain communication agent, providing restricted storage service access channels for computing tasks, wherein: Data read requests must be executed by proxy after the storage privilege domain verifies the validity of the LBA. The calculation results need to be submitted to the storage privilege domain for bad block management and wear leveling before being written back to flash memory. The hardware domain isolation unit (S510) utilizes the memory protection unit (MPU) to establish physical-level isolation between the storage privilege domain and the computing user domain: the former exclusively accesses FTL metadata and flash physical layer control registers to ensure core storage security, while the latter strictly restricts computing tasks to run within a pre-allocated DDR buffer, eliminating the risk of unauthorized intrusion into the storage system from the hardware level; the anomaly circuit breaker unit (S520) monitors computing task behavior in real time, immediately terminating the task and resetting the engine for anomalies such as unauthorized access to the storage privilege domain, timeout (triggering the S130 resource isolation threshold), or computing power exhaustion errors, achieving millisecond-level isolation and self-healing of faults; the security audit unit (S530) encrypts and records task initiation. The system identifies the user (associated with S440 authentication results), the scope of the accessed LBA, and the circuit breaker event, providing immutable log evidence for security tracing. The cross-domain communication agent (S540) provides a controlled storage service channel for computing tasks—data reading must be executed by the agent after the storage domain verifies the legality of the LBA, and the computing results written back to flash memory must be submitted to the storage domain for bad block management and wear leveling. While allowing necessary data interaction, it ensures the compliance of storage operations and the reliability of the media. The above mechanisms work together to build a hardware-enforced security boundary, real-time fault circuit interruption capability, full-link audit tracing, and a controlled cross-domain communication system, comprehensively ensuring the isolation, robustness, and data integrity of core storage functions and user computing tasks under the storage-computing integrated architecture.

[0023] A solid-state drive management system includes a controller, a flash memory storage medium, and a dynamic random access memory, wherein the controller operates in accordance with the aforementioned solid-state drive data processing method. By integrating solid-state drive (SSD) data processing methods into the controller operations of an SSD management system, deep synergy between hardware architecture and computing methods is achieved. Based on the controller's computing power scheduling capabilities, the data persistence characteristics of flash memory, and the high-speed caching advantages of DDR (Dynamic Random Access Memory), the system supports multi-task scheduling (S100) and security isolation (S500) of a lightweight operating system, heterogeneous processing of the computing acceleration engine (S200), intelligent prediction of data preloading (S300), and efficient communication of the task offloading interface (S400), thereby constructing a complete in-memory computing hardware platform at the physical layer. This integration enables the SSD management system to dynamically add... It loads and securely executes user-defined computing tasks, compressing raw data processing at the storage end through near-data computation and returning only simplified results to the host, significantly reducing bus data transfer volume by more than 60%. At the same time, hardware-level isolation mechanisms (S510-S540) ensure the parallel and reliable operation of core storage functions (such as FTL management and bad block handling) and computing tasks, avoiding resource conflicts or security risks. Ultimately, it forms an intelligent storage system with autonomous computing capabilities, elastic resource management, and a secure and reliable execution environment, fundamentally solving the bottleneck of insufficient computing power of traditional SSDs and providing a low-latency, high-throughput, and highly secure near-storage data processing infrastructure for edge computing and machine learning scenarios.

[0024] It will be apparent to those skilled in the art that the present invention is not limited to the details of the exemplary embodiments described above, and that the invention can be implemented in other specific forms without departing from its spirit or essential characteristics. Therefore, the embodiments should be considered in all respects as exemplary and non-limiting, and the scope of the invention is defined by the appended claims rather than the foregoing description. Thus, all variations falling within the meaning and scope of equivalents of the claims are intended to be included within the present invention. No reference numerals in the claims should be construed as limiting the scope of the claims.

Claims

1. A solid-state drive data processing method, characterized in that, include: S100: Lightweight operating system module, used to provide task scheduling, resource allocation management and hardware abstraction interface, and supports dynamic loading of user-defined computing task programs; S200: Computation acceleration engine module, which includes a programmable hardware processing unit for executing edge computing or machine learning operators and reading and writing data in DDR through a direct memory access (DMA) channel; S300: Data preloading module, which builds a frequency table based on logical block address (LBA) access history and preloads predicted data from flash memory to DDR when the SSD is idle; S400: Task offloading interface module, which extends the NVMe protocol instruction set to receive computation task descriptors issued by the host and return the computation results to the host; S500: Security isolation module, which isolates the storage management firmware from the computing task execution environment through a hardware-level memory protection unit.

2. The solid-state drive data processing method according to claim 1, characterized in that, The lightweight operating system module includes: S110: Task scheduling unit, which adopts a priority-preemptive scheduling strategy, assigning the highest priority to storage management tasks and dynamically adjustable priority to computing tasks; S120: Dynamic loading unit, providing an application programming interface (API) to support the host in remotely deploying, updating or uninstalling computing task programs through the task unloading interface module; S130: Resource isolation unit, which implements the following isolation for computing tasks through configurable resource quotas: Limit the maximum DDR cache size for a single task; Limit the maximum continuous execution time of a single task; Computational tasks are prohibited from directly accessing flash physical layer operation instructions; S140: Hardware Abstraction Layer (HAL) encapsulates the register operation interface of the computing acceleration engine module, so that computing tasks do not need to be aware of the underlying hardware differences.

3. The solid-state drive data processing method according to claim 2, characterized in that, The computing acceleration engine module includes: S210: Heterogeneous computing unit, integrating a programmable hardware processor and a fixed-function hardware accelerator, wherein: the programmable hardware processor supports a general computing instruction set for executing conditional branch intensive tasks. The fixed-function hardware accelerator is pre-configured with a matrix multiply-accumulator (MAC) and a convolution kernel for performing parallel computing-intensive tasks. S220: Near Data Access Channel, which connects to Dynamic Random Access Memory (DDR) via a dedicated Direct Memory Access (DMA) engine, enabling computing units to directly read and write cached data without the need for the controller CPU to relay it; S230: Dual-mode computing architecture, supporting the following operating modes: Pre-computation mode: Feature extraction is performed before data is written to flash memory, and only the processing results are stored in flash memory; Post-computation mode: responds to host commands and performs real-time analysis on cached data in DDR; S240: An extensible operator library that stores pre-compiled machine learning operators and edge computing function sets, including convolution, pooling, and hashing, and supports dynamically loading new operators through a lightweight operating system module (S100).

4. The solid-state drive data processing method according to claim 3, characterized in that, The data preloading module includes: S310: Access frequency modeling unit, which statistically analyzes the historical access frequency and timeliness of logical block addresses (LBAs) and constructs a dynamically updated frequency table, wherein: Access frequency is calculated based on the number of read and write operations within the sliding time window; Timeliness is dynamically weighted based on the difference between the most recent access time and the current time; S320: Hot data prediction unit, which identifies data blocks that meet any of the following conditions as hot data to be calculated based on the frequency table: The access frequency exceeds the first threshold; The timeliness-weighted value is higher than the second threshold; S330: Background preloading engine, which loads the hot data to be computed from the flash storage medium to the dynamic random access memory (DDR) when the SSD is idle. S340: Resource preemption response unit. When a high-priority storage operation request occurs during the preloading process, the preloading task is immediately terminated and the DDR bandwidth is released.

5. A solid-state drive data processing method according to claim 4, characterized in that, The task unloading interface module includes: S410: Computation Instruction Extension Unit, which adds computation opcodes to the NVMe protocol command set and defines the following core instructions: Computation task submission instructions: include task type identifier, target data LBA range, and a list of computation parameters; Computation status query command: returns task execution progress or exception code; S420: Descriptor resolution unit, decodes the computation task descriptor issued by the host into the following executable elements: The identifier of the computation operator invoked; The cache address of the input data in DDR; Calculation result storage location identifier; S430: Zero-copy transmission channel, employing the following mechanism to achieve efficient return of calculation results:** Create a host-shared result buffer in DDR; The buffer physical address is mapped to the host memory space through the PCIe Address Translation Service (ATS); After the calculation is completed, a doorbell notification is sent to the host, triggering the host to directly read the result data; S440: Computation security verification unit, which performs the following verification on the received computation task descriptor: Task initiator authorization authentication; Legality check of the binding relationship between operators and data ranges.

6. A solid-state drive data processing method according to claim 5, characterized in that, The security isolation module includes: S510: Hardware Domain Isolation Unit, which divides the following privileged domains through the Memory Protection Unit (MPU): Storage privilege domain: Exclusive access to flash translation layer (FTL) metadata and physical layer control registers; Computational user domain: Restricts computational tasks to access only pre-allocated buffers in dynamic random access memory (DDR); S520: Abnormal Circuit Breaker Unit, which monitors computing task behavior in real time and immediately terminates the task and resets the computing engine when any of the following conditions are triggered: Unauthorized access to the privileged address space of the storage domain; The continuous running time of a single task exceeds the threshold set by the S130 resource isolation unit; The hardware acceleration engine reported a resource exhaustion error; S530: Security Audit Unit, which records the following behavior logs of computing tasks and stores them encrypted in flash memory: Identity of the task initiator; Accessed data LBA range and timestamp; The types of abnormal events triggered and the circuit breaker response; S540: Cross-domain communication agent, providing restricted access to storage services for computing tasks, wherein: Data read requests must be executed by proxy after the storage privilege domain verifies the validity of the LBA. The calculation results need to be submitted to the storage privilege domain for bad block management and wear leveling before being written back to flash memory.

7. A solid-state drive management system, characterized in that, It includes a controller, a flash memory storage medium, and a dynamic random access memory, wherein the operation of the controller includes the solid-state drive data processing method according to any one of claims 1-6.

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