System, method, device, processor and medium for realizing multi-channel large-capacity data synchronous upload processing for channel emulator

Abstract

The present invention relates to a system for a channel emulator to realize multi-channel large-capacity data synchronous upload processing, comprising n baseband FPGA modules, a control FPGA module, n DDR4 chips and a host computer, wherein the n baseband FPGA modules are connected to the host computer through a host computer signal transmission interface and receive and transmit control signals and data signals, the DDR4 chip is connected to the baseband FPGA module through a DDR signal transmission interface and performs read and write operations, the host computer is connected to the control FPGA module through the host computer signal transmission interface and sends a data storage start signal, and the baseband FPGA module is connected to the control FPGA module. The system, method, device, processor and computer-readable storage medium for realizing multi-channel large-capacity data synchronous upload processing of the present invention are adopted to meet the requirements of multi-channel data synchronization; the number of digital domain data uploaded by the channel emulator to the host computer can be greatly increased, and it has advantages in improving the frequency accuracy of data analysis, enriching the method of data analysis, and widening the bandwidth of analyzable data.

Description

Technical Field

[0001] The present invention relates to the field of digital signal transmission, and in particular to the field of channel emulators, and specifically refers to a system, method, device, processor and computer-readable storage medium thereof for realizing multi-channel large-capacity data synchronous upload processing by a channel emulator. Background Art

[0002] In existing channel simulators, if users need to observe simulation results, they need to connect external instruments to view the analog signals output. If they need to observe digital signals in FPGA, they need to upload the digital signals in FPGA to the host computer through the digital interface, and analyze the uploaded signals through the digital signal analysis software in the host computer.

[0003] The main work content of uploading the digital signal in the FPGA to the host computer is to convert the data from the FPGA working clock domain to the host computer interface clock domain in the FPGA, and then transmit the signal from the FPGA to the host computer through the host computer interface. The clock in the host computer interface clock domain is usually of very low frequency. There are two existing methods for different usage requirements:

[0004] The first method is for signals with small bandwidth. Due to the small signal bandwidth, the sampling rate of converting the signal from analog signal to digital signal is also small, which makes the data working clock frequency of the FPGA that processes the signal very low. In this case, the signal can be directly converted from the working clock domain of the FPGA to the host computer interface clock domain through the asynchronous fifo. Since the data working clock frequency of the FPGA is very low, which is equivalent to or less than the host computer interface clock frequency, the asynchronous fifo will not be full, and the data source can be continuously uploaded to the host computer. The number of uploaded data depends on how much data the host computer can read at one time. The limitation of this method is that it is limited to signals with small bandwidth and data rate less than the rate at which the host computer interface uploads data.

[0005] The second method is for a small number of digital signals. Since there is no limit on the signal bandwidth, the sampling rate of the signal may be much greater than the maximum data transmission rate of the host computer interface. The designer needs to open up a storage space in the FPGA, which is usually an asynchronous fifo or asynchronous dual-port BRAM, to store the signal in the storage space, and then transmit the stored signal to the host computer through the asynchronous fifo and the host computer interface. Since the signal needs to be stored in a storage space first, the maximum number of data that can be uploaded depends on the size of the storage space opened. Since the storage space in the FPGA is limited and the excessive storage space utilization rate will affect the layout and routing of the signals in the FPGA, the amount of data uploaded to the host computer is very small, and the host computer needs to use the uploaded data for signal analysis. Too little data will result in too low frequency resolution and reduce the accuracy of signal analysis.

[0006] With the development of science and technology, channel emulators are also developing towards large bandwidth and high precision. The need for multi-channel simulation has also led to an increasing number of FPGAs included in channel emulators, which has led to a new need for synchronous data upload. The two existing methods for uploading digital signals can no longer meet existing usage requirements. Summary of the invention

[0007] The purpose of the present invention is to overcome the shortcomings of the above-mentioned prior art and provide a system, method, device, processor and computer-readable storage medium for channel emulator to realize multi-channel large-capacity data synchronous upload processing, which meets the requirements of large bandwidth, high precision and a wide range of applications.

[0008] In order to achieve the above-mentioned object, the system, method, device, processor and computer-readable storage medium for realizing multi-channel large-capacity data synchronous upload processing by a channel emulator of the present invention are as follows:

[0009] The system for realizing multi-channel large-capacity data synchronous upload processing for a channel emulator has the following main features: the system comprises n baseband FPGA modules, a control FPGA module, n DDR4 chips and a host computer; the n baseband FPGA modules are connected to the host computer through a host computer signal transmission interface and receive and send control signals and data signals; the DDR4 chip is connected to the baseband FPGA module through a DDR signal transmission interface and performs read and write operations; the host computer is connected to the control FPGA module through the host computer signal transmission interface and sends a start signal for data storage; and the baseband FPGA module is connected to the control FPGA module;

[0010] The baseband FPGA module is used to receive the digital signal transmitted by the analog-to-digital converter, perform channel simulation on the received digital signal, and transmit the channel simulation result to the digital-to-analog converter or the host computer; the control FPGA module is used to generate a synchronous write enable, and synchronously write the data in the baseband FPGA module into the DDR4 chip; the DDR4 chip is used to store a large amount of channel simulation results; the host computer is used to send a control signal to the baseband FPGA module, send a data storage start signal to the control FPGA module, and receive the channel simulation result signal uploaded by the baseband FPGA module, and perform data analysis on the channel simulation results.

[0011] Preferably, the baseband FPGA module includes a first asynchronous data cache fifo1, a second asynchronous data cache fifo2, and a read-write control module. The first asynchronous data cache fifo1 and the second asynchronous data cache fifo2 are both connected to the read-write control module. The first asynchronous data cache fifo1 and the second asynchronous data cache fifo2 are also connected to the DDR4 chip through a DDR signal transmission interface. The read-write control module is connected to the host computer through a host computer signal transmission interface, and the read-write control module is also connected to the control FPGA module; the first asynchronous data cache fifo1 is used to convert data in the data clock domain of the baseband FPGA module to the DDR data clock domain, the second asynchronous data cache fifo2 is used to convert data in the data clock domain of the baseband FPGA module to the host computer interface clock domain, and the read-write control module is used to generate enable, address and read-write control signals between the baseband FPGA module and the DDR chip, as well as read-write enable signals of the asynchronous cache fifo.

[0012] Preferably, the two asynchronous data cache fifos in the baseband FPGA module k are fifo1k and fifo2k, respectively, where k=1...n.

[0013] Preferably, the control FPGA module includes a control signal transceiver interface and a synchronization signal generating module. The receiving end of the control signal transceiver interface is connected to the host computer and is an asynchronous interface. It receives the start signal of data storage sent by the host computer. The sending end of the control signal transceiver interface is connected to n baseband FPGA modules and is a synchronous interface. It sends synchronization signals to n baseband FPGA modules. The synchronization signal generating module is used to generate a synchronous write enable and transmit it to the n baseband FPGA modules, so that the data in the baseband FPGA module is synchronously written into the DDR4 chip through the asynchronous cache fifo1.

[0014] Preferably, the DDR signal transmission interface includes a DDR control signal transceiver interface and a DDR data signal transceiver interface, the baseband FPGA module includes a DDR control signal transceiver interface, and the DDR4 chip includes a DDR data signal transceiver interface. The DDR control signal transceiver interface is used to send and receive control signals between the DDR4 chip and the baseband FPGA module, and the DDR data signal transceiver interface is used to send and receive data signals between the DDR4 chip and the baseband FPGA module.

[0015] Preferably, the host computer signal transmission interface includes a host computer control signal transceiver interface, a host computer data signal sending interface and a host computer data signal receiving interface, the baseband FPGA module includes a host computer control signal transceiver interface and a host computer data signal sending interface, and the host computer includes a host computer control signal transceiver interface and a host computer data signal receiving interface.

[0016] The method for implementing a multi-channel large-capacity data synchronous upload processing for a channel emulator using the above system is mainly characterized in that the method comprises the following steps:

[0017] (1) The host computer sends a reset signal reset to the baseband FPGA module and the control FPGA module. After receiving the reset signal, the baseband FPGA module sends a ddr_reset signal to the corresponding DDR4 chip. After waiting for 1 second, the DDR4 chip, the control FPGA module and the baseband FPGA module have all completed the reset and entered the initialization completion state; the host computer sends the total number of data sampling points to be uploaded total_len to the baseband FPGA module, and sends a data storage start signal to the control FPGA module;

[0018] (2) After the control FPGA module receives the signal, the synchronization signal generation module generates a synchronization signal and sends it to n baseband FPGA modules through the synchronization interface;

[0019] (3) After receiving the synchronization signal, the baseband FPGA module sets the cmd signal to 0 and outputs it to the DDR4 chip. The baseband FPGA module synchronously writes the data into the first asynchronous data buffer fifo1;

[0020] (4) If both ready and wdf_ready are high and the empty1 signal of fifo1k is low, pull up the en signal, the addr signal is 1, fifo1k reads the written data, and writes the second sampling point data to the DDR4 chip; if the conditions that both ready and wdf_ready are high and the empty1 signal of fifo1k is low cannot be met at the same time, pull down the en signal and wait for the next time when both ready and wdf_ready are high and the empty1 signal of fifo1k is low. Repeat (4) until the addr signal is total_len-1, and after the total_len sampling point data is written to the DDR4 chip, proceed to step (5);

[0021] (5) The baseband FPGA module k sends a data_ok signal to the host computer. After receiving the data_ok signals from all n baseband FPGA modules, the host computer divides the total_len sampling point data into m segments according to the data transmission capacity of the host computer signal transmission interface;

[0022] (6) The host computer sends a len signal to the baseband FPGA module 1, the read_start_addr signal is 0, and an open signal is sent; after receiving the open signal, the baseband FPGA module 1 sets the cmd signal to 1 and outputs it to the DDR4 chip;

[0023] (7) After receiving the empty2 signal sent back by the baseband FPGA module 1 as low, the host computer sends the rd_en2 signal to the baseband FPGA module 1 to read back the data in fifo21. When the empty2 signal is high, the data readback of this section is completed.

[0024] (8) Continue with steps (6) and (7), change the len signal sent to the baseband FPGA module to len2...lenm, and change the read_start_addr signal sent to the baseband FPGA module to len1...len(m-1); after the mth segment of data is read back, all the data that needs to be uploaded by the baseband FPGA module 1 has been completely uploaded;

[0025] (9) Continue steps (6) to (8) and upload all the data of baseband FPGA modules 2 to n to the host computer.

[0026] Preferably, the step (3) specifically comprises the following steps:

[0027] (3.1) If the ready and wdf_ready received by the baseband FPGA module k are both high and the empty1 signal of the first asynchronous data cache fifo1k is low, the en signal is pulled high, the addr signal is 0, the first asynchronous data cache fifo1k reads the written data, and writes the first sampling point data to the DDR4 chip k;

[0028] If the conditions that both ready and wdf_ready are high and the empty1 signal of fifo1k is low cannot be met at the same time, pull the en signal low and wait for the next time when both ready and wdf_ready are high and the empty1 signal of fifo1k is low.

[0029] Preferably, the step (6) specifically comprises the following steps:

[0030] When the ready signal is high and the full signal of fifo21 is low, the en signal is pulled high, the addr signal is 0, and the DDR4 chip writes the first sampling point data into fifo21, and the empty2 signal of fifo21 is pulled low and sent back to the host computer; if the conditions that the ready signal is high and the full signal of fifo21 is low cannot be met at the same time, the en signal is pulled low, and the next time when the ready is high and the full signal of fifo21 is low is met at the same time; when the ready signal is high again and the full signal of fifo21 is low, the en signal is pulled high, the addr signal is 1, and the DDR4 chip writes the second sampling point data into fifo21. Until the addr signal is len1-1, the DDR4 chip writes the len1th sampling point data into fifo21, and the DDR4 chip stops reading back and waits for the next open signal to arrive.

[0031] The main feature of the device for realizing synchronous uploading of multi-channel large-capacity data in a channel emulator is that the device comprises:

[0032] a processor configured to execute computer-executable instructions;

[0033] The memory stores one or more computer executable instructions. When the computer executable instructions are executed by the processor, the steps of the method for implementing the multi-channel large-capacity data synchronous upload processing for the channel simulator are implemented.

[0034] The processor for realizing multi-channel large-capacity data synchronous upload processing in a channel emulator has the main feature that the processor is configured to execute computer executable instructions. When the computer executable instructions are executed by the processor, the various steps of the above-mentioned method for realizing multi-channel large-capacity data synchronous upload processing in a channel emulator are realized.

[0035] The main feature of the computer-readable storage medium is that a computer program is stored thereon, and the computer program can be executed by a processor to implement the various steps of the above-mentioned method for implementing a channel simulator to perform multi-channel large-capacity data synchronous upload processing.

[0036] The system, method, device, processor and computer-readable storage medium thereof for realizing synchronous uploading and processing of multi-channel large-capacity data by a channel emulator of the present invention are adopted, so that the simulation results uploaded by the baseband FPGA module to the host computer are completely synchronized, and the requirements of multi-channel data synchronization can be met; according to the facilities and steps proposed in the present invention, the amount of digital domain data uploaded by the channel emulator to the host computer can be greatly increased, which has advantages in improving the frequency accuracy of data analysis, enriching the methods of data analysis, and widening the bandwidth of analyzable data. BRIEF DESCRIPTION OF THE DRAWINGS

[0037] Figure 1 The utility model is a block diagram of the facilities connection of the system for realizing multi-channel large-capacity data synchronous upload processing for a channel emulator of the present invention.

[0038] Figure 2 The present invention is a structural block diagram of a control FPGA of a system for implementing multi-channel large-capacity data synchronous upload processing for a channel emulator.

[0039] Figure 3 The present invention is a structural block diagram of a baseband FPGA of a system for implementing multi-channel large-capacity data synchronous upload processing for a channel emulator.

[0040] Figure 4 The present invention is a flowchart of the implementation steps of the method for implementing a channel emulator to perform multi-channel large-capacity data synchronous upload processing.

[0041] FIG5(a) is a diagram showing the simulation results of writing into a DDR4 chip of a system for implementing multi-channel large-capacity data synchronous upload processing using a channel emulator according to the present invention.

[0042] FIG. 5( b ) is a diagram of the simulation result uploaded to the host computer of the system for implementing multi-channel large-capacity data synchronous upload processing by the channel simulator of the present invention. DETAILED DESCRIPTION

[0043] In order to more clearly describe the technical content of the present invention, further description is given below in conjunction with specific embodiments.

[0044] The system for realizing multi-channel large-capacity data synchronous upload processing by a channel emulator of the present invention comprises n baseband FPGA modules, a control FPGA module, n DDR4 chips and a host computer, wherein the n baseband FPGA modules are connected to the host computer through a host computer signal transmission interface and receive and send control signals and data signals, the DDR4 chip is connected to the baseband FPGA module through a DDR signal transmission interface and performs read and write operations, the host computer is connected to the control FPGA module through the host computer signal transmission interface and sends a start signal for data storage, and the baseband FPGA module is connected to the control FPGA module;

[0045] The baseband FPGA module is used to receive the digital signal transmitted by the analog-to-digital converter, perform channel simulation on the received digital signal, and transmit the channel simulation result to the digital-to-analog converter or the host computer; the control FPGA module is used to generate a synchronous write enable, and synchronously write the data in the baseband FPGA module into the DDR4 chip; the DDR4 chip is used to store a large amount of channel simulation results; the host computer is used to send a control signal to the baseband FPGA module, send a data storage start signal to the control FPGA module, and receive the channel simulation result signal uploaded by the baseband FPGA module, and perform data analysis on the channel simulation results.

[0046] As a preferred embodiment of the present invention, the baseband FPGA module includes a first asynchronous data cache fifo1, a second asynchronous data cache fifo2, and a read-write control module. The first asynchronous data cache fifo1 and the second asynchronous data cache fifo2 are both connected to the read-write control module. The first asynchronous data cache fifo1 and the second asynchronous data cache fifo2 are also connected to the DDR4 chip through a DDR signal transmission interface. The read-write control module is connected to the host computer through a host computer signal transmission interface, and the read-write control module is also connected to the control FPGA module; the first asynchronous data cache fifo1 is used to convert data in the data clock domain of the baseband FPGA module to the DDR data clock domain, the second asynchronous data cache fifo2 is used to convert data in the data clock domain of the baseband FPGA module to the host computer interface clock domain, and the read-write control module is used to generate enable, address and read-write control signals between the baseband FPGA module and the DDR chip, as well as read-write enable signals of the asynchronous cache fifo.

[0047] As a preferred implementation mode of the present invention, the two asynchronous data cache fifos in the baseband FPGA module k are fifo1k and fifo2k, respectively, where k=1...n.

[0048] As a preferred embodiment of the present invention, the control FPGA module includes a control signal transceiver interface and a synchronization signal generating module. The receiving end of the control signal transceiver interface is connected to the host computer and is an asynchronous interface. It receives the start signal of data storage sent by the host computer. The sending end of the control signal transceiver interface is connected to n baseband FPGA modules and is a synchronous interface. It sends synchronization signals to n baseband FPGA modules. The synchronization signal generating module is used to generate a synchronous write enable and transmit it to n baseband FPGA modules, so that the data in the baseband FPGA module is synchronously written into the DDR4 chip through the asynchronous cache fifo1.

[0049] As a preferred embodiment of the present invention, the DDR signal transmission interface includes a DDR control signal transceiver interface and a DDR data signal transceiver interface, the baseband FPGA module includes a DDR control signal transceiver interface, and the DDR4 chip includes a DDR data signal transceiver interface. The DDR control signal transceiver interface is used to receive and send control signals between the DDR4 chip and the baseband FPGA module, and the DDR data signal transceiver interface is used to receive and send data signals between the DDR4 chip and the baseband FPGA module.

[0050] As a preferred embodiment of the present invention, the host computer signal transmission interface includes a host computer control signal transceiver interface, a host computer data signal sending interface and a host computer data signal receiving interface, the baseband FPGA module includes a host computer control signal transceiver interface and a host computer data signal sending interface, and the host computer includes a host computer control signal transceiver interface and a host computer data signal receiving interface.

[0051] The method of the present invention using the above system to implement a channel emulator for performing multi-channel large-capacity data synchronous upload processing includes the following steps:

[0052] (1) The host computer sends a reset signal reset to the baseband FPGA module and the control FPGA module. After receiving the reset signal, the baseband FPGA module sends a ddr_reset signal to the corresponding DDR4 chip. After waiting for 1 second, the DDR4 chip, the control FPGA module and the baseband FPGA module have all completed the reset and entered the initialization completion state; the host computer sends the total number of data sampling points to be uploaded total_len to the baseband FPGA module, and sends a data storage start signal to the control FPGA module;

[0053] (2) After the control FPGA module receives the signal, the synchronization signal generation module generates a synchronization signal and sends it to n baseband FPGA modules through the synchronization interface;

[0054] (3) After receiving the synchronization signal, the baseband FPGA module sets the cmd signal to 0 and outputs it to the DDR4 chip. The baseband FPGA module synchronously writes the data into the first asynchronous data buffer fifo1;

[0055] (4) If both ready and wdf_ready are high and the empty1 signal of fifo1k is low, pull up the en signal, the addr signal is 1, fifo1k reads the written data, and writes the second sampling point data to the DDR4 chip; if the conditions that both ready and wdf_ready are high and the empty1 signal of fifo1k is low cannot be met at the same time, pull down the en signal and wait for the next time when both ready and wdf_ready are high and the empty1 signal of fifo1k is low. Repeat (4) until the addr signal is total_len-1, and after the total_len sampling point data is written to the DDR4 chip, proceed to step (5);

[0056] (5) The baseband FPGA module k sends a data_ok signal to the host computer. After receiving the data_ok signals from all n baseband FPGA modules, the host computer divides the total_len sampling point data into m segments according to the data transmission capacity of the host computer signal transmission interface;

[0057] (6) The host computer sends a len signal to the baseband FPGA module 1, the read_start_addr signal is 0, and an open signal is sent; after receiving the open signal, the baseband FPGA module 1 sets the cmd signal to 1 and outputs it to the DDR4 chip;

[0058] (7) After receiving the empty2 signal sent back by the baseband FPGA module 1 as low, the host computer sends the rd_en2 signal to the baseband FPGA module 1 to read back the data in fifo21. When the empty2 signal is high, the data readback of this section is completed.

[0059] (8) Continue with steps (6) and (7), change the len signal sent to the baseband FPGA module to len2...lenm, and change the read_start_addr signal sent to the baseband FPGA module to len1...len(m-1); after the mth segment of data is read back, all the data that needs to be uploaded by the baseband FPGA module 1 has been completely uploaded;

[0060] (9) Continue steps (6) to (8) and upload all the data of baseband FPGA modules 2 to n to the host computer.

[0061] As a preferred embodiment of the present invention, the step (3) specifically comprises the following steps:

[0062] (3.1) If the ready and wdf_ready received by the baseband FPGA module k are both high and the empty1 signal of the first asynchronous data cache fifo1k is low, the en signal is pulled high, the addr signal is 0, the first asynchronous data cache fifo1k reads the written data, and writes the first sampling point data to the DDR4 chip k;

[0063] If the conditions that both ready and wdf_ready are high and the empty1 signal of fifo1k is low cannot be met at the same time, pull the en signal low and wait for the next time when both ready and wdf_ready are high and the empty1 signal of fifo1k is low.

[0064] As a preferred embodiment of the present invention, the step (6) specifically comprises the following steps:

[0065] When the ready signal is high and the full signal of fifo21 is low, the en signal is pulled high, the addr signal is 0, and the DDR4 chip writes the first sampling point data into fifo21, and the empty2 signal of fifo21 is pulled low and sent back to the host computer; if the conditions that the ready signal is high and the full signal of fifo21 is low cannot be met at the same time, the en signal is pulled low, and the next time when the ready is high and the full signal of fifo21 is low is met at the same time; when the ready signal is high again and the full signal of fifo21 is low, the en signal is pulled high, the addr signal is 1, and the DDR4 chip writes the second sampling point data into fifo21. Until the addr signal is len1-1, the DDR4 chip writes the len1th sampling point data into fifo21, and the DDR4 chip stops reading back and waits for the next open signal to arrive.

[0066] The device for realizing synchronous uploading of multi-channel large-capacity data in a channel emulator of the present invention comprises:

[0067] a processor configured to execute computer executable instructions;

[0068] The memory stores one or more computer executable instructions. When the computer executable instructions are executed by the processor, the steps of the method for implementing the multi-channel large-capacity data synchronous upload processing for the channel simulator are implemented.

[0069] The processor of the present invention is used to implement multi-channel large-capacity data synchronous upload processing in a channel emulator, wherein the processor is configured to execute computer-executable instructions. When the computer-executable instructions are executed by the processor, the various steps of the above-mentioned method for implementing multi-channel large-capacity data synchronous upload processing in a channel emulator are implemented.

[0070] The computer-readable storage medium of the present invention stores a computer program thereon, and the computer program can be executed by a processor to implement the various steps of the above-mentioned method for implementing a channel emulator to perform multi-channel large-capacity data synchronous upload processing.

[0071] In the specific implementation of the present invention, the problem of a small amount of data in the transmission of large-bandwidth digital signals between the baseband FPGA module and the host computer is solved, the problem of the need to limit the signal bandwidth when transmitting a large amount of data between the baseband FPGA module and the host computer is solved, and the problem of synchronous uploading of data in different data channels in different baseband FPGA modules is solved. The method proposed by the present invention enables the transmission of large-bandwidth and large-quantity synchronous digital signals between the baseband FPGA module and the host computer.

[0072] The invention proposes a method for realizing synchronous uploading processing of multi-channel large-capacity data by a channel simulator.

[0073] The method proposed in the present invention includes facilities such as baseband FPGA module, control FPGA module, DDR4 chip, and host computer. A channel emulator includes n baseband FPGA modules (FPGA1-FPGAn), 1 control FPGA module, n DDR4 chips (DDR4 chip 1-DDR4 chip n) and a host computer.

[0074] The facilities included in the present invention and the interfaces between the facilities are described as follows:

[0075] Baseband FPGA module: used to receive the digital signal transmitted by the analog-to-digital converter, perform channel simulation on the received digital signal, and finally transmit the result of channel simulation to the digital-to-analog converter or the host computer. It is the core component of the channel emulator. The baseband FPGA module contains two asynchronous data cache fifos. The first asynchronous data cache fifo1 is used to convert the data in the data clock domain of the baseband FPGA module to the DDR data clock domain, and the second asynchronous data cache fifo2 is used to convert the data in the data clock domain of the baseband FPGA module to the host computer interface clock domain. The baseband FPGA module also contains a read-write control module, which is used to generate control signals such as enable (en), address (addr) and read-write control (cmd) between the baseband FPGA module and the DDR chip, and the read-write enable (wr_en and rd_en) signals of the asynchronous cache fifo. The two asynchronous data cache fifos in the baseband FPGA module k (k=1...n) are called fifo1k and fifo2k. The interface used to read and write with the DDR4 chip is called the DDR signal transmission interface. The interface used to transmit control signals to the host computer and upload channel simulation result signals to the host computer is called the host computer signal transmission interface.

[0076] Control FPGA module: Contains a control signal transceiver interface and a synchronization signal generation module. The receiving end of the control signal transceiver interface in the control FPGA module is connected to the host computer and is an asynchronous interface for receiving the start signal of data storage sent by the host computer. The sending end is connected to n baseband FPGA modules and is a synchronous interface for sending synchronization signals to n baseband FPGA modules. The synchronization signal generation module is used to generate a synchronous write enable and send it to n baseband FPGA modules, so that the data in the baseband FPGA module is synchronously written to the DDR4 chip through the asynchronous cache fifo1.

[0077] DDR4 chip: A large-capacity external data storage device used to store a large amount of channel simulation results, with a data capacity of more than 1GB. It performs read and write operations with the baseband FPGA module through the DDR signal transmission interface.

[0078] Host computer: Sends control signals to the baseband FPGA module, sends data storage start signals to the control FPGA module, and is used to receive channel simulation result signals uploaded by the baseband FPGA module and perform data analysis on the channel simulation results. Control signals and data signals are sent and received with the baseband FPGA module through the host computer signal transmission interface, and the host computer signal transmission interface also sends data storage start signals to the control FPGA module through the interface.

[0079] The DDR signal transmission interface includes a control signal transceiver interface and a data signal transceiver interface, which are called DDR control signal transceiver interface and DDR data signal transceiver interface. The baseband FPGA module and the DDR4 chip respectively include a DDR control signal transceiver interface and a DDR data signal transceiver interface. The DDR control signal transceiver interface is used to receive and send control signals between the DDR4 chip and the baseband FPGA module, and the DDR data signal transceiver interface is used to receive and send data signals between the DDR4 chip and the baseband FPGA module. There are n DDR signal transmission interfaces in a channel emulator, and one baseband FPGA module corresponds to one DDR4 chip, that is, the baseband FPGA module k is connected to the DDR4 chip k through the DDR signal transmission interface k.

[0080] The host computer signal transmission interface includes a control signal transceiver interface, a data signal transmission interface, and a data signal receiving interface, which are called a host computer control signal transceiver interface, a host computer data signal transmission interface, and a host computer data signal receiving interface. The baseband FPGA module includes a host computer control signal transceiver interface and a host computer data signal transmission interface, and the host computer includes a host computer control signal transceiver interface and a host computer data signal receiving interface. There are n host computer signal transmission interfaces in a channel emulator, and the baseband FPGA module k is connected to the host computer through the host computer signal transmission interface k.

[0081] The implementation steps of the present invention are as follows:

[0082] Step 1: The host computer sends a reset signal reset to the baseband FPGA module and the control FPGA module. After receiving the reset signal, the baseband FPGA module sends a ddr_reset signal to the corresponding DDR4 chip. After waiting for 1 second, the DDR4 chip, the control FPGA module, and the baseband FPGA module have completed the reset and entered the initialization completion state. The ready and wdf_ready signals of the DDR4 chip have been pulled high. The host computer sends the total number of sampling points of the data to be uploaded, total_len, to the baseband FPGA module, and then sends a data storage start signal to the control FPGA module;

[0083] Step 2: After the control FPGA module receives it, the synchronization signal generation module generates a synchronization signal and sends it to n baseband FPGA modules through the synchronization interface;

[0084] Subsequent steps 3 to 4 are described for the baseband FPGA module and DDR4 chip numbered k (k=1...n), and the steps for the baseband FPGA modules and DDR4 chips with other numbers are the same.

[0085] Step 3: After receiving the synchronization signal, the baseband FPGA module k (k=1…n) sets the cmd signal to 0 and outputs it to the DDR4 chip. Then the baseband FPGA module k synchronously writes the data into the first asynchronous data cache fifo1k, and the empty1 signal of fifo1k is pulled low. If the ready and wdf_ready received by the baseband FPGA module k are both high and the empty1 signal of the first asynchronous data cache fifo1k is low, the en signal is pulled high, the addr signal is 0, and the first asynchronous data cache fifo1k reads the written data and writes the first sampling point data to the DDR4 chip k. Afterwards, if the conditions that both ready and wdf_ready are high and the empty1 signal of fifo1k is low cannot be met at the same time, the en signal is pulled low and waits for the next time when the conditions that both ready and wdf_ready are high and the empty1 signal of fifo1k is low are met at the same time;

[0086] Step 4: When both ready and wdf_ready are high and the empty1 signal of fifo1k is low, pull up the en signal, the addr signal is 1 (i.e., addr=addr+1), fifo1k reads the written data, and writes the second sampling point data to the DDR4 chip k. Afterwards, if the conditions that both ready and wdf_ready are high and the empty1 signal of fifo1k is low cannot be met at the same time, pull down the en signal and wait for the next time when both ready and wdf_ready are high and the empty1 signal of fifo1k is low. Repeat step 4 until the addr signal is total_len-1, and after the total_len sampling point data is written to the DDR4 chip k, proceed to step 5;

[0087] Step 5: Baseband FPGA module k sends data_ok signal to the host computer. After receiving data_ok signals from all n baseband FPGA modules, the host computer divides total_len sampling point data into m segments according to the data transmission capacity of the host computer signal transmission interface. The number of sampling point data in each segment is len1, len2...lenm, len1+len2+...+lenm=total_len.

[0088] Step 6: The host computer sends the len signal to the baseband FPGA module 1, which is len1, and the read_start_addr signal is 0, and then sends the open signal. After receiving the open signal, the baseband FPGA module 1 sets the cmd signal to 1 and outputs it to the DDR4 chip. When the ready signal is high and the full signal of fifo21 is low, the en signal is pulled high, the addr signal is 0 (i.e., read_start_addr), and the DDR4 chip 1 writes the first sampling point data into fifo21, and the empty2 signal of fifo21 is pulled low and sent back to the host computer. After that, if the conditions that the ready is high and the full signal of fifo21 is low cannot be met at the same time, the en signal is pulled low and waits for the next time when the conditions that the ready is high and the full signal of fifo21 is low are met at the same time. When ready is high again and the full signal of fifo21 is low, the en signal is pulled high, the addr signal is 1 (i.e., addr=addr+1), and the DDR4 chip 1 writes the second sampling point data into fifo21. When the addr signal is len1-1 (i.e., len-1), the DDR4 chip 1 writes the len1th (i.e., len) sampling point data into fifo21, and then the DDR4 chip 1 stops reading back and waits for the next open signal to arrive;

[0089] Step 7: After receiving the empty2 signal sent back by the baseband FPGA module 1 as low, the host computer sends the rd_en2 signal to the baseband FPGA module 1 to read back the data in fifo21. When the empty2 signal is high, the data readback of this section is completed.

[0090] Step 8: Repeat steps 6 and 7, except that the len signal sent to the baseband FPGA module is changed to len2…lenm, and the read_start_addr signal sent is changed to len1…len(m-1). After the mth segment of data is read back, all the data that needs to be uploaded by the baseband FPGA module 1 has been completely uploaded;

[0091] Step 9: Repeat steps 6 to 8 to upload all the data of baseband FPGA modules 2 to n to the host computer.

[0092] At this point, the host computer has obtained the n-channel large-capacity synchronous channel simulation data uploaded by the n baseband FPGA modules, and can perform corresponding data analysis on the uploaded data in the host computer.

[0093] Figure 1 The hardware of this embodiment is composed of a host computer, two baseband FPGA modules, two DDR4 chips and a control FPGA module. Figure 2 As shown, the control FPGA module includes a synchronization signal generation module and a control signal transceiver interface. Figure 3 As shown, the baseband FPGA module includes two asynchronous data cache fifos, a DDR signal transmission interface, a host computer signal transmission interface and a read-write control module.

[0094] This embodiment requires each baseband FPGA module to upload 1638400 continuous sampling points of the channel simulation results to the host computer so that the designer can analyze the channel simulation results. According to the transmission capacity of the host computer signal transmission interface, the 1638400 sampling point data are divided into 10 groups, and each group uploads 163840 sampling point data. Figure 4 Flow chart of the implementation steps in this embodiment.

[0095] The host computer sends a reset signal reset to baseband FPGA module 1, baseband FPGA module 2 and control FPGA module. After receiving the reset signal, baseband FPGA module 1 and baseband FPGA module 2 send ddr_reset signal to the corresponding DDR4 chip 1 and DDR4 chip 2. After waiting for 1 second, the DDR4 chip, control FPGA module and baseband FPGA module have completed the reset and entered the initialization completion state. The ready and wdf_ready signals of the DDR4 chip have been pulled high. The host computer sends the total number of data to be uploaded, 1638400, to baseband FPGA module 1 and baseband FPGA module 2, and then sends the data storage start signal to the control FPGA module. After the control FPGA module receives it, the synchronization signal generation module generates a synchronization signal and sends it to the two baseband FPGA modules through the synchronization interface.

[0096] After receiving the synchronization signal, the baseband FPGA module 1 sets the cmd signal to 0 and outputs it to the DDR4 chip 1. Then, the baseband FPGA module 1 pulls up wr_en1 to synchronously write the data into the first asynchronous data cache fifo11, and pulls down the empty1 signal of fifo11. If the ready and wdf_ready received by the baseband FPGA module 1 are both high and the empty1 signal of fifo11 is low, the en signal is pulled high, the addr signal is 0, and the rd_en1 is pulled high. Fifo11 reads the written data and writes the first sampling point data to the DDR4 chip 1. Afterwards, if the conditions that both ready and wdf_ready are high and the empty1 signal of fifo11 is low cannot be met at the same time, the en signal is pulled low and waits for the next time when both ready and wdf_ready are high and the empty1 signal of fifo11 is low. When the above conditions are met again, the en signal is pulled high again, the addr signal is 1 (i.e., addr=addr+1), fifo11 reads the written data, and writes the second sampling point data to DDR4 chip 1. Repeat the steps until the addr signal is 1638399. After the 1638400th sampling point data is written to DDR4 chip 1, the step of writing data to DDR4 chip 1 is completed. The data writing steps of baseband FPGA module 2 and DDR4 chip 2 are the same as those of baseband FPGA module 1 and DDR4 chip 1, and the data writing steps of the two baseband FPGA modules are processed in parallel.

[0097] The two baseband FPGA modules send data_ok signals to the host computer after the data writing step is completed. After receiving the data_ok signals from all two baseband FPGA modules, the host computer divides the 1638400 sampling point data into 10 segments according to the data transmission capacity of the host computer signal transmission interface, and the number of sampling point data in each segment is 163840.

[0098] The baseband FPGA module sets the cmd signal to 1 and outputs it to the DDR4 chip. The host computer sends the len signal of 163840 and the read_start_addr signal of 0 to the baseband FPGA module 1, and then sends the open signal. After receiving the open signal, when the ready signal is high and the full signal of fifo21 is low, the baseband FPGA module 1 pulls up the en signal, the addr signal is 0, and the DDR4 chip 1 writes the first sampling point data into fifo21, and pulls down the empty2 signal of fifo21 and sends it back to the host computer. After the host computer receives the empty2 signal of fifo21 and pulls down, it sends the rd_en2 signal to the baseband FPGA module 1, and the data of fifo21 is uploaded to the host computer. If the conditions that the ready is high and the full signal of fifo21 is low cannot be met at the same time, the en signal is pulled down and waits for the next time when the conditions that the ready is high and the full signal of fifo21 is low are met at the same time. When the above conditions are met again, the en signal is pulled high, the addr signal is 1 (i.e., addr=addr+1), and the DDR4 chip 1 writes the second sampling point data into fifo21. Until the addr signal is 163839, after the DDR4 chip 1 writes the 163840th sampling point data into fifo21, the DDR4 chip 1 stops reading back and waits for the next open signal to arrive. After fifo21 uploads all the first segment of 163840 sampling point data, the empty2 signal is pulled high. After receiving the empty2 signal high, the host computer pulls down rd_en2, sends the len signal of 163840 and the read_start_addr signal of 163840 (i.e., read_start_addr=read_start_addr+163840) to the baseband FPGA module 1, and then sends the open signal. Repeat the steps until all 163,840 sampling point data in the tenth segment are uploaded. The host computer receives a total of 10*163,840 sampling point data uploaded by the baseband FPGA module 1. After splicing them in sequence, 1,638,400 continuous sampling point data of the channel simulation results uploaded by the baseband FPGA module 1 are obtained.

[0099] Next, baseband FPGA module 2 uploads data to the host computer, and the steps are the same as those of baseband FPGA module 1. The data of the two baseband FPGA modules are uploaded serially, first uploading the data of baseband FPGA module 1, and then uploading the data of baseband FPGA module 2.

[0100] At this time, the data obtained by the host computer is the synchronous data of the channel simulation results of the two channels, which can be used for subsequent digital domain signal analysis and processing.

[0101] The device mentioned in the technical solution of the present invention includes n baseband FPGA modules, a control FPGA module, n DDR4 chips and a host computer. Data upload is uploaded from the inside of the baseband FPGA to the host computer outside the baseband FPGA through the host computer signal transmission interface.

[0102] The method proposed in the technical solution of the present invention is aimed at synchronously uploading multi-channel data of n baseband FPGAs, and the host computer can obtain n groups of data uploaded by the n baseband FPGAs.

[0103] The sources of the synchronous control signals and asynchronous control signals required by the technical solution of the present invention are all outside the baseband FPGA. Only the control signals generated in the read-write control module are inside the baseband FPGA. Data upload is also uploaded from the baseband FPGA to the host computer outside the FPGA. In this technical solution, one host computer can access multiple baseband FPGAs and multiple DDR4 chips.

[0104] In the technical solution of the present invention, through the two devices of the host computer and the control FPGA and the synchronization interface, according to the implementation steps, the data stored and uploaded by the n baseband FPGAs and the n DDR4 chips are large-capacity synchronous data, so as to meet the channel emulator's demand for multi-channel large-capacity synchronous data upload.

[0105] The specific implementation scheme of this embodiment can refer to the relevant description in the above embodiment, which will not be repeated here.

[0106] It can be understood that the same or similar parts of the above embodiments can be referenced to each other, and the contents not described in detail in some embodiments can refer to the same or similar contents in other embodiments.

[0107] It should be noted that, in the description of the present invention, the terms "first", "second", etc. are only used for descriptive purposes and cannot be understood as indicating or implying relative importance. In addition, in the description of the present invention, unless otherwise specified, the meaning of "plurality" refers to at least two.

[0108] Any process or method description in a flowchart or otherwise described herein may be understood to represent a module, segment or portion of code that includes one or more executable instructions for implementing the steps of a specific logical function or process, and the scope of the preferred embodiments of the present invention includes alternative implementations in which functions may not be performed in the order shown or discussed, including performing functions in a substantially simultaneous manner or in the reverse order depending on the functions involved, which should be understood by those skilled in the art to which the embodiments of the present invention belong.

[0109] It should be understood that the various parts of the present invention can be implemented by hardware, software, firmware or a combination thereof. In the above-mentioned embodiments, a plurality of steps or methods can be implemented by software or firmware stored in a memory and executed by a suitable instruction execution device. For example, if implemented by hardware, as in another embodiment, it can be implemented by any one of the following technologies known in the art or their combination: a discrete logic circuit having a logic gate circuit for implementing a logic function for a data signal, a dedicated integrated circuit having a suitable combination of logic gate circuits, a programmable gate array (PGA), a field programmable gate array (FPGA), etc.

[0110] A person skilled in the art may understand that all or part of the steps in the method for implementing the above-mentioned embodiment may be completed by instructing related hardware through a program, and the corresponding program may be stored in a computer-readable storage medium, which, when executed, includes one of the steps of the method embodiment or a combination thereof.

[0111] In addition, each functional unit in each embodiment of the present invention may be integrated into a processing module, or each unit may exist physically separately, or two or more units may be integrated into one module. The above-mentioned integrated module may be implemented in the form of hardware or in the form of a software functional module. If the integrated module is implemented in the form of a software functional module and sold or used as an independent product, it may also be stored in a computer-readable storage medium.

[0112] The storage medium mentioned above can be a read-only memory, a magnetic disk or an optical disk, etc.

[0113] In the description of this specification, the description with reference to the terms "one embodiment", "some embodiments", "examples", "specific examples", or "some examples" means that the specific features, structures, materials or characteristics described in conjunction with the embodiment or example are included in at least one embodiment or example of the present invention. In this specification, the schematic representation of the above terms does not necessarily refer to the same embodiment or example. Moreover, the specific features, structures, materials or characteristics described may be combined in any one or more embodiments or examples in a suitable manner.

[0114] The system, method, device, processor and computer-readable storage medium thereof for realizing synchronous uploading and processing of multi-channel large-capacity data by a channel emulator of the present invention are adopted, so that the simulation results uploaded by the baseband FPGA module to the host computer are completely synchronized, and the requirements of multi-channel data synchronization can be met; according to the facilities and steps proposed in the present invention, the amount of digital domain data uploaded by the channel emulator to the host computer can be greatly increased, which has advantages in improving the frequency accuracy of data analysis, enriching the methods of data analysis, and widening the bandwidth of analyzable data.

[0115] In this specification, the present invention has been described with reference to specific embodiments thereof. However, it is apparent that various modifications and variations may be made without departing from the spirit and scope of the present invention. Therefore, the specification and drawings should be regarded as illustrative rather than restrictive.

Claims

1. A system for a channel emulator to realize multi-channel large-capacity data synchronous upload processing, characterized in that: The system includes n baseband FPGA modules, a control FPGA module, n DDR4 chips and a host computer, wherein the n baseband FPGA modules are connected to the host computer through a host computer signal transmission interface and receive and send control signals and data signals, the DDR4 chip is connected to the baseband FPGA module through a DDR signal transmission interface and performs read and write operations, the host computer is connected to the control FPGA module through the host computer signal transmission interface and sends a start signal for data storage, and the baseband FPGA module is connected to the control FPGA module; The baseband FPGA module is used to receive the digital signal transmitted by the analog-to-digital converter, perform channel simulation on the received digital signal, and transmit the channel simulation result to the digital-to-analog converter or the host computer; the control FPGA module is used to generate a synchronous write enable, and synchronously write the data in the baseband FPGA module into the DDR4 chip; the DDR4 chip is used to store a large amount of channel simulation results; the host computer is used to send a control signal to the baseband FPGA module, send a data storage start signal to the control FPGA module, and receive the channel simulation result signal uploaded by the baseband FPGA module, and perform data analysis on the channel simulation results.

2. The system for realizing multi-channel large-capacity data synchronous upload processing for a channel emulator according to claim 1, characterized in that: The baseband FPGA module includes a first asynchronous data cache fifo1, a second asynchronous data cache fifo2, and a read-write control module. The first asynchronous data cache fifo1 and the second asynchronous data cache fifo2 are both connected to the read-write control module. The first asynchronous data cache fifo1 and the second asynchronous data cache fifo2 are also connected to the DDR4 chip through a DDR signal transmission interface. The read-write control module is connected to the host computer through a host computer signal transmission interface. The read-write control module is also connected to the control FPGA module; the first asynchronous data cache fifo1 is used to convert data in the baseband FPGA module data clock domain to the DDR data clock domain, the second asynchronous data cache fifo2 is used to convert data in the baseband FPGA module data clock domain to the host computer interface clock domain, and the read-write control module is used to generate enable, address and read-write control signals between the baseband FPGA module and the DDR chip, as well as the read-write enable signal of the asynchronous cache fifo.

3. The system for implementing multi-channel large-capacity data synchronous upload processing for a channel emulator according to claim 2, characterized in that: The two asynchronous data cache fifos in the baseband FPGA module k are fifo1k and fifo2k respectively, where k=1...n.

4. The system for implementing multi-channel large-capacity data synchronous upload processing for a channel emulator according to claim 1, characterized in that: The control FPGA module includes a control signal transceiver interface and a synchronization signal generating module. The receiving end of the control signal transceiver interface is connected to the host computer and is an asynchronous interface. It receives the start signal of data storage sent by the host computer. The sending end of the control signal transceiver interface is connected to n baseband FPGA modules and is a synchronous interface. It sends synchronization signals to the n baseband FPGA modules. The synchronization signal generating module is used to generate a synchronous write enable and transmit it to the n baseband FPGA modules, so that the data in the baseband FPGA module is synchronously written into the DDR4 chip through the asynchronous cache fifo1.

5. The system for implementing multi-channel large-capacity data synchronous upload processing for a channel emulator according to claim 1, characterized in that: The DDR signal transmission interface includes a DDR control signal transceiver interface and a DDR data signal transceiver interface, the baseband FPGA module includes a DDR control signal transceiver interface, and the DDR4 chip includes a DDR data signal transceiver interface. The DDR control signal transceiver interface is used to receive and send control signals between the DDR4 chip and the baseband FPGA module, and the DDR data signal transceiver interface is used to receive and send data signals between the DDR4 chip and the baseband FPGA module.

6. The system for implementing multi-channel large-capacity data synchronous upload processing for a channel emulator according to claim 1, characterized in that: The host computer signal transmission interface includes a host computer control signal transceiver interface, a host computer data signal sending interface and a host computer data signal receiving interface. The baseband FPGA module includes a host computer control signal transceiver interface and a host computer data signal sending interface. The host computer includes a host computer control signal transceiver interface and a host computer data signal receiving interface.

7. A method for implementing a channel emulator to synchronously upload multi-channel large-capacity data based on the system of claim 1, characterized in that: The method comprises the following steps: (1) The host computer sends a reset signal reset to the baseband FPGA module and the control FPGA module. After receiving the reset signal, the baseband FPGA module sends a ddr_reset signal to the corresponding DDR4 chip. After waiting for 1 second, the DDR4 chip, the control FPGA module and the baseband FPGA module have all completed the reset and entered the initialization completion state; the host computer sends the total number of data sampling points to be uploaded total_len to the baseband FPGA module, and sends a data storage start signal to the control FPGA module; (2) After the control FPGA module receives the signal, the synchronization signal generation module generates a synchronization signal and sends it to n baseband FPGA modules through the synchronization interface; (3) After receiving the synchronization signal, the baseband FPGA module sets the cmd signal to 0 and outputs it to the DDR4 chip. The baseband FPGA module synchronously writes the data into the first asynchronous data buffer fifo1; (4) If both ready and wdf_ready are high and the empty1 signal of fifo1k is low, pull up the en signal, the addr signal is 1, fifo1k reads the written data, and writes the second sampling point data to the DDR4 chip; if the conditions that both ready and wdf_ready are high and the empty1 signal of fifo1k is low cannot be met at the same time, pull down the en signal and wait for the next time when both ready and wdf_ready are high and the empty1 signal of fifo1k is low. Repeat (4) until the addr signal is total_len-1, and after the total_len sampling point data is written to the DDR4 chip, proceed to step (5); (5) The baseband FPGA module k sends a data_ok signal to the host computer. After receiving the data_ok signals from all n baseband FPGA modules, the host computer divides the total_len sampling point data into m segments according to the data transmission capacity of the host computer signal transmission interface; (6) The host computer sends a len signal to the baseband FPGA module 1, the read_start_addr signal is 0, and an open signal is sent; after receiving the open signal, the baseband FPGA module 1 sets the cmd signal to 1 and outputs it to the DDR4 chip; (7) After receiving the empty2 signal sent back by the baseband FPGA module 1 as low, the host computer sends the rd_en2 signal to the baseband FPGA module 1 to read back the data in fifo21. When the empty2 signal is high, the data readback of this section is completed. (8) Continue with steps (6) and (7), change the len signal sent to the baseband FPGA module to len2...lenm, and change the read_start_addr signal sent to the baseband FPGA module to len1...len(m-1); after the mth segment of data is read back, all the data that needs to be uploaded by the baseband FPGA module 1 has been completely uploaded; (9) Continue steps (6) to (8) and upload all the data of baseband FPGA modules 2 to n to the host computer.

8. The method for implementing a multi-channel large-capacity data synchronous upload process for a channel emulator according to claim 7, characterized in that: The step (3) specifically comprises the following steps: (3.1) If the ready and wdf_ready received by the baseband FPGA module k are both high and the empty1 signal of the first asynchronous data cache fifo1k is low, the en signal is pulled high, the addr signal is 0, the first asynchronous data cache fifo1k reads the written data, and writes the first sampling point data to the DDR4 chip k; If the conditions that both ready and wdf_ready are high and the empty1 signal of fifo1k is low cannot be met at the same time, pull the en signal low and wait for the next time when both ready and wdf_ready are high and the empty1 signal of fifo1k is low.

9. The method for implementing a multi-channel large-capacity data synchronous upload process for a channel emulator according to claim 7, characterized in that: The step (6) specifically comprises the following steps: When the ready signal is high and the full signal of fifo21 is low, the en signal is pulled high, the addr signal is 0, and the DDR4 chip writes the first sampling point data into fifo21, and the empty2 signal of fifo21 is pulled low and sent back to the host computer; if the conditions that the ready signal is high and the full signal of fifo21 is low cannot be met at the same time, the en signal is pulled low, and the next time when the ready is high and the full signal of fifo21 is low is met at the same time; when the ready signal is high again and the full signal of fifo21 is low, the en signal is pulled high, the addr signal is 1, and the DDR4 chip writes the second sampling point data into fifo21. Until the addr signal is len1-1, the DDR4 chip writes the len1th sampling point data into fifo21, and the DDR4 chip stops reading back and waits for the next open signal to arrive.

10. A device for realizing multi-channel large-capacity data synchronous upload processing in a channel emulator, characterized in that: The device comprises: a processor configured to execute computer executable instructions; A memory stores one or more computer executable instructions, which, when executed by the processor, implement the steps of the method for implementing a channel simulator for synchronously uploading multi-channel large-capacity data as described in any one of claims 7 to 9.

11. A processor for implementing multi-channel large-capacity data synchronous upload processing in a channel emulator, characterized in that: The processor is configured to execute computer executable instructions. When the computer executable instructions are executed by the processor, the steps of the method for implementing multi-channel large-capacity data synchronous upload processing for a channel simulator as described in any one of claims 7 to 9 are implemented.

12. A computer-readable storage medium, characterized in that: A computer program is stored thereon, and the computer program can be executed by a processor to implement the various steps of the method for implementing a channel simulator for synchronously uploading multi-channel large-capacity data as described in any one of claims 7 to 9.

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