Bus conversion method, system, device and storage medium

Abstract

The present application discloses a bus conversion method, system, device and storage medium, and relates to the technical field of bus conversion. The bus conversion method includes: sending a first device data read / write request through PCIE; converting the first device data read / write request into a second device data read / write request corresponding to the ISA through FPGA; sending the second device data read / write request to the ISA device through the ISA, so that the ISA device receives the second device data read / write request and completes the device data read / write task. The present application improves the compatibility of ISA devices and realizes the conversion from PCIE to ISA by providing a PCIE to ISA conversion solution based on FPGA.

Description

Technical Field

[0001] The present application relates to the field of bus conversion technology, and in particular to a bus conversion method, system, device and storage medium. Background Art

[0002] At present, the computer ISA (Industrial Standard Architecture) bus has developed to the PCIE (Peripheral Component Interconnect Express) bus stage, but the industrial control, national defense, power and other fields, especially the equipment in special computer systems, still widely use the ISA bus for communication. Therefore, the conversion from PCIE to ISA is of great significance to improve the compatibility of ISA devices. Summary of the invention

[0003] The main purpose of the present application is to provide a bus conversion method, system, device and storage medium, aiming to improve the compatibility of ISA devices and realize the conversion from PCIE to ISA.

[0004] To achieve the above object, the present application proposes a bus conversion method, which is applied to a bus conversion system, wherein the system includes a high-speed serial computer expansion bus PCIE, an industrial standard architecture bus ISA, a field programmable gate array FPGA and an ISA device, wherein the method includes:

[0005] Sending a first device data read / write request to FPGA via PCIE;

[0006] Converting the first device data read / write request into a second device data read / write request corresponding to the ISA through the FPGA;

[0007] The second device data read / write request is sent to the ISA device through the ISA, so that the ISA device receives the second device data read / write request and completes the device data read / write task.

[0008] In one embodiment, sending the first device data read / write request to the FPGA through the PCIE includes:

[0009] Obtain device data reading and writing requirements;

[0010] Based on the device data read and write requirements, generating the first device data read and write request;

[0011] Send the first device data read and write request to the FPGA through the PCIE.

[0012] In one embodiment, obtaining device data reading and writing requirements includes:

[0013] Get the preset read and write business logic;

[0014] Access the device nodes of the system driver;

[0015] Based on the preset read-write business logic and the device node, the device data read-write requirement is determined.

[0016] In one embodiment, converting the first device data read / write request into the second device data read / write request corresponding to the ISA through the FPGA includes:

[0017] Determine an address space mapping type based on the first device data read and write request;

[0018] Obtain the memory mapping base address and mapping range corresponding to the address space mapping type;

[0019] Based on the memory mapping base address, the mapping range and a preset data conversion function, the first device data read / write request is converted into a second device data read / write request corresponding to the ISA through the FPGA.

[0020] In one embodiment, based on the memory mapping base address, the mapping range and the preset data conversion function, converting the first device data read / write request into the second device data read / write request corresponding to the ISA through the FPGA includes:

[0021] Based on the memory mapping base address and the mapping range, mapping the first device data read and write request through the FPGA to generate a third device data read and write request;

[0022] Determine the read / write task type and data conversion type in the data read / write request of the third device;

[0023] Based on the read / write task type, the data conversion type and the preset data conversion function, the third device data read / write request is converted into a second device data read / write request corresponding to the ISA through the FPGA.

[0024] In one embodiment, before the mapping of the first device data read / write request by the FPGA based on the memory mapping base address and the mapping range to generate the third device data read / write request, the method further includes:

[0025] Get the PCIE device node information in the device tree;

[0026] Based on the PCIE device node information, space resources corresponding to the FPGA are allocated to initialize the FPGA.

[0027] In one embodiment, the ISA device receives the second device data read / write request and completes the device data read / write task, including:

[0028] Determine the data read / write type in the data read / write request of the second device;

[0029] Acquire a preset interface corresponding to the data read / write type and a device status of the ISA device; and based on the data read / write type and the device status, connect the ISA device through the preset interface to complete a device data read / write task.

[0030] In addition, to achieve the above purpose, the present application also proposes a bus conversion system, the bus conversion system comprising:

[0031] A sending unit, used for sending a first device data read and write request via PCIE;

[0032] A conversion unit, configured to convert the first device data read / write request into a second device data read / write request corresponding to the ISA through the FPGA;

[0033] The read / write unit is used to send the second device data read / write request to the ISA device through the ISA, so that the ISA device receives the second device data read / write request and completes the device data read / write task.

[0034] In addition, to achieve the above objectives, the present application also proposes a bus conversion device, which includes: a memory, a processor, and a computer program stored in the memory and executable on the processor, wherein the computer program is configured to implement the steps of the bus conversion method described above.

[0035] In addition, to achieve the above-mentioned purpose, the present application also proposes a storage medium, which is a computer-readable storage medium, and a computer program is stored on the storage medium. When the computer program is executed by a processor, the steps of the bus conversion method described above are implemented.

[0036] In addition, to achieve the above-mentioned purpose, the present application also provides a computer program product, which includes a computer program, and when the computer program is executed by a processor, the steps of the bus conversion method described above are implemented.

[0037] The present application provides a bus conversion method, system, device and storage medium. The bus conversion method sends a first device data read / write request to an FPGA through a PCIE, and then converts the first device data read / write request to a second device data read / write request corresponding to the ISA through the FPGA, so that the second device data read / write request is sent to the ISA device through the ISA, so that the ISA device receives the second device data read / write request and completes the device data read / write task, thereby realizing a PCIE to ISA solution based on the FPGA, thereby improving the compatibility of the ISA device and realizing hardware verification of the PCIE to ISA (i.e., ensuring that the hardware can work normally according to the specified performance and safety standards and has no design or manufacturing defects. In this embodiment, the successful conversion of PCIE to ISA indicates that the hardware verification is successful). BRIEF DESCRIPTION OF THE DRAWINGS

[0038] The accompanying drawings, which are incorporated in and constitute a part of this specification, illustrate embodiments consistent with the present application and, together with the description, serve to explain the principles of the present application.

[0039] In order to more clearly illustrate the embodiments of the present application or the technical solutions in the prior art, the drawings required for use in the embodiments or the description of the prior art will be briefly introduced below. Obviously, for ordinary technicians in this field, other drawings can be obtained based on these drawings without paying any creative work.

[0040] Figure 1 A flowchart of the first embodiment of the bus conversion method of the present application is provided;

[0041] Figure 2 A schematic diagram of the PCIE to ISA structure based on FPGA provided for the bus conversion method of this application;

[0042] Figure 3 A brief flowchart of the address space mapping type provided for the bus conversion method of the present application;

[0043] Figure 4 A brief flowchart of data conversion provided by the bus conversion method of the present application;

[0044] Figure 5 A brief flowchart of ISA reading data provided by the bus conversion method of the present application;

[0045] Figure 6 A brief flowchart of writing data to an ISA-specified address provided by the bus conversion method of the present application;

[0046] Figure 7An example diagram of the software layered framework for PCIE to ISA conversion provided by the bus conversion method of this application;

[0047] Figure 8 This is a schematic diagram of the unit structure of the bus conversion system according to an embodiment of the present application;

[0048] Fig. 9 Schematic diagram of the device structure of the hardware operating environment involved in the bus conversion method in the embodiment of the present application.

[0049] The purpose, features and advantages of this application will be further described in conjunction with the embodiments and with reference to the accompanying drawings. DETAILED DESCRIPTION

[0050] It should be understood that the specific embodiments described herein are only used to explain the technical solutions of the present application and are not used to limit the present application.

[0051] In order to better understand the technical solution of the present application, a detailed description will be given below in conjunction with the accompanying drawings and specific implementation methods.

[0052] It should be noted that the execution subject of this embodiment can be a computing service device with data processing, network communication and program running functions, such as a tablet computer, a personal computer, a mobile phone, etc., or an electronic device capable of realizing the above functions, a big data service platform, a bus conversion system, etc. The following takes the bus conversion system as an example to illustrate this embodiment and the following embodiments.

[0053] Based on this, the embodiment of the present application provides a bus conversion method, referring to Figure 1 , Figure 1 The flowchart of the first embodiment of the bus conversion method of the present application is provided. The method is applied to a bus conversion system, which includes a high-speed serial computer expansion bus PCIE, an industrial standard architecture bus ISA, a field programmable gate array FPGA and an ISA device.

[0054] In this embodiment, the bus conversion method includes steps S11 to S13:

[0055] Step S11, sending a first device data read / write request to FPGA via PCIE;

[0056] It should be noted that the high-speed serial computer expansion bus PCIE is a high-speed serial computer expansion bus proposed by Intel, which is an improved version of the PCI bus. It uses a point-to-point connection method to connect network cards, hard disks and other devices. These devices are called PCIE devices. The industrial standard architecture bus ISA refers to the previous generation bus of PCI, with a data bus bit number of 8 (data) / 16 (address) and a maximum transmission rate of 8MB / s, which is used to connect external IO devices, network cards, etc. The field programmable gate array FPGA uses logic devices and hardware programming languages ​​to flexibly realize customized integrated circuit requirements and is widely used in industrial control, automotive electronics, prototype verification and other fields.

[0057] It should be further explained that the ISA device refers to a device connected via an ISA (Industrial Standard Architecture) bus. The first device data read / write request refers to a read / write operation request for an ISA device issued by a computer system (or an application thereon), including a request type, a specific address on the ISA device, i.e., a memory address or I / O address of data to be read or written, data content (data value or data block to be written to the ISA device), data length, control flags and parameters, request identifier, and response return path, etc., which are not limited here.

[0058] Understandably, since the software implementation of the PCIE to ISA solution in the Linux system is developed by each manufacturer, with different programming and architecture styles, when the software implementation of the PCIE to ISA solution is applied to the Linux system, it is necessary to develop Linux software specifically, which leads to the traditional software implementation method being highly specialized, poorly reusable, and having low development efficiency and difficulty in expansion. Therefore, there is an urgent need for a PCIE to ISA implementation method based on a software layered framework under Linux, which can be used to achieve rapid prototyping of Linux software and hardware verification of PCIE to ISA. Figure 2 , Figure 2 A schematic diagram of the PCIE to ISA structure based on FPGA provided for the bus conversion method of the present application. Specifically, PCIE to ISA requires FPGA to act as a bridge so that PCIE to ISA can perform address space mapping and data conversion, so that the ISA address can be output to the ISA bus through the PCIE bus to realize the read and write operations of the ISA device.

[0059] Specifically, the device data read and write requirements are obtained, and then based on the device data read and write requirements, the first device data read and write request is generated, so as to send the first device data read and write request to the FPGA through the PCIE.

[0060] Step S12, converting the first device data read / write request into a second device data read / write request corresponding to the ISA through the FPGA;

[0061] It should be noted that the second device data read and write request refers to the read and write operation request for the ISA device after conversion by the FPGA.

[0062] Specifically, based on the first device data read and write request, the address space mapping type is determined, and then the memory mapping base address and mapping range corresponding to the address space mapping type are obtained, so that based on the memory mapping base address, the mapping range and the preset data conversion function, the first device data read and write request is converted into the second device data read and write request corresponding to the ISA through the FPGA.

[0063] Step S13: sending the second device data read / write request to the ISA device through the ISA, so that the ISA device receives the second device data read / write request and completes the device data read / write task.

[0064] It should be noted that the device data read and write task refers to a specific data read and write operation that the ISA device needs to perform, for example, performing a corresponding data read or write task, etc., which is not limited here and can be set according to actual conditions.

[0065] Specifically, the second device data read / write request is sent to the ISA device through the ISA, and then the data read / write type in the second device data read / write request is determined, so as to obtain a preset interface corresponding to the data read / write type and a device status of the ISA device, and then based on the data read / write type and the device status, the ISA device is connected through the preset interface to complete the device data read / write task.

[0066] In this embodiment, a first device data read / write request is sent to FPGA via PCIE, and then the first device data read / write request is converted into a second device data read / write request corresponding to ISA via FPGA, and then the second device data read / write request is sent to ISA device via ISA, so that the ISA device receives the second device data read / write request and completes the device data read / write task, thereby realizing a PCIE to ISA solution based on FPGA, thereby realizing PCIE to ISA conversion and hardware verification, allowing modern computer systems to communicate with old ISA devices via a high-speed PCIE bus, and expanding the compatibility and application scope of the system.

[0067] In a feasible implementation manner, sending the first device data read / write request to the FPGA through the PCIE includes:

[0068] Step S21, obtaining device data reading and writing requirements;

[0069] It should be noted that the device data reading and writing requirements refer to the specific requirements of the application or operating system in the computer system to read data from a device or write data to a device, including data type and format, data volume, address information, control commands, data integrity and verification, and interface and protocol requirements.

[0070] Specifically, the preset read-write business logic is obtained, and then the device node driven by the system is accessed, so as to determine the device data read-write demand based on the preset read-write business logic and the device node.

[0071] Step S22, generating the first device data read and write request based on the device data read and write requirement;

[0072] Specifically, the first device data read and write request is generated according to the device data read and write requirements and information such as the current timestamp, which is not limited here and can be set according to actual conditions.

[0073] Step S23: sending the first device data read and write request to the FPGA through the PCIE.

[0074] This embodiment obtains the device data read and write requirements, and then generates the first device data read and write request based on the device data read and write requirements, thereby sending the first device data read and write request to the FPGA through the PCIE, thereby realizing communication between a modern computer system using a PCIE bus and an old ISA device, solving the compatibility problem caused by different bus standards, significantly improving the efficiency of communication with ISA devices, reducing data transmission time, and simplifying software development.

[0075] In a feasible implementation manner, obtaining device data reading and writing requirements includes:

[0076] Step S31, obtaining preset read and write business logic;

[0077] It should be noted that the preset read and write business logic refers to a logic flow predefined for the ISA device, which is used to process data read and write operations, usually including the order, conditions, frequency of data reading and writing, and how to handle errors or abnormal situations that may occur during the reading and writing process.

[0078] Step S32, accessing the device node of the system driver;

[0079] It should be noted that the system driver refers to the code in the computer that drives the hardware to run normally, facilitating the interaction between the operating system and the hardware.

[0080] It is further noted that in Unix-like operating systems (such as Linux), device nodes refer to special files created for hardware devices in the system, usually located in the / dev directory. These files serve as an interface between hardware devices and user space programs, allowing programs to access hardware devices through standard file operations (such as read and write system calls). Device nodes correspond to specific hardware devices in the system, such as hard disks, network interface cards, serial ports, etc. Each device node is associated with a specific device driver, which is responsible for processing access requests to the device node and converting them into operations on the actual hardware.

[0081] Step S33: determining the device data read and write requirements based on the preset read and write business logic and the device node.

[0082] Specifically, according to the characteristics of the device node and the preset read and write business logic, the device data read and write requirements are determined, thereby customizing the requirements for operating the ISA device.

[0083] In addition, steps S31-S33 can be integrated and encapsulated into a business logic layer. The logic programmed in this layer is the same as operating a common driver in the system application layer, which is divided into opening a device node, reading ISA device content, writing data to the ISA device, and closing the device node after the operation is completed.

[0084] This embodiment obtains the preset read-write business logic and then accesses the device node driven by the system, thereby determining the device data read-write requirements based on the preset read-write business logic and the device node, and then clearly knowing which data the system (such as Linux) needs to read from the ISA device or write to the ISA device, which helps to design more accurate data read-write operations, thereby interacting with hardware devices more intelligently and efficiently, ensuring that the data read-write operations meet the expectations of the application, and improving the reliability and performance of the overall system.

[0085] In a feasible implementation manner, converting the first device data read / write request into the second device data read / write request corresponding to the ISA through the FPGA includes:

[0086] Step S41, determining the address space mapping type based on the first device data read and write request;

[0087] It should be noted that the address space mapping type refers to the type that determines how to map the address space of a device (such as the address space of an ISA device) to another address space (such as the address space of a PCIe bus). Address space mapping types generally include two methods: memory mapping and I / O mapping. Memory mapping refers to mapping the device address directly to the memory address space of the CPU, while I / O mapping refers to data exchange through specific I / O ports.

[0088] Specifically, the first device data read / write request includes the address information of the ISA device, i.e., a memory address or an I / O port address, and then the system driver or the virtual device layer checks the address to determine whether it points to the memory space or the I / O space of the ISA device. If it is a memory address, the address space mapping type will be determined as memory mapping; if it is an I / O port address, the address space mapping type will be determined as I / O mapping.

[0089] Step S42, obtaining a memory mapping base address and a mapping range corresponding to the address space mapping type;

[0090] It should be noted that the memory mapping base address refers to the starting point of the memory address space assigned to a specific device (such as an ISA device) in the memory mapping type. The base address is the calibrated position of the device in the system memory address space, which is used to identify the beginning of the device memory space. The mapping range refers to the size or length of the memory address space assigned to a specific device for use. The mapping range defines a continuous address space starting from the base address, and the device can perform data read and write operations in this address space.

[0091] Specifically, according to the address space mapping type, the memory mapping base address and mapping range corresponding to the address space mapping type are obtained. In one embodiment, the memory mapping base address and mapping range corresponding to the address space mapping type are dynamically allocated by the configuration function. For example, the memory mapping base address and I / O base address and range are written by the host to 0x19 to 0x1c and 0x1d to 0x20 of the PCI bus configuration register respectively. In this way, when reading and writing the ISA address space, only the mapped address space needs to be read and written. For reference, Figure 3 , Figure 3 A brief flowchart example of the address space mapping type provided for the bus conversion method of this application.

[0092] Step S43: Based on the memory mapping base address, the mapping range and the preset data conversion function, the first device data read / write request is converted into a second device data read / write request corresponding to the ISA through the FPGA.

[0093] It should be noted that the preset data conversion function refers to a set of predefined functions or algorithms for converting one data format or protocol to another. In the PCIe to ISA solution, the preset data conversion function is used to convert the data format on the PCIe bus to a format that the ISA bus can understand, or vice versa.

[0094] Specifically, based on the memory mapping base address and the mapping range, the first device data read and write request is mapped through the FPGA to generate a third device data read and write request, and then the read and write task type and the data conversion type in the third device data read and write request are determined, so that based on the read and write task type, the data conversion type and the preset data conversion function, the third device data read and write request is converted into a second device data read and write request corresponding to the ISA through the FPGA.

[0095] In addition, steps S41-S43 can be integrated and encapsulated into a data processing layer. The configuration function mmap_config() of the data processing layer needs to provide three input parameters, namely the address space mapping type (memory mapping or I / O mapping), the memory mapping base address, and the mapping range, which are used for mapping and data conversion from PCIE to ISA address space.

[0096] This embodiment determines the address space mapping type based on the first device data read and write request, and then obtains the memory mapping base address and mapping range corresponding to the address space mapping type, thereby converting the first device data read and write request into the second device data read and write request corresponding to the ISA through the FPGA based on the memory mapping base address, the mapping range and the preset data conversion function, thereby achieving compatibility between modern PCIe devices and old ISA devices, allowing them to work together in the same system, reducing the cost of hardware upgrades, and improving the performance of the overall system. At the same time, the programmability of the FPGA provides a high degree of flexibility, and the address mapping and data conversion logic can be easily adjusted as needed to adapt to different ISA devices and future changes in demand, thereby improving the flexibility and scalability of software implementation.

[0097] In a feasible implementation manner, based on the memory mapping base address, the mapping range and the preset data conversion function, converting the first device data read / write request into the second device data read / write request corresponding to the ISA through the FPGA includes:

[0098] Step S51, mapping the first device data read / write request through the FPGA based on the memory mapping base address and the mapping range to generate a third device data read / write request;

[0099] It should be noted that the third device data read and write request refers to the device data read and write request obtained after the FPGA maps the first device data read and write request, including the target address, data content, read and write instructions, etc., representing the mapping of PCIE to ISA address space, thereby realizing the conversion of PCIE bus to ISA bus.

[0100] Specifically, mapping can be performed through the configuration function mmap_config() of the data processing layer, and three input parameters, namely the address space mapping type (memory mapping or I / O mapping), the memory mapping base address, and the mapping range, are input into the configuration function, thereby generating a third device data read and write request to realize the mapping and data conversion from PCIE to ISA address space.

[0101] Step S52, determining the read / write task type and data conversion type in the data read / write request of the third device;

[0102] It should be noted that the read / write task type refers to the specific type or category of data read / write operations, such as memory read / write operations, I / O port operations, etc., and the data conversion type refers to the type of data format conversion that needs to be performed during the process of converting the data read / write request of the PCIe device to the data read / write request of the ISA device. The data conversion type may include data width conversion (for example, from 32 bits to 16 bits or 8 bits), byte order adjustment (for example, from big endian to little endian), and possible protocol-specific conversion (for example, adapting the PCIe transmission protocol to the ISA transmission protocol).

[0103] Step S53: based on the read / write task type, the data conversion type and the preset data conversion function, convert the third device data read / write request into a second device data read / write request corresponding to the ISA through the FPGA.

[0104] It should be noted that, since there is conversion between PCI bus data and ISA bus data, and ISA bus data only supports 16bit and 8bit, there are data conversions between 32bit and 16bit, 32bit and 8bit, 16bit and 8bit, 16bit and 16bit, and 8bit and 8bit. Therefore, in the data transmission between PCIE and ISA, the support of data conversion function is required.

[0105] Specifically, in one embodiment, the preset data conversion function includes:

[0106] PCIE32bit_ISA16bit(uint32_t*data,uint8_t data_dir);

[0107] PCIE32bit_ISA8bit(uint32_t*data,uint8_t data_dir);

[0108] PCIE16bit_ISA16bit(uint16_t*data,uint8_t data_dir);

[0109] PCIE16bit_ISA8bit(uint16_t*data,uint8_t data_dir);

[0110] PCIE8bit_ISA8bit(uint8_t*data,uint8_t data_dir);

[0111] Furthermore, the above five data conversion functions are collectively called by PCIEdata_To_ISAdata(uint32_t*data, uint8_t bit_type, uint8_t data_dir). Therefore, in the interface management layer function, the PCIEdata_To_ISAdata function is directly called to implement data conversion between PCIE and ISA. Figure 4 , Figure 4 A brief flowchart of data conversion provided for the bus conversion method of this application.

[0112] Figure 4 Specifically: First, determine the input variable bit_type type. There are 5 data conversion types, namely 32bit and 16bit, 32bit and 8bit, 16bit and 8bit, 16bit and 16bit, and 8bit and 8bit. For example, if the data conversion type is determined to be 16bit and 8bit, then the number of bits of the input parameter *data is forced to be converted to 16bit. Furthermore, call the PCIE16bit_ISA8bit() function, in which the read and write task type of data_dir is determined. If it is a write, *data is converted to the number of bits corresponding to ISA for transmission; if it is a read, the data read by ISA is converted to PCIE data and assigned to *data.

[0113] In this embodiment, based on the memory mapping base address and the mapping range, the FPGA maps the first device data read and write request to generate a third device data read and write request, and then determines the read and write task type and the data conversion type in the third device data read and write request, thereby converting the third device data read and write request into a second device data read and write request corresponding to the ISA based on the read and write task type, the data conversion type and the preset data conversion function, and then through the FPGA to implement address mapping and data conversion, modern PCIe-based systems can communicate with legacy ISA devices, solving compatibility issues between different generations of hardware. At the same time, the programmability of the FPGA allows system designers to adjust the mapping and conversion logic as needed to adapt to new ISA devices or changed business needs, providing a high degree of flexibility and scalability, thereby effectively improving development efficiency, data transmission efficiency and overall system performance.

[0114] In a feasible implementation manner, before mapping the first device data read / write request through the FPGA based on the memory mapping base address and the mapping range to generate a third device data read / write request, the method further includes:

[0115] Step S61, obtaining PCIE device node information in the device tree;

[0116] It should be noted that steps S61-S62 can be integrated and encapsulated into a virtual device layer, so as to structure the initialization of PCIE devices and facilitate the bottom-level read and write operations (operation registers) according to the content of the device tree registers. In the PCIE to ISA implementation scheme, the virtual device layer is responsible for simulating the hardware interface of the ISA device, so that the operating system can process hardware devices such as FPGA as ISA devices.

[0117] It should be further explained that the device tree refers to a data structure used to describe the configuration and layout of hardware devices in the system. It exists in the form of a tree hierarchy, where each node represents a hardware device or hardware component. The device tree is usually passed to the operating system by the firmware (such as UEFI) when the system starts up for automated hardware identification and configuration. Each node in the device tree contains detailed information about the corresponding hardware device, such as device type, address, interrupt number, memory area, etc.

[0118] Furthermore, the PCIE device node information refers to the information contained in the node associated with a specific PCIe device in the device tree, such as the type of device (such as network card, graphics card, etc.), unique identifier (such as PCI device ID and manufacturer ID), base address registers (BARs), interrupt information, DMA capabilities, etc., so as to correctly identify, configure and use PCIe devices.

[0119] Specifically, a PCIE device node is used in the device tree to describe the hardware information of the FPGA, which includes the name of the device and driver matching, ISA register (status, data, command, address register) address information, PCIE base address, address bus length, data bus length, etc.

[0120] Step S62: Allocate space resources corresponding to the FPGA based on the PCIE device node information to initialize the FPGA.

[0121] It should be noted that the space resources refer to memory space and I / O space resources.

[0122] Specifically, according to the PCIE device node information and the base address register (BAR), the kernel is requested to allocate space resources corresponding to the FPGA, thereby marking that the PCIE area in the FPGA has been allocated, and specifying the address bus length to prepare for the data processing layer to map the address space.

[0123] This embodiment obtains PCIE device node information in the device tree, and then allocates space resources corresponding to the FPGA based on the PCIE device node information to initialize the FPGA, thereby ensuring that the FPGA or other hardware devices are configured, and the address space mapping is started after the ISA register is set. In addition, a virtual communication bridge is established between the operating system and the ISA device, so that the operating system can operate the FPGA or other hardware devices connected to the PCIE bus like operating a real ISA device. This virtualization technology not only improves the compatibility of the system, but also increases the flexibility and scalability of the system.

[0124] In a feasible implementation manner, the ISA device receives the second device data read / write request and completes the device data read / write task, including:

[0125] Step S71, determining the data read / write type in the data read / write request of the second device;

[0126] Step S72, obtaining a preset interface corresponding to the data read / write type and a device status of the ISA device;

[0127] It should be noted that the preset interface refers to a set of functions or methods predefined for a specific type of device data read and write operations, such as an API interface, etc. These interfaces abstract the complexity of the underlying hardware operations, provide a set of standardized calling methods for the application program to perform data read and write tasks, and encapsulate the details of communicating with the hardware device (which can be set as an interface management layer, mainly providing an API interface to the business logic layer and implementing the specific operations of these APIs), such as sending specific commands, processing hardware registers, or executing data transmission protocols. In one embodiment, the preset interface can be used to read data of a certain address offset in the memory space of an ISA device, read data of a certain address length in the memory space of an ISA device, write data in the memory space of an ISA device, read data in the IO space of an ISA device, and write data in the IO space of an ISA device, etc., without limitation.

[0128] It should be further explained that the device status refers to the operating status of the hardware device at a certain moment, including but not limited to whether the device is ready, whether it is busy, whether there is data to be read, whether it can accept data to be written, etc.

[0129] Step S73, based on the data read / write type and the device status, connecting the ISA device through the preset interface to complete the device data read / write task.

[0130] Specifically, if the data read / write type is ISA read data, then according to the device state, the device data read / write task is completed by connecting the ISA device through the preset interface. Figure 5 , Figure 5 A brief flow chart of ISA data reading provided by the bus conversion method of the present application. That is, the application layer instruction is parsed (according to the specified API, the ISA address of the required read data is obtained), and then the ISA is judged whether it is in an idle state by reading the status register. If it is idle, it indicates that the data reading operation can be performed; otherwise, it is necessary to poll and wait for the previous operation to complete.

[0131] Furthermore, if it is idle, it indicates that the data read operation can be performed, and then the ISA address of the required read data is written into the address register, and 1 is written into the 0th bit of the command register to start the data read operation, and finally the status register is read to determine the ISA status. If the ISA is in the idle state, it indicates that the data read operation is completed, and the 8-bit ISA data is read through the read data register. Otherwise, wait for the data read operation to be completed.

[0132] In addition, if the data read / write type is ISA specified address writing data, then according to the device state, the device data read / write task is completed by connecting the ISA device through the preset interface. Figure 6 , Figure 6A brief flow chart of writing data at the ISA specified address provided by the bus conversion method of the present application. That is, parsing the call of the business logic layer: according to the specified API, obtaining the ISA address and ISA data where the write data is located, and then judging whether the ISA is in an idle state by reading the status register, when the ISA is idle, performing the operation of writing data at the specified address. Otherwise, waiting for the ISA to be idle.

[0133] Furthermore, when the ISA is idle, a write data operation is performed at the specified address, the specified ISA address is written to the address register, and the ISA data is written to the write data register. A 1 is written to the second bit of the command register to start the ISA write operation, and then it is determined whether the write data operation at the specified address is completed: the status register is read to determine whether the ISA is idle. If it is idle, it means that the write operation is completed. If it is not idle, the read status register is polled and re-determined.

[0134] This embodiment determines the data read / write type in the data read / write request of the second device, and then obtains the preset interface corresponding to the data read / write type and the device status of the ISA device, thereby completing the device data read / write task by connecting the ISA device through the preset interface based on the data read / write type and the device status, and then by using the preset interface, ensures that different ISA devices and different task read / write requests can be correctly understood and processed, thereby improving the compatibility and scalability of the system, enhancing maintainability, and improving development efficiency. At the same time, by checking the device status of the ISA device, it can be ensured that the read / write operation is performed when the device is ready, avoiding data damage or device damage.

[0135] For example, to help understand the implementation process of the bus conversion method, please refer to Figure 7 , Figure 7 An example diagram of the PCIE to ISA software layered framework provided for the bus conversion method of this application.

[0136] It can be understood that based on the above bus conversion method, a PCIE to ISA implementation method based on a software layered framework is proposed. This method follows the idea of ​​software layering and divides the software framework of PCIE to ISA under the Linux system into 4 layers, including a business logic layer, an interface management layer, a data processing layer, and a virtual device layer.

[0137] Specifically, the business logic layer is the application layer of the system, which mainly calls the access interface provided by the driver layer to the application layer, and implements the logic of operating ISA devices based on application scenarios; the interface management layer mainly encapsulates the interface for operating ISA devices, such as reading data from ISA devices, writing data to ISA devices, reading addresses of ISA devices, etc.; the data processing layer is responsible for the conversion of PCIE data and ISA data, and the mapping of address space; the virtual device layer initializes PCIE devices and implements the lowest-level register operations. Therefore, the PCIE access to ISA devices process can be completed based on the layering of the above software framework. When the driver is loaded, the ISA device can be written or read at the Linux application layer for easy operation. When replacing the FPGA-based PCIE to ISA hardware solution, you only need to make corresponding modifications according to the functions that the layer is responsible for, and you can quickly verify the hardware solution and improve the efficiency of the driver adapting to the Linux system.

[0138] In one embodiment, since the software framework adopts a layered structure, each layer is responsible for different functions (such as the business logic layer, the interface management layer, the data processing layer, and the virtual device layer), when the hardware solution is replaced, only the affected layer needs to be modified. For example, if the replaced FPGA hardware solution changes the register configuration or the interface protocol, only the virtual device layer and the data processing layer need to be modified accordingly, and the business logic layer and the interface management layer do not need to be modified. Therefore, through targeted modifications, the function and performance of the new hardware solution (i.e., hardware verification) can be quickly verified to ensure that the modified hardware solution can operate normally and meet system requirements.

[0139] Therefore, the unified software framework reduces the diversity of dedicated driver implementations, allows the code of the corresponding layer of the software to be modified as needed, and improves the flexibility of the system. In addition, through standardized interfaces, the management of the system is simplified, which provides a modular and concise software solution for PCIE to ISA.

[0140] It should be noted that the examples in the figure are only used to understand the present application and do not constitute a limitation on the bus conversion method of the present application. More forms of simple transformations based on this technical concept are all within the protection scope of the present application.

[0141] It should be understood that the order of execution of the steps in the above embodiment does not necessarily mean the order of execution. The execution order of each process should be determined by its function and internal logic, and should not constitute any limitation on the implementation process of the embodiment of the present invention.

[0142] This application also provides a bus conversion system, please refer to Figure 8 , the bus conversion system comprises:

[0143] A sending unit 81, configured to send a first device data read / write request via PCIE;

[0144] A conversion unit 82, configured to convert the first device data read / write request into a second device data read / write request corresponding to the ISA through the FPGA;

[0145] The read / write unit 83 is used to send the second device data read / write request to the ISA device through the ISA, so that the ISA device receives the second device data read / write request and completes the device data read / write task.

[0146] The bus conversion system is also used for:

[0147] Obtain device data reading and writing requirements;

[0148] Based on the device data read and write requirements, generating the first device data read and write request;

[0149] Send the first device data read and write request to the FPGA through the PCIE.

[0150] The bus conversion system is also used for:

[0151] Get the preset read and write business logic;

[0152] Access the device nodes of the system driver;

[0153] Based on the preset read-write business logic and the device node, the device data read-write requirement is determined.

[0154] The bus conversion system is also used for:

[0155] Determine an address space mapping type based on the first device data read and write request;

[0156] Obtain the memory mapping base address and mapping range corresponding to the address space mapping type;

[0157] Based on the memory mapping base address, the mapping range and a preset data conversion function, the first device data read / write request is converted into a second device data read / write request corresponding to the ISA through the FPGA.

[0158] The bus conversion system is also used for:

[0159] Based on the memory mapping base address and the mapping range, mapping the first device data read and write request through the FPGA to generate a third device data read and write request;

[0160] Determine the read / write task type and data conversion type in the data read / write request of the third device;

[0161] Based on the read / write task type, the data conversion type and the preset data conversion function, the third device data read / write request is converted into a second device data read / write request corresponding to the ISA through the FPGA.

[0162] The bus conversion system is also used for:

[0163] Get the PCIE device node information in the device tree;

[0164] Based on the PCIE device node information, space resources corresponding to the FPGA are allocated to initialize the FPGA.

[0165] The bus conversion system is also used for:

[0166] Determine the data read / write type in the data read / write request of the second device;

[0167] Acquire a preset interface corresponding to the data read / write type and a device status of the ISA device;

[0168] Based on the data read / write type and the device status, the device data read / write task is completed by connecting the ISA device through the preset interface.

[0169] The bus conversion system provided by the present application adopts the bus conversion method in the above embodiment, which can solve the technical problems in the background technology. Compared with the prior art, the beneficial effects of the bus conversion system provided by the present application are the same as the beneficial effects of the bus conversion method provided by the above embodiment, and other technical features of the bus conversion system are the same as the features disclosed in the above embodiment method, which will not be repeated here.

[0170] The present application provides a bus conversion device, which includes: at least one processor; and a memory that is communicatively connected to the at least one processor; wherein the memory stores instructions that can be executed by the at least one processor, and the instructions are executed by the at least one processor so that the at least one processor can execute the bus conversion method in the above-mentioned embodiment one.

[0171] Reference below Fig. 9, which shows a schematic diagram of the structure of a bus conversion device suitable for implementing an embodiment of the present application. The bus conversion device in the embodiment of the present application may include but is not limited to mobile terminals such as mobile phones, laptop computers, digital broadcast receivers, PDAs (Personal Digital Assistants), PADs (Portable Application Descriptions), PMPs (Portable Media Players), vehicle-mounted terminals (such as vehicle-mounted navigation terminals), etc., and fixed terminals such as digital TVs, desktop computers, etc. Fig. 9 The bus conversion device shown is merely an example and should not bring any limitation to the functions and scope of use of the embodiments of the present application.

[0172] like Fig. 9 As shown, the bus conversion device may include a processing device 1001 (e.g., a central processing unit, a graphics processor, etc.), which can perform various appropriate actions and processes according to a program stored in a read-only memory (ROM: Read Only Memory) 1002 or a program loaded from a storage device 1003 to a random access memory (RAM: Random Access Memory) 1004. In RAM1004, various programs and data required for the operation of the bus conversion device are also stored. The processing device 1001, ROM1002, and RAM1004 are connected to each other through a bus 1005. An input / output (I / O) interface 1006 is also connected to the bus. Generally, the following systems can be connected to the I / O interface 1006: an input device 1007 including, for example, a touch screen, a touch pad, a keyboard, a mouse, an image sensor, a microphone, an accelerometer, a gyroscope, etc.; an output device 1008 including, for example, a liquid crystal display (LCD: Liquid Crystal Display), a speaker, a vibrator, etc.; a storage device 1003 including, for example, a magnetic tape, a hard disk, etc.; and a communication device 1009. The communication device 1009 can allow the bus conversion device to communicate with other devices wirelessly or by wire to exchange data. Although the bus conversion device with various systems is shown in the figure, it should be understood that it is not required to implement or have all the systems shown. More or fewer systems can be implemented or have alternatively.

[0173] In particular, according to the embodiments disclosed in the present application, the process described above with reference to the flowchart can be implemented as a computer software program. For example, the embodiments disclosed in the present application include a computer program product, which includes a computer program carried on a computer-readable medium, and the computer program includes a program code for executing the method shown in the flowchart. In such an embodiment, the computer program can be downloaded and installed from a network through a communication device, or installed from a storage device 1003, or installed from a ROM 1002. When the computer program is executed by the processing device 1001, the above-mentioned functions defined in the method of the embodiment disclosed in the present application are executed.

[0174] The bus conversion device provided by the present application adopts the bus conversion method in the above embodiment, which can solve the technical problems in the background technology. Compared with the prior art, the beneficial effects of the bus conversion device provided by the present application are the same as the beneficial effects of the bus conversion method provided by the above embodiment, and other technical features in the bus conversion device are the same as the features disclosed in the method of the previous embodiment, which will not be repeated here.

[0175] It should be understood that the various parts disclosed in this application can be implemented by hardware, software, firmware or a combination thereof. In the description of the above embodiments, specific features, structures, materials or characteristics can be combined in any one or more embodiments or examples in a suitable manner.

[0176] The above is only a specific implementation of the present application, but the protection scope of the present application is not limited thereto. Any person skilled in the art who is familiar with the present technical field can easily think of changes or substitutions within the technical scope disclosed in the present application, which should be included in the protection scope of the present application. Therefore, the protection scope of the present application should be based on the protection scope of the claims.

[0177] The present application provides a computer-readable storage medium having computer-readable program instructions (ie, computer programs) stored thereon, and the computer-readable program instructions are used to execute the bus conversion method in the above-mentioned embodiment.

[0178] The computer-readable storage medium provided in the present application may be, for example, a USB flash drive, but is not limited to electrical, magnetic, optical, electromagnetic, infrared, or semiconductor systems, systems or devices, or any combination of the above. More specific examples of computer-readable storage media may include, but are not limited to: an electrical connection with one or more wires, a portable computer disk, a hard disk, a random access memory (RAM), a read-only memory (ROM), an erasable programmable read-only memory (EPROM or flash memory), an optical fiber, a portable compact disk read-only memory (CD-ROM), an optical storage device, a magnetic storage device, or any suitable combination of the above. In this embodiment, the computer-readable storage medium may be any tangible medium containing or storing a program that can be used by or in combination with an instruction execution system, system or device. The program code contained on the computer-readable storage medium may be transmitted using any appropriate medium, including but not limited to: wires, optical cables, RF (Radio Frequency), etc., or any suitable combination of the above.

[0179] The computer-readable storage medium may be included in the bus conversion device; or may exist independently without being assembled into the bus conversion device.

[0180] The computer-readable storage medium carries one or more programs. When the one or more programs are executed by the bus conversion device, the bus conversion device:

[0181] Sending a first device data read / write request to FPGA via PCIE;

[0182] Converting the first device data read / write request into a second device data read / write request corresponding to the ISA through the FPGA;

[0183] The second device data read / write request is sent to the ISA device through the ISA, so that the ISA device receives the second device data read / write request and completes the device data read / write task.

[0184] Computer program code for performing the operations of the present application may be written in one or more programming languages ​​or a combination thereof, including object-oriented programming languages ​​such as Java, Smalltalk, C++, and conventional procedural programming languages ​​such as "C" or similar programming languages. The program code may be executed entirely on the user's computer, partially on the user's computer, as a separate software package, partially on the user's computer and partially on a remote computer, or entirely on a remote computer or server. In the case of a remote computer, the remote computer may be connected to the user's computer through any type of network, including a local area network (LAN) or a wide area network (WAN), or may be connected to an external computer (e.g., via the Internet using an Internet service provider).

[0185] The flow chart and block diagram in the accompanying drawings illustrate the possible architecture, function and operation of the system, method and computer program product according to various embodiments of the present application. In this regard, each square box in the flow chart or block diagram can represent a module, a program segment or a part of a code, and the module, the program segment or a part of the code contains one or more executable instructions for realizing the specified logical function. It should also be noted that in some alternative implementations, the functions marked in the square box can also occur in a sequence different from that marked in the accompanying drawings. For example, two square boxes represented in succession can actually be executed substantially in parallel, and they can sometimes be executed in the opposite order, depending on the functions involved. It should also be noted that each square box in the block diagram and / or flow chart, and the combination of the square boxes in the block diagram and / or flow chart can be implemented with a dedicated hardware-based system that performs a specified function or operation, or can be implemented with a combination of dedicated hardware and computer instructions.

[0186] The modules involved in the embodiments described in this application may be implemented by software or hardware, wherein the name of the module does not constitute a limitation on the unit itself in some cases.

[0187] The readable storage medium provided by the present application is a computer-readable storage medium, which stores computer-readable program instructions (i.e., computer programs) for executing the above-mentioned bus conversion method, and can solve the technical problems in the background technology. Compared with the prior art, the beneficial effects of the computer-readable storage medium provided by the present application are the same as the beneficial effects of the bus conversion method provided by the above-mentioned embodiment, and will not be repeated here.

[0188] An embodiment of the present application provides a computer program product, including a computer program, which implements the steps of the above-mentioned bus conversion method when executed by a processor.

[0189] The computer program product provided in this application can solve the technical problems in the background technology. Compared with the prior art, the beneficial effects of the computer program product provided in the embodiment of this application are the same as the beneficial effects of the bus conversion method provided in the above embodiment, which will not be repeated here.

[0190] The above descriptions are only some embodiments of the present application, and are not intended to limit the patent scope of the present application. All equivalent structural changes made using the contents of the present application specification and drawings under the technical concept of the present application, or direct / indirect applications in other related technical fields are included in the patent protection scope of the present application.

Claims

1. A bus conversion method, characterized in that: Applicable to a bus conversion system, the system includes a high-speed serial computer expansion bus PCIE, an industrial standard architecture bus ISA, a field programmable gate array FPGA and an ISA device, including: Sending a first device data read / write request to FPGA via PCIE; Converting the first device data read / write request into a second device data read / write request corresponding to the ISA through the FPGA; The second device data read / write request is sent to the ISA device through the ISA, so that the ISA device receives the second device data read / write request and completes the device data read / write task.

2. The bus conversion method according to claim 1, characterized in that: The sending of the first device data read / write request to the FPGA through the PCIE includes: Obtain device data reading and writing requirements; Based on the device data read and write requirements, generating the first device data read and write request; Send the first device data read and write request to the FPGA through the PCIE.

3. The bus conversion method according to claim 2, characterized in that: The obtaining of device data reading and writing requirements includes: Get the preset read and write business logic; Access the device nodes of the system driver; Based on the preset read-write business logic and the device node, the device data read-write requirement is determined.

4. The bus conversion method according to claim 1, characterized in that: The converting the first device data read / write request into the second device data read / write request corresponding to the ISA through the FPGA includes: Determine an address space mapping type based on the first device data read and write request; Obtain the memory mapping base address and mapping range corresponding to the address space mapping type; Based on the memory mapping base address, the mapping range and a preset data conversion function, the first device data read / write request is converted into a second device data read / write request corresponding to the ISA through the FPGA.

5. The bus conversion method according to claim 4, characterized in that: The converting the first device data read / write request into the second device data read / write request corresponding to the ISA through the FPGA based on the memory mapping base address, the mapping range and the preset data conversion function includes: Based on the memory mapping base address and the mapping range, mapping the first device data read and write request through the FPGA to generate a third device data read and write request; Determine the read / write task type and data conversion type in the data read / write request of the third device; Based on the read / write task type, the data conversion type and the preset data conversion function, the third device data read / write request is converted into a second device data read / write request corresponding to the ISA through the FPGA.

6. The bus conversion method according to claim 5, characterized in that: Before mapping the first device data read / write request through the FPGA based on the memory mapping base address and the mapping range to generate a third device data read / write request, the method further includes: Get the PCIE device node information in the device tree; Based on the PCIE device node information, space resources corresponding to the FPGA are allocated to initialize the FPGA.

7. The bus conversion method according to claim 1, characterized in that: The ISA device receives the second device data read / write request and completes the device data read / write task, including: Determine the data read / write type in the data read / write request of the second device; Acquire a preset interface corresponding to the data read / write type and a device status of the ISA device; Based on the data read / write type and the device status, the device data read / write task is completed by connecting the ISA device through the preset interface.

8. A bus conversion system, characterized in that: include: A sending unit, used for sending a first device data read and write request via PCIE; A conversion unit, configured to convert the first device data read / write request into a second device data read / write request corresponding to the ISA through the FPGA; The read / write unit is used to send the second device data read / write request to the ISA device through the ISA, so that the ISA device receives the second device data read / write request and completes the device data read / write task.

9. A bus conversion device, characterized in that: The bus conversion device comprises: a memory, a processor, and a computer program stored in the memory and executable on the processor, wherein the computer program is configured to implement the steps of the bus conversion method according to any one of claims 1 to 7.

10. A storage medium, characterized in that: The storage medium is a computer-readable storage medium, and a computer program is stored on the storage medium. When the computer program is executed by a processor, the steps of the bus conversion method according to any one of claims 1 to 7 are implemented.

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