An interface switching device and method based on NAND FLASH SCA protocol
By designing an interface adapter based on the NAND FLASH SCA protocol, the SCA protocol is converted to traditional timing, which solves the problem of unintuitive waveforms and difficulty in maintaining the verification platform under the SCA protocol, and the compatibility between SCA and traditional timing is achieved, and verification efficiency and designer work efficiency are improved.
Patent Information
- Application Number
- CN202411945647.1
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2024-12-27
- Publication Date
- 2025-04-01
AI Technical Summary
The parallel transmission of commands/addresses/data of CA bus and data of DQ bus under the SCA protocol leads to unintuitive waveforms. Designers and verification personnel need to spend energy to convert them into familiar traditional timings. The existing verification platform analyzes and checks based on the traditional time-sharing multiplexing form, which leads to the time-consuming and labor-intensive analysis and inspection of SCA protocol, and requires maintenance of two sets of inspection mechanisms.
Design an interface adapter based on the NAND FLASH SCA protocol, including the SCA judgment module, the SCA header collection module, the SCA header judgment module, the DQ bus processing is a traditional timing module and the CA bus processing is a traditional timing module. Through these modules, the SCA protocol is converted into a traditional timing and output to the traditional command/address/data interface and the traditional data interface.
It solves the problem of unintuitive waveforms under the SCA protocol, avoids the laboriousness when adding SCA resolution mechanism, realizes compatibility between SCA timing and traditional timing, simplifies the maintenance of the verification platform, improves verification efficiency and designers' waveform viewing and problem positioning speed.
Smart Images
Figure CN119739659A_ABST
Abstract
Description
Technical Field
[0001] The present invention relates to the field of memory, and in particular to an interface switching device and method based on a NAND FLASH SCA protocol. Background Art
[0002] With the development of memory technology, NAND FLASH memory has been widely used in various electronic products. As the NAND IO data transmission speed increases, the IO efficiency becomes worse because the command / address transmission time has not been improved accordingly. And the worse IO efficiency will affect the storage performance. Therefore, the SCA (Separate Command Address) protocol was proposed. SCA is a protocol that can be used to improve the efficiency of the NAND interface. It can perform command input during data input / output by changing the function of traditional pins and separating the command / address bus (CA bus) from the data bus (DQ bus), reducing the command overhead of traditional methods and improving data input / output efficiency.
[0003] However, although the SCA protocol improves NAND IO efficiency, the command / address transmitted by the CA bus in bit format is not intuitive in the waveform. When designers and verifiers view the waveform of the SCA protocol, they need to spend time converting it into the familiar traditional timing before locating the problem. The command / address / data of the CA bus and the data of the DQ bus under the SCA protocol can be parallel, but the command / address / data of the traditional method cannot be parallel. However, the existing verification platform is based on the analysis and inspection of the traditional command / address / data time-division multiplexing transmission format, and it is time-consuming and labor-intensive to parse and inspect the SCA protocol separately. In addition, the two sets of inspections using the traditional method and the SCA method have some commonalities. When modifications are required, both sets of inspections may need to be maintained. Summary of the invention
[0004] In view of the defects of the prior art, the present invention provides an interface adapter device and method based on the NAND FLASH SCA protocol, which inputs a group of NAND FLASH interfaces and outputs two groups of traditional interface timings. By converting the SCA protocol into the traditional timing, the problem of the unintuitive waveform under the SCA protocol is solved, and the problem of the need to add the SCA parsing mechanism, which is laborious and time-consuming, is avoided.
[0005] In order to solve the technical problem, the technical solution adopted by the present invention is: an interface switching transposition based on the NAND FLASH SCA protocol, comprising: The SCA judgment module has an input end connected to the NAND FLASH interface input. The timing of the NAND FLASH interface input includes the traditional command / address / data time-division multiplexing transmission form and the SCA protocol. The SCA judgment module is used to judge whether the timing of the NAND FLASH interface input uses the SCA protocol or the traditional command / address / data time-division multiplexing transmission form; An SCA header collection module, whose input end is connected to the SCA judgment module, is used to collect the SCA timing inputted by the NAND FLASH interface as the SCA header when the SCA judgment module judges that the timing inputted by the NAND FLASH interface uses the SCA protocol; The SCA header judgment module, whose input end is connected to the SCA header collection module, is used to judge whether the collected SCA header meets the set conditions; The DQ bus is processed as a traditional timing module, and the input end is connected to the SCA header judgment module. It is used to convert the command / address / data of the SCA timing received by the CA bus in the NAND FLASH input interface into the traditional timing and output it to the traditional command / address / data interface when the collected SCA header meets the set conditions; The CA bus is processed as a traditional timing module, and the input end is connected to the SCA header judgment module. It is used to convert the SCA timing data received by the DQ bus in the NAND FLASH input interface into the traditional timing and output it to the traditional data interface when the collected SCA header does not meet the set conditions; A traditional command / address / data collection module, whose input end is connected to the SCA judgment module, is used to collect the traditional timing in the NAND FLASH interface input as the command / address / data currently being transmitted when the SCA judgment module determines that the timing of the NAND FLASH interface input uses the traditional command / address / data time-division multiplexing transmission form; The CA bus / DQ bus judgment module has an input end connected to the traditional command / address / data collection module and is used to judge whether the command / address / data currently being transmitted is via the CA bus or the DQ bus in the SCA protocol. If the CA bus is used, the data is output to the traditional command / address / data interface; if the DQ bus is used, the data is output to the traditional data interface.
[0006] Furthermore, the device is added to a NAND FLASH verification platform, and the SCA judgment module is connected to the NAND FLASH interface input of the NAND FLASH verification platform.
[0007] Furthermore, the SCA judgment module judges the timing of the NAND FLASH interface input based on whether the SCA enable pin sca_en of the NAND FLASH is pulled high. If the SCA enable pin sca_en is pulled high, the timing of the NAND FLASH interface input is the SCA protocol. If the SCA enable pin sca_en is not pulled high, the timing of the NAND FLASH interface input is the traditional command / address / data time-division multiplexing transmission form.
[0008] Furthermore, the SCA header collection module collects the SCA timing input by the NAND FLASH interface as the SCA header process: each time when the write enable pin WE_n of the NAND FLASH starts to vibrate, the values of ALE and CLE during the first two vibrations are collected as the SCA header.
[0009] Furthermore, the SCA header determination module determines whether the collected SCA header meets the set condition by determining whether the SCA header composed of the values of ALE and CLE is SCE, where SCE is a fixed value.
[0010] The present invention also discloses an interface switching method based on the NAND FLASH SCA protocol, comprising the following steps: S01, input NAND FLASH interface, determine the timing of input NAND FLASH interface, if the timing is SCA timing, execute steps S02, S03, S04, S05, if the timing is the traditional command / address / data time-division multiplexing transmission form, execute steps S06, S07; S02, collect the SCA timing of the NAND FLASH interface as an SCA header; S03, determine whether the SCA header is SCE, if so, proceed to step S04, if not, proceed to step S05; S04. According to the type of the SCA header, the command / address / data of the SCA sequence subsequently received through the CA bus of the NAND FLASH interface is converted into the traditional sequence, and output to the traditional command / address / data interface; S05, converting the SCA timing data received by the SCE through the DQ bus of the NAND FLASH interface into the traditional timing data, and outputting it to the traditional data interface; S06, collecting the traditional timing of the NAND FLASH interface input as the command / address / data currently being transmitted; S07. Determine whether the traditional command / address / data currently being transmitted should go through the CA bus or the DQ bus in the SCA protocol. If it goes through the CA bus, output the command / address / data currently being transmitted to the traditional command / address / data interface; if it goes through the DQ bus, output the data currently being transmitted to the traditional data interface.
[0011] Furthermore, steps S04 and S05 are executed in parallel.
[0012] Furthermore, in step S01, the timing of the NAND FLASH interface input is determined by whether the SCA enable pin sca_en of the NAND FLASH is pulled high. If the SCA enable pin sca_en is pulled high, the timing of the NAND FLASH interface input is the SCA protocol. If the SCA enable pin sca_en is not pulled high, the timing of the NAND FLASH interface input is the traditional command / address / data time-division multiplexing transmission form.
[0013] Furthermore, in step S02, the SCA timing of the NAND FLASH interface is collected as an SCA header. Specifically, each time the write enable pin WE_n of the NAND FLASH starts to vibrate, the values of ALE and CLE during the first two vibrations are collected as the SCAheader.
[0014] Furthermore, in step S04, the types of the SCA header include data output, data input, address input, and command input.
[0015] Beneficial effects of the present invention: The present invention converts the SCA protocol into a traditional timing, thereby solving the problem of the waveform being non-intuitive under the SCA protocol and avoiding the need to add an SCA parsing mechanism, which is laborious and time-consuming. At the same time, the two sets of output interfaces also solve the problem of incompatibility between the SCA timing (parallel) and the existing traditional timing (serial) on the existing platform. The present invention facilitates compatibility on the existing platform, speeds up the verification process, and facilitates the verification and design personnel to view the waveform and locate the problem. BRIEF DESCRIPTION OF THE DRAWINGS
[0016] Figure 1 This is a functional block diagram of the device described in Example 1; Figure 2 This is a flow chart of the method described in Example 2. DETAILED DESCRIPTION
[0017] The present invention will be further described below in conjunction with the accompanying drawings and specific embodiments. First, the English expressions appearing in the present invention are explained: SCA (Separate Command Address) protocol: separate command address protocol.
[0018] CA bus: command / address bus.
[0019] DQ bus: data bus.
[0020] SCA header: SCA header. The SCA protocol defines multiple SCA headers to distinguish different CA bus input data packet types.
[0021] ALE: Address latch enable signal.
[0022] CLE: Command latch enable signal.
[0023] SCE (Selected Chip Enable): Selected chip enable, an SCA header defined in the SCA protocol, used to start or resume data bursts on the DQ bus.
[0024] sca_en: SCA enable pin.
[0025] WE_n: write enable pin.
[0026] In the present invention, the tradition refers to the existing transmission form of time-division multiplexing of commands / addresses / data.
[0027] Example 1 This embodiment discloses an interface adapter device based on the NAND FLASH SCA protocol, such as Figure 1 As shown, including: The SCA judgment module, the input end is connected to the NAND FLASH interface input, the timing of the NAND FLASH interface input includes the traditional command / address / data time-sharing multiplexing transmission form and the SCA protocol, and the SCA judgment module is used to judge whether the timing of the NAND FLASH interface input uses the SCA protocol or the traditional command / address / data time-sharing multiplexing transmission form. In this embodiment, the SCA judgment module judges the timing of the NAND FLASH interface input based on whether the SCA enable pin sca_en of the NAND FLASH is pulled high. If the SCA enable pin sca_en is pulled high, the timing of the NAND FLASH interface input is the SCA protocol. If the SCA enable pin sca_en is not pulled high, the timing of the NAND FLASH interface input is the traditional command / address / data time-sharing multiplexing transmission form.
[0028] The SCA header collection module, whose input end is connected to the SCA judgment module, is used to collect the SCA timing of the NAND FLASH interface input as the SCA header when the SCA judgment module determines that the timing of the NAND FLASH interface input uses the SCA protocol. In this embodiment, the SCA header collection module collects the SCA timing of the NAND FLASH interface input as the SCA header process: each time when the write enable pin WE_n of the NAND FLASH starts to vibrate, the values of ALE and CLE during the first two vibrations are collected as the SCA header.
[0029] The SCA header judgment module, whose input end is connected to the SCA header collection module, is used to judge whether the collected SCA header meets the set conditions. In this embodiment, the set conditions are: whether the SCA header composed of the values of ALE and CLE is SCE, SCE is a fixed value 1101, if the values of ALE and CLE collected by the first vibration are 11, and the values of ALE and CLE collected by the second vibration are 01, then the ALE and CLE values collected by the two vibrations are combined into 1101, which meets the set conditions. If the ALE and CLE values collected by the two vibrations are other situations, the set conditions are not met.
[0030] The DQ bus is processed as a traditional timing module, and its input end is connected to the SCA header judgment module. It is used to convert the SCA timing command / address / data received by the CA bus in the NAND FLASH input interface into traditional timing when the collected SCA header meets the set conditions, and output it to the traditional command / address / data interface.
[0031] The CA bus is processed as a traditional timing module, and its input end is connected to the SCA header judgment module. It is used to convert the SCA timing data received by the DQ bus in the NAND FLASH input interface into traditional timing and output it to the traditional data interface when the collected SCA header does not meet the set conditions.
[0032] The traditional command / address / data collection module has an input end connected to the SCA judgment module, and is used to collect the traditional timing in the NAND FLASH interface input as the command / address / data currently being transmitted when the SCA judgment module determines that the timing of the NAND FLASH interface input uses the traditional command / address / data time-division multiplexing transmission form.
[0033] The CA bus / DQ bus judgment module has an input end connected to the traditional command / address / data collection module and is used to judge whether the command / address / data currently being transmitted is via the CA bus or the DQ bus in the SCA protocol. If the CA bus is used, the data is output to the traditional command / address / data interface; if the DQ bus is used, the data is output to the traditional data interface.
[0034] When the NAND FLASH interface input by this device uses the traditional command / address / data time-division multiplexing transmission form, although this module outputs 2 sets of traditional interface timings, namely the traditional timings of command / address / data using CA bus under SCA protocol, and the traditional timings of data using DQ bus under SCA protocol, these two sets of interfaces will not perform timing transmission in parallel, that is, when one set of interfaces moves, the other set of interfaces will not move.
[0035] When the module inputs the NAND FLASH interface using the timing of the SCA protocol, the output of the two groups of traditional interface timing can achieve two groups of parallel transmission, that is, the two groups of interfaces can be activated at the same time. Because SCA header collection and SCA header judgment are both ongoing, multiple SCA headers can be collected, and after judging one SCA header, the next SCA header can be judged. When the output of the traditional command / address / data interface brought by the judgment of one SCA header is not completed, the other SCA header is judged to be output according to the traditional data interface. At this time, both the traditional command / address / data interface and the traditional data interface work and transmit in parallel.
[0036] This device is added to the existing NAND FLASH verification platform, and the SCA judgment module is connected to the NAND FLASH interface input of the NAND FLASH verification platform. The analysis of its interface is still the same as the traditional method, but it is changed from one group of interfaces to two groups of interfaces, which not only solves the problem of unintuitive waveform under the SCA protocol, but also avoids the problem of adding the SCA analysis mechanism, which is laborious and time-consuming.
[0037] The existing verification platform monitors a set of serial interface timings of the traditional method for processing. When verifying the functions under the SCA protocol, since the SCA interface timing can be parallel, the verification platform must monitor two groups of interfaces for processing. If this module is not loaded into the verification platform, two sets of verification environments must be maintained, one for the traditional set of interfaces and one for the SCA two sets of interfaces. When adding this module to the existing verification platform, you only need to maintain an environment with two sets of interfaces and monitor two sets of output interfaces in parallel, except that the two sets of interfaces will not move at the same time for the traditional method. That is, this module also solves the problem of incompatibility between SCA timing (parallel) and existing traditional timing (serial) through two sets of output interfaces, avoiding the waste of manpower to maintain two sets of verification environments.
[0038] This embodiment provides an interface adapter device based on the NAND FLASH SCA protocol, which is convenient for rapid compatibility on existing platforms, effectively speeds up the research and development progress of verifying SCA protocol related functions, effectively speeds up the speed of waveform viewing and problem location for verification and design personnel, improves test efficiency and reduces costs.
[0039] Example 2 This embodiment discloses an interface switching method based on the NAND FLASH SCA protocol, such as Figure 1 The method comprises the following steps: S01, input NAND FLASH interface, determine the timing of inputting NAND FLASH interface, if the timing is SCA timing, execute steps S02, S03, S04, S05, if the timing is the traditional command / address / data time-division multiplexing transmission form, execute steps S06, S07. In this embodiment, the timing of inputting NAND FLASH interface is determined by whether the SCA enable pin sca_en of NAND FLASH is pulled high, if the SCA enable pin sca_en is pulled high, the timing of inputting NAND FLASH interface is SCA protocol, if the SCA enable pin sca_en is not pulled high, the timing of inputting NAND FLASH interface is the traditional command / address / data time-division multiplexing transmission form.
[0040] S02. Collect the SCA timing of the NAND FLASH interface as an SCA header. Specifically, each time the write enable pin WE_n of the NAND FLASH starts to vibrate, collect the values of ALE and CLE during the first two vibrations as an SCA header.
[0041] S03. Determine whether the SCA header is SCE. If so, proceed to step S04. If not, proceed to step S05.
[0042] S04. According to the type of the SCA header, the command / address / data of the SCA sequence subsequently received through the CA bus of the NAND FLASH interface is converted into a traditional sequence, and output to the traditional command / address / data interface.
[0043] S05, converting the SCA timing data received by the SCE through the DQ bus of the NAND FLASH interface into the traditional timing data, and outputting it to the traditional data interface.
[0044] S06. The NAND FLASH interface inputs the traditional timing collection as the command / address / data currently being transmitted.
[0045] S07. Determine whether the traditional command / address / data currently being transmitted should go through the CA bus or the DQ bus in the SCA protocol. If it goes through the CA bus, output the command / address / data currently being transmitted to the traditional command / address / data interface; if it goes through the DQ bus, output the data currently being transmitted to the traditional data interface.
[0046] In this embodiment, step S02 is continuously performed to collect multiple SCA headers, and step S03 is continuously performed. After judging one SCA header, another SCA header is judged. When the traditional command / address / data interface output brought about by the judgment of one SCA header is not completed, the other SCA header is judged to output according to the traditional data interface. At this time, both the traditional command / address / data interface and the traditional data interface work, that is, steps S04 and S05 are run in parallel.
[0047] In step S04, the types of SCA header include data output, data input, address input, and command input.
[0048] The above description is only the basic principle and preferred embodiments of the present invention. Improvements and substitutions made by those skilled in the art based on the present invention belong to the protection scope of the present invention.
Claims
1. An interface transfer transposition based on NAND FLASH SCA protocol, characterized by: including: The SCA judgment module has an input end connected to the NAND FLASH interface input. The timing of the NAND FLASH interface input includes the traditional command / address / data time-division multiplexing transmission form and the SCA protocol. The SCA judgment module is used to judge whether the timing of the NAND FLASH interface input uses the SCA protocol or the traditional command / address / data time-division multiplexing transmission form; The SCA header collection module, whose input end is connected to the SCA judgment module, is used to collect the SCA timing input by the NAND FLASH interface as the SCAheader when the SCA judgment module determines that the timing input by the NAND FLASH interface uses the SCA protocol; The SCA header judgment module, whose input end is connected to the SCA header collection module, is used to judge whether the collected SCA header meets the set conditions; The DQ bus is processed as a traditional timing module, and the input end is connected to the SCA header judgment module. It is used to convert the SCA timing command / address / data received by the CA bus in the NAND FLASH input interface into the traditional timing and output it to the traditional command / address / data interface when the collected SCA header meets the set conditions; The CA bus is processed as a traditional timing module, and the input end is connected to the SCA header judgment module. It is used to convert the SCA timing data received by the DQ bus in the NAND FLASH input interface into the traditional timing and output it to the traditional data interface when the collected SCA header does not meet the set conditions; A traditional command / address / data collection module, whose input end is connected to the SCA judgment module, is used to collect the traditional timing in the NAND FLASH interface input as the command / address / data currently being transmitted when the SCA judgment module determines that the timing of the NAND FLASH interface input uses the traditional command / address / data time-division multiplexing transmission form; The CA bus / DQ bus judgment module has an input end connected to the traditional command / address / data collection module and is used to judge whether the command / address / data currently being transmitted is via the CA bus or the DQ bus in the SCA protocol. If the CA bus is used, the data is output to the traditional command / address / data interface; if the DQ bus is used, the data is output to the traditional data interface.
2. The interface adapter based on the NAND FLASH SCA protocol according to claim 1, characterized in that: The device is added to the NAND FLASH verification platform, and the SCA judgment module is connected to the NAND FLASH interface input of the NAND FLASH verification platform.
3. The interface adapter based on NAND FLASH SCA protocol according to claim 1, characterized in that: The SCA judgment module judges the timing of the NAND FLASH interface input based on whether the SCA enable pin sca_en of the NAND FLASH is pulled high. If the SCA enable pin sca_en is pulled high, the timing of the NAND FLASH interface input is the SCA protocol. If the SCA enable pin sca_en is not pulled high, the timing of the NAND FLASH interface input is the traditional command / address / data time-sharing multiplexing transmission form.
4. The interface adapter device based on the NAND FLASH SCA protocol according to claim 1, characterized in that: The SCAheader collection module collects the SCA timing input from the NAND FLASH interface as the SCA header. The process is as follows: each time the write enable pin WE_n of the NAND FLASH starts to vibrate, the values of ALE and CLE during the first two vibrations are collected as the SCA header.
5. The interface adapter device based on NAND FLASH SCA protocol according to claim 4, characterized in that: The SCAheader judgment module judges whether the collected SCA header meets the set conditions: judge whether the SCA header composed of the values of ALE and CLE is SCE, which is a fixed value.
6. An interface switching method based on NAND FLASH SCA protocol, characterized in that: The following steps are involved: S01, input NAND FLASH interface, determine the timing of input NAND FLASH interface, if the timing is SCA timing, execute steps S02, S03, S04, S05, if the timing is the traditional command / address / data time-division multiplexing transmission form, execute steps S06, S07; S02, collect the SCA timing of the NAND FLASH interface as an SCA header; S03, determine whether the SCA header is SCE, if so, proceed to step S04, if not, proceed to step S05; S04. According to the type of the SCA header, the command / address / data of the SCA sequence subsequently received through the CA bus of the NAND FLASH interface is converted into the traditional sequence, and output to the traditional command / address / data interface; S05, converting the SCA timing data received by the SCE through the DQ bus of the NAND FLASH interface into the traditional timing data, and outputting it to the traditional data interface; S06, collecting the traditional timing of the NAND FLASH interface input as the command / address / data currently being transmitted; S07. Determine whether the traditional command / address / data currently being transmitted should go through the CA bus or the DQ bus in the SCA protocol. If it goes through the CA bus, output the command / address / data currently being transmitted to the traditional command / address / data interface; if it goes through the DQ bus, output the data currently being transmitted to the traditional data interface.
7. The interface switching method based on NAND FLASH SCA protocol according to claim 6, characterized in that: Steps S04 and S05 are executed in parallel.
8. The interface switching method based on NAND FLASH SCA protocol according to claim 6, characterized in that: In step S01, the timing of the NAND FLASH interface input is determined by whether the SCA enable pin sca_en of the NAND FLASH is pulled high. If the SCA enable pin sca_en is pulled high, the timing of the NAND FLASH interface input is the SCA protocol. If the SCA enable pin sca_en is not pulled high, the timing of the NAND FLASH interface input is the traditional command / address / data time-division multiplexing transmission form.
9. The interface switching method based on NAND FLASH SCA protocol according to claim 6, characterized in that: In step S02, the SCA timing of the NAND FLASH interface is collected as the SCA header. Specifically, each time the write enable pin WE_n of the NAND FLASH starts to vibrate, the values of ALE and CLE during the previous two vibrations are collected as the SCA header.
10. The interface switching method based on NAND FLASH SCA protocol according to claim 6, characterized in that: In step S04, the types of SCA header include data output, data input, address input, and command input.