Serial peripheral interface communication system and method

Abstract

The invention relates to a serial peripheral interface communication system and method. A method (20, 30) of serial peripheral interface (SPI) communication. The method includes transmitting a data packet from a master device to a slave device. The data packet comprises a read register address (21, 32), a write register address (22, 33) and write data (23, 34). The read register address (21, 32) and the write register address (22, 33) correspond to a data register of a plurality of data registers of the slave device. The method also includes receiving, at the slave device, a portion of the data packet. The portion of the data packet comprises a read register address (21, 32). The method further comprises reading, at the slave device, a read register address (21, 32) in the data packet. The method further comprises, after reading the read register address (21, 32), sending, from the slave device to the master device, data (25, 38) from the data register corresponding to the read register address (21, 32) of the slave device.

Description

Technical Field

[0001] The present disclosure relates to methods and systems for serial data communication between a master device and one or more slave devices. Background Art

[0002] The Serial Peripheral Interface (SPI) is a communication interface commonly used for data communication between a master device (e.g., computers and microcontrollers) and a slave device (e.g., a peripheral slave chip used in conjunction with a peripheral device (e.g., a peripheral integrated circuit (IC) such as a shift register, a sensor, an analog-to-digital converter (ADC), a digital-to-analog converter (DAC), and a memory device)).

[0003] The traditional SPI interface uses 4 wires, each of which transmits the following signals: a serial clock (or clock signal); a master node output and a slave node input (MOSI) for sending data from a master node (i.e., a master device or a controller device) to a slave node (i.e., a slave device or a peripheral device); a master node input and a slave node output (MISO) for sending data from the slave node to the master node; and a chip select line for selecting which peripheral device to communicate with.

[0004] To start SPI communication, the master device uses the chip select line to establish communication with the slave device. Once communication with the slave device is established, the master device sends a starting register address (i.e., address byte) to the slave device, which indicates from which slave register address the slave device will start reading data for the master device's read operation, or from which slave register address the master device will start writing data to the slave device.

[0005] Typically, the master device requests new data (or information) from the slave device as needed, or writes data to the slave device. In order to read data from the slave device, the master device sends a read address to the register of the slave device, from which the master device wishes to read the data content. In order to write data to the slave device, the master device sends a write address to the register of the slave device, from which the master device wishes to write the data content. Finally, the slave device sends the requested data content or the confirmation that the data has been written to the slave device back to the master device. However, both read requests and write requests are separate communications. Therefore, before performing both read and write operations, the master device needs to communicate with the slave device twice (i.e., two communication cycles).

[0006] Therefore, there may be a need for an improved SPI communication interface that uses SPI communications more efficiently. Summary of the invention

[0007] The present disclosure seeks to address the problems associated with conventional SPI communications, particularly reducing the number of communications between a master device and slave devices.

[0008] According to a first aspect, a method for peripheral interface SPI communication is disclosed. In particular, the method includes the step of sending a data packet from a master device to a slave device. Alternatively, the master device can be referred to as a controller, and the slave device can be referred to as a peripheral device. The data packet includes a read register address, a write register address, and write data. The read register address and the write register address correspond to a data register among a plurality of data registers of the slave device. The method also includes the step of receiving a part of the data packet at the slave device. A part of the data packet includes the read register address. The method also includes the step of reading the read register address in the data packet at the slave device. The method also includes the step of sending the data from the data register corresponding to the read register address of the slave device from the slave device to the master device after the read register address is read. In one form, once the read register address is read and before the master device completes sending the data packet, the data from the data register corresponding to the read register address of the slave device is sent from the slave device to the master device.

[0009] In this way, the master device can send both read and write operations to the slave device in the same communication. In this way, the number of data packets sent between the master device and the slave device is minimized, which enables faster and more efficient communication between the master device and the slave device. The slave device sends data to the master device before the master device sends the entire data packet, which results in faster read operations. In addition, the slave device does not need to store information between subsequent communications because both read and write operations are sent in one data packet.

[0010] In one form, the method further comprises sending a read register address of the slave device to the master device, so that the master device can determine whether the correct register is read at the slave device.

[0011] In one form, the method further comprises reading a write register address at a slave device. The write register address corresponds to a data register in a plurality of data registers of the slave device for storing write data. The method further comprises the step of storing the write data at the write register address of the slave device. In this way, write data (or any data to be written to a slave device) can be sent and subsequently stored at a corresponding register of the slave device.

[0012] In one form, a delay is provided between reading the read register address of the slave device at the slave device and sending data from the read register address of the slave device from the slave device. Thus, the slave device sends data to the master device in addition to writing the data to the register of the slave device.

[0013] In one form, the delay corresponds to the length of the write register address sent by the master device. Thus, the length of the data packet sent from the slave device corresponds to the length of the data packet sent to the slave device. In addition, the delay provides enough time for the slave device to discover, prepare and send data to the master device.

[0014] In one form, the data packet includes parity data so that each portion of the data packet can be verified to be correct.

[0015] In one form, the read register address of the slave device sent to the master device includes a read address parity check. In this way, the master device can verify whether the correct read address has been received at the slave device and the data sent to the master device is the requested data.

[0016] In one form, the method also includes sending verification data from the slave device to the master device. In this way, the slave device can verify that both the read operation and the write operation have been successfully completed.

[0017] In one form, data is sent from the slave device to the master device and write data is sent from the master device to the slave device simultaneously. In this way, information can be sent between the slave device and the master device at the same time, thereby providing more efficient communication, and no additional communication cycle is required to send information between the master device and the slave device.

[0018] In a second aspect, a serial peripheral interface (SPI) communication system is disclosed. The serial peripheral interface (SPI) communication system includes a master device and a slave device. The master device is configured to send a data packet to the slave device. The data packet includes a read register address, a write register address, and write data. The read register address and the write register address correspond to a data register among a plurality of data registers of the slave device. The slave device is configured to receive and read a portion of the data packet containing the read register address, and send data from the read register address of the slave device to the master device after the read register address has been read.

[0019] In one form, the slave device is configured to send a read register address of the slave device to the master device.

[0020] In one form, the slave device is configured to read the write register address, the write register address containing the register location of the write data to be stored, and store the write data at the write register address of the slave device.

[0021] In one form, the slave device is configured to provide a delay between reading a read register address of the slave device at the slave device and sending data from the read register address of the slave device from the slave device.

[0022] In one form, the delay corresponds to the length of the write register address sent by the master device.

[0023] In one form, the slave device is configured to send data to the master device at the same time as the master device sends write data to the slave device. BRIEF DESCRIPTION OF THE DRAWINGS

[0024] The specific embodiments will be described with reference to the accompanying drawings, in which:

[0025] Figure 1 SPI communication according to the prior art is shown;

[0026] Figure 2 shows SPI communication according to the present invention; and

[0027] Figure 3 A 64-bit SPI communication according to the present invention is shown. DETAILED DESCRIPTION

[0028] The following description presents exemplary embodiments and is related to the accompanying Figure 1 The present invention is intended to explain the principles of the present disclosure. However, the scope of the present invention is not intended to be limited to the precise details of the embodiments or to the precise conformity of all system features and / or method steps, as variations will be obvious to those skilled in the art and are considered to be covered by the specification. The terms used herein for components should be given a broad interpretation, which also includes equivalent functions and features.

[0029] In some cases, several alternative terms (synonyms) for structural, system or method features have been provided, but these terms are not intended to be exhaustive. Descriptive terms should also be given the broadest interpretation; for example, the term "comprising" used in this specification means "consisting at least in part of...", so that every statement in this specification including the term "comprising" is interpreted that there may also be features other than the features beginning with the term. Related terms such as "include" and "comprising" are interpreted in the same manner.

[0030] The description herein relates to embodiments with a specific combination of steps or features, however, it is contemplated that further combinations and cross-combinations of compatible steps or features between the embodiments will be possible. In fact, separate features can function as the present invention independently of other features, and are not necessarily required to be implemented as a complete combination.

[0031] It should be understood that the illustrated embodiments show applications for illustrative purposes only. In fact, the present invention can be applied to many different configurations, where the embodiments are straightforward to implement for those skilled in the art.

[0032] As background, Figure 1SPI communication 10 between a master device and a slave device (not shown) is shown. SPI communication 10 occurs via four signal lines: a chip select (CS) line; a clock signal (CLK) line; a MOSI data line; and a MISO data line. In the illustrated example, when serial data communication is not intended to occur between the master device and the slave device, the CS signal 11 is maintained in a high state on the CS line. If the master device needs to communicate with a slave device, the CS signal 11 to the slave device is maintained in a low state during serial data communication between the master device and the slave device. Alternatively, the high state and the low state may be reversed. Although not shown, it is known in the art that multiple slave devices can be connected to a master device, wherein the CS line is used to activate at least one slave device connected to the master device so that serial data communication can occur between the master device and the selected slave device. According to Figure 1 Once a write operation or a read operation is successfully completed, the master device deactivates the CLK signal 12 and sets the CS signal 11 to a high state.

[0033] In SPI communication, the clock signal 12 is a periodic signal that synchronizes data transfer between the master device and the slave device, and is usually sent by the master device. The clock signal 12 determines the maximum data transfer rate and the bit timing of the data transfer. It is important that the slave device uses the clock signal 12 to determine when to receive data. Depending on the configuration of the master device and the slave device, the clock signal can be sent first in a high state or a low state.

[0034] like Figure 1 As shown in the example of , SPI communication between the master device and the slave device can occur once the CS signal 11 is maintained in a low state and the master device transmits a clock signal 12 on the CLK line. The master device sends a data packet to the slave device on the MOSI line. Importantly, the data packet includes a read or write address 13. In addition, the data packet includes data 14, which includes information to be written to the slave device at the write address 13, or if the master device needs to read data from the read address of the slave device, the data packet includes a read command 14. The data packet is received at the slave device, and the slave device receives and reads the data packet based on the CLK signal 11.

[0035] The slave device includes a plurality of registers, each register having a corresponding register address. Each register corresponds to a parameter stored by the slave device. For example, one such parameter may be a temperature reading stored in a register of the slave device. If the master device needs to read data from a register of the slave device, the master device sends a read register address 13 of the register from which it needs to read data. Data 14 includes a read command, which indicates to the slave device that the master device needs to read data from the slave device. Once the slave device receives the data packet, the slave device copies the data from the register corresponding to the sent read address to the SPI transmission register before sending it to the master device. Once this occurs, the slave device sends the data packet back to the master device via the MISO line. The data packet includes a read address 15 of the register from which the data was read and data 16 from the SPI transmission register. The data packet is received at the master device, and the master device receives and reads the data packet according to the CLK signal 11.

[0036] Alternatively, if the master device needs to write data to the register of the slave device, the master device sends the write address 13 and the write data 14 in the data packet on the MOSI line to the slave device. The write address 13 corresponds to the register of the slave device to which the data is to be written. The data packet is received at the slave device, and the slave device receives and reads the data packet according to the CLK signal 11. The slave device stores the write data 14 at the register corresponding to the write address 13. In return, the slave device sends the data packet back to the master device on the MISO line. The data packet includes the write address 15 of the register of the slave device to which the data 14 is written, and includes data 16 of a status code indicating whether the operation is successful or unsuccessful.

[0037] Therefore, due to Figure 1 Due to the limitation of the SPI communication method, the master device must send two data packets (i.e., two separate messages) to send a read command and a write command. In this way, the read command and the write command occur on two communication cycles, which causes communication delays because the master device needs to send two messages before the two commands (or operations) are completed.

[0038] Figure 2 SPI communication 20 between a master device and a slave device according to the present invention is shown, wherein a read command and a write command can be sent in one data packet (i.e., in one communication cycle). To achieve this, the master device sends a data packet to the slave device on the MOSI line. The data packet includes a read address 21, a write address 22, and write data 23. The read address 21 corresponds to the register of the slave device from which the master device needs to read. The write address 22 corresponds to the register of the slave device to which the master device needs to write data. The write data 23 includes the data to be written to the write address 22 corresponding to the data register of the slave device.

[0039] The slave receives the data packet and reads the information from the data packet. Once the slave reads the read address 21 in the data packet from the master, the slave sends a data packet to the master with the read address 24 of the register from which the data 25 is to be read and the data 25 contained at that particular read address 24 of the slave. The transmission of the data packet to the master is defined by the SPI clock.

[0040] A delay 26 (corresponding to a time delay in a CLK signal cycle) between the transmission of the read address 24 and the data 25 can be implemented so that the slave device has enough time to receive and read the read address 21 and prepare the data 25 at the read address 21 to be sent to the master device in a data packet. For example, the delay 26 (or waiting time) can be based on the cycle of the CLK signal 12, or the delay 26 can correspond to the time taken by the master device to send the write address 22 (e.g., in a cycle of the CLK signal 12). In one example, the slave device does not send the data 25 to the master device within the delay 26. During the delay 26, the slave device prepares the data by copying the relevant data to the SPI data transfer register of the slave device within the delay 26. Subsequently, the slave device sends the data 25 to the master device synchronously with the SPI clock (i.e., in the time frame, the master device sends the write data 23 to the slave device). Therefore, once the read address 24 is read and before the master device completes the send communication (i.e., data packet), the slave device sends the data 25 to the master device.

[0041] In addition, each of the read address 21, the write address 22 and the write data 23 may include parity data. The parity data packet includes a parity bit or a control bit to ensure that the read address 21, the write address 22 and / or the write data 23 are not corrupted during the communication process. Similarly, each of the read address 24 and the data 25 may also include a parity bit or a control bit. Optionally, the parity data may include a checksum. The checksum includes one or more bits to verify data integrity.

[0042] Additionally, the slave device may send an acknowledgement bit (or OK bit) at the end of the data packet. Once the parity bit is successful and the correct data packet has been verified to be sent to the master device, the acknowledgement bit may be sent by the slave device. The acknowledgement bit provides confirmation to the master device that the communication was successful. If the slave device does not send an acknowledgement bit, the master device may resend the data packet as it may be assumed that the previous communication was unsuccessful.

[0043] Figure 3 An exemplary 64-bit SPI communication 30 between a master device and a slave device is shown. Figure 3 A 64-bit SPI communication 30 is shown, but it should be understood that SPI communications according to the present invention may occur using any of 8-bit, 16-bit, and 32-bit SPI communications.

[0044] Typically, the most significant bit 31 of the data packet is sent to the slave device first. Alternatively, the least significant bit of the data packet is sent to the slave device first. In this way, the read address 32 is the first part of the data packet to be sent to the slave device, followed by a parity (P) bit 35 for ensuring that the read address is correctly sent and received. Then, the write address 33 and the corresponding parity bit 35 are sent to the slave device. Subsequently, the write data 34 and the parity bit 35 are sent to the slave device. Although the parity bit 35 has been described, the parity bit 35 can be replaced or used in combination with the parity check. The parity check includes at least one bit for verifying the integrity of the data. For example, the parity check can be a checksum. The DC bit 36 ​​or the data command bit 36 ​​can be sent in the data packet to indicate the polarity of the data clock. In addition, when the DC bit 36 ​​is high, the data on the MOSI line is interpreted as a command. When the DC bit 36 ​​is low, the data on the MOSI line is interpreted as data. Depending on the configuration of the master device and the slave device, the DC bit 36 ​​can be sent first or last in the communication.

[0045] In response to the data packet sent by the master device, the slave device sends a read address 37 back to the master device on the MISO line. The read address 37 includes a parity bit 35 to verify that the read address 37 was sent correctly. After sending the read address 37, a delay 40 is initiated, which corresponds to the length of time (e.g., in the cycle of the CLK signal 12) taken by the master device to send the write address 33 and the corresponding parity bit 35. Once the write address 33 and the parity bit 35 are sent to the slave device, the slave device sends data 38 from the read address 37 of the register of the slave device. In addition, the data 35 includes the parity bit 35 and the confirmation bit 39.

[0046] With this approach, the master only needs to communicate with the slave once to write data to the slave's register and receive new information directly from the slave's read address. In addition, the master receives confirmation that both the read and write operations were successful via the confirmation bit 39.

Claims

1. A method for serial peripheral interface SPI communication, the method comprising the following steps: Sending a data packet from a master device to a slave device, the data packet comprising a read register address, a write register address, and write data, wherein the read register address and the write register address correspond to a data register among a plurality of data registers of the slave device; receiving, at the slave device, a portion of the data packet, the portion of the data packet including the read register address; reading the read register address in the data packet at the slave device; After the read register address is read, data from a data register corresponding to the read register address of the slave device is sent from the slave device to the master device.

2. The method for SPI communication according to claim 1, further comprising the following steps: The read register address of the slave device is sent to the master device.

3. The method for SPI communication according to claim 1 or 2, further comprising the following steps: reading the write register address at the slave device, the write register address corresponding to a data register for storing the write data among the plurality of data registers of the slave device; as well as The write data is stored at the write register address of the slave device.

4. The method for SPI communication according to any one of claims 1 to 3, wherein: A delay is provided between reading the read register address of the slave device at the slave device and sending data from the read register address of the slave device from the slave device.

5. The method for SPI communication according to claim 4, wherein: The delay corresponds to the length of the write register address sent by the master device.

6. The method for SPI communication according to any one of claims 1 to 5, wherein: The data packet includes parity data.

7. The SPI communication method according to any one of claims 2 to 6, wherein: The read register address of the slave device sent to the master device includes a read address parity check.

8. The method for SPI communication according to any one of claims 1 to 7, further comprising the following steps: Verification data is sent from the slave device to the master device.

9. The SPI communication method according to any one of claims 1 to 8, wherein: The sending of data from the slave device to the master device occurs simultaneously with the sending of the write data from the master device to the slave device.

10. A serial peripheral interface (SPI) communication system, the SPI communication system comprising: Master and slave devices; The master device is configured to send a data packet to the slave device, the data packet comprising a read register address, a write register address, and write data, wherein the read register address and the write register address correspond to a data register among a plurality of data registers of the slave device, and The slave device is configured to receive and read a portion of the data packet including the read register address, and to send data from the read register address of the slave device to the master device after reading the read register address.

11. The SPI communication system according to claim 10, wherein: The slave device is configured to send the read register address of the slave device to the master device.

12. The SPI communication system according to claim 10 or 11, wherein: The slave device is configured to read the write register address, which includes a register location for storing the write data, and store the write data at the write register address of the slave device.

13. The SPI communication system according to any one of claims 10 to 12, wherein: The slave device is configured to provide a delay between reading the read register address of the slave device at the slave device and sending data from the read register address of the slave device from the slave device.

14. The SPI communication system according to claim 13, wherein: The delay corresponds to the length of the write register address sent by the master device.

15. The SPI communication system according to any one of claims 10 to 14, wherein: The slave device is configured to send data to the master device simultaneously with the master device sending the write data to the slave device.

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