Server mainboard, control method and equipment

Abstract

The invention provides a server mainboard, a control method and equipment, relates to the technical field of computers, and aims to solve the problem of DDC signal communication failure caused by I2C address conflict of displays of the same model in related server application scenarios. The server mainboard comprises a first device, a plurality of video graphic array interface modules and a switching circuit, each video graphic array interface module sends an in-place signal to the switching circuit when detecting that a display is accessed; the first device generates a write register signal according to the in-place signal and sends the write register signal to the switching circuit; the switching circuit generates a selection signal according to the write register signal, and conducts a display data channel bus between the target video graphic array interface module and the first device according to the selection signal; and the first device reads the extended display identification data information of the target display accessed to the target video graphic array interface module to complete configuration of the target display.

Description

Technical Field

[0001] The embodiments of the present application relate to the field of computer technology, and in particular to a server motherboard, a control method and a device. Background Art

[0002] Servers are the core of Internet infrastructure, and their reliability and efficiency have a direct impact on network service quality and user experience. VGA (Video Graphics Array) interfaces are widely used in server products for display device feature exchange. VGA interfaces contain DDC (Direct Digital Control) signals, which are used to read EDID (Extended Display Identification Data), allowing the system to automatically identify the display's properties and optimize display settings.

[0003] In server application scenarios, there are two VGA interfaces, one for the front window and the other for the rear window, but in a single server system, there is only one first device, that is, there is an application scenario where two displays are connected to a single DDC bus. In this scenario, when using the same model of display, the I2C (Inter-Integrated Circuit) address of the front and rear window displays will be the same. Due to the line and form on the physical link, an address conflict will occur, resulting in the inability to identify the device and the failure of data transmission interaction, which will cause the DDC signal communication to fail and the inability to configure the optimal display settings. Summary of the invention

[0004] The embodiments of the present application provide a server motherboard, a control method and a device, which are intended to solve the problem of I2C address conflicts of the same model of displays in related server application scenarios, resulting in DDC signal communication failure and inability to configure optimal display settings.

[0005] A first aspect of an embodiment of the present application provides a server mainboard, comprising: a first device, a plurality of video graphics array interface modules, and a switching circuit; Each video graphics array interface module sends a presence signal to the switching circuit when detecting that a display is connected to the video graphics array interface module; The first device receives the in-position signal sent by the switching circuit, generates a write register signal according to the in-position signal, and sends the write register signal to the switching circuit; The switching circuit generates a selection signal according to the write register signal, selects a target video graphics array interface module from a plurality of video graphics array interface modules according to the selection signal, and conducts a display data channel bus between the target video graphics array interface module and the first device; The first device reads the extended display identification data information of the target display connected to the target video graphics array interface module through the display data channel bus, and completes the configuration of the target display.

[0006] In an optional implementation, the switching circuit includes: a second device, an analog switch; The second device receives the in-position signal and sends the in-position signal to the first device, and receives the write register signal sent by the first device, generates the selection signal according to the write register signal, and sends the selection signal to the analog switch; The analog switch receives the selection signal sent by the second device, selects a target video graphics array interface module according to the selection signal, and conducts a display data channel bus between the target video graphics array interface module and the first device.

[0007] In an optional implementation, the first video graphics array interface module includes: a first video graphics array interface; The second video graphics array interface module includes: A second video graphics array interface of the front window input and output board and a sideband signal connector are arranged in the server mainboard, and a cable is connected between the second video graphics array interface of the front window input and output board and the sideband signal connector.

[0008] In an optional implementation manner, the second device is specifically used for: When only the first in-position signal is received, controlling the analog switch to be connected to the first video graphics array interface module, the first video graphics array interface module being used to access the rear window display; In the case of receiving only the second in-position signal, controlling the analog switch to be connected to the second video graphics array interface module, the second video graphics array interface module being used to access the front window display; When the first in-position signal and the second in-position signal are received, the analog switch is controlled to be turned on with the first video graphics array interface module in a first time period, and the analog switch is controlled to be turned on with the second video graphics array interface module in a second time period, in the order of the first video graphics array interface module having a higher priority and the second video graphics array interface module having a lower priority, wherein the second time period is a time period after the first time period; In the case that the first presence signal and the second presence signal are not received, the analog switch is controlled to be connected to the first video graphics array interface module.

[0009] In an optional implementation, the analog switch includes at least a first input port, a second input port, a first output port, a second output port, a third output port, and a fourth output port; The step of selecting a target video graphics array interface module according to the selection signal and connecting a display data channel bus between the target video graphics array interface module and the first device comprises: The first input port, the first output port and the second output port form a first group, the second input port, the third output port and the fourth output port form a second group, the first group of input ports and output ports transmit display data channel clock signals, and the second group of input ports and output ports transmit display data channel data signals; When the selection signal is at a low level, the analog switch connects the first input port and the second input port to the first output port and the third output port respectively, so as to connect the display data channel bus between the first video graphics array interface module and the first device; When the selection signal is at a high level, the analog switch connects the first input port and the second input port to the second output port and the fourth output port respectively, thereby connecting the display data channel bus between the second video graphics array interface module and the first device.

[0010] In an optional implementation manner, the first device and the second device are connected via an integrated circuit bus link, and the configuration of the target display is completed according to the following steps: When the selection signal is at a low level, the first device sends the write register signal to the second device through the integrated circuit bus link, controls the second device to set the selection pin of the analog switch to a low level state, and realizes the conduction of the display data channel bus between the first video graphics array interface module and the first device; the first device reads the extended display identification data information of the rear window display connected to the first video graphics array interface module through the display data channel bus, and completes the configuration of the rear window display; When the selection signal is at a high level, the first device sends the write register signal to the second device through the integrated circuit bus link, controls the second device to set the selection pin of the analog switch to a high level state, and realizes the conduction of the display data channel bus between the second video graphics array interface module and the first device; the first device reads the extended display identification data information of the front window display connected to the second video graphics array interface module through the display data channel bus, and completes the configuration of the front window display.

[0011] In an optional implementation, the rear window display and the front window display are of the same model and have the same corresponding address; the first device and the second device are connected via an integrated circuit bus link, and the configuration of the target display is completed according to the following steps: When the selection signal is at a low level, the first device sends the write register signal to the second device through the integrated circuit bus link, controls the second device to set the selection pin of the analog switch to a low level state, and realizes the conduction of the display data channel bus between the first video graphics array interface module and the first device; the first device reads the extended display identification data information of the rear window display connected to the first video graphics array interface module through the display data channel bus according to the address, and completes the configuration of the rear window display; When the selection signal is at a high level, the first device sends the write register signal to the second device through the integrated circuit bus link, controls the second device to set the selection pin of the analog switch to a high level state, and realizes the conduction of the display data channel bus between the second video graphics array interface module and the first device; the first device reads the extended display identification data information of the front window display connected to the second video graphics array interface module through the display data channel bus according to the address, and completes the configuration of the front window display.

[0012] In an optional implementation, the server mainboard further includes: a level conversion device; The level conversion device is used to convert the output signal level of the display data channel bus of the first device into a standard level.

[0013] A second aspect of an embodiment of the present application provides a control method, which is applied to a second device, including: Acquire presence signals of a plurality of video graphics array interface modules, and send the presence signals to the first device, wherein the presence signals indicate whether a display is connected to a corresponding video graphics array interface module; receiving a write register signal sent by the first device according to the presence signal; A selection signal is generated according to the write register signal, and a target video graphics array interface module is selected from multiple video graphics array interface modules according to the selection signal, and a display data channel bus between the target video graphics array interface module and the first device is turned on, so that the first device reads the extended display identification data information of the target display connected to the target video graphics array interface module through the display data channel bus, and completes the configuration of the target display.

[0014] A third aspect of an embodiment of the present application provides an electronic device, comprising: a processor, a memory, and a computer program stored in the memory and executable on the processor, wherein the processor implements the control method of the second aspect of the embodiment of the present application when executing the computer program.

[0015] In this embodiment, the switching circuit detects the in-place signal sent when the display is connected to the corresponding video graphics array interface module, and sends the in-place signal to the first device; the first device generates a write register signal according to the in-place signal and sends it to the switching circuit; the switching circuit generates a selection signal according to the write register signal, and selects the target video graphics array interface module according to the selection signal, and connects the display data channel bus between the target video graphics array interface module and the first device; the first device reads the extended display identification data information of the target display connected to the target video graphics array interface module through the display data channel bus, and completes the configuration of the target display. Through the in-place signal and the switching circuit, time-sharing multiplexing of the front window display and the rear window display can be achieved, effectively solving the problem of I2C address conflicts of displays of the same model and the inability to correctly implement DDC bus communication, expanding the use scenarios and applicability of server products. BRIEF DESCRIPTION OF THE DRAWINGS

[0016] In order to more clearly illustrate the technical solutions of the embodiments of the present application, the drawings required for use in the description of the embodiments of the present application will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying any creative labor.

[0017] Figure 1 It is a topological diagram of a display data channel interface connected to two displays in the present application; Figure 2 It is a structural schematic diagram of a server mainboard proposed in an embodiment of the present application; Figure 3 It is a topological diagram of display data channel signal switching of a server mainboard proposed in an embodiment of the present application; Figure 4This is a schematic diagram of the interconnection topology of switching between the display data channel interface and the video graphics array interface of the server mainboard proposed in one embodiment of the present application; Figure 5 It is a schematic diagram of an electronic device proposed in an embodiment of the present application. DETAILED DESCRIPTION

[0018] The following will be combined with the drawings in the embodiments of the present application to clearly and completely describe the technical solutions in the embodiments of the present application. Obviously, the described embodiments are part of the embodiments of the present application, not all of the embodiments. Based on the embodiments in the present application, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of this application.

[0019] The development of the Internet has driven the continuous development of infrastructure. In today's Internet era, servers are the cornerstone of Internet infrastructure and the key to the operation of modern digital society. Their reliability and efficiency directly affect the quality of network services and user experience. Although modern data centers tend to use remote management tools for headless operations (i.e., not directly connected to monitors and peripherals), monitors still maintain an indispensable position in physical access, emergency maintenance, or specific scenarios to ensure the intuitiveness and efficiency of server operation and maintenance. The application and importance of monitors in server management and maintenance are mainly reflected in the following aspects: viewing server status information through the monitor, including system logs, resource usage, error reports, etc., for real-time monitoring and troubleshooting; in the initial deployment or hardware maintenance stage of the server, the monitor directly connected to the server can help administrators perform basic work such as BIOS (Basic Input / Output System) settings, RAID (Redundant Array of Independent Disks) configuration, and operating system installation to ensure that the server can be correctly set up as required; when the server encounters a hardware failure or system crash, the monitor can display error codes or POST (Power-On Self Test) information, which is crucial for quickly locating the root cause of the problem, helping to shorten repair time and reduce the impact of downtime; using a monitor to connect to the server for performance benchmarking, load testing and other operations can help administrators evaluate the server's processing capabilities, perform performance tuning accordingly, and ensure efficient operation of the service.

[0020] Judging from the current application scenarios and shipping configurations of servers, the VGA interface is the most widely used in server products. The VGA interface is a protocol standard for display device feature exchange based on the I2C physical bus. It is mainly used to connect computer graphics cards and monitors to transmit video signals. The host of the VGA interface is the first device, and a single first device integrates a set of VGA interfaces. The VGA interface contains RGB primary color signals, HSYNC and VSYNC synchronization signals, and DDC signals. One of the core functions of DDC is to realize EDID reading, allowing the system to automatically identify the properties of the display, such as resolution, refresh rate, color depth, and manufacturer information, so as to optimize the display settings and automatically configure the display settings to match the best performance of the display.

[0021] In the server application scenario, there are two VGA interfaces configured for the front window and the rear window, and in a single server system, there is only one first device, that is, there is an application scenario where a single DDC bus is connected to two displays. The related art is a connection topology diagram of the DDC bus when the current server system is designed to support dual displays of the front window and the rear window, such as Figure 1 As shown. The first device is located in the mainboard, and the first device integrates a DDC bus interface, including DDCCLK (DDC clock signal) and DDCDATA (DDC data signal); the signal level standard output by the first device is 3.3V, and after passing through the level conversion device, the level is converted to the 5V level standard; the DDCCLK and DDCDATA signals after the level conversion are connected to the rear window VGA interface in the mainboard and the sideband signal connector connected to the front window IO (input and output) board in the mainboard by wired mode; the sideband signal connector in the mainboard and the front window VGA interface of the front window IO board are connected by cables.

[0022] However, the physical layer of the DDC signal is based on the I2C protocol. Each monitor is an independent I2C slave device and is uniquely identified by its own I2C address. If the same model of monitor device is used at the customer site or in the laboratory environment, the I2C addresses of the front and rear monitors may be the same. In this application scenario, the front and rear VGA interfaces use the line-and-type form on the physical link, which will cause address conflicts and make it impossible to identify the device, resulting in data transmission interaction failure, leading to DDC signal communication failure, causing the server system to be unable to prepare to obtain display EDID information, and unable to correctly configure the display settings to match the best performance of the monitor.

[0023] Reference Figure 2 , Figure 2 The server mainboard is a schematic diagram of a structure of a server mainboard proposed in an embodiment of the present application. The server mainboard includes: a first device, a plurality of video graphics array interface modules, and a switching circuit.

[0024] Each video graphics array interface module sends a presence signal to the switching circuit when detecting that a display is connected to the video graphics array interface module.

[0025] In this embodiment, the presence signal is a signal used to detect whether the device is correctly connected and in an active state. Each VGA interface module detects whether a corresponding display is connected through its internal circuit and pins. Once the display is connected, the VGA interface module generates a presence signal and sends the presence signal to the switching circuit.

[0026] Furthermore, the first video graphics array interface module includes: a first video graphics array interface; the second video graphics array interface module includes: a second video graphics array interface of the front window input and output board, and a sideband signal connector arranged in the server mainboard, and a cable is connected between the second video graphics array interface of the front window input and output board and the sideband signal connector.

[0027] In this embodiment, with respect to the first VGA interface module and the second VGA interface module, the first VGA interface module includes: a first VGA interface (rear window VGA interface), and the first VGA interface is used to access the rear window display. The second VGA interface module includes: a second VGA interface (front window VGA interface) of the front window input and output board, and a sideband signal connector disposed in the server mainboard, the second VGA interface and the sideband signal connector are connected via a cable, and the second VGA interface is used to access the front window display.

[0028] The first device receives the in-place signal sent by the switching circuit, generates a write register signal according to the in-place signal, and sends the write register signal to the switching circuit.

[0029] In this embodiment, the first device will identify and process the in-position signal sent by the switching circuit, and can determine that the VGA interface module is in a connected state with the display according to the in-position signal. At this time, the first device will generate a write register signal according to a preset logic or algorithm and send it to the switching circuit to confirm the conduction mode of the DDC bus.

[0030] In addition, the BMC can also record the usage history and status information of each VGA interface module and display to facilitate fault analysis and prevention.

[0031] The switching circuit generates a selection signal according to the write register signal, selects a target video graphics array interface module from a plurality of video graphics array interface modules according to the selection signal, and conducts a display data channel bus between the target video graphics array interface module and the first device.

[0032] In this embodiment, the switching circuit receives the write register signal sent by the first device, performs a write operation on the corresponding register according to the content of the signal, and generates a selection signal. The selection signal is a level signal, and the target VGA interface module is determined from multiple VGA interface modules according to the selection signal, and the DDC bus between the target VGA interface module and the first device is turned on through the internal switch.

[0033] Further, the switching circuit includes: a second device, an analog switch; The second device receives the in-position signal and sends the in-position signal to the first device, and receives the write register signal sent by the first device, generates the selection signal according to the write register signal, and sends the selection signal to the analog switch; The analog switch receives the selection signal sent by the second device, selects a target video graphics array interface module according to the selection signal, and conducts a display data channel bus between the target video graphics array interface module and the first device.

[0034] In this embodiment, the switching circuit includes: a second device and an analog switch. The second device is a digital circuit hardware device that can implement different logic functions through programming to meet various complex design requirements. The second device receives the write register signal sent by the first device, and performs a write operation on the corresponding register according to the content of the signal, thereby generating a selection signal and sending it to the analog switch. The analog switch determines the target VGA interface module from multiple VGA interface modules according to the selection signal, and turns on the DDC bus between the target VGA interface module and the first device. By using the second device and the analog switch, it is helpful to realize time-sharing multiplexing of the front window display and the rear window display to expand the use scenarios and applicability of server products.

[0035] Further, the analog switch at least includes a first input port, a second input port, a first output port, a second output port, a third output port and a fourth output port; The step of selecting a target video graphics array interface module according to the selection signal and connecting a display data channel bus between the target video graphics array interface module and the first device comprises: The first input port, the first output port and the second output port form a first group, the second input port, the third output port and the fourth output port form a second group, the first group of input ports and output ports transmit display data channel clock signals, and the second group of input ports and output ports transmit display data channel data signals; When the selection signal is at a low level, the analog switch connects the first input port and the second input port to the first output port and the third output port respectively, so as to connect the display data channel bus between the first video graphics array interface module and the first device; When the selection signal is at a high level, the analog switch connects the first input port and the second input port to the second output port and the fourth output port respectively, thereby connecting the display data channel bus between the second video graphics array interface module and the first device.

[0036] In this embodiment, the analog switch at least includes a first input port (1A1), a second input port (2A1), a first output port (1B1), a second output port (1B2), a third output port (2B1) and a fourth output port (2B2), which are divided into two groups, i.e., 1A1, 1B1, 1B2 are the first group, and 2A1, 2B1, 2B2 are the second group. The DDC bus transmits a DDC clock signal and a DDC data signal. The first group of input ports and output ports transmits the DDC clock signal, and the second group of input ports and output ports transmits the DDC data signal. The analog switch controls the conduction state of the input pin A and the output pin B according to the level state of the selection pin corresponding to the selection signal.

[0037] See Figure 3 When the selection signal is at a low level, the selection pin is set to a low level, that is, the A and B1 pins are turned on, that is, the first input port and the second input port are respectively turned on with the first output port and the third output port, so that the DDC bus between the first VGA interface module and the first device can be turned on. When the selection signal is at a high level, the selection pin is set to a high level, A=B2, that is, A and B2 are turned on, that is, the first input port and the second input port are respectively turned on with the second output port and the fourth output port, so that the DDC bus between the second VGA interface module and the first device can be turned on.

[0038] Furthermore, the first device and the second device are connected via an integrated circuit bus link, and the configuration of the target display is completed according to the following steps: When the selection signal is at a low level, the first device sends the write register signal to the second device through the integrated circuit bus link, controls the second device to set the selection pin of the analog switch to a low level state, and realizes the conduction of the display data channel bus between the first video graphics array interface module and the first device; the first device reads the extended display identification data information of the rear window display connected to the first video graphics array interface module through the display data channel bus, and completes the configuration of the rear window display; When the selection signal is at a high level, the first device sends the write register signal to the second device through the integrated circuit bus link, controls the second device to set the selection pin of the analog switch to a high level state, and realizes the conduction of the display data channel bus between the second video graphics array interface module and the first device; the first device reads the extended display identification data information of the front window display connected to the second video graphics array interface module through the display data channel bus, and completes the configuration of the front window display.

[0039] In this embodiment, the first device and the second device are connected via an integrated circuit bus (I2C) link. When the selection signal is at a low level, the first device sends a write register signal to the second device via the I2C link, controls the second device to set the selection pin of the analog switch to a low level state, realizes the DDC bus conduction between the first VGA interface module and the first device, and the first device reads the EDID information of the rear window display connected to the first VGA interface module via the DDC bus, and completes the configuration of the rear window display. When the selection signal is at a high level, the first device sends a write register signal to the second device via the I2C link, controls the second device to set the selection pin of the analog switch to a high level state, realizes the DDC bus conduction between the second VGA interface module and the first device, and the first device reads the EDID information of the front window display connected to the second VGA interface module via the DDC bus, and completes the configuration of the front window display.

[0040] Furthermore, the rear window display and the front window display have the same model and the same corresponding address; the first device and the second device are connected via an integrated circuit bus link, and the configuration of the target display is completed according to the following steps: When the selection signal is at a low level, the first device sends the write register signal to the second device through the integrated circuit bus link, controls the second device to set the selection pin of the analog switch to a low level state, and realizes the conduction of the display data channel bus between the first video graphics array interface module and the first device; the first device reads the extended display identification data information of the rear window display connected to the first video graphics array interface module through the display data channel bus according to the address, and completes the configuration of the rear window display; When the selection signal is at a high level, the first device sends the write register signal to the second device through the integrated circuit bus link, controls the second device to set the selection pin of the analog switch to a high level state, and realizes the conduction of the display data channel bus between the second video graphics array interface module and the first device; the first device reads the extended display identification data information of the front window display connected to the second video graphics array interface module through the display data channel bus according to the address, and completes the configuration of the front window display.

[0041] In this embodiment, the configuration of the target display can be completed for the scenario where the rear window display and the front window display have the same model and the same corresponding address. This address is usually a part of the EDID stored in the display. Specifically, when the selection signal is low, the first device sends a write register signal to the second device through the I2C link, controls the second device to set the selection pin of the analog switch to a low level state, realizes the DDC bus conduction between the first VGA interface module and the first device, and the first device uses the address to read the EDID information of the rear window display connected to the first VGA interface module through the DDC bus, and completes the configuration of the rear window display. When the selection signal is high, the first device sends a write register signal to the second device through the I2C link, controls the second device to set the selection pin of the analog switch to a high level state, realizes the DDC bus conduction between the second VGA interface module and the first device, and the first device uses the address to read the EDID information of the front window display connected to the second VGA interface module through the DDC bus, and completes the configuration of the front window display. By determining the conduction mode through the in-position signal, the second device and the analog switch, time-sharing multiplexing of the front window display and the rear window display can be achieved, effectively solving the problem of I2C address conflict of displays of the same model and the inability to correctly implement DDC bus communication.

[0042] By determining the conduction mode through the in-position signal, the second device and the analog switch, it can also be applied to the scenario where the display models are different and the corresponding addresses are also different. In this scenario, the first device uses the respective addresses to read the EDID information of the rear window display connected to the first VGA interface module and the EDID information of the front window display connected to the second VGA interface module through the DDC bus to complete the configuration of the display.

[0043] Furthermore, the second device is specifically used for: When only the first in-position signal is received, controlling the analog switch to be connected to the first video graphics array interface module, the first video graphics array interface module being used to access the rear window display; In the case of receiving only the second in-position signal, controlling the analog switch to be connected to the second video graphics array interface module, the second video graphics array interface module being used to access the front window display; When the first in-position signal and the second in-position signal are received, the analog switch is controlled to be turned on with the first video graphics array interface module in a first time period, and the analog switch is controlled to be turned on with the second video graphics array interface module in a second time period, in the order of the first video graphics array interface module having a higher priority and the second video graphics array interface module having a lower priority, wherein the second time period is a time period after the first time period; In the case that the first presence signal and the second presence signal are not received, the analog switch is controlled to be connected to the first video graphics array interface module.

[0044] In this embodiment, the first in-place signal refers to the signal generated by the first VGA interface (rear window VGA interface) in the first VGA interface module when the rear window display is connected to the first VGA interface module, and the second in-place signal refers to the signal generated by the second VGA interface (front window VGA interface) in the second VGA interface module when the front window display is connected to the second VGA interface module.

[0045] If only the first in-place signal is received, the second device controls the analog switch to be turned on with the first VGA interface module, and the first VGA interface module is used to access the rear window display; if only the second in-place signal is received, the second device controls the analog switch to be turned on with the second VGA interface module, and the second VGA interface module is used to access the front window display; if the first in-place signal and the second in-place signal are received, the second device controls the analog switch to be turned on with the first VGA interface module in the first time period, and controls the analog switch to be turned on with the second VGA interface module in the second time period, in the order of high priority of the first VGA interface module and low priority of the second VGA interface module, and the second time period is the time period after the first time period, so as to realize time-division multiplexing of the conduction logic of the analog switch; if neither the first in-place signal nor the second in-place signal is received, the second device controls the analog switch to be turned on with the first VGA interface module by default.

[0046] When the first VGA interface module and the second VGA interface module are connected to the display at the same time, that is, the front window VGA interface and the rear window VGA interface are connected to the display at the same time, the conduction logic of the analog switch is controlled in time-sharing multiplexing according to the set priority, which can effectively solve the I2C address conflict of the same model display and the problem of inability to correctly implement DDC bus communication.

[0047] Furthermore, the server mainboard further comprises: a level conversion device; The level conversion device is used to convert the output signal level of the display data channel bus of the first device into a standard level.

[0048] In this embodiment, the VGA interface is a traditional display interface, and its level standard is usually higher, generally 5V. The signal level standard output by the first device is 3.3V. Therefore, a level conversion device is required to convert the 3.3V level to the 5V level standard to ensure the correct exchange and communication of signals between different circuit modules.

[0049] The first device reads the extended display identification data information of the target display connected to the target video graphics array interface module through the display data channel bus, and completes the configuration of the target display.

[0050] In this embodiment, after the DDC bus between the target VGA interface module and the first device is turned on, the first device reads the EDID information of the target display connected to the target VGA interface module through the DDC bus, and automatically identifies the properties of the target display based on this information, such as resolution, refresh rate, color depth and manufacturer information, thereby optimizing the display settings to match the optimal performance of the target display, and finally completing the configuration of the target display.

[0051] The switching circuit detects the in-place signal sent when the display is connected to the corresponding video graphics array interface module, and sends the in-place signal to the first device; the first device generates a write register signal according to the in-place signal and sends it to the switching circuit; the switching circuit generates a selection signal according to the write register signal, and selects the target video graphics array interface module according to the selection signal, and connects the display data channel bus between the target video graphics array interface module and the first device; the first device reads the extended display identification data information of the target display connected to the target video graphics array interface module through the display data channel bus, and completes the configuration of the target display. Through the in-place signal and the switching circuit, time-sharing multiplexing of the front window display and the rear window display can be realized, effectively solving the problem of I2C address conflicts of displays of the same model and the inability to correctly realize DDC bus communication, expanding the use scenarios and applicability of server products.

[0052] Reference Figure 4 , Figure 4 FIG. 1 is a schematic diagram of the interconnection topology of the display data channel interface and the video graphics array interface switching of the server motherboard proposed in one embodiment of the present application. Figure 4 As shown in the figure, the interconnection process is as follows: The first device is located in the server motherboard. The first device integrates a DDC bus interface, including a DDC clock signal and a DDC clock signal. The DDC clock signal and the DDC clock signal output by the first device have a level standard of 3.3V. After passing through a level conversion device, the level is converted to a 5V level standard. After the DDC signal passes through the level conversion device, an analog switch is added to the server motherboard. After passing through the internal logic of the second device, it is time-sharingly connected to the first VGA interface (rear window VGA interface) and the sideband signal connector. The sideband signal connector is connected to the second VGA interface (front window VGA interface) through a cable. The rear window VGA interface and the front window VGA interface are respectively designed to be connected to the second device with an in-position signal. The second device outputs a selection signal connected to the analog switch. The second device receives a BMC instruction through an I2C signal to control the conduction mode of the analog switch. By adding an in-position signal and an analog switch on the motherboard end, the time-sharing multiplexing of the display connected to the front window and rear window VGA interfaces can be realized, which can effectively solve the problem of I2C address conflict of the same model display and the inability to correctly realize DDC bus communication, and expand the use scenarios and applicability of server products.

[0053] Based on the same inventive concept, an embodiment of the present application provides a control method, which is applied to a second device, including: Acquire presence signals of a plurality of video graphics array interface modules, and send the presence signals to the first device, wherein the presence signals indicate whether a display is connected to a corresponding video graphics array interface module; receiving a write register signal sent by the first device according to the presence signal; A selection signal is generated according to the write register signal, and a target video graphics array interface module is selected from multiple video graphics array interface modules according to the selection signal, and a display data channel bus between the target video graphics array interface module and the first device is turned on, so that the first device reads the extended display identification data information of the target display connected to the target video graphics array interface module through the display data channel bus, and completes the configuration of the target display.

[0054] Based on the same inventive concept, an embodiment of the present application provides an electronic device, referring to Figure 5 , Figure 5 FIG. 1 is a schematic diagram of an electronic device shown in an embodiment of the present application. Figure 5 As shown, the electronic device 100 includes: a memory 110 and a processor 120. The memory 110 and the processor 120 are connected via a bus communication. A computer program is stored in the memory 110. The computer program can be run on the processor 120 to implement the steps in the control method of the embodiment of the present disclosure.

[0055] The various embodiments in this specification are described in a progressive manner, and each embodiment focuses on the differences from other embodiments. The same or similar parts between the various embodiments can be referenced to each other.

[0056] Those skilled in the art will appreciate that the embodiments of the present application may be provided as methods, devices, or computer program products. Therefore, the embodiments of the present application may adopt the form of complete hardware embodiments, complete software embodiments, or embodiments in combination with software and hardware. Moreover, the embodiments of the present application may adopt the form of a computer program product implemented on one or more computer-usable storage media (including but not limited to disk storage, CD-ROM, optical storage, etc.) that contain computer-usable program code.

[0057] The embodiments of the present application are described with reference to the flowcharts and / or block diagrams of the methods, terminal devices (systems), and computer program products according to the embodiments of the present application. It should be understood that each process and / or box in the flowchart and / or block diagram, as well as the combination of the processes and / or boxes in the flowchart and / or block diagram, can be implemented by computer program instructions. These computer program instructions can be provided to a processor of a general-purpose computer, a special-purpose computer, an embedded processor, or other programmable data processing terminal device to generate a machine, so that the instructions executed by the processor of the computer or other programmable data processing terminal device generate instructions for implementing the processes in the flowchart and / or block diagram. Figure 1 A process or multiple processes and / or boxes Figure 1 A device that provides the functions specified in a block or multiple blocks.

[0058] These computer program instructions may also be stored in a computer-readable memory capable of directing a computer or other programmable data processing terminal device to operate in a specific manner, so that the instructions stored in the computer-readable memory produce a manufactured product including an instruction device, which implements the process Figure 1 A process or multiple processes and / or boxes Figure 1 A function specified in one or more boxes.

[0059] These computer program instructions can also be loaded onto a computer or other programmable data processing terminal device so that a series of operating steps are executed on the computer or other programmable terminal device to produce a computer-implemented process, thereby providing instructions for executing on the computer or other programmable terminal device to implement the process. Figure 1 A process or multiple processes and / or boxes Figure 1 The steps for the functions specified in one or more boxes.

[0060] Although the preferred embodiments of the present application have been described, those skilled in the art may make additional changes and modifications to these embodiments once they have learned the basic creative concept. Therefore, the appended claims are intended to be interpreted as including the preferred embodiments and all changes and modifications that fall within the scope of the embodiments of the present application.

[0061] Finally, it should be noted that, in this article, relational terms such as first and second, etc. are only used to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Moreover, the terms "include", "comprise" or any other variants thereof are intended to cover non-exclusive inclusion, so that a process, method, article or terminal device including a series of elements includes not only those elements, but also other elements not explicitly listed, or also includes elements inherent to such process, method, article or terminal device. In the absence of further restrictions, the elements defined by the sentence "comprise a ..." do not exclude the existence of other identical elements in the process, method, article or terminal device including the elements.

[0062] The server motherboard, control method and device provided by the present application are introduced in detail above. The principle and implementation mode of the present application are explained in detail by using specific examples. The description of the above embodiments is only used to help understand the method and core idea of ​​the present application. At the same time, for those skilled in the art, according to the idea of ​​the present application, there will be changes in the specific implementation mode and application scope. In summary, the content of this specification should not be understood as limiting the present application.

Claims

1. A server motherboard, characterized in that: include: A first device, a plurality of video graphics array interface modules, and a switching circuit; Each video graphics array interface module sends a presence signal to the switching circuit when detecting that a display is connected to the video graphics array interface module; The first device receives the in-place signal sent by the switching circuit, generates a write register signal according to the in-place signal, and sends the write register signal to the switching circuit; The switching circuit generates a selection signal according to the write register signal, selects a target video graphics array interface module from a plurality of video graphics array interface modules according to the selection signal, and conducts a display data channel bus between the target video graphics array interface module and the first device; The first device reads the extended display identification data information of the target display connected to the target video graphics array interface module through the display data channel bus, and completes the configuration of the target display.

2. The server motherboard according to claim 1, characterized in that: The switching circuit includes: a second device and an analog switch; The second device receives the in-position signal and sends the in-position signal to the first device, and receives the write register signal sent by the first device, generates the selection signal according to the write register signal, and sends the selection signal to the analog switch; The analog switch receives the selection signal sent by the second device, selects a target video graphics array interface module according to the selection signal, and conducts a display data channel bus between the target video graphics array interface module and the first device.

3. The server motherboard according to claim 1, characterized in that: The first video graphics array interface module includes: a first video graphics array interface; The second video graphics array interface module includes: A second video graphics array interface of the front window input and output board and a sideband signal connector are arranged in the server mainboard, and a cable is connected between the second video graphics array interface of the front window input and output board and the sideband signal connector.

4. The server motherboard according to claim 2, characterized in that: The second device is specifically used for: In the case where only the first in-position signal is received, controlling the analog switch to be connected to the first video graphics array interface module, the first video graphics array interface module being used to access the rear window display; In the case of receiving only the second in-position signal, controlling the analog switch to be connected to the second video graphics array interface module, the second video graphics array interface module being used to access the front window display; When the first in-position signal and the second in-position signal are received, the analog switch is controlled to be turned on with the first video graphics array interface module in a first time period, and the analog switch is controlled to be turned on with the second video graphics array interface module in a second time period, in the order of the first video graphics array interface module having a higher priority and the second video graphics array interface module having a lower priority, wherein the second time period is a time period after the first time period; In the case that the first presence signal and the second presence signal are not received, the analog switch is controlled to be connected to the first video graphics array interface module.

5. The server motherboard according to claim 2, characterized in that: The analog switch at least includes a first input port, a second input port, a first output port, a second output port, a third output port and a fourth output port; The step of selecting a target video graphics array interface module according to the selection signal and connecting a display data channel bus between the target video graphics array interface module and the first device comprises: The first input port, the first output port and the second output port form a first group, the second input port, the third output port and the fourth output port form a second group, the first group of input ports and output ports transmit display data channel clock signals, and the second group of input ports and output ports transmit display data channel data signals; When the selection signal is at a low level, the analog switch connects the first input port and the second input port to the first output port and the third output port respectively, so as to connect the display data channel bus between the first video graphics array interface module and the first device; When the selection signal is at a high level, the analog switch connects the first input port and the second input port to the second output port and the fourth output port respectively, thereby connecting the display data channel bus between the second video graphics array interface module and the first device.

6. The server motherboard according to claim 2, characterized in that: The first device and the second device are connected via an integrated circuit bus link, and the configuration of the target display is completed according to the following steps: When the selection signal is at a low level, the first device sends the write register signal to the second device through the integrated circuit bus link, controls the second device to set the selection pin of the analog switch to a low level state, and realizes the conduction of the display data channel bus between the first video graphics array interface module and the first device; the first device reads the extended display identification data information of the rear window display connected to the first video graphics array interface module through the display data channel bus, and completes the configuration of the rear window display; When the selection signal is at a high level, the first device sends the write register signal to the second device through the integrated circuit bus link, controls the second device to set the selection pin of the analog switch to a high level state, and realizes the conduction of the display data channel bus between the second video graphics array interface module and the first device; the first device reads the extended display identification data information of the front window display connected to the second video graphics array interface module through the display data channel bus, and completes the configuration of the front window display.

7. The server motherboard according to claim 6, characterized in that: The rear window display and the front window display have the same model and the same corresponding address; the first device and the second device are connected via an integrated circuit bus link, and the configuration of the target display is completed according to the following steps: When the selection signal is at a low level, the first device sends the write register signal to the second device through the integrated circuit bus link, controls the second device to set the selection pin of the analog switch to a low level state, and realizes the conduction of the display data channel bus between the first video graphics array interface module and the first device; the first device reads the extended display identification data information of the rear window display connected to the first video graphics array interface module through the display data channel bus according to the address, and completes the configuration of the rear window display; When the selection signal is at a high level, the first device sends the write register signal to the second device through the integrated circuit bus link, controls the second device to set the selection pin of the analog switch to a high level state, and realizes the conduction of the display data channel bus between the second video graphics array interface module and the first device; the first device reads the extended display identification data information of the front window display connected to the second video graphics array interface module through the display data channel bus according to the address, and completes the configuration of the front window display.

8. The server motherboard according to any one of claims 1 to 7, characterized in that: The server mainboard further comprises: a level conversion device; The level conversion device is used to convert the output signal level of the display data channel bus of the first device into a standard level.

9. A control method, characterized in that: Applied to a second device, comprising: Acquire presence signals of a plurality of video graphics array interface modules, and send the presence signals to the first device, wherein the presence signals indicate whether a display is connected to a corresponding video graphics array interface module; receiving a write register signal sent by the first device according to the presence signal; A selection signal is generated according to the write register signal, and a target video graphics array interface module is selected from multiple video graphics array interface modules according to the selection signal, and a display data channel bus between the target video graphics array interface module and the first device is turned on, so that the first device reads the extended display identification data information of the target display connected to the target video graphics array interface module through the display data channel bus, and completes the configuration of the target display.

10. An electronic device, characterized in that: include: A processor, a memory, and a computer program stored in the memory and executable on the processor, wherein the processor implements the control method described in claim 9 when executing the computer program.

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