Parallel bus link training method and device, electronic equipment and storage medium

Abstract

The embodiment of the invention provides a parallel bus link training method and device, electronic equipment, a computer readable storage medium and a computer program product, and relates to the technical field of integrated circuits. The method comprises the following steps: acquiring a unit time interval of a to-be-adjusted parallel bus, dividing the unit time interval based on a preset phase adjustment window, acquiring a plurality of clock stages, sequentially performing phase adjustment on the to-be-adjusted parallel bus based on the plurality of clock stages, and determining a target phase adjustment value, and adjusting the to-be-adjusted parallel bus based on the target phase adjustment value. According to the embodiment of the invention, the unit time interval is divided through the phase adjustment window, so that phase adjustment is carried out, link training is completed, precise capture of a tiny effective sampling window in the high-speed parallel bus is realized, and the signal transmission efficiency of the parallel bus is improved.

Description

Technical Field

[0001] The present application relates to the field of integrated circuit technology. Specifically, the present application relates to a parallel bus link training method, device, electronic device, computer-readable storage medium and computer program product. Background Art

[0002] With the continuous development of integrated circuit technology and the continuous increase in data throughput requirements, the use of parallel buses for data transmission has become more common. For some application scenarios with special requirements for latency and parallel data transmission, wide-bit parallel buses have irreplaceable advantages. As the data transmission rate increases, the time that the signal exists on the bus becomes very short, and there may be a very narrow effective window for obtaining data.

[0003] The existing parallel bus achieves clock and data alignment by simply switching the clock rising and falling edge sampling method. However, when the effective sampling window of the data is extremely small, the existing method cannot correctly obtain the data, and data transmission cannot proceed normally, reducing the signal transmission efficiency of the parallel bus. Summary of the invention

[0004] The embodiments of the present application provide a parallel bus link training method, device, electronic device, computer-readable storage medium and computer program product, which are intended to solve the technical problem that data and clock cannot be aligned when the data sampling window is extremely small, resulting in a low signal transmission rate.

[0005] In a first aspect, a parallel bus link training method is provided, the method comprising: Get the unit time interval of the parallel bus to be adjusted; Dividing the unit time interval based on a preset phase adjustment window to obtain multiple clock phases; The parallel bus to be adjusted is phase-adjusted sequentially based on multiple clock phases, a target phase adjustment value is determined, and the parallel bus to be adjusted is adjusted based on the target phase adjustment value.

[0006] Optionally, a unit time interval is divided based on a preset phase adjustment window to obtain multiple clock phases, including: Based on a preset phase adjustment window, a unit time interval is continuously divided into a plurality of non-overlapping clock segments; The clock segments are sequentially accumulated to obtain multiple clock stages.

[0007] Optionally, sequentially performing phase adjustment on the parallel bus to be adjusted based on multiple clock phases to determine a target phase adjustment value includes: Determining a phase adjustment value for the parallel bus to be adjusted based on each clock phase; The phases of the parallel buses to be adjusted are adjusted in sequence based on the phase adjustment values, and the adjusted parallel buses are detected to determine the target phase adjustment value.

[0008] Optionally, sequentially performing phase adjustment on the parallel buses to be adjusted based on the phase adjustment values, and detecting the adjusted parallel buses to determine the target phase adjustment value, includes: sequentially performing phase adjustment on the parallel buses to be adjusted based on the phase adjustment values; Performing link detection on the adjusted parallel bus to obtain corresponding detection results; Based on each detection result, a target phase adjustment value is determined.

[0009] Optionally, performing link detection on the adjusted parallel bus to obtain a corresponding detection result includes: Obtaining a preset detection cycle; the detection cycle includes multiple unit time intervals; Perform link detection on the adjusted parallel bus based on the detection cycle to obtain the connection status corresponding to each unit time interval; Get the detection result based on the connection status.

[0010] Optionally, the connection status includes connection success; Based on the connection status, obtain the detection results, including: Determine the number of consecutive intervals during which the connection state is successfully connected; If the proportion of the number of consecutive intervals of successful connection to the detection period is greater than or equal to the preset threshold, the detection result is determined to be passed; If the proportion of the number of consecutive intervals of successful connection to the detection period is less than a preset threshold, the detection result is determined to be failed.

[0011] Optionally, determining a target phase adjustment value based on each detection result includes: Based on each detection result, clustering each phase adjustment value corresponding to the detection result to obtain multiple clusters and corresponding cluster centers; The cluster center whose corresponding detection result is passed is taken as the candidate cluster center; The candidate cluster center with the largest cluster among the candidate cluster centers is taken as the target cluster center; Based on the target cluster center, a target phase adjustment value is determined.

[0012] Optionally, based on each detection result, each phase adjustment value corresponding to the detection result is clustered to obtain multiple clusters and corresponding cluster centers, including: Arrange the detection results according to the corresponding phase adjustment values ​​to obtain an arrangement result; the first detection result and the last detection result in the arrangement result are adjacent; Based on the arrangement result, each phase adjustment value corresponding to the detection result is clustered to obtain multiple clusters and corresponding cluster centers.

[0013] Optionally, adjusting the parallel bus to be adjusted based on the target phase adjustment value includes: Adjusting the clock phase of the parallel bus to be adjusted based on the target phase adjustment value; Performing link detection on the adjusted parallel bus; If the link detection passes, the phase adjustment of the parallel bus is completed.

[0014] In a second aspect, a parallel bus link training device is provided, the device comprising: An interval acquisition module, used for acquiring a unit time interval of the parallel bus to be adjusted; A phase division module, used to divide the unit time interval based on a preset phase adjustment window to obtain multiple clock phases; The phase adjustment module is used to sequentially perform phase adjustment on the parallel bus to be adjusted based on multiple clock phases, determine a target phase adjustment value, and adjust the parallel bus to be adjusted based on the target phase adjustment value.

[0015] In a third aspect, an electronic device is provided, the electronic device comprising: A memory, a processor and a computer program stored in the memory, wherein the processor executes the computer program to implement the steps of any method in the first aspect of the present application.

[0016] In a fourth aspect, a computer-readable storage medium is provided, on which a computer program is stored. When the computer program is executed by a processor, the parallel bus link training method shown in any one of the first aspects of the present application is implemented.

[0017] In a fifth aspect, a computer program product is provided, comprising a computer program, which implements the steps of any one of the methods in the first aspect of the present application when the computer program is executed by a processor.

[0018] The beneficial effects of the technical solution provided by the embodiment of the present application are: The parallel bus link training method provided in the present application divides the unit time interval into smaller segments by a preset phase adjustment window, thereby obtaining a more refined clock phase for phase adjustment and completing link training. The target phase adjustment value obtained in this way is applied to a high-speed parallel bus, which enables the data signal to be correctly sampled within a very small effective interval. For example, on a 16-bit or 32-bit high-speed parallel bus, when the available reliable sampling window is less than 5% of the unit time interval, reliable transmission at a higher rate can be maintained, thereby effectively improving the signal transmission efficiency of the high-speed parallel bus.

[0019] Furthermore, the phase of the parallel bus is adjusted in sequence based on the phase adjustment value determined in the clock stage. After each phase adjustment, the link detection is performed on the parallel bus to determine whether the link is connected normally. A certain number of unit time intervals can be set during the link detection process, and the connection status is determined for each unit time interval. According to the number of cycles in which the connection status is successful in these unit time intervals, it is determined whether the corresponding phase adjustment detection result passes according to the number of successful cycles. Phase adjustment values ​​with smaller fluctuations in the periodic connection status can be screened out, and the obtained target phase adjustment value is more accurate, thereby improving the stability of the high-speed parallel bus signal transmission process.

[0020] In addition, according to the detection results corresponding to different phase adjustment values, the corresponding phase adjustment values ​​are clustered to obtain multiple clusters. The link detection results in each cluster are the same. The cluster center of the cluster is determined, and the candidate cluster center whose corresponding detection result passes is determined. The target cluster center with the largest cluster is selected, and the phase adjustment value corresponding to the cluster center is used as the target phase adjustment value. A relatively stable adjustment value range can be determined through the largest cluster. The cluster center is selected within the range to determine the target phase adjustment value. The parallel bus is more stable after adjustment based on the target phase adjustment value. Even if the clock phase deviation occurs due to other reasons during the communication process, the stable connection of the signal can still be maintained. BRIEF DESCRIPTION OF THE DRAWINGS

[0021] In order to more clearly illustrate the technical solutions in the embodiments of the present application, the drawings required for use in describing the embodiments of the present application are briefly introduced below.

[0022] Figure 1 A schematic diagram of an application scenario of a parallel bus link training method provided in an embodiment of the present application; Figure 2 A flowchart of a parallel bus link training method provided in an embodiment of the present application; Figure 3 A schematic diagram of a phase adjustment window of a parallel bus link training method provided in an embodiment of the present application; Figure 4 A schematic diagram of an effective sampling window in a parallel bus link training method provided in an embodiment of the present application; Figure 5 A schematic diagram of a circular arrangement of detection results of a parallel bus link training method provided in an embodiment of the present application; Figure 6 A flowchart of an example of a parallel bus link training method provided in an embodiment of the present application; Figure 7 A schematic diagram of the structure of a parallel bus link training device provided in an embodiment of the present application; Figure 8 A schematic diagram of the structure of an electronic device applicable to a parallel bus link training method provided in an embodiment of the present application. DETAILED DESCRIPTION

[0023] The embodiments of the present application are described below in conjunction with the drawings in the present application. It should be understood that the implementation methods described below in conjunction with the drawings are exemplary descriptions for explaining the technical solutions of the embodiments of the present application and do not constitute a limitation on the technical solutions of the embodiments of the present application.

[0024] It will be understood by those skilled in the art that, unless specifically stated, the singular forms "one", "an", "said" and "the" used herein may also include plural forms. It should be further understood that the terms "including" and "comprising" used in the embodiments of the present application refer to that the corresponding features can be implemented as the presented features, information, data, steps, operations, elements and / or components, but do not exclude the implementation as other features, information, data, steps, operations, elements, components and / or combinations thereof supported by the present technical field. It should be understood that when we call an element "connected" or "coupled" to another element, the one element may be directly connected or coupled to the other element, or it may refer to that the one element and the other element establish a connection relationship through an intermediate element. In addition, the "connection" or "coupling" used herein may include wireless connection or wireless coupling. The terms "or", "and / or", "including at least one of the following" etc. used in the present application may be interpreted as inclusive, or mean any one or any combination. For example, “including at least one of the following: A, B, C” means “any of the following: A; B; C; A and B; A and C; B and C; A and B and C” and, for example, “A, B or C” or “A, B and / or C” means “any of the following: A; B; C; A and B; A and C; B and C; A and B and C”.

[0025] In the embodiments of the present application, the term "module" or "unit" refers to a computer program or a part of a computer program that has a predetermined function and works together with other related parts to achieve a predetermined goal, and can be implemented in whole or in part by using software, hardware (such as processing circuits or memories), or a combination thereof. Similarly, a processor (or multiple processors or memories) can be used to implement one or more modules or units. In addition, each module or unit can be part of an overall module or unit that includes the function of the module or unit.

[0026] In the specific implementation of this application, any data related to the object, such as the data involved in the process of the object using the application, is involved. When the embodiment of this application is applied to a specific product or technology, it is necessary to obtain the permission or consent of the object, and the collection, use and processing of the relevant data must comply with the relevant laws, regulations and standards of the relevant countries and regions. In other words, if any of the above-mentioned data related to the object is involved in the embodiment of this application, these data must be obtained with the authorization and consent of the object and in compliance with the relevant laws, regulations and standards of the country and region.

[0027] In order to make the objectives, technical solutions and advantages of the present application clearer, the implementation methods of the present application will be further described in detail below with reference to the accompanying drawings.

[0028] First, the technical terms involved in this application are introduced and explained: Clock cycle: refers to the time required for the clock signal to complete a complete cycle (from the lowest point to the highest point and then back to the lowest point) in bus operation. This cycle is the basic time unit for parallel bus data transmission. It determines the rate and frequency of data transmission. Clock cycle alignment is the key to ensuring correct data transmission.

[0029] Phase: refers to the position of a specific moment in a periodic signal relative to the entire period. Adjusting the phase usually refers to adjusting the time relationship between the data signal and the clock signal to ensure that the data is captured or sent at the correct clock edge, which can ensure that the data is correctly sampled and identified during the transmission process. Misalignment of the clock phase can lead to data transmission errors or losses.

[0030] With the continuous development of integrated circuit technology and the continuous increase in data throughput requirements, traditional serial high-speed interfaces have been widely used in many occasions. However, for some application scenarios with special requirements for latency and parallel data transmission, wide bit width parallel buses still have irreplaceable advantages.

[0031] In high-speed parallel data transmission, in order to ensure data synchronization between bits and achieve reliable sampling, link training is usually required to automatically adjust the sampling windows of the transmitter and receiver. However, in some systems, the transceiver side may not have complex link training hardware, or only provide a simple fixed transmission mode, resulting in the inability to directly complete adaptive high-speed training.

[0032] In response to this situation, traditional solutions often seek to align the data and clock phases by simply switching the clock's upper and lower edge sampling or adding a fixed phase delay. However, when the target rate is gradually increased to hundreds of megahertz or even higher, due to factors such as process and line, each data line has a slight delay difference, and the receiver lacks the function of fine compensation for data delay. There is great uncertainty in the alignment of the clock phase and the data sampling window, resulting in a very narrow effective window that can accommodate sampling. If the sampling clock cannot be accurately adjusted to the only extremely small window, the system will face the risk of unstable link or even failure to link.

[0033] Therefore, a new parallel bus link training method based on dynamic phase adjustment is needed to provide a higher reliable data transmission rate on a high-speed parallel bus, and to achieve a high-bandwidth stable connection even when only one end has some or all training functions, such as sending fixed data and checking whether the link is successful.

[0034] The parallel bus link training method, device, electronic device, computer-readable storage medium and computer program product provided in the present application are intended to solve at least one of the above technical problems in the prior art.

[0035] In response to at least one of the above-mentioned technical problems or areas that need improvement in the related art, the present application proposes a parallel bus link training method, device, electronic device, computer-readable storage medium and computer program product. The parallel bus link training method provided by the scheme divides the unit time interval by a preset phase adjustment window, and can divide the unit time interval into smaller segments to obtain a more refined clock stage for phase adjustment. The target phase adjustment value obtained in this way is applied to a high-speed parallel bus, which can enable the data signal to be correctly sampled within a very small effective interval. For example, on a 16-bit or 32-bit high-speed parallel bus, when the available reliable sampling window is less than 5% of the unit time interval, reliable transmission at a higher rate can be maintained, effectively improving the signal transmission efficiency of the high-speed parallel bus.

[0036] Furthermore, the phase of the parallel bus is adjusted in sequence based on the phase adjustment value determined in the clock stage. After each phase adjustment, the link detection is performed on the parallel bus to determine whether the link is connected normally. A certain number of unit time intervals can be set during the link detection process, and the connection status is determined for each unit time interval. According to the number of cycles in which the connection status is successful in these unit time intervals, it is determined whether the corresponding phase adjustment detection result passes according to the number of successful cycles. Phase adjustment values ​​with smaller fluctuations in the periodic connection status can be screened out, and the obtained target phase adjustment value is more accurate, thereby improving the stability of the high-speed parallel bus signal transmission process.

[0037] In addition, according to the detection results corresponding to different phase adjustment values, the corresponding phase adjustment values ​​are clustered to obtain multiple clusters. The link detection results in each cluster are the same. The cluster center of the cluster is determined, and the candidate cluster center whose corresponding detection result passes is determined. The target cluster center with the largest cluster is selected, and the phase adjustment value corresponding to the cluster center is used as the target phase adjustment value. A relatively stable adjustment value range can be determined through the largest cluster. The cluster center is selected within the range to determine the target phase adjustment value. The parallel bus is more stable after adjustment based on the target phase adjustment value. Even if the clock phase deviation occurs due to other reasons during the communication process, the stable connection of the signal can still be maintained.

[0038] The following describes several exemplary embodiments to illustrate the technical solutions of the embodiments of the present application and the technical effects produced by the technical solutions of the present application. It should be noted that the following embodiments can refer to, draw on or combine with each other, and the same terms, similar features and similar implementation steps in different embodiments will not be described repeatedly.

[0039] Figure 1 A schematic diagram of an application scenario of a parallel bus link training method provided in an embodiment of the present application, wherein the application environment may include a signal transmitting end 100 and a signal receiving end 200, wherein the signal transmitting end 100 may include a CPU (Central Processing Unit), and the signal receiving end 200 may include an FPGA (Field-Programmable Gate Array), and the CPU and the FPGA are connected via a parallel bus.

[0040] Specifically, the signal receiving end 200 obtains the unit time interval of the parallel bus to be adjusted, divides the unit time interval based on a preset phase adjustment window, obtains multiple clock stages, performs phase adjustment on the parallel bus to be adjusted based on the multiple clock stages in sequence, determines a target phase adjustment value, and adjusts the parallel bus between the signal sending end 100 to be adjusted and the signal receiving end 200 based on the target phase adjustment value.

[0041] In a specific implementation process, the signal receiving end 200 may include a link training control module 300 and a phase control module 400. The link training control module 300 obtains a unit time interval of the parallel bus to be adjusted, divides the unit time interval based on a preset phase adjustment window, and obtains multiple clock phases. The link training control module 300 controls the phase control module 400 to perform phase adjustment on the parallel bus to be adjusted based on the multiple clock phases in sequence, determines a target phase adjustment value, and adjusts the parallel bus to be adjusted based on the target phase adjustment value, so that the parallel bus after adjustment can receive and send signals between the signal sending end 100 and the signal receiving end 200 more stably.

[0042] In the specific implementation process, the signal transmitting end 100 and the signal receiving end 200 can be integrated circuit chips, and data is transmitted through a parallel bus. The signal transmitting end 100 only needs to have the function of sending a fixed sequence or simple detection, and can cooperate with the dynamic phase adjustment of the signal receiving end 200 to achieve link training, which greatly improves the rate. For example, for a 16-bit parallel bus, the transmission rate can be increased from 25MHz to 400MHz through the above-mentioned link training. The signal receiving end 200 only needs to have simple sending and detection functions to achieve a stable connection of the high-speed parallel bus, which provides feasibility for many scenarios where only single-ended chips can be modified.

[0043] The above application scenario is only an example and does not limit the application scenario of the parallel bus link training method of the present application.

[0044] In some possible implementations, taking the execution subject as a signal receiving end as an example, the embodiment of the present application provides a parallel bus link training method, such as Figure 2 As shown, the following steps may be included: S210, obtaining a unit time interval of the parallel bus to be adjusted.

[0045] The parallel bus to be adjusted is a parallel bus between a signal transmitting end and a signal receiving end.

[0046] The unit time interval is usually expressed by unit time UI.

[0047] Specifically, the clock cycle of the parallel bus to be adjusted is obtained, and the corresponding unit time interval is determined based on the clock cycle. The clock cycle is the time required for the parallel bus to be adjusted to complete a data transmission. The clock cycle can be pre-set in the parallel bus system. The range of clock phase adjustment is determined based on the unit time interval, and the phase of the clock signal is adjusted to ensure that data passing through multiple data lines of the parallel bus are sent and received at the correct time.

[0048] Specifically, for a system where the signal is sampled on both the rising and falling edges, the time it takes for the clock signal to go from one rising edge to the next rising edge (or from one falling edge to the next falling edge) is taken as the clock cycle. At this time, the length of the two unit time intervals is equal to the length of the clock cycle. If the signal is only sampled on the rising edge or the falling edge, then the length of the unit time interval is equal to the length of the clock cycle.

[0049] In the specific implementation process, before obtaining the unit time interval of the parallel bus to be adjusted, it includes: detecting that the signal sending end has been powered on and starts to send fixed-mode data, setting the state to an idle state, and entering a phase adjustment process, wherein the fixed-mode data includes a series of known data that can be used to detect and adjust the performance of the communication link. The signal receiving end may also start the phase adjustment step after receiving the fixed-mode data sent by the signal sending end. A signal receiving module may be set in the signal receiving end to detect the signal sent by the signal sending end, such as a signal instructing the signal receiving end to start a phase adjustment process.

[0050] In the specific implementation process, the link training process can be summarized as the signal sending end starts to send a known fixed-mode training sequence, the signal receiving end receives the training sequence, evaluates the signal quality and signal reception, adjusts and tests the phase of the clock signal, and after determining the target phase adjustment value to adjust the clock phase, synchronizes the data transmission of the sending and receiving ends according to the clock signal to ensure that the data is correctly sampled on the bus, and then starts to transmit actual data. By optimizing and adjusting the signal transmission parameters in the communication link through link training, the stability and efficiency of the communication are guaranteed.

[0051] S220, dividing the unit time interval based on a preset phase adjustment window to obtain multiple clock phases.

[0052] Specifically, the phase adjustment window is determined based on the requirement of the effective window size. The phase adjustment window represents the accuracy of the phase adjustment. Based on the phase accuracy requirement, 1 / 4, 1 / 8, 1 / 16, 1 / 32 or 1 / 64 of the unit time interval can be used as the size of the phase adjustment window. The unit time interval is divided based on the phase adjustment window to obtain multiple clock phases. Phase adjustment values ​​of different sizes can be flexibly obtained according to requirements, thereby improving the precision of phase adjustment. The clock phase can be adjusted to an extremely small effective window, and the link can be connected normally even in relatively harsh conditions, thereby ensuring the stability of the parallel bus link.

[0053] For example, if Figure 3As shown, the unit time interval can be divided into 8 clock segments according to needs, each clock segment corresponds to 1 / 8 of the unit time interval, and multiple clock stages are obtained in units of clock segments, such as 1 / 8, 2 / 8, 5 / 8, and 7 / 8, so as to adjust the clock phase on the parallel bus based on the clock stage, determine the optimal phase, align the clock signals, ensure the stable connection of the data link, and ensure normal data transmission.

[0054] In the specific implementation process, Figure 4 As shown, the application scenario of this solution is the interconnection between small chip modules or different chips. The data transmitted by each signal line in the parallel bus (i.e., Lane 0 to Lane 15 shown in the figure) is sampled through the sampling window and spliced ​​to receive the correct data (i.e., the data shown in the figure). For wide parallel buses, such as 16 bits, 32 bits or higher, as the bus width increases and the number of data lines increases, the clock skew (i.e., the skew shown in the figure), that is, the difference in clock arrival time on different data lines may increase, which will cause the sampling window at the signal receiving end to become very small. For example, for a parallel bus link with 16 signal lines, the effective sampling window is only 5% of the length of the unit time interval (i.e., 5% UI shown in the figure), which is difficult to sample correctly. However, the present application solution can accurately align the effective sampling windows of the accompanying clock and the multi-channel data to ensure that the data on all data lines are sampled at the correct clock edge, which can effectively improve the operating rate of the high-speed parallel bus.

[0055] S230, sequentially performing phase adjustment on the parallel bus to be adjusted based on multiple clock phases, determining a target phase adjustment value, and adjusting the parallel bus to be adjusted based on the target phase adjustment value.

[0056] Specifically, the phase of the parallel bus to be adjusted is adjusted in sequence based on multiple clock stages. After each phase adjustment, the adjusted parallel bus link can be tested to determine whether the corresponding data can be accurately obtained, so as to determine the target phase adjustment value among the phase adjustment values ​​corresponding to the multiple clock stages, and set the parallel bus based on the target phase adjustment value to complete the link training of the corresponding parallel bus. Adjusting the phase of the clock signal can affect the sampling time of the data, thereby affecting the correct reading of the data, thereby improving the efficiency of data transmission by the parallel bus.

[0057] During the specific implementation process, the unit time interval can be divided into n clock segments according to needs, and each clock segment corresponds to a 1 / n unit time interval. During the first phase adjustment, the phase is moved by 1 / n through the phase adjuster. When entering the phase adjustment stage for the mth time, the phase is moved by m / n through the phase adjuster, where m is less than n. The phase adjuster may include an MMCM (Mixed-Mode Clock Manager) module or other structure that can dynamically adjust the clock phase.

[0058] In the specific implementation process, the target phase adjustment value is determined, and the phase adjuster MMCM can be controlled to modify the phase. The phase of the parallel bus to be adjusted is adjusted based on the target phase adjustment value. Then, the adjusted parallel bus can be subjected to a link test. After the test is passed, the phase can be set by PLL (Phase-Locked Loop) and the phase relationship between the signals can be maintained, so that the phase stability and the accuracy of data transmission can be maintained, the bit error rate can be reduced, and the overall performance of the system where the parallel bus is located can be improved. The PLL is used to provide a clock to the chip at the other end, and a clock with a fixed phase difference from the adjusted optimal receiving clock phase as the sending clock of this end, which is sent to the other end as the clock to be received at the other end. The embodiment of the present application relies on general modules such as MMCM and PLL inside the integrated circuit to complete the link training process of the parallel bus. There is no need to design complex high-speed link training hardware. It can be quickly implemented in the existing mature chip design process, and has high scalability and economy.

[0059] In some possible implementations, the above steps divide the unit time interval based on the preset phase adjustment window to obtain multiple clock phases, including: Based on a preset phase adjustment window, a unit time interval is continuously divided into a plurality of non-overlapping clock segments; The clock segments are sequentially accumulated to obtain multiple clock stages.

[0060] Specifically, based on a preset phase adjustment window size, clock segments of corresponding sizes can be continuously divided on a unit time interval, or the unit time interval can be equally divided based on the phase adjustment window size to obtain various clock segments, and then the clock segments are accumulated in sequence to obtain multiple clock stages. For example, a unit time interval is from 0ns to 3ns, and the effective window size is 300ps. The unit time interval can be divided into continuous clock segments, each clock segment has a length of 300ps, including: 0 to 300ps, 300 to 600ps, 600 to 900ps..., and then the clock segments are accumulated in sequence to obtain clock stages: 0 to 300ps, 0 to 600ps, 0 to 900ps..., then when entering the phase adjustment stage for the first time, the phase can be adjusted to 300ps, and the second phase adjustment can be adjusted to 600ps, and so on.

[0061] In the specific implementation process, based on the preset parameter N, 1 UI is divided into N uniform phase points. For the case where 1 UI is equal to 3ns and N is 10, these phase points represent 10 phase adjustment situations where the clock phase is offset by 0ps, 300ps, 600ps, 900ps...2700ps relative to the original clock. Each phase adjustment stage corresponds to a phase point, and the phase adjustment is completed based on the corresponding phase point, and then the link is detected.

[0062] In the specific implementation process, the method for obtaining the phase adjustment window includes: obtaining the effective window size of the data signal at the receiving end of the parallel bus, and determining the size of the phase adjustment window based on the effective window size, wherein the phase adjustment window is less than or equal to the effective window. This ensures that the step size of the phase adjustment can fall on the effective window, which can improve the accuracy of data acquisition at the signal receiving end and make the parallel bus link more stable.

[0063] In the specific implementation process, the unit time interval can be divided into n clock segments, each clock segment corresponds to a 1 / n unit time interval, and the first clock stage is 1 / n. Each time a phase adjustment operation is added, the clock stage increases by a clock segment length, that is, the second clock stage is 2 / n. When entering the phase adjustment stage for the mth time, the clock stage is m / n, where m is less than n. In this way, the phase adjustment values ​​are accumulated in sequence to obtain the corresponding clock stage.

[0064] In some possible implementations, the above steps sequentially perform phase adjustment on the parallel bus to be adjusted based on multiple clock phases to determine the target phase adjustment value, including: Determining a phase adjustment value for the parallel bus to be adjusted based on each clock phase; The phases of the parallel buses to be adjusted are adjusted in sequence based on the phase adjustment values, and the adjusted parallel buses are detected to determine the target phase adjustment value.

[0065] Specifically, based on each clock stage obtained, the corresponding phase adjustment value is determined, and the phase of the parallel bus is adjusted based on different phase adjustment values. According to the increasing relationship of the phase adjustment value, the phase is adjusted from small to large. After the adjustment, it is also necessary to determine whether the parallel bus link is connected normally, and the connection results of each phase adjustment value are obtained, so as to obtain the required target phase adjustment value.

[0066] For example, a unit time interval is from 0ns to 10ns, the effective window size is 2ns, and the resulting clock stages are 0 to 2ns, 0 to 4ns, 0 to 6ns, 0 to 8ns and 0 to 10ns. The corresponding phase adjustment values ​​are determined to be 2ns, 4ns, 6ns, 8ns and 10ns, and the phase of the corresponding parallel bus is adjusted in sequence from small to large according to the phase adjustment values. In actual use, the unit time interval and the effective window unit may be smaller. This is only used as an adjustment illustration and does not limit the size and gap of the effective window mixed clock stage.

[0067] In the specific implementation process, the training control module of the signal receiving end establishes N phase adjustment stages according to the setting of preset parameters. The phase of each stage moves 1 / N unit time interval UI, and moves N times in total. For the mth movement, the phase moves m / N UI. Because the clock is periodic, the uniform detection of the parameterized phase group is completed through N phase movement stages. For example, for an 800Mbps signal, one UI is 1.25ns. When the phase traversal parameter is set to 64, the value of each phase shift is approximately 19.53ps. Through 64 phase shifts, the detection of 64 phase points with an interval of 19.53ps can be completed. In particular, for the case of a 16-bit bus communicating at 800Mbps, the available sampling window length is about 5%UI, that is, an available sampling window of 62.5ps. Then, 3 phase settings in the traversed sampling phases will fall within this interval. The optimal sampling phase can be accurately located through the maximum cluster algorithm to achieve a stable link connection.

[0068] In some possible implementations, the above steps sequentially perform phase adjustment on the parallel bus to be adjusted based on each phase adjustment value, and detect the adjusted parallel bus to determine the target phase adjustment value, including: sequentially performing phase adjustment on the parallel buses to be adjusted based on the phase adjustment values; Performing link detection on the adjusted parallel bus to obtain corresponding detection results; Based on each detection result, a target phase adjustment value is determined.

[0069] The link detection is used to test whether the link connection is stable; the detection result includes whether the link detection passes or fails.

[0070] Specifically, the phase of the parallel bus is adjusted according to the phase adjustment value in turn, and the link detection result of each phase adjustment value is obtained. Based on the link detection result, the phase adjustment value that passes the detection is determined, and the target phase adjustment value is determined from the passed phase adjustment values ​​to ensure that the parallel bus can be stably connected.

[0071] During the specific implementation process, the signal sending end can send fixed pattern data to test the link to determine whether the parallel bus link can stably receive the pattern data. If the parallel bus link can stably receive after the phase adjustment, the link under the current adjustment value is recorded as available, otherwise it is recorded as unavailable. The test steps are repeated until the detection of all phase adjustment values ​​is completed and the detection results of all phase adjustment values ​​are obtained. For example, if there are 64 clock stages during the phase adjustment, the final detection result can be 64-bit data. The detection pass can be recorded as 1, and the detection fail can be recorded as 0. The obtained data is composed of 1 and 0.

[0072] In some possible implementations, performing link detection on the adjusted parallel bus in the above steps to obtain corresponding detection results includes: Get the preset detection cycle; Perform link detection on the adjusted parallel bus based on the detection cycle to obtain the connection status corresponding to each unit time interval; Get the detection result based on the connection status.

[0073] The detection cycle includes a plurality of unit time intervals.

[0074] The connection status may include connection success or connection failure, and the connection status may indicate whether the link is connected normally and whether the data received through the link is correct.

[0075] Specifically, a preset detection cycle is obtained, and for each phase adjustment value, the connection status corresponding to each unit time interval in the corresponding detection cycle is determined in turn, and the detection result is obtained based on the connection status of multiple unit time intervals, so as to select a phase adjustment value with a better connection status.

[0076] In the specific implementation process, the phase of the parallel bus is adjusted based on the phase adjustment value, and then the connection status corresponding to each clock is determined within a predetermined detection cycle to detect whether the data sent by the signal sending end can be correctly received within a certain number of consecutive cycles, thereby obtaining the detection result corresponding to the phase adjustment value based on a certain number of connection states.

[0077] In some possible implementations, obtaining the detection result based on the connection status in the above steps includes: Determine the number of consecutive intervals during which the connection state is successfully connected; If the proportion of the number of consecutive intervals of successful connection to the detection period is greater than or equal to the preset threshold, the detection result is determined to be passed; If the proportion of the number of consecutive intervals of successful connection to the detection period is less than a preset threshold, the detection result is determined to be failed.

[0078] The connection status includes connection success or connection failure.

[0079] Specifically, during the detection period, the number of consecutive intervals in which the connection status is successfully connected is determined. If the proportion of the consecutive intervals in which the connection is successfully connected to the detection period is greater than or equal to the preset threshold, the detection result is determined to be passed. If the proportion of the consecutive intervals in which the connection is successfully connected to the detection period is less than the preset threshold, the detection result is determined to be failed. The detection results are judged for all phase adjustment values ​​until the detection is completed.

[0080] For example, a connection status of successful connection may indicate that the data or data frame received by the signal receiving end is correct. The detection period is set to 500 unit time intervals to determine whether the link can continuously and correctly receive a preset number of data or data frames within the 500 unit time interval. The receiving counter can be used to record the number of correct receptions. If the reception is correct, the receiving counter is incremented by one. If an error occurs in the reception, the receiving counter is cleared to continue detecting the data in the next unit time interval. If the number of consecutive correct receptions recorded by the counter reaches the preset number, the detection result of the phase adjustment value corresponding to the detection period is passed. Otherwise, the detection result of the phase adjustment value corresponding to the detection period is failed.

[0081] In the specific implementation process, if it is determined whether the data is received correctly, the unit used for receiving the determination is the data of a unit time interval, that is, the data sampled once by multiple parallel signal lines; if it is determined whether the data frame is received correctly, the unit used for receiving the determination is a data frame of a certain length. If the data frame is received correctly, the receiving counter is increased by one. Once a frame header is wrong, the receiving counter will be cleared and the counting will start again. The data frame includes a fixed data length and a corresponding frame header. For example, there is a frame header every 64 bits of data, and the frame header is used for frame alignment.

[0082] In some possible implementations, determining the target phase adjustment value based on each detection result in the above steps includes: Based on each detection result, clustering each phase adjustment value corresponding to the detection result to obtain multiple clusters and corresponding cluster centers; The cluster center whose corresponding detection result is passed is taken as the candidate cluster center; The candidate cluster center with the largest cluster among the candidate cluster centers is taken as the target cluster center; Based on the target cluster center, a target phase adjustment value is determined.

[0083] The largest cluster means that the cluster contains the most phase adjustment values ​​and has the largest length.

[0084] Specifically, based on each detection result, each phase adjustment value corresponding to the detection result is clustered, that is, each phase adjustment value for which the detection result is passed is clustered, and each phase adjustment value for which the detection result is not passed is clustered, and multiple clusters and corresponding cluster centers are obtained, and the cluster center for which the corresponding detection result is passed is used as a candidate cluster center, and the candidate cluster center with the largest cluster among the candidate cluster centers is used as a target cluster center, and the phase adjustment value area corresponding to the largest cluster is obtained, and the target phase adjustment value is selected from the area, so that the corresponding optimal phase value can be determined to set the phase of the parallel bus to the optimal phase value. By selecting the largest reliable adjustment area and determining the cluster center position of the area as the target phase adjustment value, it can be ensured that the link still has sufficient tolerance when there is jitter or temperature or voltage changes, thereby ensuring the stable connection of the link.

[0085] During the specific implementation process, each detection result can be arranged based on the size of the phase adjustment value, and adjacent detection results with the same detection results can be regarded as a cluster, and multiple clusters and corresponding cluster centers can be obtained. Since the detection results in the clusters are the same, the cluster with a passed cluster center is taken as a candidate cluster, and the largest cluster is selected from the candidate clusters. The phase adjustment value corresponding to the cluster center of the largest cluster is obtained as the target phase adjustment value.

[0086] For example, if there are n clock stages, the detection result can be n-bit data. Passing the detection can be recorded as 1, and failing the detection can be recorded as 0. The obtained data is composed of 1 and 0. The adjacent available 1s in the n-bit result data are regarded as continuous clusters of passing the detection. The cluster center of the largest continuous cluster of passing the detection is determined as the target cluster center. Furthermore, the adjacency between the 0th bit and the n-1th bit is also considered, including the situation where the target cluster center is at the junction of the head and the tail, so that the selection of the phase adjustment value of this scheme is more reliable.

[0087] In some possible implementations, in the above steps, based on the detection results, the phase adjustment values ​​corresponding to the detection results are clustered to obtain multiple clusters and corresponding cluster centers, including: Arrange the detection results according to the corresponding phase adjustment values ​​to obtain an arrangement result; Based on the arrangement result, each phase adjustment value corresponding to the detection result is clustered to obtain multiple clusters and corresponding cluster centers.

[0088] Among them, the first detection result and the last detection result in the arrangement result are adjacent.

[0089] Specifically, each detection result is arranged according to the size of the corresponding phase adjustment value, which can be arranged from small to large or from large to small, and the sorted arrangement result is obtained. Based on the arrangement result, the phase adjustment values ​​corresponding to the detection result are clustered to obtain multiple clusters and corresponding cluster centers.

[0090] In the specific implementation process, Figure 5 As shown, the detection results are arranged, and the first detection result and the last detection result are adjacent to each other, so as to obtain the ring structure shown in the figure. The detection results corresponding to each phase adjustment value are searched in a ring to find a cluster consisting of all phase adjustment values ​​that can be stably connected. Since the phase is periodic, for the detection results of n phase adjustment values, the 0th bit is adjacent to the n-1th bit, and a continuous and available phase segment can also be formed in the adjacent phase adjustment values. The detection result of passing is marked as 1, and the detection result of failing is marked as 0. The longest available cluster is selected as the candidate phase range, that is, the largest cluster passing through the 0th bit and the n-1th bit and having the detection result marked as 1 can be selected.

[0091] In the specific implementation process, the largest cluster and the optimal phase adjustment value corresponding to the cluster center can be found based on the register. If the phase adjustment has N clock stages, the N-bit detection result is saved in the register, where the leftmost bit of the register is the highest bit N-1, and the rightmost bit is the lowest bit 0, N-1>0, and the data in the register is cyclically right-shifted N times. The cyclic right shift refers to moving from the n-bit detection result to the n-1-bit detection result (n>0), and then from the 0th bit to the N-1th bit. Each time the cyclic right shift is performed, the value in the register will be updated. For example, the detection result of passing is marked as 1, and the detection result of failing is marked as 0, and a 5-bit data such as 01110 is obtained. After cyclic right shift once, it becomes 00111. The maximum number obtained by the current circular right shift will be saved in the register. The current value is compared with the saved maximum number. If the current value is greater than the saved maximum number, the maximum number and the number of times the maximum number is moved are updated, otherwise it is not updated. After the circular right shift N times, the saved maximum number is the cluster with the maximum length. For an n-bit register, the largest cluster can be found after n shifts. For example, the largest number after 1001111001111 is 1111100111100 after multiple shifts. It can be determined that the largest cluster is 11111, realizing the search for the maximum cluster of the ring structure. Then, the center of the largest cluster is found according to the algorithm, and the position of the optimal target phase adjustment value is calculated according to the number of moves corresponding to the current largest cluster and the center point.

[0092] In some possible implementations, in the above steps, adjusting the parallel bus to be adjusted based on the target phase adjustment value includes: Adjusting the clock phase of the parallel bus to be adjusted based on the target phase adjustment value; Performing link detection on the adjusted parallel bus; If the link detection passes, the phase adjustment of the parallel bus is completed.

[0093] Specifically, the clock phase of the parallel bus to be adjusted is adjusted based on the target phase adjustment value, and the link detection is performed again on the adjusted parallel bus. If the link detection passes, the phase adjustment of the parallel bus is completed. If the detection confirms that a stable connection can be made, the phase adjustment of the parallel bus is completed. Otherwise, the above process is re-executed to determine a new phase adjustment value.

[0094] In the specific implementation process, the solution in the embodiment of the present application can be used in conjunction with the dynamic phase adjustment of the signal receiving end to achieve link phase optimization when the signal sending end only has the function of sending fixed pattern data or a simple detection packet. Even if the signal sending end does not have a complex training structure, as long as it has the function of sending fixed pattern data or a simple packet structure for connection checking, the solution can also be applied. This provides feasibility for many scenarios where only single-ended chips can be modified.

[0095] In the above embodiment, the unit time interval is divided by a preset phase adjustment window, so that the unit time interval can be divided into smaller segments, and a more precise clock stage is obtained for phase adjustment. The target phase adjustment value obtained in this way is applied to a high-speed parallel bus, which enables the data signal to be correctly sampled within a very small effective interval. For example, on a 16-bit or 32-bit high-speed parallel bus, when the available reliable sampling window is less than 5% of the unit time interval, reliable transmission at a higher rate can be maintained, effectively improving the signal transmission efficiency of the high-speed parallel bus.

[0096] Furthermore, the phase of the parallel bus is adjusted in sequence based on the phase adjustment value determined in the clock stage. After each phase adjustment, the link detection is performed on the parallel bus to determine whether the link is connected normally. A certain number of unit time intervals can be set during the link detection process, and the connection status is determined for each unit time interval. According to the number of cycles in which the connection status is successful in these unit time intervals, it is determined whether the corresponding phase adjustment detection result passes according to the number of successful cycles. Phase adjustment values ​​with smaller fluctuations in the periodic connection status can be screened out, and the obtained target phase adjustment value is more accurate, thereby improving the stability of the high-speed parallel bus signal transmission process.

[0097] In addition, according to the detection results corresponding to different phase adjustment values, the corresponding phase adjustment values ​​are clustered to obtain multiple clusters. The link detection results in each cluster are the same. The cluster center of the cluster is determined, and the candidate cluster center whose corresponding detection result passes is determined. The target cluster center with the largest cluster is selected, and the phase adjustment value corresponding to the cluster center is used as the target phase adjustment value. A relatively stable adjustment value range can be determined through the largest cluster. The cluster center is selected within the range to determine the target phase adjustment value. The parallel bus is more stable after adjustment based on the target phase adjustment value. Even if the clock phase deviation occurs due to other reasons during the communication process, the stable connection of the signal can still be maintained.

[0098] In one example, the parallel bus link training method of the present application is as follows: Figure 6 As shown, it may include: The signal receiving end detects that the signal transmitting end starts to send a signal and starts link training, wherein the link training is used to adjust the clock phase of the parallel bus to optimize the performance of the parallel bus communication link; Determining a unit time interval of the parallel bus to be adjusted; Based on a preset phase adjustment window, a unit time interval is continuously divided into multiple (i.e., N as shown in the figure) non-overlapping clock segments, and the clock segments are sequentially accumulated to obtain multiple clock phases; Based on each clock phase (i.e., n phases shown in the figure), determining a phase adjustment value for the parallel bus to be adjusted; Based on each phase adjustment value, the phase of the parallel bus to be adjusted is adjusted in sequence (i.e., the phase is moved to n / N as shown in the figure); Obtaining a preset detection cycle, wherein the detection cycle includes a plurality of unit time intervals; Performing link detection on the parallel bus after phase adjustment based on the detection cycle to obtain the connection status corresponding to each unit time interval; wherein the connection status includes successful connection; Determine the number of consecutive intervals during which the connection state is successfully connected; If the ratio of the number of consecutive intervals of successful connection to the detection period is greater than or equal to the preset threshold, the detection result is determined to be passed; if the ratio of the number of consecutive intervals of successful connection to the detection period is less than the preset threshold, the detection result is determined to be failed (i.e., the check link shown in the figure can be connected); Record the detection results after each phase adjustment value is adjusted until the detection results of all phase adjustment values ​​are obtained (i.e., n=N-1 as shown in the figure); Arrange the detection results according to the corresponding phase adjustment values ​​to obtain an arrangement result; wherein the first detection result and the last detection result in the arrangement result are adjacent (i.e., a ring shape as shown in the figure); Based on the arrangement results, the phase adjustment values ​​corresponding to the detection results are clustered to obtain multiple clusters and corresponding cluster centers; The cluster center with the corresponding detection result of passing is taken as the candidate cluster center; the candidate cluster center with the largest cluster among the candidate cluster centers (that is, the largest cluster in the figure) is taken as the target cluster center (that is, the central position shown in the figure); Based on the target cluster center, determining a target phase adjustment value; Adjust the clock phase of the parallel bus to be adjusted based on the target phase adjustment value (i.e., set the optimal phase of movement as shown in the figure), and perform link detection on the adjusted parallel bus; Determine whether the link detection is passed. If the link detection is passed, complete the phase adjustment of the parallel bus and exit the link training process; If the link test fails, continue with the above steps (i.e. if it fails as shown in the figure, restart the line training).

[0099] The above-mentioned parallel bus link training method divides the unit time interval by a preset phase adjustment window, and can divide the unit time interval into smaller segments to obtain a more precise clock stage for phase adjustment. The target phase adjustment value obtained in this way is applied to a high-speed parallel bus, which can enable the data signal to be correctly sampled within a very small effective interval. For example, on a 16-bit or 32-bit high-speed parallel bus, when the available reliable sampling window is less than 5% of the unit time interval, reliable transmission at a higher rate can be maintained, effectively improving the signal transmission efficiency of the high-speed parallel bus.

[0100] Furthermore, the phase of the parallel bus is adjusted in sequence based on the phase adjustment value determined in the clock stage. After each phase adjustment, the link detection is performed on the parallel bus to determine whether the link is connected normally. A certain number of unit time intervals can be set during the link detection process, and the connection status is determined for each unit time interval. According to the number of cycles in which the connection status is successful in these unit time intervals, it is determined whether the corresponding phase adjustment detection result passes according to the number of successful cycles. Phase adjustment values ​​with smaller fluctuations in the periodic connection status can be screened out, and the obtained target phase adjustment value is more accurate, thereby improving the stability of the high-speed parallel bus signal transmission process.

[0101] In addition, according to the detection results corresponding to different phase adjustment values, the corresponding phase adjustment values ​​are clustered to obtain multiple clusters. The link detection results in each cluster are the same. The cluster center of the cluster is determined, and the candidate cluster center whose corresponding detection result passes is determined. The target cluster center with the largest cluster is selected, and the phase adjustment value corresponding to the cluster center is used as the target phase adjustment value. A relatively stable adjustment value range can be determined through the largest cluster. The cluster center is selected within the range to determine the target phase adjustment value. The parallel bus is more stable after adjustment based on the target phase adjustment value. Even if the clock phase deviation occurs due to other reasons during the communication process, the stable connection of the signal can still be maintained.

[0102] The present application embodiment provides a parallel bus link training device, such as Figure 7 As shown, the parallel bus link training device 70 may include: an interval acquisition module 701, a phase division module 702 and a phase adjustment module 703, wherein: The interval acquisition module 701 is used to acquire the unit time interval of the parallel bus to be adjusted; A phase division module 702, configured to divide a unit time interval based on a preset phase adjustment window to obtain a plurality of clock phases; The phase adjustment module 703 is used to sequentially perform phase adjustment on the parallel bus to be adjusted based on multiple clock phases, determine a target phase adjustment value, and adjust the parallel bus to be adjusted based on the target phase adjustment value.

[0103] As an optional embodiment, in the device, the stage division module 702 is specifically used to: Based on a preset phase adjustment window, a unit time interval is continuously divided into a plurality of non-overlapping clock segments; The clock segments are sequentially accumulated to obtain multiple clock stages.

[0104] As an optional embodiment, in the device, the phase adjustment module 703 is specifically used for: Determining a phase adjustment value for the parallel bus to be adjusted based on each clock phase; The phases of the parallel buses to be adjusted are adjusted in sequence based on the phase adjustment values, and the adjusted parallel buses are detected to determine the target phase adjustment value.

[0105] As an optional embodiment, in the device, the phase adjustment module 703 is specifically used for: sequentially performing phase adjustment on the parallel buses to be adjusted based on the phase adjustment values; Performing link detection on the adjusted parallel bus to obtain corresponding detection results; Based on each detection result, a target phase adjustment value is determined.

[0106] As an optional embodiment, in the device, the phase adjustment module 703 is specifically used for: Obtaining a preset detection cycle; the detection cycle includes multiple unit time intervals; Perform link detection on the adjusted parallel bus based on the detection cycle to obtain the connection status corresponding to each unit time interval; Get the detection result based on the connection status.

[0107] As an optional embodiment, in the device, the phase adjustment module 703 is specifically used for: The number of consecutive intervals during which the connection state is determined to be a successful connection; the connection state includes a successful connection; If the proportion of the number of consecutive intervals of successful connection to the detection period is greater than or equal to the preset threshold, the detection result is determined to be passed; If the proportion of the number of consecutive intervals of successful connection to the detection period is less than a preset threshold, the detection result is determined to be failed.

[0108] As an optional embodiment, in the device, the phase adjustment module 703 is specifically used for: Based on each detection result, clustering each phase adjustment value corresponding to the detection result to obtain multiple clusters and corresponding cluster centers; The cluster center whose corresponding detection result is passed is taken as the candidate cluster center; The candidate cluster center with the largest cluster among the candidate cluster centers is taken as the target cluster center; Based on the target cluster center, a target phase adjustment value is determined.

[0109] As an optional embodiment, in the device, the phase adjustment module 703 is specifically used for: Arrange the detection results according to the corresponding phase adjustment values ​​to obtain an arrangement result; the first detection result and the last detection result in the arrangement result are adjacent; Based on the arrangement result, each phase adjustment value corresponding to the detection result is clustered to obtain multiple clusters and corresponding cluster centers.

[0110] As an optional embodiment, in the device, the phase adjustment module 703 is specifically used for: Adjusting the clock phase of the parallel bus to be adjusted based on the target phase adjustment value; Performing link detection on the adjusted parallel bus; If the link detection passes, the phase adjustment of the parallel bus is completed.

[0111] The parallel bus link training device provided in the present application divides the unit time interval into smaller segments by a preset phase adjustment window, thereby obtaining a more refined clock phase for phase adjustment. The target phase adjustment value obtained in this way is applied to a high-speed parallel bus, which enables the data signal to be correctly sampled within an extremely small effective interval. For example, on a 16-bit or 32-bit high-speed parallel bus, when the available reliable sampling window is less than 5% of the unit time interval, reliable transmission at a higher rate can be maintained, thereby effectively improving the signal transmission efficiency of the high-speed parallel bus.

[0112] Furthermore, the phase of the parallel bus is adjusted in sequence based on the phase adjustment value determined in the clock stage. After each phase adjustment, the link detection is performed on the parallel bus to determine whether the link is connected normally. A certain number of unit time intervals can be set during the link detection process, and the connection status is determined for each unit time interval. According to the number of cycles in which the connection status is successful in these unit time intervals, it is determined whether the corresponding phase adjustment detection result passes according to the number of successful cycles. Phase adjustment values ​​with smaller fluctuations in the periodic connection status can be screened out, and the obtained target phase adjustment value is more accurate, thereby improving the stability of the high-speed parallel bus signal transmission process.

[0113] In addition, according to the detection results corresponding to different phase adjustment values, the corresponding phase adjustment values ​​are clustered to obtain multiple clusters. The link detection results in each cluster are the same. The cluster center of the cluster is determined, and the candidate cluster center whose corresponding detection result passes is determined. The target cluster center with the largest cluster is selected, and the phase adjustment value corresponding to the cluster center is used as the target phase adjustment value. A relatively stable adjustment value range can be determined through the largest cluster. The cluster center is selected within the range to determine the target phase adjustment value. The parallel bus is more stable after adjustment based on the target phase adjustment value. Even if the clock phase deviation occurs due to other reasons during the communication process, the stable connection of the signal can still be maintained.

[0114] The device of the embodiment of the present application can execute the method provided by the embodiment of the present application, and its implementation principle is similar and has corresponding technical effects. The actions performed by each module in the device of each embodiment of the present application correspond to the steps in the method of each embodiment of the present application. For the detailed functional description of each module of the device, please refer to the description in the corresponding method shown in the previous text, which will not be repeated here.

[0115] An electronic device is provided in an embodiment of the present application, including a memory, a processor and a computer program stored in the memory, and the processor executes the above computer program to implement the steps of the method provided in any optional embodiment of the present application. Compared with the prior art, it can be achieved that: by dividing the unit time interval through a preset phase adjustment window, the unit time interval can be divided into smaller segments, and a more refined clock phase is obtained to perform phase adjustment. The target phase adjustment value obtained in this way is applied to a high-speed parallel bus, which can enable the data signal to be correctly sampled within a very small effective interval. For example, on a 16-bit or 32-bit high-speed parallel bus, when the available reliable sampling window is less than 5% of the unit time interval, reliable transmission at a higher rate can be maintained, effectively improving the signal transmission efficiency of the high-speed parallel bus.

[0116] In an alternative embodiment, an electronic device is provided, such as Figure 8 As shown, Figure 8 The electronic device 8000 shown includes: a processor 8001 and a memory 8003. The processor 8001 and the memory 8003 are connected, such as through a bus 8002. Optionally, the electronic device 8000 may also include a transceiver 8004, which may be used for data interaction between the electronic device and other electronic devices, such as data transmission and / or data reception. It should be noted that in actual applications, the transceiver 8004 is not limited to one, and the structure of the electronic device 8000 does not constitute a limitation on the embodiments of the present application.

[0117] The processor 8001 may be a CPU (Central Processing Unit), a general-purpose processor, a DSP (Digital Signal Processor), an ASIC (Application Specific Integrated Circuit), an FPGA (Field Programmable Gate Array) or other programmable logic devices, transistor logic devices, hardware components or any combination thereof. It may implement or execute various exemplary logic blocks, modules and circuits described in conjunction with the disclosure of this application. The processor 8001 may also be a combination that implements computing functions, such as a combination of one or more microprocessors, a combination of a DSP and a microprocessor, etc.

[0118] The bus 8002 may include a path to transmit information between the above components. The bus 8002 may be a PCI (Peripheral Component Interconnect) bus or an EISA (Extended Industry Standard Architecture) bus. The bus 8002 may be divided into an address bus, a data bus, a control bus, etc. For ease of representation, Figure 8 Only one thick line is used in the diagram, but this does not mean that there is only one bus or only one type of bus.

[0119] The memory 8003 may be a ROM (Read Only Memory) or other types of static storage devices that can store static information and instructions, a RAM (Random Access Memory) or other types of dynamic storage devices that can store information and instructions, or an EEPROM (Electrically Erasable Programmable Read Only Memory), a CD-ROM (Compact Disc Read Only Memory) or other optical disk storage, optical disk storage (including compressed optical disk, laser disk, optical disk, digital versatile disk, Blu-ray disk, etc.), magnetic disk storage medium, other magnetic storage devices, or any other medium that can be used to carry or store computer programs and can be read by a computer, without limitation herein.

[0120] The memory 8003 is used to store the computer program for executing the embodiment of the present application, and the execution is controlled by the processor 8001. The processor 8001 is used to execute the computer program stored in the memory 8003 to implement the steps shown in the above method embodiment.

[0121] The electronic equipment includes but is not limited to: a terminal or a server configured with a parallel bus transmission system.

[0122] An embodiment of the present application provides a computer-readable storage medium, on which a computer program is stored. When the computer program is executed by a processor, the steps and corresponding contents of the aforementioned method embodiment can be implemented.

[0123] It should be noted that the computer-readable storage medium mentioned above in the present application may be a computer-readable signal medium or a computer-readable storage medium or any combination of the above two. The computer-readable storage medium may be, for example, but not limited to, an electrical, magnetic, optical, electromagnetic, infrared, or semiconductor system, device or device, or any combination of the above. More specific examples of computer-readable storage media may include, but are not limited to: an electrical connection with one or more wires, a portable computer disk, a hard disk, a random access memory (RAM), a read-only memory (ROM), an erasable programmable read-only memory (EPROM or flash memory), an optical fiber, a portable compact disk read-only memory (CD-ROM), an optical storage device, a magnetic storage device, or any suitable combination of the above.

[0124] The embodiment of the present application also provides a computer program product, including a computer program, which can implement the steps and corresponding contents of the aforementioned method embodiment when executed by a processor.

[0125] The terms "first", "second", "third", "fourth", "1", "2", etc. (if any) in the specification and claims of this application and the above-mentioned drawings are used to distinguish similar objects, and are not necessarily used to describe a specific order or sequence. It should be understood that the numbers used in this way can be interchanged where appropriate, so that the embodiments of the present application described herein can be implemented in an order other than that shown or described in the drawings.

[0126] The flow chart and block diagram in the accompanying drawings illustrate the possible architecture, function and operation of the system, method and computer program product according to various embodiments of the present application. In this regard, each square box in the flow chart or block diagram can represent a module, a program segment or a part of a code, and the module, the program segment or a part of the code contains one or more executable instructions for realizing the specified logical function. It should also be noted that in some alternative implementations, the functions marked in the square box can also occur in a sequence different from that marked in the accompanying drawings. For example, two square boxes represented in succession can actually be executed substantially in parallel, and they can sometimes be executed in the opposite order, depending on the functions involved. It should also be noted that each square box in the block diagram and / or flow chart, and the combination of the square boxes in the block diagram and / or flow chart can be implemented with a dedicated hardware-based system that performs a specified function or operation, or can be implemented with a combination of dedicated hardware and computer instructions.

[0127] It should be understood that, although each operation step is indicated by arrows in the flowchart of the embodiment of the present application, the implementation order of these steps is not limited to the order indicated by the arrows. Unless clearly stated herein, in some implementation scenarios of the embodiment of the present application, the implementation steps in each flowchart can be performed in other orders according to demand. In addition, some or all of the steps in each flowchart may include multiple sub-steps or multiple stages based on actual implementation scenarios. Some or all of these sub-steps or stages may be executed at the same time, and each sub-step or stage in these sub-steps or stages may also be executed at different times respectively. In different scenarios of execution time, the execution order of these sub-steps or stages may be flexibly configured according to demand, and the embodiment of the present application does not limit this.

[0128] The above is only an optional implementation method for some implementation scenarios of the present application. It should be pointed out that for ordinary technicians in this technical field, without departing from the technical concept of the solution of the present application, other similar implementation methods based on the technical ideas of the present application are also within the protection scope of the embodiments of the present application.

Claims

1. A parallel bus link training method, characterized in that: include: Get the unit time interval of the parallel bus to be adjusted; Dividing the unit time interval based on a preset phase adjustment window to obtain multiple clock phases; The parallel bus to be adjusted is phase-adjusted in sequence based on the multiple clock phases, a target phase adjustment value is determined, and the parallel bus to be adjusted is adjusted based on the target phase adjustment value.

2. The parallel bus link training method according to claim 1, characterized in that: The step of dividing the unit time interval based on a preset phase adjustment window to obtain a plurality of clock phases includes: Based on the preset phase adjustment window, a plurality of non-overlapping clock segments are continuously divided in a unit time interval; The clock segments are sequentially accumulated to obtain the multiple clock phases.

3. The parallel bus link training method according to claim 1, characterized in that: The step of sequentially performing phase adjustment on the parallel bus to be adjusted based on the multiple clock phases to determine a target phase adjustment value includes: Determining a phase adjustment value for the parallel bus to be adjusted based on each of the clock phases; The phase of the parallel bus to be adjusted is adjusted in sequence based on each of the phase adjustment values, and the adjusted parallel bus is detected to determine a target phase adjustment value.

4. The parallel bus link training method according to claim 3, characterized in that: The phase adjustment of the parallel bus to be adjusted is performed in sequence based on each of the phase adjustment values, and the adjusted parallel bus is detected to determine a target phase adjustment value, including: sequentially performing phase adjustment on the parallel bus to be adjusted based on each of the phase adjustment values; Performing link detection on the adjusted parallel bus to obtain corresponding detection results; Based on each of the detection results, the target phase adjustment value is determined.

5. The parallel bus link training method according to claim 4, characterized in that: The performing link detection on the adjusted parallel bus to obtain a corresponding detection result includes: Obtaining a preset detection cycle; the detection cycle includes a plurality of the unit time intervals; Performing link detection on the adjusted parallel bus based on the detection period to obtain a connection state corresponding to each unit time interval; Based on the connection status, the detection result is obtained.

6. The parallel bus link training method according to claim 5, characterized in that: The connection status includes connection success; The acquiring the detection result based on the connection state includes: Determine the number of consecutive intervals in which the connection state is successfully connected; If the proportion of the number of consecutive intervals of successful connection to the detection period is greater than or equal to a preset threshold, the detection result is determined to be passed; If the proportion of the number of consecutive intervals of successful connection to the detection period is less than the preset threshold, the detection result is determined to be failed.

7. The parallel bus link training method according to claim 6, characterized in that: The step of determining the target phase adjustment value based on each of the detection results includes: Based on the detection results, clustering the phase adjustment values ​​corresponding to the detection results to obtain a plurality of clusters and corresponding cluster centers; The cluster center whose corresponding detection result is passed is taken as the candidate cluster center; The candidate cluster center with the largest cluster among the candidate cluster centers is used as the target cluster center; Based on the target cluster center, the target phase adjustment value is determined.

8. The parallel bus link training method according to claim 7, characterized in that: Based on the detection results, clustering the phase adjustment values ​​corresponding to the detection results to obtain multiple clusters and corresponding cluster centers includes: Arrange the detection results according to the corresponding phase adjustment values ​​to obtain an arrangement result, wherein the first detection result and the last detection result in the arrangement result are adjacent; Based on the arrangement result, the phase adjustment values ​​corresponding to the detection results are clustered to obtain the multiple clusters and corresponding cluster centers.

9. The parallel bus link training method according to claim 1, characterized in that: The adjusting the parallel bus to be adjusted based on the target phase adjustment value comprises: Adjusting the clock phase of the parallel bus to be adjusted based on the target phase adjustment value; Performing link detection on the adjusted parallel bus; If the link detection passes, the phase adjustment of the parallel bus is completed.

10. A parallel bus link training device, characterized in that: include: An interval acquisition module, used for acquiring a unit time interval of the parallel bus to be adjusted; A phase division module, used to divide the unit time interval based on a preset phase adjustment window to obtain multiple clock phases; The phase adjustment module is used to sequentially perform phase adjustment on the parallel bus to be adjusted based on the multiple clock phases, determine a target phase adjustment value, and adjust the parallel bus to be adjusted based on the target phase adjustment value.

11. An electronic device comprising a memory, a processor and a computer program stored in the memory, characterized in that: The processor executes the computer program to implement the steps of the parallel bus link training method according to any one of claims 1 to 9.

12. A computer-readable storage medium having a computer program stored thereon, characterized in that: When the computer program is executed by a processor, the steps of the parallel bus link training method according to any one of claims 1 to 9 are implemented.

13. A computer program product, comprising a computer program, characterized in that When the computer program is executed by a processor, the steps of the parallel bus link training method according to any one of claims 1 to 9 are implemented.

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