A FPGA heterogeneous cloud computing method supporting concurrent access

Abstract

The present application discloses an FPGA heterogeneous cloud computing method supporting concurrent access. For a CPU-FPGA heterogeneous cloud computing architecture, the FPGA heterogeneous cloud computing method comprises: virtualizing the FPGA and dividing the FPGA into a static area, a service area, and a dynamic area; and using a virtual memory to load a resource scheduling algorithm, so that the service area can load corresponding functional circuits according to specific needs, and when the corresponding function is not needed, the corresponding hardware resources of the service area are allocated to the dynamic area; through the design of the FPGA heterogeneous cloud computing method of the present application, the user experience is maximized and the waste of FPGA computing resources is minimized.

Description

Technical Field

[0001] The present application belongs to the field of cloud computing technology, and in particular, relates to an FPGA heterogeneous cloud computing method supporting concurrent access. Background Art

[0002] In recent decades, cloud computing has become popular due to its powerful computing power, storage capacity, and pay-as-you-go functionality. After using cloud computing services, users do not need to maintain infrastructure such as computing power, storage, and communication equipment, which greatly reduces the cost of using computing resources. This infrastructure-as-a-service (IaaS) provides computing power support for computing-intensive tasks such as simulation, media decompression, deep learning, and big data processing. The increasing computing demand brought by artificial intelligence networks has led to the inability of traditional CPU (Central Processing Unit) parallel computing to meet our demand for computing power, which has further accelerated the introduction of hardware accelerators. Common hardware accelerators include GPU (Graphics Processing Unit), FPGA (Field-Programmable Gate Array, FPGA), and ASIC (Application Specific Integrated Circuit). CPU is software programmable, with high versatility, and can be used for various software algorithms; ASIC circuit is a proprietary hardware circuit, which is not programmable and can only accelerate specific algorithms. It can achieve high-performance algorithm performance but has poor versatility; GPU is also software programmable. The difference from CPU is that GPU has many computing units. For algorithms that can be parallelized and require a lot of calculations at the same time, GPU has higher computing efficiency than CPU, but it cannot optimize the algorithm at the RTL (register transfer level) level; FPGA is a hardware circuit programmable accelerator. The same as ASIC is that it is also a hardware circuit built for algorithms, but it can design corresponding hardware circuits for each algorithm for hardware acceleration. Among various hardware accelerators, "CPU-FPGA" has become a mainstream heterogeneous computing method for performing computationally intensive tasks due to its programming flexibility, energy efficiency, and hardware optimization for algorithms.

[0003] Although "CPU-FPGA" heterogeneous computing can achieve several times or even dozens of times improvement in performance and energy efficiency compared to the more traditional "CPU-GPU" heterogeneous computing architecture, their programming paradigm in embedded systems and prototype design makes it difficult to program, deploy and securely manage them. Even if users use cloud-based FPGA computing resources, they still need to deal with complex hardware constraints and timing optimization issues during use. This makes the "CPU-FPGA" heterogeneous computing method far less easy to use than "CPU-GPU", because the latter uses the CUDA (Compute Unified Device Architecture) library to shield users from hardware details, and users do not need any technical knowledge about accelerator hardware to write corresponding heterogeneous computing programs. In order to solve the above problems of the "CPU-FPGA" heterogeneous computing method, some researchers borrowed the ideas of the "CPU-GPU" heterogeneous computing method and proposed Accelerator-as-a-Service (AaaS) for "CPU-FPGA" heterogeneous cloud computing based on Infrastructure as a Service (IaaS). AaaS virtualizes the computing resources of FPGA and shields the hardware details from users. Common FPGA computing resources include: storage resources RAM (random access memory), ROM (read-only memory), DRAM (distributed random access memory), etc.; computing resources: usually the area on the FPGA board that can be reconfigured by users; network resources: network stack, etc. The virtualized FPGA is divided into a static area and a dynamic area. The static area contains the necessary functions of partial reconfiguration (PR), the function of communicating with the CPU, and the network stack, etc. The dynamic area contains user logic and the user logic interface (UIL) responsible for connecting the dynamic area and the static area. Users can burn the hardware acceleration code to be executed into the dynamic area in the form of PR. At the same time, in order to improve the utilization rate of a single FPGA, a common practice is to further divide the dynamic area of ​​FPGA to obtain multiple virtualized vFPGAs (virtual FPGAs). Different users can burn their own user logic into different vFPGAs of a single FPGA in the form of PR to reduce the idle rate of FPGA resources. Although multi-user FPGA cloud resources can greatly improve resource utilization, they can also cause information leakage between different tenants.

[0004] At present, there are many challenges in the virtualization technology of "CPU-FPGA" heterogeneous cloud computing resources. The first challenge: There is a lack of a standardized virtualization method to virtualize FPGA into cloud resources, and it is impossible to efficiently and securely virtualize "CPU-FPGA" computing resources. The second challenge: The current "CPU-FPGA" heterogeneous cloud computing resources do not fully virtualize FPGAs, which means that users of "CPU-FPGA" heterogeneous cloud computing resources still need to have relevant hardware knowledge and the ability to handle hardware constraints and timing optimization problems, and have not truly realized AaaS. The third challenge: Multi-user "CPU-FPGA" heterogeneous cloud computing resources need to process hardware acceleration requests from different users in real time, but because the context switch of FPGA uses PR to switch between different user logics, each context switch requires a large time overhead. Therefore, how to design a reasonable scheduling algorithm to maximize the transmission rate, resource utilization, and minimize system power consumption or completion time is a problem that needs to be solved at present. Summary of the invention

[0005] The purpose of this application is to: in order to overcome the problems of the prior art, disclose an FPGA heterogeneous cloud computing method that supports concurrent access, and through the design of the FPGA heterogeneous cloud computing method of this application, maximize the user experience and minimize the waste of FPGA computing resources.

[0006] The purpose of this application is achieved through the following technical solutions:

[0007] An FPGA heterogeneous cloud computing method supporting concurrent access, for a CPU-FPGA heterogeneous cloud computing architecture, the FPGA heterogeneous cloud computing method includes:

[0008] Virtualize the FPGA and divide it into static area, service area and dynamic area. Use virtual memory to load resource scheduling algorithm, so that the service area can load corresponding functional circuits according to specific needs, and allocate corresponding hardware resources of the service area to the dynamic area when the corresponding function is not needed.

[0009] Wherein, the static area includes: an xDMA data path for communication between the PGA and the CPU, a circuit for partitioning the dynamic area and the service area, and partially reconstructing the dynamic area and the service area;

[0010] The service area is an expandable general functional area, and the expandable content includes: a network protocol stack, an FPGA memory management module; and uses the RDMA protocol to remotely access the memory of the FPGA;

[0011] The dynamic area includes: a read-write state machine, a bypass translation buffer TLB, a user logic interface UIL, and a partially reconfigurable user logic area for storing user logic, and the user logic area is divided into a plurality of vFPGAs.

[0012] According to a preferred embodiment, during the operation of the CPU-FPGA heterogeneous cloud computing architecture,

[0013] The CPU-side driver reads the static region configuration from the FPGA, sets up data structures for the vFPGA set to be supported, and communicates with the FPGA's xDMA data path;

[0014] The xDMA data path uses the xDMA engine to implement data communication between the FPGA and the CPU, and transmits it to different blocks of the FPGA through the data bus;

[0015] The partial reconstruction circuit is responsible for accepting the PR request initiated by the CPU through the xDMA data path, and reconstructing the bit stream part of the corresponding circuit to the user logic area of ​​the corresponding vFPGA through the internal configuration access port; the partial reconstruction circuit can also reconstruct the dynamic area or service area to meet the extended function requirements of different users.

[0016] According to a preferred embodiment, the network protocol stack in the service area is responsible for processing various sending and receiving requests from the TCP / IP or RDMA protocol, and distributing them to the user logic interface of the corresponding vFPGA unit through the data bus in the form of AXI4 stream;

[0017] The FPGA memory management module is responsible for processing data transmission between vFPGA and FPGA off-chip memory, and each DDR has a corresponding DDR control unit in the FPGA memory management module to process data access requests between vFPGA and the specified FPGA off-chip DDR.

[0018] According to a preferred embodiment, the FPGA memory management module copies the physical memory content allocated by the host to the vFPGA to the FPGA memory through the xDMA engine, and establishes a unified mapping between the FPGA memory to the virtual memory and the host memory to the virtual memory;

[0019] vFPGA accesses the physical address corresponding to the vFPGA virtual address by sending the user logic descriptor to the read / write state machine. When a page fault exception occurs, the read / write state machine sends a page fault interrupt to the host driver. The host then updates the missing page of the host memory and copies it to the FPGA memory through the xDMA engine.

[0020] According to a preferred embodiment, the FPGA memory management module creates a corresponding number of DDR control units based on the actual number of DDRs. The DDR control units are responsible for sending data to the specified vFPGA read-write state machine through the data bus, and the read-write state machine integrates the data content of each DDR into serial data and sends it to the user logic area.

[0021] According to a preferred embodiment, the read / write state machine is responsible for processing data received and sent from different sources, including: data copied from the xDMA engine by the xDMA data path, data transmitted via the TCP / IP protocol, and forwarding communication data between the user logic and different sources;

[0022] The TLB is responsible for processing the mapping relationship between virtual memory and physical memory, so that the user logic can access the FPGA off-chip memory and the host memory using the xDMA engine in the static area in the form of virtual memory. The TLB and the read-write state machine together form the memory management unit MMU of the vFPGA, providing sandboxed memory access for the user logic.

[0023] The user logic interface is responsible for transmitting data communication between the user logic and the read / write state machine or other sources;

[0024] The user logic area is responsible for storing the general hardware acceleration circuit specified by the user or the hardware acceleration circuit customized by the user.

[0025] According to a preferred embodiment, the read / write state machine completes data processing from different sources through the following process, including:

[0026] The user logic implements the read and write requests by sending the user logic descriptor to the vFPGA configuration unit of the read and write state machine; the access request initiated by the host to the FPGA memory is converted into the host descriptor to realize the data transfer;

[0027] The read state machine is responsible for responding to the read request from the host or vFPGA and checking whether there is a page fault exception. When there is a page fault exception in the FPGA memory, the read state machine sends a page fault interrupt to the host driver, and the host driver loads the page corresponding to the virtual memory into the host memory and copies it to the FPGA memory through the xDMA engine.

[0028] The write state machine is responsible for responding to write requests from the host or vFPGA and checking whether there is a page fault exception. The user logic control signal is responsible for specifying the write address and write length.

[0029] According to a preferred embodiment, a TLB mutex lock is provided between the read state machine and the write state machine, and the TLB mutex lock is used to ensure that reading and writing are mutually exclusive operations, thereby ensuring the consistency of data in the memory.

[0030] According to a preferred implementation, the virtual memory loading resource scheduling algorithm includes a general hardware acceleration algorithm and a custom hardware acceleration algorithm.

[0031] The aforementioned main scheme of the present application and its further options can be freely combined to form multiple schemes, all of which are schemes that can be adopted and claimed for protection in the present application. After understanding the scheme of the present application, those skilled in the art can understand that there are multiple combinations based on the prior art and common knowledge, all of which are technical schemes to be protected by the present application, and they are not exhaustively listed here.

[0032] Beneficial effects of this application:

[0033] The present invention supports a unified FPGA virtualization execution environment for multiple users, secure time-space multiplexing of FPGA resources between tenants, and virtual memory, communication and memory management under a unified execution environment: the present invention divides the FPGA into a static area, a service area and a dynamic area, and provides an MMU for each vFPGA. The MMU module is responsible for processing the mapping between the vFPGA virtual address and the CPU physical memory address or the FPGA off-chip memory address, so that the user logic can access the CPU host memory or the FPGA off-chip memory in a sandboxed manner, and ensure that there is no memory sharing between different tenants. At the same time, the CPU side communicates with the FPGA side by accessing the memory area belonging to a specific vFPGA in the memory. In addition, the virtualization environment provides optional TCP / IP and RDMA protocol stacks in the service area. Users can choose to implement remote data communication of the FPGA through the TCP / IP or RDMA protocol on the FPGA side according to their needs, rather than using the TCP / IP protocol on the CPU side.

[0034] The present invention implements AaaS for some general hardware acceleration algorithms, and provides users with a hardware algorithm development framework with a high degree of encapsulation, simplifying the development process of heterogeneous acceleration algorithms. The present invention pre-synthesizes the bit files of some general hardware acceleration algorithms, such as large matrix multiplication, sparse matrix multiplication, large matrix SVD (single value decomposition) decomposition and QR decomposition, etc. Users can implement heterogeneous acceleration of corresponding algorithms by calling software APIs. In addition, users can also write custom hardware circuits as needed and synthesize bit files, burn them into vFPGA in a PR manner, and implement heterogeneous acceleration of algorithms with the help of virtualized FPGA resources. This FPGA virtualized execution environment shields users from details such as data communication and memory management. When developing custom hardware circuit logic, users only need to process data transmission in the form of AXI4 transactions at the hardware level and write corresponding user logic code, reducing the complexity of heterogeneous programming.

[0035] Aiming at FPGA heterogeneous cloud computing environment, a virtual memory loading resource scheduling algorithm is proposed to maximize user experience and minimize the running time of FPGA computing resources. This scheduling algorithm regards FPGA heterogeneous cloud computing resources as a resource pool and divides it into general algorithm acceleration area and custom algorithm acceleration area. Linear programming is used to allocate users' hardware acceleration requests to different vFPGAs and reduce the number of PR of vFPGAs. BRIEF DESCRIPTION OF THE DRAWINGS

[0036] Figure 1 It is a schematic diagram of the system architecture of the FPGA heterogeneous computing method applicable to the cloud platform proposed by the present invention;

[0037] Figure 2 It is a schematic diagram of virtualizing a single FPGA;

[0038] Figure 3 This is the working principle of the read and write state machine of vFPGA;

[0039] Figure 4 It is a schematic diagram of the virtual memory mapping between FPGA and CPU;

[0040] Figure 5 It is a schematic diagram of the working principle of the FPGA memory management unit in the service area;

[0041] Figure 6 This is a schematic diagram of the user logic interface of the vFPGA;

[0042] Figure 7 It is the FPGA cloud computing resource scheduling algorithm proposed by the present invention. DETAILED DESCRIPTION

[0043] The following describes the embodiments of the present application through specific examples, and those skilled in the art can easily understand other advantages and effects of the present application from the contents disclosed in this specification. The present application can also be implemented or applied through other different specific embodiments, and the details in this specification can also be modified or changed in various ways based on different viewpoints and applications without departing from the spirit of the present application. It should be noted that the following embodiments and features in the embodiments can be combined with each other without conflict.

[0044] In addition, the present application would like to point out that, in the present application, unless the specific structure, connection relationship, positional relationship, power source relationship, etc. are specifically written out, the structure, connection relationship, positional relationship, power source relationship, etc. involved in the present application are all known by those skilled in the art on the basis of the prior art without creative work.

[0045] The present application discloses an FPGA heterogeneous cloud computing method supporting concurrent access. For a CPU-FPGA heterogeneous cloud computing architecture, the FPGA heterogeneous cloud computing method comprises: virtualizing the FPGA and dividing the FPGA into a static area, a service area, and a dynamic area; and using a virtual memory to load a resource scheduling algorithm so that the service area can load corresponding functional circuits according to specific needs, and when the corresponding functions are not needed, the corresponding hardware resources of the service area are allocated to the dynamic area.

[0046] The static area contains configuration information, the xDMA (xilinx direct memory access) data path for FPGA and CPU communication, and the necessary circuits for partitioning the dynamic area and service area and partial reconstruction. The service area is an expandable general functional area, and common expandable contents include: network protocol stack, FPGA memory management, etc. When users are sensitive to computing latency, they can choose to use the RDMA (remote direct memory access) protocol to remotely access the FPGA's memory to bypass PCIe, thereby reducing data communication latency. The dynamic area contains the read and write state machine, the translation lookaside buffer (TLB), and a partially reconfigurable user logic area that stores user logic.

[0047] In the case of FPGA virtualization, users can use virtual memory to write heterogeneous acceleration programs like writing CPU programs. They only need to process data transmission in the form of AXI4 transactions without having to consider too many hardware details, which significantly improves the programmability and usability of the system. The scalable service area can load the corresponding functional circuit according to the specific needs of the user. When the user does not need this function, the hardware resources of the service block can be allocated to the dynamic area to improve the utilization of idle hardware resources. This method provides users with a bit file that pre-synthesizes the general hardware acceleration algorithm. Users do not need to have knowledge of hardware development and can implement heterogeneous acceleration of the corresponding algorithm by calling the software API.

[0048] In addition, users can also use customized hardware acceleration algorithms as needed, and simplify the heterogeneous hardware acceleration algorithm development process with the help of hardware unified programming interfaces. This unified virtualization method provides users with a heterogeneous acceleration algorithm development environment at the software and hardware layers, reducing the complexity of heterogeneous acceleration algorithm development and improving the ease of use of FPGA heterogeneous cloud computing methods.

[0049] In terms of multi-user use, a single FPGA is divided into multiple vFPGAs, and the hardware acceleration requests of multiple users can be deployed to different vFPGAs of a single FPGA in the form of PR, which can improve the time and space utilization of FPGA computing resources under the premise of complying with the resource scheduling algorithm. When a user applies for multiple vFPGAs at the same time, data communication between multiple vFPGAs can be achieved through the inter-region communication queue of the user logic interface, thereby realizing the collaborative operation of multiple vFPGAs.

[0050] In terms of the optimal resource scheduling algorithm design, this application considers two user usage scenarios: general hardware acceleration algorithms and custom hardware acceleration algorithms. For general hardware acceleration algorithms, users can use pre-synthesized hardware algorithm bit files to implement heterogeneous hardware acceleration by calling software APIs. Therefore, in this scenario, the scheduling algorithm needs to consider the user's hardware acceleration algorithm type and user priority. Under conditions of tight computing resources, the scheduling algorithm assigns hardware acceleration requirements with the same acceleration algorithm type to the same task queue to reduce the number of PRs of vFPGA and minimize the waste of FPGA resources. For custom hardware acceleration algorithms, the scheduling algorithm gives priority to hardware algorithms with shorter execution time under the condition of the same priority, and increases the priority of remaining hardware algorithms after execution to avoid users waiting too long, so as to ensure the maximum user experience.

[0051] See also Figure 1 The system architecture of the FPGA heterogeneous computing method suitable for cloud platforms is as follows: Figure 1As shown, the firewall, routing, load balancing, database and database backup, cloud monitoring, and "CPU-FPGA" heterogeneous computing cluster required for FPGA heterogeneous cloud computing resources are included. Among them, the firewall is responsible for monitoring network traffic and filtering and managing network traffic according to preset rules to prevent network attacks, viruses and other network security threats, ensuring the availability of FPGA heterogeneous cloud computing resources and the privacy and security of users; routing and load balancing are responsible for processing user access requests to cloud computing resources, and according to the resource scheduling algorithm, assigning users to the corresponding cloud servers in the heterogeneous cluster to improve the availability, reliability and scalability of FPGA heterogeneous cloud computing resources; the database is responsible for storing user status information, bit files of general hardware acceleration algorithms, necessary software components of cloud computing services, bit files of user-defined hardware acceleration algorithms, hardware development environment and other necessary data. This part uses a backup database to ensure data reliability; cloud monitoring, as a management unit of cloud computing resources, is used to monitor the performance, availability and security of cloud resources, and is used to monitor the operating status, resource usage, network traffic, logs and alarms of cloud services, and provide real-time data analysis and visualization to help users quickly discover and solve problems and improve business stability and security; the heterogeneous computing cluster adopts the form of "CPU-FPGA". The FPGA cloud server is connected to the network through a dedicated PCIe (Peripheral Component Interconnect) Express, PCIe) structure is connected to the FPGA instance, and the resources of a single FPGA instance are virtualized and provided to users in the form of a resource pool. The resource pool is further divided into a general hardware acceleration algorithm resource pool and a custom hardware algorithm resource pool, providing users with a heterogeneous acceleration algorithm development environment at the software and hardware layers, reducing the complexity of heterogeneous acceleration algorithm development and improving the availability of FPGA heterogeneous cloud computing.

[0052] See also Figure 2 The virtualization method of a single FPGA is as follows: Figure 2The present invention divides a single FPGA into a static area, a service area, and a dynamic area. The static area includes an xDMA data path for communication between the FPGA and the CPU, and a necessary circuit for partitioning the dynamic area and partial reconstruction (PR). After the system is started, the driver on the CPU side reads the configuration of the static area from the FPGA, sets the data structure for the vFPGA set to be supported, and is responsible for communicating with the xDMA data path of the FPGA. In addition, the driver is also responsible for handling the page fault exception initiated by the MMU of the vFPGA; the xDMA data path uses the xDMA engine to realize the data communication between the FPGA and the CPU, and transmits it to different blocks of the FPGA through the data bus, among which xDMA path 1 is responsible for transmitting the static area configuration and the partially reconstructed circuit structure information, xDMA path 2 is responsible for transmitting the communication data between the host and the FPGA, xDMA data path 3 is responsible for transmitting the memory data communication between the host and the FPGA, and xDMA data path 4 is used to transmit the communication data required for the service area (in the figure, it is responsible for transmitting the FPGA memory data to the host memory); the partial reconstruction circuit is responsible for accepting the PR request initiated by the CPU side through the xDMA data path 1, and reconstructing the bit stream of the corresponding circuit to the user logic area of ​​the corresponding vFPGA through the internal configuration access port (internal configuration access port, ICAP). In addition, the partial reconstruction circuit can reconstruct the dynamic area or service area separately to meet the extended function requirements of different users.

[0053] The service area contains expandable content such as: network protocol stack, FPGA memory management and other optional content. Whether to enable the optional content of the service area is determined according to the specific needs of the user, so that the extra space can be used for the user logic area. Among them, the network protocol stack is responsible for processing various sending and receiving requests from the TCP / IP or RDMA protocol, and distributes them to the user logic interface of the corresponding vFPGA unit through the data bus in the form of AXI4 stream; FPGA memory management is responsible for processing data transmission between vFPGA and FPGA off-chip memory. Each DDR (double data rate synchronous dynamic random access memory) has a corresponding DDR control unit in the memory management unit to process data access requests from vFPGA and the specified FPGA off-chip DDR.

[0054] The dynamic area includes the read-write state machine, TLB, user logic interface (UIL), and a partially reconfigurable user logic area that stores user logic. The read-write state machine is responsible for processing data sent and received from different sources, such as data copied from the xDMA engine by the xDMA data path, data transmitted through the TCP / IP protocol, etc., and forwarding communication data between user logic and different sources; TLB is responsible for processing the mapping relationship between virtual memory and physical memory, so that user logic can use virtual memory to process user logic access to FPGA off-chip memory and host memory using the xDMA engine in the static area. TLB and the read-write state machine together constitute the vFPGA's memory management unit (MMU), providing sandboxed memory access for user logic; the user logic interface is a lower-level physical interface responsible for transmitting data communications between user logic and the read-write state machine or other sources. The detailed structural diagram is shown in Figure 6 As shown; the user logic area is responsible for storing the general hardware acceleration circuit specified by the user (the netlist data and other information of the hardware circuit are stored in the database on the CPU side, and are loaded onto the FPGA through the xDMA engine when used) or the hardware acceleration circuit customized by the user.

[0055] See also Figure 3 The working structure of the FPGA dynamic area read and write state machine is as follows: Figure 3 As shown. The user logic implements the read and write request by sending the user logic descriptor (base address + length) to the vFPGA configuration unit of the read and write state machine. The access request initiated by the host to the FPGA memory is also converted into a host descriptor to realize data transmission. Among them, the read state machine is responsible for responding to the read request of the host or vFPGA and checking whether there is a page fault exception. When there is a page fault exception in the FPGA memory, the read state machine sends a page fault interrupt to the host driver, and the host driver loads the page corresponding to the virtual memory into the host memory and copies it to the FPGA memory through the xDMA engine. The write state machine is responsible for responding to the write request of the host or vFPGA and checking whether there is a page fault exception. The user logic control signal is responsible for specifying the write address and write length. The TLB mutex lock is used to ensure that read and write are mutually exclusive operations to ensure the consistency of data in memory. TLB is responsible for caching the mapping table from virtual address to physical address. The mapping objects of this mapping table have two types of page tables: 4KB and 2MB. The existence of 2MB large page memory is to reduce the number of page fault interrupts, provide data memory pages with better continuity, and reduce the increase in computing latency caused by frequent page fault interrupts. When a page fault occurs in the virtual address requested by the user, the host driver will send a TLB update request through the host control signal to ensure the validity of the TLB entry. The vFPGA configuration unit is responsible for receiving the initialization information and control information of the read-write state machine from the host control signal, and accepting the read-write request sent by the user logic to the read-write state machine.

[0056] See also Figure 4 The unified virtual memory mapping between FPGA and CPU is as follows: Figure 4 As shown. When the FPGA management unit of the service area is enabled, the virtualization solution will copy the physical memory content allocated by the host to the vFPGA to the FPGA memory through the xDMA engine, and establish a unified mapping between the FPGA memory to the virtual memory and the host memory to the virtual memory. The vFPGA can send user logic descriptors to the read-write state machine to access the physical address corresponding to the vFPGA virtual address. When there is a page fault exception (on the FPGA memory), the read-write state machine will send a page fault interrupt to the host driver, and then the host will update the missing page of the host memory and copy it to the FPGA memory through the xDMA engine.

[0057] See also Figure 5 . The memory management unit of the FPGA service area is as follows Figure 5 When the FPGA management unit of the service area is enabled, the virtualization solution will create a corresponding number of DDR control units according to the actual number of DDRs (see Figure 2 ). The control unit is responsible for sending data to the specified vFPGA read / write state machine through the data bus, and then the read / write state machine integrates the data content of multiple DDRs into serial data and sends it to the user logic area. It should be noted that in order to fully utilize the performance of DDR, this virtualization solution chooses to disperse the data of a single memory page (2MB or 4KB) of vFPGA into different DDRs, because there is bandwidth optimization space when vFPGA quickly accesses multiple channels, which can improve data throughput.

[0058] See also Figure 6 The schematic diagram of the user logic interface is as follows: Figure 6 As shown. The user logic interface (ULI) provides a port for user logic to interact with the outside world in the form of a lower-level physical port. The high-speed data bus (using the AXI4-Full protocol) is responsible for transmitting high-throughput data from the host to the FPGA. clk (clock) and rst (reset) are the clock signal and reset signal required by the FPGA circuit, respectively. The user logic descriptor is responsible for sending the read and write requests of the user logic to the read and write state machine. The control bus (using the AXI4-Lite protocol) is responsible for transmitting the control signal of the host. The lower-level interface of the host data stream, network data stream, and memory data stream is the read and write state machine, which forwards the data sent by the corresponding source to the user logic. In addition, when a user uses multiple vFPGAs to perform tasks at the same time, the inter-region communication queue between vFPGAs (using the AXI4-Stream protocol) can be used to achieve high-speed communication between user regions. When a user only occupies one vFPGA resource, its inter-region communication pair will be prohibited from use.

[0059] See also Figure 7 FPGA computing resource pools are divided into general hardware algorithm acceleration resource pools and custom hardware acceleration algorithm resource pools. In the resource scheduling process, non-preemptive scheduling is usually used because FPGA does not have the ability to save on-site. In addition, frequent switching of the algorithm type executed by a single vFPGA should be avoided as much as possible during the scheduling process, because this will bring about a large PR overhead and reduce the utilization rate of FPGA resources. Figure 7 As shown. In the general hardware algorithm acceleration pool, FPGA computing resources are allocated to users according to the type of algorithm requested by the user: when the general FPGA resources are idle, the user request is allocated to the priority queue of the idle vFPGA; when the general FPGA resources are tight, the user is allocated to the vFPGA priority queue with the required acceleration algorithm, and the priority is assigned to it according to the execution time of the algorithm (the code with a short execution time has a higher priority), and the priority of the algorithm that has not been executed for a long time is increased to avoid the phenomenon of "starvation"; under the premise that the general FPGA computing resources are extremely tight, some custom FPGA computing resources can be appropriately borrowed. In the custom hardware algorithm acceleration pool, it is difficult to unify the algorithm type executed by the user, so the priority is assigned to it only according to the execution time of the algorithm: when the custom FPGA computing resources are idle, the user request is allocated to the priority queue of the idle vFPGA; when the custom FPGA resources are tight, the priority is assigned to it according to the execution of the user algorithm, and it is placed in the vFPGA priority queue with a shorter execution time of the preceding algorithm, and the priority of the algorithm that has not been executed for a long time is increased to avoid the phenomenon of "starvation".

[0060] The above description is only a preferred embodiment of the present application and is not intended to limit the present application. Any modifications, equivalent substitutions and improvements made within the spirit and principles of the present application should be included in the protection scope of the present application.

Claims

1. An FPGA heterogeneous cloud computing method supporting concurrent access, characterized in that: For the CPU-FPGA heterogeneous cloud computing architecture, the FPGA heterogeneous cloud computing method includes: Virtualize the FPGA and divide it into static area, service area and dynamic area. Use virtual memory to load resource scheduling algorithm, so that the service area can load corresponding functional circuits according to specific needs, and allocate corresponding hardware resources of the service area to the dynamic area when the corresponding function is not needed. Wherein, the static area includes: an xDMA data path for communication between the PGA and the CPU, a circuit for partitioning the dynamic area and the service area, and partially reconstructing the dynamic area and the service area; The service area is an expandable general functional area, and the expandable content includes: a network protocol stack, an FPGA memory management module; and uses the RDMA protocol to remotely access the memory of the FPGA; The dynamic area includes: a read-write state machine, a bypass translation buffer TLB, a user logic interface UIL, and a partially reconfigurable user logic area for storing user logic, and the user logic area is divided into a plurality of vFPGAs.

2. The FPGA heterogeneous cloud computing method according to claim 1, characterized in that: During the operation of CPU-FPGA heterogeneous cloud computing architecture, The CPU-side driver reads the static region configuration from the FPGA, sets up data structures for the vFPGA set to be supported, and communicates with the FPGA's xDMA data path; The xDMA data path uses the xDMA engine to implement data communication between the FPGA and the CPU, and transmits it to different blocks of the FPGA through the data bus; The partial reconstruction circuit is responsible for accepting the PR request initiated by the CPU through the xDMA data path, and reconstructing the bit stream part of the corresponding circuit to the user logic area of ​​the corresponding vFPGA through the internal configuration access port; the partial reconstruction circuit can also reconstruct the dynamic area or service area to meet the extended function requirements of different users.

3. The FPGA heterogeneous cloud computing method according to claim 1, characterized in that: The network protocol stack in the service area is responsible for processing various sending and receiving requests from the TCP / IP or RDMA protocol, and distributing them to the user logic interface of the corresponding vFPGA unit through the data bus in the form of AXI4 stream; The FPGA memory management module is responsible for processing data transmission between vFPGA and FPGA off-chip memory, and each DDR has a corresponding DDR control unit in the FPGA memory management module to process data access requests between vFPGA and the specified FPGA off-chip DDR.

4. The FPGA heterogeneous cloud computing method according to claim 3, characterized in that: The FPGA memory management module copies the physical memory content allocated by the host to the vFPGA to the FPGA memory through the xDMA engine, and establishes a unified mapping between the FPGA memory to the virtual memory and the host memory to the virtual memory; vFPGA accesses the physical address corresponding to the vFPGA virtual address by sending the user logic descriptor to the read / write state machine. When a page fault exception occurs, the read / write state machine sends a page fault interrupt to the host driver. The host then updates the missing page of the host memory and copies it to the FPGA memory through the xDMA engine.

5. The FPGA heterogeneous cloud computing method according to claim 3, characterized in that: The FPGA memory management module creates a corresponding number of DDR control units according to the actual number of DDRs. The DDR control unit is responsible for sending data to the specified vFPGA read-write state machine through the data bus, and the read-write state machine integrates the data content of each DDR into serial data and sends it to the user logic area.

6. The FPGA heterogeneous cloud computing method according to claim 1, characterized in that: The read / write state machine is responsible for processing data received and sent from different sources, including: data copied from the xDMA engine by the xDMA data path, data transmitted via the TCP / IP protocol, and forwarding communication data between the user logic and different sources; The TLB is responsible for processing the mapping relationship between virtual memory and physical memory, so that the user logic can access the FPGA off-chip memory and the host memory using the xDMA engine in the static area in the form of virtual memory. The TLB and the read-write state machine together form the memory management unit MMU of the vFPGA, providing sandboxed memory access for the user logic. The user logic interface is responsible for transmitting data communication between the user logic and the read / write state machine or other sources; The user logic area is responsible for storing the general hardware acceleration circuit specified by the user or the hardware acceleration circuit customized by the user.

7. The FPGA heterogeneous cloud computing method according to claim 6, characterized in that: The read / write state machine completes data processing from different sources through the following process, including: The user logic implements the read and write requests by sending the user logic descriptor to the vFPGA configuration unit of the read and write state machine; the access request initiated by the host to the FPGA memory is converted into the host descriptor to realize the data transfer; The read state machine is responsible for responding to the read request from the host or vFPGA and checking whether there is a page fault exception. When there is a page fault exception in the FPGA memory, the read state machine sends a page fault interrupt to the host driver, and the host driver loads the page corresponding to the virtual memory into the host memory and copies it to the FPGA memory through the xDMA engine. The write state machine is responsible for responding to write requests from the host or vFPGA and checking whether there is a page fault exception. The user logic control signal is responsible for specifying the write address and write length.

8. The FPGA heterogeneous cloud computing method according to claim 7, characterized in that: A TLB mutex lock is provided between the read state machine and the write state machine, and the TLB mutex lock is used to ensure that reading and writing are mutually exclusive operations, thereby ensuring the consistency of data in the memory.

9. The FPGA heterogeneous cloud computing method according to claim 1, characterized in that: The virtual memory loading resource scheduling algorithm includes a general hardware acceleration algorithm and a custom hardware acceleration algorithm.

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