A CPU-FPGA heterogeneous computing architecture for matrix singular value decomposition

Abstract

The present application discloses a CPU-FPGA heterogeneous computing architecture for matrix singular value decomposition, including a virtualized FPGA, and the FPGA is divided into a static area, a service area, and a dynamic area; the FPGA is based on a virtual memory loading resource scheduling algorithm, so that the service area can load corresponding functional circuits according to specific needs, and when the corresponding function is not needed, the corresponding hardware resources of the service area are allocated to the dynamic area; wherein the static area includes: an xDMA data path for PGA and CPU communication, a circuit for partitioning and partially reconstructing the dynamic area and the service area; the dynamic area includes: a read-write state machine, a bypass translation buffer TLB, a user logic interface UIL, and a partially reconstructible user logic area for storing user logic, and the user logic area is divided into several vFPGAs, each of which is loaded with a single-sided Jacobi matrix singular value decomposition algorithm. The architecture design of the present application simplifies the development process of heterogeneous acceleration algorithms and realizes efficient parallelization of singular value decomposition calculations.

Description

Technical Field

[0001] The present application belongs to the technical field of matrix singular value decomposition, and in particular, relates to a CPU-FPGA heterogeneous computing architecture for performing matrix singular value decomposition. Background Art

[0002] Singular Value Decomposition (SVD) is a basic computational tool for least squares regression, principal component analysis (PCA), and pattern recognition, and is widely used in data analysis, data processing, machine learning, recommendation systems, direction of arrival estimation, image compression, and wireless communications. Although some dedicated hardware processors have been proposed to accelerate computationally intensive SVD, these designs have poor flexibility and scalability, and do not fully consider the computational and data movement challenges associated with SVD. SVD is a computationally intensive task, and most SVD algorithms have cubic complexity in terms of problem size, making SVD a computational bottleneck for related algorithms. Common SVD algorithms can be divided into two types: SVD based on bidiagonalization methods and SVD based on Jacobi. The bidiagonalization method is an SVD algorithm proposed by Golub and Kanha in 1965. The algorithm first uses the Householder transformation to bidiagonalize the input matrix, and then calculates the singular values ​​of the bidiagonal matrix. The algorithm has a fast convergence speed, but the Householder transform needs to repeatedly update the complete data of the matrix during implementation, which makes it difficult to parallelize the Householder transform, resulting in the algorithm not being able to fully utilize the performance of modern hardware accelerators. The Jacobi-based method uses the Givens transform to iteratively eliminate all column pairs (column-pair) or row pairs (raw-pair) in the input matrix until the covariance between any column pairs or row pairs is less than the maximum error value, then the iteration is stopped. This method does not need to double diagonalize the matrix, and a Givens change only involves two columns of the matrix, so it can make good use of hardware performance for parallelization. Furthermore, the Jacobi method can be subdivided into the one-sided Jacobi algorithm (Hestenes-Jacobi) and the two-sided Jacobi algorithm. The one-sided Jacobi algorithm only performs Givens rotation on one side of the matrix, gradually diagonalizing the matrix to approximate the singular values. The characteristics of its one-sided operation make the algorithm only need to process the column pairs (or row pairs) of the matrix, and the implementation is relatively simple. The bilateral Jacobi algorithm needs to perform Givens rotations on the left and right sides of the matrix to approximate the singular values, so each iteration of the algorithm needs to process both column pairs and row pairs of the matrix. Compared with the SVD decomposition of the unilateral version, the bilateral version can perform Givens transformations on both rows and columns of the matrix to accelerate the convergence of the algorithm, but it also brings difficulties to the parallelization of the algorithm, and more complex parallel optimization problems need to be considered.

[0003] Although the one-sided Jacobi algorithm has many potential benefits, the one-sided Jacobi algorithm isThe performance of the single-sided Jacobi algorithm is poor in CPU and GPU environments because thread synchronization can significantly reduce the parallel potential of the single-sided Jacobi algorithm. FPGA (Field-Programmable Gate Array) is a hardware circuit programmable accelerator that can design corresponding hardware circuits for each algorithm for hardware acceleration. Among various hardware accelerators, "CPU-FPGA" has become a mainstream heterogeneous computing method for performing computationally intensive tasks due to its programming flexibility, energy efficiency, and hardware optimization for algorithms. How to effectively parallelize the single-sided Jacobi algorithm with the hardware design of modern FPGA devices remains an unexplored problem. In order to retain the advantages of the single-sided Jacobi when designing hardware implementations, complex accuracy and resource utilization challenges must be overcome. The key problem of using FPGAs for SVD of large matrices is that the on-chip data reuse of FPGAs is not explored, resulting in severe performance degradation once the on-chip cache is exhausted. Although the issues of bandwidth and data reuse have been widely studied in distributed system scenarios, these issues have received little attention in recent FPGA-based large matrix SVD. In addition, using floating-point operations in FPGA will result in large time overhead and delay, while fixed-point operations are a unique form of data processing in FPGAs, which significantly reduces resource consumption and delay at the expense of dynamic range. Therefore, fixed-point operations on FPGAs are usually performed using fixed-point operations. However, using fixed-point operations requires consideration of additional optimization issues to ensure that the algorithm can achieve an accuracy equivalent to that of floating-point precision, and to ensure the stability and effectiveness of the algorithm.

[0004] In addition, although the "CPU-FPGA" heterogeneous computing method can achieve several times or even dozens of times improvement in performance and energy efficiency compared to the more traditional "CPU" or "CPU-GPU" heterogeneous computing architecture, their programming paradigm in embedded systems and prototype design makes it difficult to program, deploy and securely manage them. Developers of acceleration algorithms still need to consider complex hardware constraints and timing optimization issues during the development process, and cannot develop by calling APIs like software development. This results in the "CPU-FPGA" heterogeneous computing method being far less easy to use than "CPU-GPU", because the latter uses the CUDA (Compute Unified Device Architecture) library to shield users from hardware details, and users do not need any technical knowledge about the accelerator hardware to write corresponding heterogeneous computing programs. Summary of the invention

[0005] The purpose of this application is to overcome the problems of the prior art and disclose a CPU-FPGA heterogeneous computing architecture for matrix singular value decomposition. The architecture design of this application simplifies the development process of heterogeneous acceleration algorithms and realizes efficient parallelization of singular value decomposition calculations.

[0006] The purpose of this application is achieved through the following technical solutions:

[0007] A CPU-FPGA heterogeneous computing architecture for performing matrix singular value decomposition, the CPU-FPGA heterogeneous computing architecture comprising a virtualized FPGA, and the FPGA is divided into a static area, a service area, and a dynamic area; the FPGA loads a resource scheduling algorithm based on a virtual memory, so that the service area can load corresponding functional circuits according to specific needs, and when the corresponding function is not needed, the corresponding hardware resources of the service area are allocated to the dynamic area;

[0008] Wherein, the static area includes: an xDMA data path for communication between the PGA and the CPU, a circuit for partitioning the dynamic area and the service area, and partially reconstructing the dynamic area and the service area;

[0009] The service area is an expandable general functional area, and the expandable content includes: a network protocol stack, an FPGA memory management module; and uses the RDMA protocol to remotely access the memory of the FPGA;

[0010] The dynamic area includes: a read-write state machine, a bypass translation buffer TLB, a user logic interface UIL, and a partially reconfigurable user logic area for storing user logic, and the user logic area is divided into several vFPGAs, each vFPGA is loaded with a single-sided Jacobi matrix singular value decomposition algorithm.

[0011] According to a preferred embodiment, the process of performing matrix singular value decomposition based on a one-sided Jacobi matrix singular value decomposition algorithm includes:

[0012] The one-sided Jacobi algorithm first initializes two matrices U and V, where the U matrix is ​​the input matrix read into the algorithm and the V matrix is ​​the unit matrix; then, the one-sided Jacobi algorithm iteratively performs the calculation steps: vector norm calculation, vector angle calculation, and Givens rotation.

[0013] According to a preferred embodiment, the vector norm calculation process includes: taking two columns U from the input matrix U i and U j , and calculate their respective l2 norms, as well as the covariance between the two columns;

[0014] The vector angle calculation process includes: using the vector norm and covariance to calculate the vector angle θ, as well as the corresponding sine and cosine values;

[0015] The Givens rotation process includes: applying a Givens rotation on two column vectors in the Gives transformation process based on the calculated trigonometric function values, and performing two rotation operations to complete the update of corresponding items of matrices U and V.

[0016] This application breaks down the basic steps of the one-sided Jacobi singular value decomposition algorithm into: calculating the column pair norm and covariance, calculating the rotation angle, updating the maximum covariance and performing Givens rotation. In view of the scalability bottleneck caused by the delay difference between the one-sided Jacobi singular value decomposition calculation blocks, a set of algorithms are implemented to balance the delay of parallel calculation blocks and eliminate data dependencies to achieve efficient pipelines. In view of the characteristics of FPGA fixed-point number calculations, this application can determine the part that can use low-precision fixed-point numbers based on the input matrix size and numerical range, while ensuring that the calculation results of the algorithm have the same accuracy as the algorithm using floating-point numbers. In view of the problem of unbalanced resource utilization caused by the large amount of DSP (Digital Signal Processor) resources required for one-sided Jacobi multiplication operations, this application can use the CORDIC algorithm to calculate the vector modulus length and Givens rotation between queues to achieve more balanced resource consumption. The CORDIC algorithm is an iterative method that uses only shift-add operations and lookup tables. It can be used to calculate elementary functions, trigonometric functions, vector rotations, etc. It can largely alleviate the problem of unbalanced resource utilization of FPGA when performing SVD decomposition of large matrices.

[0017] According to a preferred embodiment, during the operation of the CPU-FPGA heterogeneous cloud computing architecture, the driver on the CPU side reads the configuration of the static area from the FPGA, sets the data structure for the vFPGA set to be supported, and communicates with the xDMA data path of the FPGA;

[0018] The xDMA data path uses the xDMA engine to implement data communication between the FPGA and the CPU, and transmits it to different blocks of the FPGA through the data bus;

[0019] The partial reconstruction circuit is responsible for accepting the PR request initiated by the CPU through the xDMA data path, and reconstructing the bit stream part of the corresponding circuit to the user logic area of ​​the corresponding vFPGA through the internal configuration access port; the partial reconstruction circuit can also reconstruct the dynamic area or service area to meet the extended function requirements of different users.

[0020] According to a preferred embodiment, the network protocol stack in the service area is responsible for processing various sending and receiving requests from the TCP / IP or RDMA protocol, and distributing them to the user logic interface of the corresponding vFPGA unit through the data bus in the form of AXI4 stream;

[0021] The FPGA memory management module is responsible for processing data transmission between vFPGA and FPGA off-chip memory, and each DDR has a corresponding DDR control unit in the FPGA memory management module to process data access requests between vFPGA and the specified FPGA off-chip DDR.

[0022] According to a preferred embodiment, the FPGA memory management module copies the physical memory content allocated by the host to the vFPGA to the FPGA memory through the xDMA engine, and establishes a unified mapping between the FPGA memory to the virtual memory and the host memory to the virtual memory;

[0023] vFPGA accesses the physical address corresponding to the vFPGA virtual address by sending the user logic descriptor to the read / write state machine. When a page fault exception occurs, the read / write state machine sends a page fault interrupt to the host driver. The host then updates the missing page of the host memory and copies it to the FPGA memory through the xDMA engine.

[0024] According to a preferred embodiment, the FPGA memory management module creates a corresponding number of DDR control units based on the actual number of DDRs. The DDR control units are responsible for sending data to the specified vFPGA read-write state machine through the data bus, and the read-write state machine integrates the data content of each DDR into serial data and sends it to the user logic area.

[0025] According to a preferred embodiment, the read / write state machine is responsible for processing data received and sent from different sources, including: data copied from the xDMA engine by the xDMA data path, data transmitted via the TCP / IP protocol, and forwarding communication data between the user logic and different sources;

[0026] The TLB is responsible for processing the mapping relationship between virtual memory and physical memory, so that the user logic can access the FPGA off-chip memory and the host memory using the xDMA engine in the static area in the form of virtual memory. The TLB and the read-write state machine together form the memory management unit MMU of the vFPGA, providing sandboxed memory access for the user logic.

[0027] The user logic interface is responsible for transmitting data communication between the user logic and the read / write state machine or other sources;

[0028] The user logic area is responsible for storing the general hardware acceleration circuit specified by the user or the hardware acceleration circuit customized by the user.

[0029] According to a preferred implementation, the virtual memory loading resource scheduling algorithm includes a general hardware acceleration algorithm and a custom hardware acceleration algorithm.

[0030] The aforementioned main scheme of the present application and its further options can be freely combined to form multiple schemes, all of which are schemes that can be adopted and claimed for protection in the present application. After understanding the scheme of the present application, those skilled in the art can understand that there are multiple combinations based on the prior art and common knowledge, all of which are technical schemes to be protected by the present application, and they are not exhaustively listed here.

[0031] Beneficial effects of this application:

[0032] The present application supports a unified FPGA virtualization execution environment, secure time-space multiplexing of FPGA resources, and virtual memory, communication, and memory management under a unified execution environment: the present invention divides the FPGA into a static area, a service area, and a dynamic area, and provides an MMU (memory management unit) for each vFPGA. The MMU module is responsible for processing the mapping between the vFPGA virtual address and the CPU physical memory address or the FPGA off-chip memory address, so that the user logic can access the CPU host memory or the FPGA off-chip memory in a sandboxed manner, and ensure that there is no memory sharing between different user logics. At the same time, the CPU side communicates with the FPGA side by accessing the memory area in the memory belonging to a specific vFPGA. This unified virtualization method provides users with a heterogeneous acceleration algorithm development environment at the software layer and the hardware layer, reduces the complexity of heterogeneous acceleration algorithm development, and simplifies the heterogeneous acceleration algorithm development process.

[0033] In addition, the present application implements a parallelized one-sided Jacobi SVD algorithm on FPGA, making full use of different computing resources of FPGA, and improving the algorithm calculation efficiency while ensuring the calculation accuracy: the present invention dynamically determines the use of fixed-point numbers to calculate the vector norm and the additional bit width required for Givens selection according to the matrix size, ensuring that the calculation result has the same accuracy as the floating-point number; in the vector norm calculation module with higher calculation delay, a multi-level ping-pong buffer is designed to match the calculation delay of different module times, so as to realize the efficient parallel pipeline of the one-sided Jacobi SVD algorithm; in terms of the use of computing resources, the present invention uses the CORDIC algorithm to assist in the calculation of vector norm and Givens rotation, alleviating the problem of tight multiplication resources when FPGA executes large matrix SVD. BRIEF DESCRIPTION OF THE DRAWINGS

[0034] Figure 1 It is a schematic diagram of the virtualization structure of FPGA in the CPU-FPGA heterogeneous computing architecture of this application;

[0035] Figure 2 It is a schematic diagram of unified virtual memory mapping between FPGA and CPU in this application;

[0036] Figure 3It is a flowchart of the parallelized one-sided Jacobi SVD algorithm. DETAILED DESCRIPTION

[0037] The following describes the embodiments of the present application through specific examples, and those skilled in the art can easily understand other advantages and effects of the present application from the contents disclosed in this specification. The present application can also be implemented or applied through other different specific embodiments, and the details in this specification can also be modified or changed in various ways based on different viewpoints and applications without departing from the spirit of the present application. It should be noted that the following embodiments and features in the embodiments can be combined with each other without conflict.

[0038] It should be noted that similar numbers and letters represent similar items in the following drawings, so once an item is defined in one drawing, it does not need to be further defined and explained in the subsequent drawings. In addition, the present application should point out that in the present application, if the specific structure, connection relationship, position relationship, power source relationship, etc. are not specifically written, the structure, connection relationship, position relationship, power source relationship, etc. involved in the present application are all known by those skilled in the art based on the existing technology without creative work.

[0039] The present invention discloses a CPU-FPGA heterogeneous computing architecture for performing matrix singular value decomposition, wherein the CPU-FPGA heterogeneous computing architecture includes a virtualized FPGA. The FPGA is divided into a static area, a service area, and a dynamic area; the FPGA loads a resource scheduling algorithm based on a virtual memory, so that the service area can load corresponding functional circuits according to specific needs, and when the corresponding function is not needed, the corresponding hardware resources of the service area are allocated to the dynamic area.

[0040] Preferably, in terms of the design of the optimized virtual memory loading resource scheduling algorithm, the present application considers two user usage scenarios: general hardware acceleration algorithm and custom hardware acceleration algorithm. For general hardware acceleration algorithms, users can use pre-synthesized hardware algorithm bit files to implement heterogeneous hardware acceleration by calling software APIs. Therefore, in this scenario, the scheduling algorithm needs to consider the user's hardware acceleration algorithm type and user priority. Under conditions of tight computing resources, the scheduling algorithm assigns hardware acceleration requirements with the same acceleration algorithm type to the same task queue to reduce the number of PRs of vFPGA and minimize the waste of FPGA resources. For custom hardware acceleration algorithms, the scheduling algorithm gives priority to hardware algorithms with shorter execution time under the condition of the same priority, and increases the priority of the remaining hardware algorithms after execution to avoid users waiting too long to ensure maximum user experience.

[0041] See also Figure 1 , the virtualization method of a single FPGA is as follows Figure 1 As shown. This application divides a single FPGA into a static area, a service area, and a dynamic area. The static area includes the xDMA data path for communication between the FPGA and the CPU, the partitioning of the dynamic area, and the necessary circuits for partial reconstruction (PR). After the system is started, the driver on the CPU side reads the configuration of the static area from the FPGA, sets the data structure for the vFPGA set to be supported, and is responsible for communicating with the xDMA data path of the FPGA. In addition, the driver is also responsible for handling the page fault exception initiated by the MMU of the vFPGA; the xDMA data path uses the xDMA engine to realize the data communication between the FPGA and the CPU, and transmits it to different blocks of the FPGA through the data bus, among which xDMA path 1 is responsible for transmitting the static area configuration and the partially reconstructed circuit structure information, xDMA path 2 is responsible for transmitting the communication data between the host and the FPGA, xDMA data path 3 is responsible for transmitting the memory data communication between the host and the FPGA, and xDMA data path 4 is used to transmit the communication data required for the service area (in the figure, it is responsible for transmitting the FPGA memory data to the host memory); the partial reconstruction circuit is responsible for accepting the PR request initiated by the CPU side through the xDMA data path 1, and reconstructing the bit stream of the corresponding circuit to the user logic area of ​​the corresponding vFPGA through the internal configuration access port (internal configuration access port, ICAP). In addition, the partial reconstruction circuit can reconstruct the dynamic area or service area separately to meet the extended function requirements of different users.

[0042] The service area contains expandable content such as: network protocol stack, FPGA memory management and other optional content. Whether to enable the optional content of the service area is determined according to the specific needs of the user, so that the extra space can be used for the user logic area. Among them, the network protocol stack is responsible for processing various sending and receiving requests from the TCP / IP or RDMA protocol, and distributes them to the user logic interface of the corresponding vFPGA unit through the data bus in the form of AXI4 stream; FPGA memory management is responsible for processing data transmission between vFPGA and FPGA off-chip memory. Each DDR (double data rate synchronous dynamic random access memory) has a corresponding DDR control unit in the memory management unit to process data access requests from vFPGA and the specified FPGA off-chip DDR.

[0043] A single vFPGA in the dynamic area contains a read / write state machine, TLB, user logic interface (UIL), and a partially reconfigurable user logic area for storing user logic. The read / write state machine is responsible for processing and receiving data from different sources, such as data copied from the xDMA engine by the xDMA data path, data transmitted through the TCP / IP protocol, and forwarding communication data between the user logic and different sources; the TLB is responsible for processing the mapping relationship between virtual memory and physical memory, so that the user logic can use virtual memory to process user logic access to FPGA off-chip memory and host memory using the xDMA engine in the static area. The TLB and the read / write state machine together constitute the vFPGA's memory management unit (MMU), providing sandboxed memory access for user logic; the user logic interface is a lower-level physical interface responsible for transmitting data communication between the user logic and the read / write state machine or other sources; the user logic area is responsible for storing the hardware acceleration circuit specified by the user. Multiple vFPGA partitions are used to execute multiple unrelated hardware acceleration algorithms. Users can divide the FPGA into one or more vFPGAs according to their needs.

[0044] See also Figure 2 , the unified virtual memory mapping between FPGA and CPU is as follows Figure 2 As shown. When the FPGA management unit of the service area is enabled, the virtualization solution will copy the physical memory content allocated by the host to the vFPGA to the FPGA memory through the xDMA engine, and establish a unified mapping between the FPGA memory to the virtual memory and the host memory to the virtual memory, so that the program written by the user on the CPU side can communicate with the FPGA side program. The vFPGA can send user logic descriptors to the read-write state machine to access the physical address corresponding to the vFPGA virtual address. When there is a page fault exception (on the FPGA memory), the read-write state machine will send a page fault interrupt to the host driver, and then the host will update the missing page of the host memory and copy it to the FPGA memory through the xDMA engine.

[0045] As shown in Table 1, for matrix A n*m ,The unilateral Jacobi algorithm first initializes two matrices U and V, where the U matrix is ​​read into the input matrix of the algorithm and the V matrix is ​​the identity matrix. Then, the algorithm iteratively performs three main calculation steps: vector norm calculation, vector angle calculation and Givens rotation.

[0046] In the vector norm calculation step (9-11 corresponding to Algorithm 1 in Table 1): this module takes two columns U from the input matrix U i and U j, and calculate their respective l2 norms, as well as the covariance between the two columns. This is followed by the vector angle calculation: This step uses the vector norm and covariance to calculate the angle θ of the vector, as well as the corresponding sine and cosine values. Givens rotation: Using the trigonometric function values ​​calculated in the previous step, a Givens rotation is applied to the two column vectors in the subsequent Gives transformation process (19-24 corresponding to Algorithm 1 in Table 1). This operation is performed twice to update the corresponding items of matrices U and V.

[0047] From the execution flow of Algorithm 1, we can see that one of the main advantages of the unilateral Jacobi algorithm is that it can achieve a high level of parallelization: First, in the process of vector norm calculation and vector angle calculation, the algorithm only takes out two columns in the matrix each time to calculate the norm and rotation angle, and there is no interference between different columns. Therefore, the algorithm can be parallelized by running multiple norm calculation modules and angle calculation modules. Finally, after multiple iterations, when the maximum value of the covariance is less than the preset threshold, the algorithm stops iterating and outputs the singular value v and the decomposed matrices U and V.

[0048] Table 1 Pseudocode of one-sided Jacobi SVD algorithm

[0049]

[0050] See also Figure 3 The parallelized Jacobi one-sided SVD decomposition algorithm is as follows Figure 3 As shown. For a given N×N size matrix A, the Jacobi algorithm needs to execute 5N times to completely traverse all column pairs of the matrix 10 times 3 Givens rotations. If the vector norm calculation, vector angle calculation, Givens rotation, and IO operations are fully pipelined, the theoretical fastest running time of the algorithm should be clock cycle, where C represents the parallelized vector norm and the number of Givens rotation modules. This algorithm uses polling scheduling to decompose the matrix traversal process into n-1 rounds (such as 6 in Table 1), and the average calculation per round is (7 in Table 1) The rotation angles of the columns are calculated and Givens rotation is applied. At the beginning of each round, the algorithm uses a separate parallel execution unit as part of the pipeline to generate indexes for all column pairs in that round, and sends the matrix indexes to the unit responsible for matrix reading and writing, and clears the pipeline after each round of algorithm execution to avoid the risk of read-after-write data between the tail pair of the i-th round and the head pair of the i+1th round. In addition, the algorithm also stores the maximum covariance between column pairs for comparison after a round of traversal to determine whether the algorithm has converged. In the parallelization process of the vector norm calculation module, the algorithm divides it into two basic modules: vector element multiplication (Norm-Mult) and partial sum (Norm-Sum). In the Norm-Mult stage, for the two input column vectors, the algorithm uses N multiplication modules with a delay of L in parallel, and a buffer for storing the output results of the multiplication module, whose size is N*L. When the multiplication calculation of the two column vectors is completed, the algorithm merges the calculation results of the buffer to obtain a partial sum buffer with a length of L. Then, in the Norm-Sum stage, the data in the partial sum buffer is calculated through the accumulator to obtain the norm of the vector. At the same time, in order to match the computational latency of the Norm-Sum and Norm-Mult stages, the buffer used by the algorithm is a ping-pong buffer, and the buffer is updated for each column pair in the Norm-Mult loop, which effectively reduces the latency of the Norm-Sum stage. In the parallelization process of the vector angle calculation module and Givens rotation, since the computational latency of these two modules is low and the data flow is unidirectional, the pipelined parallel execution of the algorithm can be achieved without using a buffer.

[0051] In terms of fixed-point number calculation. As shown in rows 9 to 11 corresponding to Algorithm 1 in Table 1, the size of the l2 norm of the column pair is proportional to the column size of the input matrix, which leads to a significant impact of the matrix size on the dynamic range of the operands in the algorithm. In practical applications, as the size of the matrix increases, the number of bits required to represent the dynamic range of the matrix elements will increase logarithmically, which poses a key design challenge for fixed-point algorithms. Therefore, before performing the one-sided Jacobi SVD decomposition, this algorithm needs to preprocess the input matrix, normalize the matrix elements to the interval [-1,1], and convert the numerical type from floating point numbers to fixed-point numbers of the same length. However, the dynamic range of the input is an inevitable design limitation of fixed-point operations. For precision-sensitive applications with extreme dynamic ranges, the bit width needs to be appropriately expanded. In the stage of calculating the vector norm, the algorithm introduces additional bit width to improve the calculation accuracy of the vector norm, which is proportional to the matrix size. In the stage of vector angle calculation, the algorithm converts the fixed-point number results of the previous stage into floating point numbers to calculate the exact trigonometric function values. In the Givens rotation stage, the algorithm converts the floating-point results of the previous stage into fixed-point numbers to reduce the latency caused by a large number of floating-point multiplication operations.

[0052] In terms of auxiliary calculation of the CORDIC algorithm. In order to adapt to the fixed-point execution characteristics of the CORDIC algorithm, this algorithm uses fixed-point numbers as the input of the module in the vector norm calculation and Givens change stages, so that in these two stages, computing resources such as DSP, lookup tables, and adders can be used simultaneously to perform operations. In addition, this algorithm dynamically adjusts the proportion of CORDIC, hybrid CORDIC, and pure DSP methods in the above two stages according to resource usage to achieve an optimal total resource utilization.

[0053] The above description is only a preferred embodiment of the present application and is not intended to limit the present application. Any modifications, equivalent substitutions and improvements made within the spirit and principles of the present application should be included in the protection scope of the present application.

Claims

1. A CPU-FPGA heterogeneous computing architecture for performing matrix singular value decomposition, characterized in that: The CPU-FPGA heterogeneous computing architecture includes a virtualized FPGA, and the FPGA is divided into a static area, a service area, and a dynamic area; the FPGA is based on a virtual memory loading resource scheduling algorithm, so that the service area can load corresponding functional circuits according to specific needs, and when the corresponding function is not needed, the corresponding hardware resources of the service area are allocated to the dynamic area; Wherein, the static area includes: an xDMA data path for communication between the PGA and the CPU, a circuit for partitioning the dynamic area and the service area, and partially reconstructing the dynamic area and the service area; The service area is an expandable general functional area, and the expandable content includes: a network protocol stack, an FPGA memory management module; and uses the RDMA protocol to remotely access the memory of the FPGA; The dynamic area includes: a read-write state machine, a bypass translation buffer TLB, a user logic interface UIL, and a partially reconfigurable user logic area for storing user logic, and the user logic area is divided into several vFPGAs, each vFPGA is loaded with a single-sided Jacobi matrix singular value decomposition algorithm.

2. The CPU-FPGA heterogeneous computing architecture according to claim 1, wherein: The process of matrix singular value decomposition based on the one-sided Jacobi matrix singular value decomposition algorithm includes: The one-sided Jacobi algorithm first initializes two matrices U and V, where the U matrix is ​​the input matrix read into the algorithm and the V matrix is ​​the unit matrix; then, the one-sided Jacobi algorithm iteratively performs the calculation steps: vector norm calculation, vector angle calculation, and Givens rotation.

3. The CPU-FPGA heterogeneous computing architecture according to claim 2, wherein: The vector norm calculation process includes: taking two columns U from the input matrix U i and U j , and calculate their respective l2 norms, as well as the covariance between the two columns; The vector angle calculation process includes: using the vector norm and covariance to calculate the vector angle θ, as well as the corresponding sine and cosine values; The Givens rotation process includes: applying a Givens rotation on two column vectors in the Gives transformation process based on the calculated trigonometric function values, and performing two rotation operations to complete the update of corresponding items of matrices U and V.

4. The CPU-FPGA heterogeneous computing architecture according to claim 1, wherein: During the operation of CPU-FPGA heterogeneous cloud computing architecture, The CPU-side driver reads the static region configuration from the FPGA, sets up data structures for the vFPGA set to be supported, and communicates with the FPGA's xDMA data path; The xDMA data path uses the xDMA engine to implement data communication between the FPGA and the CPU, and transmits it to different blocks of the FPGA through the data bus; The partial reconstruction circuit is responsible for accepting the PR request initiated by the CPU through the xDMA data path, and reconstructing the bit stream part of the corresponding circuit to the user logic area of ​​the corresponding vFPGA through the internal configuration access port; the partial reconstruction circuit can also reconstruct the dynamic area or service area to meet the extended function requirements of different users.

5. The CPU-FPGA heterogeneous computing architecture according to claim 1, wherein: The network protocol stack in the service area is responsible for processing various sending and receiving requests from the TCP / IP or RDMA protocol, and distributing them to the user logic interface of the corresponding vFPGA unit through the data bus in the form of AXI4 stream; The FPGA memory management module is responsible for processing data transmission between vFPGA and FPGA off-chip memory, and each DDR has a corresponding DDR control unit in the FPGA memory management module to process data access requests between vFPGA and the specified FPGA off-chip DDR.

6. The CPU-FPGA heterogeneous computing architecture according to claim 5, wherein: The FPGA memory management module copies the physical memory content allocated by the host to the vFPGA to the FPGA memory through the xDMA engine, and establishes a unified mapping between the FPGA memory to the virtual memory and the host memory to the virtual memory; vFPGA accesses the physical address corresponding to the vFPGA virtual address by sending the user logic descriptor to the read / write state machine. When a page fault exception occurs, the read / write state machine sends a page fault interrupt to the host driver. The host then updates the missing page of the host memory and copies it to the FPGA memory through the xDMA engine.

7. The CPU-FPGA heterogeneous computing architecture according to claim 5, wherein: The FPGA memory management module creates a corresponding number of DDR control units according to the actual number of DDRs. The DDR control unit is responsible for sending data to the specified vFPGA read-write state machine through the data bus, and the read-write state machine integrates the data content of each DDR into serial data and sends it to the user logic area.

8. The CPU-FPGA heterogeneous computing architecture according to claim 1, wherein: The read / write state machine is responsible for processing data received and sent from different sources, including: data copied from the xDMA engine by the xDMA data path, data transmitted via the TCP / IP protocol, and forwarding communication data between the user logic and different sources; The TLB is responsible for processing the mapping relationship between virtual memory and physical memory, so that the user logic can access the FPGA off-chip memory and the host memory using the xDMA engine in the static area in the form of virtual memory. The TLB and the read-write state machine together form the memory management unit MMU of the vFPGA, providing sandboxed memory access for the user logic. The user logic interface is responsible for transmitting data communication between the user logic and the read / write state machine or other sources; The user logic area is responsible for storing the general hardware acceleration circuit specified by the user or the hardware acceleration circuit customized by the user.

9. The CPU-FPGA heterogeneous computing architecture according to claim 1, wherein: The virtual memory loading resource scheduling algorithm includes a general hardware acceleration algorithm and a custom hardware acceleration algorithm.

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