Method for identifying and detecting PCB (Printed Circuit Board) hot bonding pad based on Yolov8n-Seg model

Abstract

The invention relates to the technical field of PCB hot pad detection, in particular to a recognition and detection method for a PCB hot pad based on a Yov8n-Seg model, and the method comprises the steps: obtaining a PCB picture data set, and dividing the PCB picture data set into a training set and a verification set; labeling and removing the training set and the verification set; a Yov8n-Seg model is constructed, and the Yov8n-Seg model is trained; carrying out verification to obtain an optimal Yov8n-Seg model; and carrying out identification detection on the PCB picture by utilizing the optimal Yolov8n-Seg model, and outputting an identification detection result of the PCB hot bonding pad corresponding to the PCB picture. According to the method, the PCB hot bonding pad is identified and detected based on the Yov8n-Seg model, so that the identification and detection time of the PCB hot bonding pad can be shortened, the automation degree is relatively high, the identification and detection efficiency of the PCB hot bonding pad can be improved, and meanwhile, the identification and detection precision of the PCB hot bonding pad can also be improved.

Description

Technical Field

[0001] The present invention relates to the technical field of PCB thermal pad detection, and in particular to a PCB thermal pad recognition and detection method based on a Yolov8n-Seg model. Background Art

[0002] PCB (printed circuit board) thermal pads refer to: in PCB design, in order to improve the reliability and strength of welding, some key pads are specially treated. Thermal pads have larger areas and better heat dissipation performance. They are usually used in situations where they need to withstand higher welding temperatures or greater welding stresses. Common thermal pad shapes include: circular, polygonal, and elliptical. In order to ensure welding quality, improve production efficiency, ensure product safety, optimize production processes, meet quality standards, and meet customer requirements, the identification and detection of thermal pads should be strengthened during the production of PCB boards. To this end, we need to propose a PCB thermal pad identification and detection method based on the Yolov8n-Seg model.

[0003] At present, the identification and detection method of the thermal pad of the PCB board is: manual method, that is, manually identifying and detecting the thermal pad of each PCB board. However, manual identification and detection is time-consuming and labor-intensive, and the degree of automation is low, which will affect the identification and detection efficiency of the thermal pad of the PCB board. Summary of the invention

[0004] The technical problem to be solved by the present invention is: in order to solve the technical problem that the existing manual method for identifying and detecting the thermal pads of a PCB board has low efficiency, the present invention provides a method for identifying and detecting the thermal pads of a PCB board based on a Yolov8n-Seg model, and by improving the identification and detection method of the thermal pads of a PCB board, the identification and detection efficiency of the thermal pads of a PCB board can be improved.

[0005] The technical solution adopted by the present invention to solve the technical problem is: a method for identifying and detecting a thermal pad of a PCB board based on a Yolov8n-Seg model, comprising the following steps: S1. Obtain a PCB board image dataset, and divide the PCB board image dataset into a PCB board image dataset for training a model and a PCB board image dataset for verifying a model; S2, obtaining the PCB board image dataset for the training model in step S1, and marking and eliminating the PCB board image dataset for the training model to obtain a PCB board image dataset for the training model after marking and eliminating; S3, obtaining the PCB board image dataset for the verification model in step S1, and annotating the PCB board image dataset for the verification model to obtain an annotated PCB board image dataset for the verification model, and then eliminating the annotated PCB board image dataset for the verification model to obtain an annotated and eliminated PCB board image dataset for the verification model, and at the same time, retaining the original image data corresponding to the annotated and eliminated PCB board image data for the verification model to obtain an annotated and eliminated original PCB board image dataset for the verification model; S4, constructing a Yolov8n-Seg model, and obtaining the PCB board image dataset for the training model after elimination and annotation in step S2, and training the Yolov8n-Seg model by using the PCB board image dataset for the training model after elimination and annotation to obtain a trained Yolov8n-Seg model; S5, obtaining the PCB board image dataset for verification model after being marked and eliminated in step S3, the original PCB board image dataset for verification model after being marked and eliminated, and the Yolov8n-Seg model after being trained in step S4, and verifying the trained Yolov8n-Seg model through the PCB board image dataset for verification model after being marked and eliminated and the original PCB board image dataset for verification model after being marked and eliminated. If the verification result meets the requirements, the trained Yolov8n-Seg model is the optimal Yolov8n-Seg model. If the verification result does not meet the requirements, repeat steps S4 and S5 for multiple times until the trained Yolov8n-Seg model meets the requirements, and record the Yolov8n-Seg model that meets the requirements as the optimal Yolov8n-Seg model; S6. Obtain the optimal Yolov8n-Seg model in step S5, use the optimal Yolov8n-Seg model to identify and detect the PCB board image, and output the identification and detection result of the PCB board thermal pad corresponding to the PCB board image.

[0006] Therefore, compared with the manual identification and detection method, the method of identifying and detecting the thermal pads of the PCB board based on the Yolov8n-Seg model can shorten the identification and detection time of the thermal pads of the PCB board, and has a high degree of automation, which can improve the identification and detection efficiency of the thermal pads of the PCB board, and at the same time, can also improve the identification and detection accuracy of the thermal pads of the PCB board.

[0007] Furthermore, in step S2 and step S3, the PCB board image is labeled by using Labelme software; wherein: after labeling, a PCB board image and a labeling information file containing the PCB board image will be formed.

[0008] Furthermore, in step S2 and step S3, the elimination method refers to: directly viewing the labeled PCB board image through Labelme software, and viewing the labeled PCB board image, if it meets the labeling rules, it is saved, if it does not meet the labeling rules, it is eliminated.

[0009] Furthermore, in step S2 and step S3, the annotated shapes of the thermal pads of the PCB board are: rect, round, oblong, octag and flash.

[0010] Furthermore, in step S2 and step S3, the labeling requirements for labeling the PCB board image using Labelme software are as follows: a. All thermal pads in the PCB board area are marked without omission; b. Thermal pads of different shapes are marked according to the marked shape category; c. The marked outer frame fits the outer line of the thermal pad.

[0011] Further, in step S1, the ratio of the PCB board image dataset for training the model to the PCB board image dataset for verification model is 8:2; wherein: the PCB board image dataset for training the model is used for training the Yolov8n-Seg model, and the PCB board image dataset for verification model is used for verification of the Yolov8n-Seg model after training, and for reverse optimization of training parameters.

[0012] Furthermore, in step S4, the number of pictures that the Yolov8n-Seg model checks each time is 35, the number of cycles of the Yolov8n-Seg model is 300, and the size of the input picture is 640×640 pixels.

[0013] Further, in step S4, train / box_loss refers to: the annotation shape loss in the training stage of the Yolov8n-Seg model, which is used to represent the difference between the bounding box predicted by the Yolov8n-Seg model and the actual bounding box verified; train / seg_loss refers to: the segmentation loss in the training stage of the Yolov8n-Seg model, which is used to represent the difference between the segmentation area of ​​the Yolov8n-Seg model and the actual area verified; train / cls_loss refers to: the classification loss in the training stage of the Yolov8n-Seg model, which is used to represent the difference between the predicted category of the Yolov8n-Seg model and the actual category verified; val / box_loss, val / seg_loss, and val / cls_loss all refer to: the computational loss in the verification stage of the Yolov8n-Seg model, and correspond to the annotation shape loss, segmentation loss, and classification loss in the training stage of the Yolov8n-Seg model, and are used to evaluate the performance of the Yolov8n-Seg model on the PCB board image dataset used to verify the model.

[0014] Further, in step S5, the verification process is: inputting the original PCB board image data for the verification model after annotation and elimination into the trained Yolov8n-Seg model to obtain the annotation result image data corresponding to the original image data; if the image data of the annotation result is consistent with the matching result of the PCB board image data set for the verification model after annotation and elimination, it indicates that the verification result meets the requirements; if the image data of the annotation result is inconsistent with the matching result of the PCB board image data set for the verification model after annotation and elimination, it indicates that the verification result does not meet the requirements.

[0015] Further, in step S6, before the PCB board thermal pad is identified and detected, the PCB board image to be processed is cut so that the size of the input PCB board image is consistent with the size of the PCB board image required during the Yolov8n-Seg model training. Thus, it can be ensured that the identification and detection accuracy of the PCB board thermal pad each time is consistent with the accuracy during the Yolov8n-Seg model training, so as to improve the identification and detection accuracy of the PCB board thermal pad.

[0016] Compared with the prior art, the present invention has the following beneficial effects: The method of identifying and detecting the thermal pads of the PCB board based on the Yolov8n-Seg model can shorten the identification and detection time of the thermal pads of the PCB board compared with the manual identification and detection method, and has a high degree of automation, which can improve the identification and detection efficiency of the thermal pads of the PCB board, and at the same time, can also improve the identification and detection accuracy of the thermal pads of the PCB board. BRIEF DESCRIPTION OF THE DRAWINGS

[0017] The present invention is further described below in conjunction with the accompanying drawings and embodiments.

[0018] Figure 1 It is a flow chart of the identification and detection method of the PCB thermal pad based on the Yolov8n-Seg model of the present invention; Figure 2 It is the original picture of the PCB board of the present invention; Figure 3 It is a marking effect diagram or an identification and detection effect diagram of the PCB board of the present invention; Figure 4 It is the marking effect diagram of rect of the present invention; Figure 5 This is a marked effect diagram of round of the present invention; Figure 6 It is the marking effect diagram of oblong of the present invention; Figure 7 This is a diagram showing the effect of the octag of the present invention; Figure 8 It is the annotation effect diagram of the flash of the present invention; Fig. 9 It is a curve graph of train / box_loss of the present invention; Fig.10 It is a curve graph of train / seg_loss of the present invention; Fig.11 It is a curve graph of train / cls_loss of the present invention; Fig.12 It is a curve graph of val / box_loss, val / seg_loss, and val / cls_loss of the present invention. DETAILED DESCRIPTION

[0019] The present invention will now be described in further detail with reference to the accompanying drawings. These drawings are simplified schematic diagrams, which only illustrate the basic structure of the present invention in a schematic manner, and therefore only show the components related to the present invention.

[0020] In the description of the present invention, it should be understood that the terms "center", "longitudinal", "lateral", "length", "width", "thickness", "up", "down", "front", "back", "left", "right", "vertical", "horizontal", "top", "bottom", "inside", "outside", "clockwise", "counterclockwise", "axial", "radial", "circumferential" and the like indicate positions or positional relationships based on the positions or positional relationships shown in the accompanying drawings, and are only for the convenience of describing the present invention and simplifying the description, rather than indicating or implying that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation, and therefore cannot be understood as a limitation on the present invention. In addition, features defined as "first" and "second" may explicitly or implicitly include one or more of the features. In the description of the present invention, unless otherwise specified, "multiple" means two or more.

[0021] In the description of the present invention, it should be noted that, unless otherwise clearly specified and limited, the terms "installed", "connected", and "connected" should be understood in a broad sense, for example, it can be a fixed connection, a detachable connection, or an integral connection; it can be a mechanical connection or an electrical connection; it can be a direct connection, or it can be indirectly connected through an intermediate medium, or it can be the internal communication of two components. For ordinary technicians in this field, the specific meanings of the above terms in the present invention can be understood according to specific circumstances.

[0022] like Figures 1 to 12 As shown in FIG. 1 , it is the best embodiment of the present invention. The identification and detection method of the PCB thermal pad based on the Yolov8n-Seg model of the present embodiment comprises the following steps: S1. Obtain a PCB board image dataset, and divide the PCB board image dataset into a PCB board image dataset for training a model and a PCB board image dataset for verifying a model; S2, obtaining the PCB board image dataset for the training model in step S1, and marking and eliminating the PCB board image dataset for the training model to obtain a PCB board image dataset for the training model after marking and eliminating; S3, obtaining the PCB board image dataset for the verification model in step S1, and annotating the PCB board image dataset for the verification model to obtain an annotated PCB board image dataset for the verification model, and then eliminating the annotated PCB board image dataset for the verification model to obtain an annotated and eliminated PCB board image dataset for the verification model, and at the same time, retaining the original image data corresponding to the annotated and eliminated PCB board image data for the verification model to obtain an annotated and eliminated original PCB board image dataset for the verification model; S4, constructing a Yolov8n-Seg model, and obtaining the PCB board image dataset for the training model after elimination and annotation in step S2, and training the Yolov8n-Seg model by using the PCB board image dataset for the training model after elimination and annotation to obtain a trained Yolov8n-Seg model; S5, obtaining the PCB board image dataset for verification model after being marked and eliminated in step S3, the original PCB board image dataset for verification model after being marked and eliminated, and the Yolov8n-Seg model after being trained in step S4, and verifying the trained Yolov8n-Seg model through the PCB board image dataset for verification model after being marked and eliminated and the original PCB board image dataset for verification model after being marked and eliminated. If the verification result meets the requirements, the trained Yolov8n-Seg model is the optimal Yolov8n-Seg model. If the verification result does not meet the requirements, repeat steps S4 and S5 for multiple times until the trained Yolov8n-Seg model meets the requirements, and record the Yolov8n-Seg model that meets the requirements as the optimal Yolov8n-Seg model; S6, obtaining the optimal Yolov8n-Seg model in step S5, using the optimal Yolov8n-Seg model to identify and detect the PCB board image, and outputting the identification and detection result of the PCB board thermal pad corresponding to the PCB board image. Thus, by identifying and detecting the PCB board thermal pad based on the Yolov8n-Seg model, compared with the manual identification and detection method, this method can shorten the identification and detection time of the PCB board thermal pad, and has a high degree of automation, which can improve the identification and detection efficiency of the PCB board thermal pad, and at the same time, can also improve the identification and detection accuracy of the PCB board thermal pad.

[0023] For example, a PCB board image is obtained using Gerber data viewing software (i.e., PCB Gerber file), and a circuit layer image with fixed pixels (i.e., 640×640 pixels) is exported for subsequent annotation. The purpose of this operation is to unify the resolution of the output image.

[0024] In this embodiment, in step S1, the ratio of the PCB board image dataset for training the model to the PCB board image dataset for verifying the model is 8:2; wherein: the PCB board image dataset for training the model is used for training the Yolov8n-Seg model, and the PCB board image dataset for verifying the model is used for verifying the Yolov8n-Seg model after training, and for reverse optimization of training parameters.

[0025] In this embodiment, in step S2 and step S3, the PCB board image is annotated by Labelme software; wherein: after the annotation, a PCB board image and an annotation information file containing the PCB board image are formed; the elimination method refers to: directly viewing the annotated PCB board image through Labelme software, and viewing the annotated PCB board image, if it meets the annotation rules, it is saved, if it does not meet the annotation rules, it is eliminated; the annotation shape of the PCB board thermal pad is: rect (such as Figure 4 As shown, the internal pad is rectangular), round (such as Figure 5 As shown, the internal pad is circular), oblong (such as Figure 6 As shown, the internal pad is an elongated circle), octag (such as Figure 7 As shown, the internal pad is an octagon) and flash (as Figure 8 As shown, any shape other than the above graphics); The labeling requirements for labeling PCB board images using Labelme software are as follows: a. All hot pads in the PCB board area are marked and cannot be omitted; b. Hot pads of different shapes are marked according to the marked shape category; c. The marked outer frame fits the outer line of the hot pad. Specifically, if there is a missing label, the Yolov8n-Seg model will not be able to recognize and detect the features of the hot pad target graphics with high quality during training (for example: there are five targets in the PCB board, but only four are marked, then during training, it will be considered that the missed graphic is not what we need, and it will be ignored), thereby affecting the final accuracy; when labeling, the purpose of the edge labeling is: if it is not close enough, the labeling is more casual, and the surrounding areas that do not belong to the hot pad target graphics will also be marked. During training, the hot pad feature recognition detection is not accurate enough, and the features that should not belong to the hot pad target graphics are also considered to be hot pads, thereby affecting the accuracy of the final application.

[0026] In this embodiment, in step S4, the number of images (batch) viewed by the Yolov8n-Seg model each time is 35, the number of epochs of the Yolov8n-Seg model is 300, and the size of the input image is 640×640 pixels; train / box_loss refers to: the annotation shape (i.e., bounding box, target box) loss, which is used to represent the difference between the bounding box predicted by the Yolov8n-Seg model and the actual bounding box for verification; train / seg_loss refers to the segmentation loss in the training stage of the Yolov8n-Seg model, which is used to represent the difference between the segmented area of ​​the Yolov8n-Seg model and the actual area for verification (i.e., it is used to evaluate the segmentation performance of the Yolov8n-Seg model at the pixel level); train / cls_loss refers to the classification loss in the training stage of the Yolov8n-Seg model, which is used to represent the difference between the predicted category of the Yolov8n-Seg model and the actual category for verification (i.e., it represents the performance of the Yolov8n-Seg model on the classification task); val / box_loss, val / seg_loss, and val / cls_loss all refer to the computational loss in the verification stage of the Yolov8n-Seg model, and correspond to the annotation shape loss, segmentation loss, and classification loss in the training stage of the Yolov8n-Seg model, and are used to evaluate the performance of the Yolov8n-Seg model on the PCB board image dataset used for the verification model. Specifically, in order to reduce train / box_loss, use fine PCB board image annotation or increase the number of epochs; in order to reduce train / seg_loss, improve the annotation accuracy, increase the number of epochs or increase the number of batches; in order to reduce train / cls_loss, when annotating PCB board images, select more easily confused targets or annotate erroneous hot pads during detection and put them into the training model for training using the PCB board image dataset; in order to reduce val / box_loss, val / seg_loss, and val / cls_loss, increase the number of epochs or increase the number of batches.

[0027] In this embodiment, in step S5, the verification process is: inputting the original PCB board image data for the verification model after annotation and elimination into the trained Yolov8n-Seg model to obtain the annotation result image data corresponding to the original image data; if the image data of the annotation result is consistent with the matching result of the PCB board image data set for the verification model after annotation and elimination, it indicates that the verification result meets the requirements; if the image data of the annotation result is inconsistent with the matching result of the PCB board image data set for the verification model after annotation and elimination, it indicates that the verification result does not meet the requirements. Specifically, the verification operation can test the generalization ability of the Yolov8n-Seg model on unseen images; by comparing and counting the matching results, the test accuracy can reach 85%; the improvement directions for the accuracy that does not reach 85% include: a. Optimizing the PCB board image dataset (for example: the size and clarity of the PCB board image dataset are inconsistent, and some unqualified data are omitted during cleaning. Both of the above situations will affect the final recognition and detection results of the PCB board thermal pad); b. By analyzing the loss function and adjusting different parameters, the Yolov8n-Seg model results can be observed to find the optimal Yolov8n-Seg model parameters.

[0028] In this embodiment, in step S6, before the PCB board thermal pad is identified and detected, the PCB board image to be processed is cut so that the size of the input PCB board image is consistent with the size of the PCB board image required during the Yolov8n-Seg model training. Thus, it can be ensured that the identification and detection accuracy of the PCB board thermal pad each time is consistent with the accuracy during the Yolov8n-Seg model training, so as to improve the identification and detection accuracy of the PCB board thermal pad.

[0029] In summary, the present invention uses a method for identifying and detecting the thermal pads of the PCB board based on the Yolov8n-Seg model. Compared with the manual identification and detection method, this method can shorten the identification and detection time of the thermal pads of the PCB board, and has a high degree of automation. It can improve the identification and detection efficiency of the thermal pads of the PCB board, and at the same time, it can also improve the identification and detection accuracy of the thermal pads of the PCB board.

[0030] The above description is based on the ideal embodiment of the present invention. Through the above description, relevant personnel can make various changes and modifications without departing from the technical concept of the present invention. The technical scope of the present invention is not limited to the content in the specification, and its technical scope must be determined according to the scope of the claims.

Claims

1. A method for identifying and detecting a thermal pad of a PCB board based on a Yolov8n-Seg model, characterized in that: The following steps are involved: S1. Obtain a PCB board image dataset, and divide the PCB board image dataset into a PCB board image dataset for training a model and a PCB board image dataset for verifying a model; S2, obtaining the PCB board image dataset for the training model in step S1, and marking and eliminating the PCB board image dataset for the training model to obtain a PCB board image dataset for the training model after marking and eliminating; S3, obtaining the PCB board image dataset for the verification model in step S1, and annotating the PCB board image dataset for the verification model to obtain an annotated PCB board image dataset for the verification model, and then eliminating the annotated PCB board image dataset for the verification model to obtain an annotated and eliminated PCB board image dataset for the verification model, and at the same time, retaining the original image data corresponding to the annotated and eliminated PCB board image data for the verification model to obtain an annotated and eliminated original PCB board image dataset for the verification model; S4, constructing a Yolov8n-Seg model, and obtaining the PCB board image dataset for the training model after elimination and annotation in step S2, and training the Yolov8n-Seg model by using the PCB board image dataset for the training model after elimination and annotation to obtain a trained Yolov8n-Seg model; S5, obtaining the PCB board image dataset for verification model after being marked and eliminated in step S3, the original PCB board image dataset for verification model after being marked and eliminated, and the Yolov8n-Seg model after being trained in step S4, and verifying the trained Yolov8n-Seg model through the PCB board image dataset for verification model after being marked and eliminated and the original PCB board image dataset for verification model after being marked and eliminated. If the verification result meets the requirements, the trained Yolov8n-Seg model is the optimal Yolov8n-Seg model. If the verification result does not meet the requirements, repeat steps S4 and S5 for multiple times until the trained Yolov8n-Seg model meets the requirements, and record the Yolov8n-Seg model that meets the requirements as the optimal Yolov8n-Seg model; S6, obtaining the optimal Yolov8n-Seg model in step S5, using the optimal Yolov8n-Seg model to identify and detect the PCB board image, and outputting the identification and detection result of the PCB board thermal pad corresponding to the PCB board image; In step S6, before identifying and detecting the thermal pads of the PCB board, the PCB board image to be processed is cut so that the size of the input PCB board image is consistent with the size of the PCB board image required for Yolov8n-Seg model training.

2. The method for identifying and detecting the thermal pad of a PCB board based on the Yolov8n-Seg model according to claim 1, characterized in that: In step S2 and step S3, the PCB board image is labeled by using Labelme software; Among them: after marking, a PCB board picture and a marking information file containing the PCB board picture will be generated.

3. The method for identifying and detecting the thermal pad of a PCB board based on the Yolov8n-Seg model according to claim 1, characterized in that: In step S2 and step S3, the elimination method refers to: Use Labelme software to directly view the labeled PCB board image, and view the labeled PCB board image. If it meets the labeling rules, save it; if it does not meet the labeling rules, remove it.

4. The method for identifying and detecting the thermal pad of a PCB board based on the Yolov8n-Seg model according to claim 1, characterized in that: In step S2 and step S3, the annotated shape of the thermal pad of the PCB board is: rect, round, oblong, octag, and flash.

5. The method for identifying and detecting the thermal pad of a PCB board based on the Yolov8n-Seg model according to claim 1, characterized in that: In step S2 and step S3, the labeling requirements for labeling the PCB board image using Labelme software are as follows: a. All thermal pads in the PCB area must be marked and not be missed; b. Thermal pads of different shapes are marked according to the marked shape categories; c. Mark the outer line of the frame to fit the thermal pad.

6. The method for identifying and detecting the thermal pad of a PCB board based on the Yolov8n-Seg model according to claim 1, characterized in that: In step S1, the ratio of the PCB board image dataset used for the training model to the PCB board image dataset used for the verification model is 8:2; Among them: the PCB board image dataset used for training the model is used for training the Yolov8n-Seg model, and the PCB board image dataset used for verification of the Yolov8n-Seg model after training is used for reverse optimization of training parameters.

7. The method for identifying and detecting the thermal pad of a PCB board based on the Yolov8n-Seg model according to claim 1, characterized in that: In step S4, the number of pictures that the Yolov8n-Seg model checks each time is 35, the number of cycles of the Yolov8n-Seg model is 300, and the size of the input picture is 640×640 pixels.

8. The method for identifying and detecting the thermal pad of a PCB board based on the Yolov8n-Seg model according to claim 1, characterized in that: In step S4, train / box_loss refers to: the annotation shape loss in the training phase of the Yolov8n-Seg model, which is used to represent the difference between the bounding box predicted by the Yolov8n-Seg model and the actual bounding box for verification; train / seg_loss refers to the segmentation loss of the Yolov8n-Seg model during the training phase, which is used to represent the difference between the segmented area of ​​the Yolov8n-Seg model and the actual area of ​​verification; train / cls_loss refers to the classification loss in the training phase of the Yolov8n-Seg model, which is used to represent the difference between the predicted category of the Yolov8n-Seg model and the actual category of the verification; val / box_loss, val / seg_loss, and val / cls_loss all refer to the computational loss in the Yolov8n-Seg model verification phase, and correspond to the annotation shape loss, segmentation loss, and classification loss in the Yolov8n-Seg model training phase. They are used to evaluate the performance of the Yolov8n-Seg model on the PCB board image dataset used to verify the model.

9. The method for identifying and detecting the thermal pad of a PCB board based on the Yolov8n-Seg model according to claim 1, characterized in that: In step S5, the verification process is: The original PCB board image data for the verification model after annotation and elimination is input into the trained Yolov8n-Seg model to obtain the annotation result image data corresponding to the original image data. If the image data of the annotation result is consistent with the matching result of the PCB board image data set for the verification model after annotation and elimination, it indicates that the verification result meets the requirements. If the image data of the annotation result is inconsistent with the matching result of the PCB board image data set for the verification model after annotation and elimination, it indicates that the verification result does not meet the requirements.

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