Processing method and structure of FC chip cavity inverted embedded packaging substrate

Abstract

The invention relates to the technical field of chip packaging, and discloses a processing method and structure of an FC chip cavity inverted embedded packaging substrate, and the method comprises the steps: S100, carrying out the etching and circuit manufacturing of a copper-clad surface of an incoming substrate, and obtaining a first core plate, a second core plate and a third core plate; s200, etching an alignment target spot on the first core plate to obtain a cover plate layer; s300, manufacturing a mounting groove in the second core board to obtain a cavity layer; S400, carrying out adhesive dispensing and soldering aid on an FC chip mounting position, corresponding to the mounting groove, on the third core board, then carrying out ball mounting, and carrying out flip-chip application on the FC chip on the mounting position to obtain a chip flip-chip layer; and S500, sequentially laminating the cover plate layer, the cavity layer and the chip flip layer according to the alignment target spot, and then pressing to complete FC chip packaging. According to the scheme, the FC chip is embedded in the cavity layer to complete packaging, the size and the thickness after packaging are reduced, the chip can be protected to a great extent through the closed internal environment of the cavity, and the anti-interference capacity of signal transmission is improved.

Description

Technical Field

[0001] The invention relates to the technical field of chip packaging, and in particular to a processing method and structure of an FC chip cavity flip-chip embedded packaging substrate. Background Art

[0002] Modern electronic products tend to be miniaturized and lightweight, and at the same time have extremely high requirements for signal transmission, especially for radio frequency and micro-sensor signals, which will become more and more stringent. Conventional FC chips are flipped on the outside of the substrate to achieve telecommunications performance conduction, and then they will be filled at the bottom of the chip and solidified to achieve the purpose of packaging. The FC process itself has excellent electrical performance, and performs well in power and electrical signal distribution and signal noise reduction. With the changes in the consumer market, consumers have higher and higher requirements for product performance. Product iterations will make the internal electronic components more and more integrated, which is not only not conducive to the stable transmission of signals and the miniaturization of electronic products, but also the highly integrated electronic components make the packaging space more compact, increase the packaging density, and increase the complexity and difficulty of packaging testing.

[0003] Therefore, providing a FC chip processing and packaging method with strong signal transmission anti-interference ability has become an urgent problem to be solved. Summary of the invention

[0004] The main purpose of the present invention is to provide a method for processing an FC chip cavity flip-chip embedded packaging substrate, aiming to solve the technical problem of poor anti-interference ability of FC chip signal transmission.

[0005] To achieve the above-mentioned purpose, the present invention provides a structure of an FC chip cavity flip-chip embedded packaging substrate, comprising: S100: etching the copper-clad surface of the incoming substrate and making circuits to obtain a first core board, a second core board and a third core board; S200: etching the first core board to obtain a cover layer; S300: making a mounting groove on the second core board to obtain a cavity layer; S400: performing glue and fluxing on the FC chip mounting position corresponding to the mounting groove on the third core board, and then performing ball planting, and flip-chipping the FC chip at the mounting position to obtain a chip flip-chip layer; S500: stacking the cover layer, the cavity layer and the chip flip-chip layer in sequence according to the alignment target, and then pressing them to complete the FC chip packaging.

[0006] Preferably, in step S100, the incoming substrate is coded and marked, and after the substrate is baked, positioning holes for positioning the etching area of ​​the copper-clad surface are drilled.

[0007] Preferably, in step S200, after etching the alignment target point, the first core board is subjected to X-ray targeting and expansion and contraction stacking in sequence to obtain the cover board layer.

[0008] Preferably, step S210 is further included between step S200 and step S300: performing ultra-roughening cleaning on the copper-clad surface of the second core board.

[0009] Preferably, step S220 is further included between step S210 and step S300: pre-attaching an adhesive film to the surface of the second core board in a vacuum environment, and subsequently processing the installation groove at a preset position by X-ray targeting and laser grooving processes.

[0010] Preferably, in step S400, a high-precision dispensing machine is used to dispense glue on the second core board, and the offset error of the high-precision dispensing machine is ±15um. A high-precision placement machine is used to perform FC chip placement on the second core board, and the offset error of the high-precision placement machine is ±10um.

[0011] Preferably, in step S400, after the FC chip is flip-chip applied, the chip flip-chip layer is sequentially subjected to die bonding and vacuum reflow treatments.

[0012] Preferably, in step S400, after the die bonding and vacuum reflow are completed, X-ray targeting and expansion and shrinkage stacking are sequentially performed to obtain the chip flip-chip layer.

[0013] Preferably, in step S500, the cover layer, the cavity layer and the chip flip layer are sequentially stacked and then expanded and shrunk, and then pre-riveted and stacked using a high-precision hot-melt riveting machine, and finally packaged using a pressing device.

[0014] The present invention also provides a packaging structure of an FC chip cavity flip-chip embedded substrate, comprising: a cover layer, one or both sides of the cover layer are provided with alignment target points; a cavity layer, the cavity layer is provided with a mounting groove for mounting the FC chip; a chip flip-chip layer, the cover layer, the cavity layer and the chip flip-chip layer are stacked and pressed in sequence from top to bottom, the chip flip-chip layer, the cover layer and the mounting groove enclose a cavity for packaging the FC chip, and the FC chip is flip-chip applied in a corresponding circuit area of ​​the chip flip-chip layer.

[0015] In the technical solution provided by the present invention, the cavity FC chip is buried inside the cavity layer to complete the packaging, reducing the volume and thickness after packaging. The closed internal environment of the cavity can protect the chip to a great extent, effectively shorten the connection distance between the semiconductor and the packaging substrate, and improve the anti-interference ability of signal transmission. Moreover, because the packaging method of the cavity FC chip buried inside the cavity layer is simpler and more direct than the traditional packaging method, it effectively reduces the packaging and testing costs of the packaging and testing factory. BRIEF DESCRIPTION OF THE DRAWINGS

[0016] One or more embodiments are exemplarily described by corresponding drawings, which do not constitute limitations on the embodiments. Elements with the same reference numerals in the drawings represent similar elements, and the figures in the drawings do not constitute proportional limitations unless otherwise stated.

[0017] Figure 1 It is a schematic flow chart of a method for processing a FC chip cavity flip-chip embedded package substrate of the present invention;

[0018] Figure 2 It is a schematic flow chart of a method for processing a FC chip cavity flip-chip embedded package substrate of the present invention;

[0019] Figure 3 It is a structural schematic diagram of the FC chip cavity flip-chip embedded package substrate structure during processing of the present invention;

[0020] Figure 4 It is a structural schematic diagram of the stacking process of the FC chip cavity flip-chip embedded package substrate structure of the present invention;

[0021] Figure 5 It is a schematic structural diagram of the FC chip cavity flip-chip embedded package substrate structure after pressing.

[0022] In the figure: 1, cover layer; 2, cavity layer; 21, cavity; 22, mounting groove; 3, chip flip layer; 31, ball planting; 4, FC chip. DETAILED DESCRIPTION

[0023] In order to facilitate the understanding of the present invention, the present invention is described in more detail below in conjunction with the accompanying drawings and specific embodiments. It should be noted that when an element is described as "fixed to" another element, it can be directly on another element, or there can be one or more centered elements therebetween. When an element is described as "connected" to another element, it can be directly connected to another element, or there can be one or more centered elements therebetween. The terms "vertical", "horizontal", "left", "right", "inside", "outside" and similar expressions used in this specification are only for illustrative purposes. In the description of the present invention, the terms "first" and "second" are used only for descriptive purposes and cannot be understood as indicating relative importance or implicitly indicating the number of technical features indicated. Therefore, unless otherwise specified, the features defined as "first" and "second" may explicitly or implicitly include one or more of the features; the meaning of "multiple" is two or more. The term "include" and any variation thereof means non-exclusive inclusion, and one or more other features, integers, steps, operations, units, components and / or combinations thereof may be present or added.

[0024] In addition, unless otherwise expressly specified and limited, the terms "installed", "connected" and "connected" should be understood in a broad sense, for example, it can be a fixed connection, a detachable connection, or an integral connection; it can be a mechanical connection or an electrical connection; it can be a direct connection, an indirect connection through an intermediate medium, or a connection between two components. All technical and scientific terms used in this specification have the same meaning as those generally understood by technicians in the technical field of the present invention. The terms used in the specification of the present invention are only for the purpose of describing specific embodiments and are not intended to limit the present invention. The term "and / or" used in this specification includes any and all combinations of one or more related listed items.

[0025] In addition, the technical features involved in different embodiments of the present invention described below can be combined with each other as long as they do not conflict with each other.

[0026] Please refer to Figures 1 to 4 In this embodiment, the present invention provides a structure of an FC chip 4 cavity flip-chip embedded packaging substrate, including: S100: etching the copper-clad surface of the incoming substrate and making circuits to obtain a first core board, a second core board and a third core board; S200: etching the alignment target on the first core board to obtain a cover layer 1; S300: making a mounting groove 22 on the second core board to obtain a cavity layer 2: S400: performing glue dispensing and soldering on the FC chip 4 mounting position corresponding to the mounting groove 22 on the third core board, and then performing ball planting 31, and flip-chipping the FC chip 4 on the mounting position to obtain a chip flip-chip layer 3; S500: stacking the cover layer 1, the cavity layer 2 and the chip flip-chip layer 3 in sequence according to the alignment target, and then pressing them to complete the FC chip 4 packaging.

[0027] In the technical solution provided by the present invention, the cavity FC chip 4 is buried inside the cavity layer 2 to complete the packaging, reducing the volume and thickness after packaging. The closed internal environment of the cavity 21 can protect the chip to a great extent, effectively shorten the connection distance between the semiconductor and the packaging substrate, and improve the anti-interference ability of signal transmission. Moreover, because the packaging method of the cavity FC chip 4 buried inside the cavity layer 2 is simpler and more direct than the traditional packaging method, it effectively reduces the packaging and testing costs of the packaging and testing factory.

[0028] Please refer to Figures 1 to 4 In this embodiment, in step S100, the incoming substrate is coded and marked, and then the locating holes for locating the etching area of ​​the copper-clad surface are drilled. In the processing of the packaging substrate, the coding is used to identify the substrate and track information in the production process; the main function of the baking plate is to eliminate moisture and volatile organic matter in the incoming substrate to prepare for the subsequent circuit etching, and the copper-clad surface etching area is subsequently located through the locating holes.

[0029] Please refer to Figures 1 to 4 In this embodiment, in step S200, after etching the alignment target, the first core plate is subjected to X-ray targeting and expansion and contraction stacking in sequence to obtain the cover plate layer 1. After etching the alignment target, X-ray targeting can accurately locate the target position to verify the accuracy and integrity of the target, and the subsequent expansion and contraction stacking process can ensure that the expansion and contraction degree of each core plate is similar, thereby reducing the alignment error caused by the expansion and contraction difference during the pressing process. This helps to improve the pressing accuracy and ensure the accurate alignment of the cover plate layer 1 and the lower cavity layer 2.

[0030] Please refer to Figures 1 to 4 In this embodiment, step S210 is further included between step S200 and step S300: ultra-roughening and cleaning the copper-clad surface of the second core board. The surface of the copper-clad board is roughened to increase its surface area and roughness, thereby improving the bonding force between the cavity layer 2 and the cover layer 1 and the chip flip-chip layer 3, and improving the accuracy of subsequent pressing and alignment.

[0031] Please refer to Figures 1 to 4 In this embodiment, step S220 is further included between step S210 and step S300: pre-attaching the second core board surface with an adhesive film in a vacuum environment, and then sequentially processing the mounting groove 22 at the preset position by X-ray target shooting and laser groove burning process. The laser equipment used to burn the mounting groove 22 needs to meet the high precision requirement.

[0032] Please refer to Figures 1 to 4 In this embodiment, in step S400, a high-precision glue dispenser is used in a high-cleanliness dust-free room to dispense glue on the second core board, and the offset error of the high-precision glue dispenser is ±15um. A high-precision chip mounter is used to mount the FC chip 4 on the second core board, and the offset error of the high-precision chip mounter is ±10um. Compared with the traditional packaging FC chip 4, which is basically flip-chip mounted at the strip level (photoresist stripping process), a single strip needs to be replaced and repeatedly grabbed and aligned to meet the requirements of wafer mounting. Its high-capacity demand needs to be achieved through a large number of DIE devices (solid crystal equipment). The present invention uses a whole PCB work board for flip-chip mounting, and the wafer uses a high-precision automatic ball planting 31 device to complete the solder ball in advance, and then the whole PCB work board is aligned and glued, and finally the wafer is mounted. At the same time, the high-precision DIE device used can automatically divide and align. On the premise of improving the capacity demand, it can also ensure the high-precision alignment demand, greatly improving the yield and reliability of the product.

[0033] Please refer to Figures 1 to 4In this embodiment, in step S400, after the FC chip 4 is flip-chip mounted, the chip flip-chip layer 3 is sequentially subjected to die bonding and vacuum reflow treatment. After the chip is mounted, die bonding and reflow are required. Because the board surface is a pure copper surface, vacuum reflow is required. Its equipment has the ability to vacuum and isolate oxygen during the production process. For pure copper panels, due to their good thermal conductivity and electrical properties, the use of vacuum reflow technology can more effectively control the temperature distribution and oxygen content during the reflow process, thereby improving the reliability and stability of die bonding.

[0034] Please refer to Figures 1 to 4 In this embodiment, in step S400, after the die bonding and vacuum reflow are completed, X-ray targeting and expansion and shrinkage stacking are performed in sequence to obtain the chip flip-chip layer 3. Through the X-ray image, the internal structure of the chip after the die bonding and vacuum reflow can be clearly observed, and whether the chip has defects such as voids, cracks, dislocations, etc. can be detected. These defects may affect the performance and reliability of the chip. Through X-ray targeting, these defects can be discovered and repaired in time, and the alignment error caused by the expansion and shrinkage difference can be reduced, thereby improving the alignment accuracy of the chip flip-chip layer 3 and the cavity layer 2.

[0035] Please refer to Figures 1 to 4 In this embodiment, in step S500, the cover layer 1, the cavity layer 2 and the chip flip-chip layer 3 are stacked in sequence and then expanded and shrunk, and then pre-riveted and stacked using a high-precision hot-melt riveting machine, and finally packaged using a press-fit device. The press-fit device can use a traditional oil pressure or voltage device to finally obtain the FC chip 4 packaging structure.

[0036] Please refer to Figures 3 to 5 The present invention also provides a packaging structure of an FC chip 4 cavity flip-chip embedded substrate, comprising: a cover layer 1, one or both sides of the cover layer 1 are provided with alignment target points; a cavity layer 2, the cavity layer 2 is provided with a mounting groove 22 for mounting the FC chip 4; a chip flip-chip layer 3, the cover layer 1, the cavity layer 2 and the chip flip-chip layer 3 are stacked and pressed in sequence from top to bottom, the chip flip-chip layer 3, the cover layer 1 and the mounting groove 22 enclose a cavity 21 for packaging the FC chip 4, and the FC chip 4 is flip-chip applied in the corresponding circuit area of ​​the chip flip-chip layer 3.

[0037] The above embodiments are only used to illustrate the technical solutions of the present invention, rather than to limit them. Under the concept of the present invention, the technical features in the above embodiments or different embodiments may also be combined, the steps may be implemented in any order, and there are many other changes in different aspects of the present invention as described above, which are not provided in detail for the sake of simplicity. Although the present invention has been described in detail with reference to the above embodiments, a person of ordinary skill in the art should understand that the technical solutions described in the above embodiments may still be modified, or some of the technical features may be replaced by equivalents. However, these modifications or replacements do not deviate the essence of the corresponding technical solutions from the scope of the technical solutions of the embodiments of the present invention.

Claims

1. A method for processing a FC chip cavity flip-chip embedded package substrate, characterized in that: include: S100: etching the copper-clad surface of the incoming substrate and making circuits to obtain a first core board, a second core board and a third core board; S200: etching the first core board at the target point to obtain a cover board layer (1); S300: Making a mounting groove (22) on the second core board to obtain a cavity layer (2): S400: performing glue dispensing and soldering on the FC chip (4) installation position corresponding to the installation groove (22) on the third core board, and then performing ball planting (31), and flip-chipping the FC chip (4) on the installation position to obtain a chip flip-chip layer (3); S500: stacking the cover layer (1), the cavity layer (2) and the chip flip layer (3) in sequence according to the alignment target point and then pressing them together to complete the packaging of the FC chip (4).

2. The processing method of the FC chip cavity flip-chip embedded package substrate according to claim 1 is characterized in that: In step S100, the incoming substrate is coded and marked, and after the substrate is baked, positioning holes for positioning the etching area of ​​the copper-clad surface are drilled.

3. The processing method of the FC chip cavity flip-chip embedded package substrate according to claim 2 is characterized in that: In step S200, after etching the alignment target point, the first core board is subjected to X-ray targeting and expansion and contraction stacking in sequence to obtain the cover board layer (1).

4. The processing method of the FC chip cavity flip-chip embedded package substrate according to claim 3 is characterized in that: The method further includes step S210 between step S200 and step S300: performing ultra-roughening cleaning on the copper-clad surface of the second core board.

5. The processing method of the FC chip cavity flip-chip embedded package substrate according to claim 4 is characterized in that: Also included between step S210 and step S300 is step S220: pre-attaching an adhesive film to the surface of the second core board in a vacuum environment, and subsequently processing the installation groove (22) at a preset position by X-ray targeting and laser grooving processes.

6. The method for processing the FC chip cavity flip-chip embedded package substrate according to any one of claims 1 to 5, characterized in that: In step S400, a high-precision glue dispenser is used to dispense glue on the second core board, and the offset error of the high-precision glue dispenser is ±15um. A high-precision chip mounter is used to mount the FC chip (4) on the second core board, and the offset error of the high-precision chip mounter is ±10um.

7. The method for processing the FC chip cavity flip-chip embedded package substrate according to claim 6, characterized in that: In step S400, after the FC chip (4) is flip-chip mounted, the chip flip-chip layer (3) is sequentially subjected to die bonding and vacuum reflow treatments.

8. The method for processing the FC chip cavity flip-chip embedded package substrate according to claim 7, characterized in that: In step S400, after the die bonding and vacuum reflow are completed, X-ray targeting and expansion and shrinkage stacking are sequentially performed to obtain the chip flip-chip layer (3).

9. The method for processing the FC chip cavity flip-chip embedded package substrate according to claim 8, characterized in that: In step S500, the cover layer (1), the cavity layer (2) and the flip chip layer (3) are stacked in sequence and then expanded and shrunk and stacked, and then pre-riveted and stacked using a high-precision hot-melt riveting machine, and finally packaged using a pressing device.

10. A packaging structure of an FC chip cavity flip-chip embedded substrate, characterized in that: include: A cover plate layer (1), wherein one or both sides of the cover plate layer (1) are provided with alignment target points; A cavity layer (2), wherein the cavity layer (2) is provided with a mounting groove (22) for mounting an FC chip (4); The chip flip layer (3), the cover layer (1), the cavity layer (2) and the chip flip layer (3) are stacked and pressed together in sequence from top to bottom, the chip flip layer (3), the cover layer (1) and the mounting groove (22) enclose a cavity (21) for packaging an FC chip (4), and the FC chip (4) is flip-chip applied in a corresponding circuit area of ​​the chip flip layer (3).

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