Hierarchical beamformer

Abstract

Apparatuses and methods for uplink and / or downlink beamforming operations are disclosed. In one embodiment, each distributed secondary beamformer processor of a plurality of distributed secondary beamformer processors is associated with a respective region of an antenna array and with a respective beamforming sub-matrix. Each transmit or receive beamforming sub-matrix contains beamforming combination weights associated with antenna elements in the respective region of the antenna array. Further, each secondary beamformer processor forms a respective plurality of sets of beamformed frequency domain IQ data points using the respective beamforming sub-matrix and a respective set of frequency domain IQ data points (representing a user data layer for transmission, or FDIQ data received from a corresponding set of transceiver ICs).

Description

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This application claims the benefit of U.S. Provisional Application No. 63 / 357,587, filed on June 30, 2022, entitled “HIERARCHICAL BEAMFORMER,” inventors Yaniv Kafer, Effie Dror, Jong-Hyun Kim, and Robert Irwin, the entire contents of which are hereby incorporated by reference into this document for all purposes. Background Art

[0003] The present disclosure relates to the field of telecommunications, and more specifically to the distribution of signals for transmission through antenna radiating elements. It can be applied to the field of wireless communications such as 2G / 3G / 4G, LTE, Advanced LTE and 5G.

[0004] This section is intended to introduce the reader to various aspects of the art that may be related to various aspects of the present disclosure described and / or claimed below. It is believed that this discussion helps to provide the reader with background information to promote a better understanding of various aspects of the systems and methods described herein. Therefore, it should be understood that these statements should be read from this perspective, rather than as an admission of the prior art. Summary of the invention

[0005] Embodiments described herein include a hierarchical beamformer apparatus having a primary beamformer processor and a set of secondary beamformer processors. In these embodiments, the primary beamformer processor assigns beamforming combination weights (combined with pre-decoder combination weights, as appropriate) to form a full beamforming matrix, and then distributes portions of the beamforming matrix to respective secondary beamformer processors. In some embodiments, the transceiver ICs may be partitioned according to their physical location on the panel, wherein each set of transceiver ICs or transceiver IC subarrays in a given partition is served by and interconnected with a corresponding secondary beamforming processor, wherein the secondary beamformer processors may, in some embodiments, be distributed across the panel to be adjacent to or within the partition. Each distributed secondary beamformer processor may perform transmit beamforming, receive beamforming, or both. In the transmit direction (i.e., downlink or DL), the secondary beamformers receive frequency-domain subcarrier IQ user data layers and apply corresponding distributed beamforming weights to the IQ user data layers to compute fully beamformed IQ data points for distribution to their corresponding separated transceiver ICs or transceiver IC subarray subsets. In the receive direction (i.e., uplink or UL), the secondary beamformers receive frequency-domain subcarrier IQ data packets from the transceiver ICs and apply corresponding distributed receive beamforming weights to the IQ receive packets to compute one or more partially beamformed IQ data packets and forward them to the primary receive beamformer, where these partially beamformed IQ data are combined with other partially beamformed packets from other secondary receive beamformers. In some embodiments, the secondary receive beamformers each compute one partially beamformed packet per receive data layer. In other embodiments, each partially beamformed packet may correspond to a separately tilted beam. Implementations of the secondary beamformer processor may include digital signal processor circuitry executing software instructions to perform matrix multiplication operations, or may take the form of data registers interconnected with hardware multiplier circuitry to perform matrix operations.

[0006] According to embodiments described herein, an apparatus includes: a primary receive beamformer processor; a plurality of distributed secondary receive beamformer processors connected to the primary receive beamformer processor, the plurality of distributed secondary receive beamformer processors being physically distributed such that each distributed secondary receive beamformer processor is located within or near a respective region of an antenna array associated with a respective receive beamforming submatrix of a plurality of receive beamforming submatrices, each receive beamforming submatrix containing receive beamforming combination weights associated with antenna elements in a respective region of the antenna array; and a plurality of sets of transceiver integrated circuit (IC) subarrays connected to the plurality of distributed secondary receive beamformer processors, wherein: (i) Each set of transceiver IC subarrays is connected to a corresponding distributed secondary receive beamformer processor in the plurality of distributed secondary receive beamformer processors and is located within a corresponding region of the antenna array associated with the corresponding distributed secondary receive beamformer processor; and (ii) each distributed secondary receive beamformer processor is configured to receive one or more corresponding sets of frequency-domain IQ data points from the corresponding set of transceiver IC subarrays, and to form corresponding multiple sets of frequency-domain IQ data points for receive partial beamforming using the corresponding sets of frequency-domain IQ data points and the corresponding receive beamforming submatrix, and to transmit the corresponding multiple sets of frequency-domain IQ data points for receive partial beamforming to the main receive beamformer processor.

[0007] In some embodiments, the main receive beamformer processor is configured to combine corresponding receive partially beamformed frequency domain IQ data point sets received from all of the plurality of distributed secondary receive beamformer processors to form a plurality of fully beamformed frequency domain subcarrier IQ user data layers. In addition, in some embodiments, the main receive beamformer processor is configured to separate a receive beamforming matrix of beamforming combination weights into a plurality of receive beamforming sub-matrices, and transmit each respective receive beamforming sub-matrix to a corresponding distributed secondary receive beamformer processor in the plurality of distributed secondary receive beamformer processors.

[0008] In some embodiments, each distributed secondary receive beamformer processor is further configured to form a corresponding plurality of sets of partially beamformed frequency-domain IQ points by applying the receive beamforming combining weights of the corresponding receive beamforming sub-matrix to the corresponding set of frequency-domain IQ data points. In some embodiments, the corresponding plurality of sets of partially beamformed frequency-domain IQ data points represent a corresponding plurality of partially beamformed frequency-domain subcarrier IQ user data layers.

[0009] In some embodiments, each distributed secondary receive beamformer processor includes a packet processor configured to use the corresponding plurality of sets of receive partial beamformed frequency domain IQ data points to form frequency domain IQ data packets corresponding to the plurality of receive partial beamformed for transmission to the primary receive beamformer processor. In this regard, in some embodiments, the frequency domain IQ data packets corresponding to the plurality of receive partial beamformed have a header indicating at least component carrier information. Further, in some embodiments, each distributed secondary receive beamformer processor includes a serial data interface circuit for communicating with each transceiver IC or each transceiver IC subarray in the corresponding set of transceiver ICs or IC subarrays.

[0010] Additionally, in some embodiments, the device also includes: a transmit main beamforming processor; and a plurality of distributed auxiliary transmit beamformer processors connected to the transmit main beamforming processor, wherein the main transmit beamformer processor and the main receive beamformer processor are implemented in a signal processor circuit, a field programmable gate array (FPGA), etc., and wherein the plurality of distributed auxiliary transmit beamformer processors and the plurality of distributed auxiliary receive beamformer processors include a plurality of distributed auxiliary beamformer processors, each distributed auxiliary beamformer processor performing both transmit beamforming operations and receive beamforming operations.

[0011] According to embodiments described herein, a method includes receiving, at each of a plurality of distributed secondary receive beamformer processors connected to a primary receive beamformer processor, a corresponding set of frequency-domain IQ data points from a corresponding set of transceiver integrated circuits (ICs) or transceiver IC subarrays in a plurality of sets of transceiver IC subarrays, wherein the plurality of distributed secondary receive beamformer processors are physically distributed such that each distributed secondary receive beamformer processor is located within a corresponding region of an antenna array associated with a corresponding receive beamforming submatrix in a plurality of receive beamforming submatrices or within a region of an antenna array associated with a corresponding receive beamforming submatrix in a plurality of receive beamforming submatrices. wherein each receive beamforming sub-matrix contains receive beamforming combination weights associated with antenna elements in a corresponding region of the antenna array, and wherein a corresponding set of transceiver IC sub-arrays are located within a corresponding region of the antenna array associated with the distributed secondary receive beamformer processor; forming, by each distributed secondary receive beamformer processor, corresponding multiple sets of frequency domain IQ data points for receive partial beamforming using the corresponding set of frequency domain IQ data points and the corresponding receive beamforming sub-matrix; and transmitting, by each distributed secondary receive beamformer processor, the corresponding multiple sets of frequency domain IQ data points for receive partial beamforming to the main receive beamformer processor.

[0012] In some embodiments, the method further includes combining, by the main receive beamformer processor, corresponding sets of receive partial beamforming frequency-domain IQ data points received from all multiple distributed secondary receive beamformer processors to form multiple frequency-domain subcarrier IQ user data layers. In some embodiments, calculating, by each distributed secondary receive beamformer processor, corresponding sets of partial beamforming frequency-domain IQ data points using corresponding sets of frequency-domain IQ data points and corresponding receive beamforming submatrices includes: applying receive beamforming combining weights of corresponding receive beamforming submatrices to corresponding sets of frequency-domain IQ data points. In addition, in some embodiments, corresponding sets of receive partial beamforming frequency-domain IQ data points represent corresponding multiple partial beamforming frequency-domain subcarrier IQ user data layers.

[0013] In addition, in some embodiments, the method includes separating, by the primary receive beamformer processor, a receive beamforming matrix of beamforming combination weights into a plurality of receive beamforming sub-matrices, and transmitting each respective receive beamforming sub-matrix to a corresponding distributed secondary receive beamformer processor of the plurality of distributed secondary receive beamformer processors. The weights may be transmitted via a control plane message containing the weights or containing a beamforming index pointing to a predetermined beamformer weight stored at the secondary beamformer. In some embodiments, the frequency domain IQ data packet corresponding to the plurality of receive partial beamforming has a header indicating at least component carrier information.

[0014] Additionally, in some embodiments, each distributed secondary receive beamformer processor includes serial data interface circuitry for communicating with each transceiver IC or with each transceiver IC subarray in a corresponding set of transceiver IC subarrays.

[0015] References in the specification to "one embodiment," "an embodiment," "an example embodiment," etc. indicate that the described embodiment may include a particular feature, structure, or characteristic; however, not every embodiment must include the particular feature, structure, or characteristic. Furthermore, such phrases are not necessarily referring to the same embodiment. Furthermore, when a particular feature, structure, or characteristic is described in conjunction with an embodiment, that feature, structure, or characteristic may be used in conjunction with other embodiments whether or not explicitly described. BRIEF DESCRIPTION OF THE DRAWINGS

[0016] Figure 1 One embodiment of an active antenna array assembly or active antenna unit (AAU) is depicted;

[0017] Figure 2 depicts a radio unit architecture having multiple sets of serially connected transceivers for processing RF communication signals associated with corresponding sets of antenna radiating elements in accordance with some embodiments;

[0018] Figure 3 depicts a group of such serially connected transceivers according to some embodiments, wherein an incoming packet for transmission is received at a first transceiver and propagated over a serial data connection to other transceivers in the group, and wherein the incoming RF signal is processed and packetized for forwarding back along the serial transceiver chain;

[0019] Figure 4 is an alternative embodiment of a radio unit architecture having a hierarchical data distribution topology to respective serially connected transceiver groups;

[0020] Figure 5 An embodiment of a synchronization and clock distribution circuit for use with transceivers distributed across an active antenna array assembly is depicted;

[0021] Figure 6 depicts various clock distribution trees for providing clock signals to a transceiver array to reduce clock skew according to some embodiments;

[0022] Figure 7 is a block diagram of an ORAN (Open Radio Access Network) based system including a distributed unit (DU) connected to a radio unit (RU) via a fronthaul data interface and a hierarchical beamformer architecture within the radio unit according to some embodiments;

[0023] Figure 8 is a graphical representation of a downlink transmit beamforming operation using a beamforming / precoding matrix operating on a user data layer to generate antenna-specific IQ data in accordance with some embodiments;

[0024] Fig. 9 is an illustration of conversion of a user data layer to a beamformed downlink transmission data stream according to a precoding operation followed by a beamforming operation according to some embodiments;

[0025] Fig.10 is an illustration of conversion of a user data layer to a beamformed data stream according to a generalized combined precoding and beamforming operation in accordance with some embodiments;

[0026] Fig.11 is an illustration of receive uplink signal processing including receive beamforming and layer decoding according to some embodiments;

[0027] Fig.12is a transceiver device architecture for forming a serially connected set of transceivers according to some embodiments, wherein each transceiver includes an integrated digital signal processor for converting frequency domain digital data to / from time domain digital data, a plurality of integrated digital power amplifiers for converting digital baseband time domain signals to amplified analog RF signals, and an analog RF downconverter and an analog-to-digital converter;

[0028] Fig.13A and Fig. 13B are block diagrams of a transceiver device transmit circuit that generates a plurality of amplified multi-carrier RF signals and a transceiver device receive circuit that generates a plurality of down-converted and sampled OFDM signals, respectively, according to some embodiments;

[0029] Fig.14 According to some embodiments, Fig.12 , Fig.13A and Fig. 13B a signal processing flow for dual-carrier, dual-polarization communication signals of a transceiver device;

[0030] Fig.15 According to some embodiments, Fig.12 , Fig.13A and Fig. 13B two serially connected transceiver devices to generate a signal processing stream of a four-carrier, dual-polarized communication signal;

[0031] Fig.16 depicts various additional details of multi-level beamforming according to some embodiments; and

[0032] Fig.17 Aspects of beamforming weight errors within a subarray-beamforming signal processing system are shown according to some embodiments. DETAILED DESCRIPTION

[0033] Figure 1 An antenna array assembly 100 is depicted in accordance with some embodiments. As depicted, the antenna array assembly 102 has a grid of radiating elements (also referred to herein as antenna elements or antenna radiating elements) generally arranged in rows (e.g., rows 104) and columns (e.g., columns 100) on a panel 102, which may be a printed circuit board (PCB) or other suitable support structure for the radiating elements. Positions within the grid, such as position 116, may have juxtaposed radiating elements (such as elements 112 and 114) to provide different polarizations of radiation, generally referred to as horizontal and vertical polarizations, or equivalently, positive 45 degrees (+45°) and negative 45 degrees (-45°). The radiating element grid may be as shown in FIG. Figure 1In one embodiment, the radiating elements are positioned about 1 / 2 wavelength (λ) apart, where the wavelength λ is associated with the desired frequency operating range of the antenna array, which may be associated with the carrier frequency of the system, or more generally, the center frequency of the system, particularly in embodiments employing a frequency division duplex system (FDD) utilizing multiple carrier frequencies. Some embodiments may operate within multiple frequency bands, and in one such embodiment, such as Figure 1 The array shown in FIG. 1 can be configured to use a 1 operating within a first frequency band of a first frequency, and at a wavelength λ 2 =2λ 1 In this embodiment, the first frequency band (λ 1 ) can be operated by spacing them apart as shown in the figure. 1 adjacent antenna radiating element, but for the second lower frequency band (with wavelength λ 2 ), the elements spaced two apart (e.g., every other row or every other column) have a spacing of .5λ 2 , and can therefore be used for operation in the second frequency band.

[0034] Although the antenna array panel can be configured with more antenna pairs (e.g., 128, 194, 256, 512, etc.) or even fewer antennas (e.g., 32, 16, etc.), Figure 1 The particular array of depicts 64 horizontal radiating elements and 64 vertical radiating elements, juxtaposed in pairs and arranged in an 8×8 square configuration on a panel of approximately 35 to 40 centimeters by 35 to 40 centimeters, with the radiating elements spaced approximately 4.3 centimeters apart. The antenna array assembly 100 also includes a circuit board assembly 128, which includes a power module 130, a clock distribution circuit 132, a global positioning satellite (GPS) receiver 134, a processor circuit 138 for performing packet protocol processing and, in some embodiments, beamforming, etc., a network data interface 136, a power source connector 140, and a GPS connector 142.

[0035] In various embodiments described below, the radiating elements may be grouped into subarrays, such as a column subarray 106 having eight vertical radiating elements and eight horizontal radiating elements, or smaller subarrays, such as groups 108 and 122 each having four horizontal elements and four vertical elements, or groups 110, 120, 124, 126 each having two vertical radiating elements and two horizontal radiating elements. In some embodiments, the antenna subarray may include a two-dimensional set of elements, such as four cross-polarized radiating elements arranged in a square configuration, or six cross-polarized pairs arranged in a 2×3 grid. Alternatives include a set of two or more adjacent vertically polarized elements forming an antenna element subarray, and a corresponding set of vertically polarized elements of the cross-polarized pairs forming a separate subarray. In another embodiment, each cross-polarized pair of radiating elements may be an array element that is driven individually.

[0036] Each radiating element subarray may be driven by a radio frequency (RF) signal generated by a set of transceivers located near the antenna. As used herein, the term "antenna subarray" refers to a grouping of radiating elements positioned in a corresponding array pattern that are functionally related to each other primarily based on their connection to a corresponding set of cooperating RF transceiver integrated circuits (ICs) that are used to process RF signals associated with the radiating elements of the antenna subarray. In this case, the transceiver circuitry includes a set of serially connected transceiver integrated circuit packages (hereinafter referred to as "transceiver ICs") having a first transceiver IC connected to a beamformer processor via a serial data connection (or "link"), and a series of point-to-point serial data connections between the transceiver ICs, wherein, in some embodiments, the data path terminates at the last transceiver IC of the group. In alternative embodiments, the transceiver ICs may be interconnected in a ring configuration, wherein the last transceiver IC in the chain may be connected back to the beamformer processor using an additional serial data connection, or may be connected to the last transceiver IC in a separate chain of serially connected transceiver IC subarrays.

[0037] Note that in some embodiments, a given set of transceiver ICs in a transceiver IC subarray (i.e., a set of serially connected transceiver ICs) associated with a corresponding antenna subarray may be capable of processing independent RF signals for each radiating element. Thus, as used herein, the term "antenna subarray" refers to a set of antenna elements (of a potentially larger array of antenna elements) associated with a given set of transceiver ICs. In some embodiments described herein, a group of radiating elements may operate in a coordinated manner by transmitting the same or similar RF signals (or sets of RF signals for H and V polarizations) with possible phase differences therebetween in order to achieve a desired radiation pattern for beamforming, antenna tilt, or similar directivity.

[0038] Figure 2 Depicted is a radio unit architecture having multiple sets of serially connected transceivers for processing RF communication signals associated with corresponding sets of antenna radiating elements in accordance with some embodiments. Figure 2 As shown, each serially connected transceiver IC group contains at least two serially connected transceiver ICs physically arranged in a transceiver IC sub-array. Specifically, transceiver IC 222 connected to beamformer processor 202 via serial data link 206 is also serially connected to transceiver IC 232 via full-duplex serial data link 228, thereby forming a vertically oriented transceiver IC sub-array along the column of the panel array (such as grouping 110). Similarly, transceiver IC 212 is connected to transceiver IC 230, thereby forming another transceiver IC sub-array.

[0039] Each serial data link (e.g., 228) from a beamformer (primary and / or secondary) and a transceiver IC and (for embodiments using IC subarrays) between transceiver ICs utilizes a Serdes (serializer / deserializer) transceiver or a collection of Serdes to establish a point-to-point link. In one embodiment, each transceiver IC includes two such Serdes transceivers. Alternatively, a higher number of Serdes devices may be included to provide a higher level of interconnectivity between transceiver ICs. The Serdes may be implemented as a low voltage I / O transceiver that utilizes a standard serial data signaling format, such as a 2-level pulse amplitude modulation (PAM2) non-return-to-zero (NRZ) differential signal transmitted on a pair of wires. Signaling based on PAM3 and PAM4 is also applicable. Higher-level protocols may be used in conjunction with a physical layer SERDES, such as PCIe (Peripheral Component Interconnect Express) or USB (Universal Serial Bus), etc. The serial data connection may include a multi-channel link (a plurality of serial data connections operating in parallel in each link). In one embodiment, the data rate of 6 Gigabit per second (Gbps) PAM2 is sufficient to transmit aggregated signal port IQ data packets (including headers), as well as provide additional throughput capacity for transmitting control plane messages to the transceiver ICs. The serial link data rate can be selected to accommodate data packets to and from each transceiver IC subarray based on the desired deployment, including the desired number of independent signal ports, the desired number of component carriers, multi-band operation (thereby adding additional carriers), FDD or TDD, the number of transceiver ICs connected in the transceiver IC subarray, etc.

[0040] Additionally, in some embodiments, each serial data link between the beamformer processor 202 and a given transceiver IC or transceiver IC subarray, as well as the serial data links serially interconnecting individual transceiver ICs within a given transceiver IC subarray, may have sufficient data rates to accommodate data packets carrying IQ data in the frequency or time domain. In this regard, each transceiver IC or IC subarray may, for example, (i) receive / transmit aggregated frequency-domain IQ data packets from / to a beamformer processor where frequency-domain-to-time-domain conversion (on the transmit DL side) and time-domain-to-frequency-domain conversion (on the receive UL side) are performed at a separate transceiver IC (e.g., via iFFT (Inverse Fast Fourier Transform) and FFT (Fast Fourier Transform) processing, respectively); or (ii) receive / transmit aggregated time-domain IQ data packets from / to a beamformer processor where frequency-domain-to-time-domain conversion (on the transmit DL side) and time-domain-to-frequency-domain conversion (on the receive UL side) are performed at the beamformer processor instead (e.g., via iFFT and FFT processing, respectively).

[0041] As an example of serial link data rates, one symbol of a 100Mhz OFDM 5G carrier with 30kHz subcarrier spacing will be transmitted in a 33.33 microsecond (μsec) time window. The data rate required for such transmission on two signal ports (e.g., separate signals for H and V polarizations) with 3,300 subcarriers with 2 samples (I / Q) per subcarrier (e.g., 12 bits / sample) for each of the 14 OFDM symbol slots results in 2*3,300*2*12=158.4kbps, and the 14 OFDM symbols will be transmitted in a 5ms transmission slot, resulting in a net required data rate of 158.4k*14 bits / .5ms=4.43Gbps. If 8b-10b encoding is used on the serial data link, and an additional 10% is added for packet headers and protocol overhead, a throughput of approximately 1.1*4.43*10 / 8 Gbps=6.1 Gbps will be required per carrier for dual signal ports. In some embodiments, 6.1 Gbps of serial data transmission capacity is sufficient for each transceiver IC. For transceiver IC subarrays (i.e., a collection of serially linked transceiver ICs), 6.1 Gbps is still sufficient for many deployment scenarios. For other embodiments with independently controlled signal ports at each transceiver IC, a total throughput of approximately 12 Gbps or even 20 Gbps is sufficient for most applications and configurations as described herein, although 30 Gbps can be achieved if desired for certain other embodiments.

[0042] For lower capacity deployments, lower serial data rates are sufficient. For example, a dual-polarized 20MHz 4G LTE data signal (which uses an FFT size of 2,048 and occupies a 66.67μsec transmission slot time window) requires a data throughput of: 2 ports * 1,200 subcarriers × 2 (I / Q samples / subcarrier) × 12 (bits / sample) / 66.67μsec window = 1,200 × 2 × 12 × / 66.67μsec = approximately 864Mbps. If the data rate is increased by 10 / 8 to accommodate 8b-10b encoding, and 10% is added for overhead, the data rate is approximately 1.2Gbps.

[0043] In another embodiment of the transceiver IC serial data port, a four-wire interface can be used to double the data rate. Alternatively, so-called integral NRZ (ENRZ) signaling using correlated signals in the form of vector signal codes can be sent on four wires to carry 3 bits / baud (i.e., per signaling interval), resulting in three times the data transmission rate (at the same baud rate) instead of just two times. Thus, using a 7.5G baud / second signaling rate, a data throughput of 22.5 Gbps can be reliably achieved over the distance from the beamformer to the transceiver IC subarray. As another alternative, PAM4 signaling (in combination with NRZ or ENRZ signaling) or other vector signal formats (e.g., correlated NRZ (so-called CNRZ-5), using correlated signals to transmit 5 bits on six wires) can be used to provide increased data throughput without significantly increasing the signaling baud rate.

[0044] Overall, Figure 2 A total of 8 columns of transceiver ICs are depicted, each column having 8 transceiver ICs, for a total of 64 transceiver ICs, where each transceiver IC is configured to handle two separate transmit signals (e.g., different RF signals on the H and V signal ports) and two separate receive signals (H / V signal ports). However, because Figure 2 In the embodiment of the present invention, the first two rows of 8 transceiver ICs are connected in pairs, so these 16 transceiver ICs form a single "row" 238a of 8 transceiver IC groups (also referred to herein as transceiver IC subarrays). Similarly, the other transceiver ICs are grouped into another 3 "rows" (238b, 238c, 238d), each with 8 transceiver subarrays, for a total of 8 columns x 4 rows of transceiver IC groups (32 transceiver IC subarrays). In physical dimensions, each column is the width associated with a single collocated cross-polarized antenna, but each "row" of transceiver IC groups covers two rows of cross-polarized antenna elements.

[0045] Further described below Figure 432 transceiver IC subarrays in an 8x4 transceiver IC subarray configuration are also depicted. However, each transceiver IC subarray includes three transceiver ICs connected in series. Note that the transceiver IC subarrays are positioned adjacent to corresponding radiating antenna elements arranged in corresponding antenna subarrays in an element-by-element manner. In some embodiments, the transceiver IC subarrays are located on the back side of the antenna array panel 102, but are still adjacent to (i.e., close to) the corresponding radiating elements for transmitting and / or receiving RF communication signals associated with a given transceiver IC. In some embodiments, the transceiver ICs may be coupled to the radiating elements via vias, intermediate structures, and / or circuits (such as transmission and reception filters mounted on a panel or positioned on a subpanel behind a structure supporting an array of antenna radiating elements).

[0046] Adjacent on an element-by-element basis refers to the relative positioning of the transceiver IC subarrays and corresponding antenna subarrays overlying one another such that each individual transceiver IC in a given transceiver IC subarray is located in an area of ​​the panel 102 associated with a corresponding antenna radiating element in the antenna array or subarray that will be used to transmit and receive signals associated with that individual transceiver IC.

[0047] As another example of being adjacent in an element-by-element manner, in some embodiments such as a frequency division duplex (FDD) system, two transceiver ICs (one transceiver IC dedicated to generating two transmit (H / V) signals at a transmit frequency and the other transceiver IC for processing two receive (H / V) signals at a receive frequency) may form a transceiver IC subarray associated with an antenna subarray consisting of a single collocated cross-polarized antenna. In a dual-band FDD configuration, four transceiver ICs may be linked as a transceiver subarray and positioned adjacent to an antenna subarray consisting of a single collocated cross-polarized antenna.

[0048] The feature of being adjacent in an element-by-element manner provides a distributed transceiver IC architecture that allows the amplified transmitted RF signal generated by each given transceiver IC to experience very little power loss or noise degradation when traversing the very short physical connection from the transceiver IC to the radiating element. In some embodiments, different ratios of transceiver ICs and radiating elements may be adjacent in pairs, such as two transceiver ICs may be placed adjacent to each set of three cross-polarized elements, and so on.

[0049] Throughout this specification, many embodiments are depicted as utilizing a transceiver IC (e.g., 212, 222, 230, 232, etc.) that includes two independent full-duplex transceivers having two transmitters / amplifiers and two independent receivers, each associated with an RF signal port (e.g., 214 or 216) interconnected to a corresponding antenna radiating element (e.g., 218, 220, respectively). Thus, in one embodiment, a single transceiver IC includes an integrated circuit having two full transceivers that transmit and receive two independent RF signals, the two full transceivers being configured such that one RF signal port (tx / rx) is associated with an H-polarized signal port (e.g., 214) and one RF signal port (tx / rx) is associated with a V-polarized signal port (e.g., 216). In such embodiments, each transceiver IC may be referred to as a 2T2R transceiver IC and may be associated with a pair of collocated cross-polarized radiating elements. As an illustrative example, each cross-polarized radiating element pair (218, 220), (224, 226), and (234, 236) is associated with a respective single transceiver integrated circuit, such as transceiver IC 212 is associated with cross-polarized radiating element (218, 220), transceiver IC 222 is associated with element (224, 226), and transceiver IC 232 is associated with element (234, 236).

[0050] In other embodiments, the transceiver ICs may each be configured to provide, for example, four separate analog RF transmit and receive paths through four independent signal ports (4T4R). Such embodiments may include dual PLLs for generating carrier frequencies for both transmit and receive carriers to fully utilize the transceiver ICs when operating in FDD signaling mode. The specific number of transceivers included within a given transceiver IC may depend on factors such as the total desired output power of the panel, the use of additional external power amplifiers, FDD or TDD operation, the data carrying capacity of the serial data link providing interconnection between the transceiver ICs, and many other factors.

[0051] More generally refer to Figure 2, the circuitry of the radio unit 200 (all of which may be deployed within a single active antenna panel assembly) includes a high throughput packet-based interface 252 to a base station or distributed unit (DU) (not shown). The interface 252 may include multiple separate physical network interfaces, such as four separate 25Gbit Ethernet links provided over a fiber optic cable using a small form factor pluggable (SFP) module 242 or a quad SFP (QSFP) module. Information may be transmitted over the interface 240 using an Ethernet protocol, a CPRI / eCPRI protocol, or a similar protocol. The beamformer processor (BFP) 202 performs pre-coding and beamforming operations on the downlink transmission data, and responsively generates aggregate signal port IQ data packets for transmission to the corresponding transceiver IC subarrays, as described below with reference to Figure 8 , Fig. 9 and Fig.10 In some embodiments, the IQ data packet may include frequency domain IQ values ​​of subcarriers within an OFDM (Orthogonal Frequency Division Multiplexing) communication system (such as an LTE or 5G communication system). In other embodiments, the IQ data packet may alternatively include time domain IQ values ​​representing the sum of subcarriers within the OFDM communication system. In the uplink direction, the BFP 202 performs beamformer combining to obtain virtual beamforming antenna port signals, and further combines to recover the user data layer, as described below with respect to Fig.11 Further described.

[0052] exist Figure 2 In the depicted embodiment, the beamformer processor 202 is connected to each transceiver IC subarray via a serial data link, such as link 206. Depending on the length of the data link (depicted as 4 sets 204a, 204b, 204c, 204d, each set having 8 links), each data link may utilize a Serdes repeater / retimer 208, 210 to extend the range of the serial data link from the BFP 202 to the area in the panel 102 where a given transceiver IC subarray (and corresponding antenna subarray elements) is located. Figure 4 In the alternative embodiment shown, the BFP 400 is connected to a set of transceiver IC subarrays via a high-speed Serdes link 402, whereby a Serdes multiplexer (MUX) 404 (and corresponding high-speed links to Serdes MUXs 422, 424, 426) demultiplexes (i.e., separates) a high-rate serial data stream into lower-rate serial data streams 406, which are directed to each individual transceiver IC subarray. The Serdes MUX devices 404, 422, 424, 426 perform an inverse multiplexing operation on uplink data transmitted from the transceiver IC subarrays to the BFP 202.

[0053] refer to Figure 2 , an example transceiver IC subarray includes a transceiver IC 222 and a transceiver IC 232 coupled via a serial data link 228. The two transceiver ICs are located near their respective antenna radiating elements 224, 226 and 234, 236, respectively. In some embodiments, they are placed on one side of the PC board, adjacent to the antenna elements, and are electrically connected using through vias or through intervening circuit elements such as filters, duplexers, quadplexers, SPDT (single pole double throw) TDM switches, etc. As shown in FIG. Figure 2 As shown, each transceiver IC generates two separate RF transmission downlink (DL) signals for H polarity and V polarity, and receives and processes two separate RF uplink (UL) signals. Also depicted is an observation transceiver 260 connected to the BFP 202 via a serial data link 256, with an RF signal connection 258 interconnecting each transceiver through a calibration network.

[0054] Figure 3 A group of such serially connected transceivers is depicted which would be placed in transceiver IC subarray locations adjacent to antenna radiating elements of corresponding antenna subarrays located within the antenna panel array 102 in an element-by-element manner. Incoming packets for DL ​​transmissions are received from the BFP via serial data link 308 at a first transceiver IC 312, and at least some of these packets are propagated via serial data connections 348, 364 to other transceiver circuits in transceiver ICs 350, 366 in the transceiver group. Similarly, incoming RF signals on the UL are processed and packetized for forwarding back along the serial data transceiver IC chain 362, 346, 310. In this embodiment, each transceiver IC is configured to handle two separate transmit signal paths and two separate receive signal paths via two separate signal ports typically associated with two corresponding antenna radiating elements. Operation in TDD Mode Figure 3 The transceiver subarray is configured such that transceiver IC 312 transmits and receives RF signals on first signal port 328 and transmits and receives RF signals on second signal port 344. Similarly, transceiver IC 350 is associated with signal ports 356 and 360, while transceiver IC 366 is associated with signal ports 370 and 378.

[0055] As previously described, the two transceiver signal ports of the transceiver IC can be interconnected to a single set of cross-polarized antenna elements. For TDD operation, this provides 2T2R (two transmissions and two receptions) signal processing capabilities. In an alternative embodiment, the two signal ports can each be connected to corresponding radiating elements in two different cross-polarized antenna pairs, for example, where the first transceiver of the transceiver IC processes the transmission and reception signals of the vertically polarized elements of the first cross-polarized radiating element pair, and the second transceiver of the same transceiver IC processes the transmission and reception signals of the vertically polarized elements of the second cross-polarized radiating element pair. The second transceiver IC can then be used to process the signals associated with the two horizontally polarized elements of the two cross-polarized pairs.

[0056] In other alternative embodiments, the output of each signal port may be split and connected to multiple radiating elements in parallel, such as one signal port connected in parallel to the vertically polarized radiating elements of two (or three, etc.) cross-polarized pairs, and another signal port connected in parallel to the horizontally polarized radiating elements of the same two (or three, etc.) cross-polarized pairs. In still other embodiments described below, the amplified RF signals produced by a transceiver IC or by multiple transceiver ICs may be provided to additional amplifier stages external to the transceiver IC, and / or combined, before being provided to the radiating elements.

[0057] In some embodiments, frequency domain I / Q data packets are transmitted to a collection of serially connected transceiver ICs distributed on an active antenna panel. The aggregated data packets are superpositions of frequency domain subcarrier specific data, typically representing resource blocks (RBs) allocated across many data layers and possibly many users, with different beamforming weights applied, and therefore containing fully beamformed (including MIMO precoding when used) subcarrier IQ sample data for a specified frequency band, component carrier, and signal port. Each IQ data packet may have a single header, but still include concatenated or interleaved data for multiple signal ports (such as for H and V signal ports). Such packets may be referred to as dual signal port packets. In some embodiments, the packet header may include identification data associated with a specific transceiver IC, and may include IQ data for any number of signal ports processed by the transceiver IC, and may be generally referred to as multi-signal port data.

[0058] Figure 3The user aggregated frequency domain data of packet 302 in 0 indicates a packet of frequency domain IQ data that is processed collectively by the transceiver ICs in a given transceiver IC subarray. Packet 302 may include a header (not shown for clarity) that identifies various aspects of the type of data contained in the packet, as well as packet identification data (such as one or more of the following: frequency band ID, component carrier ID, signal port ID, and / or transceiver ID). The main payload data in packet 302 includes subcarrier specific IQ data for a signal port (not limited to, for example, horizontally polarized RF signals for a particular component carrier, in Figure 3 The same packet (or, in some embodiments, a separate packet with a separate header and ID data field) includes subcarrier IQ data for a second signal port (e.g., for a vertically polarized RF signal of the same component carrier, e.g., Figure 3 302 is a packet of IQ data for a subcarrier having an H polarization signal port and a V polarization signal port, but the IQ data may also be interleaved, such as an IQ sample pair for the H signal port and a pair for the V signal port for subcarrier 1, followed by an IQ sample pair for H and V for subcarrier 2, etc. Each I sample and Q sample may be represented as a certain number of bits, such as 12, 14, or 16, etc., depending on the desired signal resolution. Packet 302 may contain IQ sample data for multiple subcarriers, such as 612, 1,596, 3,276, or more subcarriers, for each signal port, for a particular carrier and frequency band.

[0059] Note that the aggregated beamforming IQ data packets communicated on the serial data connection (link) from / to the BFP (beamformer processor) and the transceiver IC may contain frequency domain IQ data or time domain IQ data. In this regard, it should be noted that packet data transmission of aggregated beamforming frequency domain IQ data packets on the serial data connection from / to the BFP and the transceiver IC is more efficient than packet data transmission of aggregated beamforming time domain IQ data. Specifically, the frequency domain IQ data specifies the in-phase and quadrature (IQ) values ​​of specific subcarriers to be used for data transmission (and reception) in a given communication system. However, for DL ​​signals, such as in an OFDM communication system (e.g., an LTE or 5G communication system), before converting the frequency domain IQ data to time domain digital data via iFFT, it may be necessary to insert zero values ​​into the IQ data set to account for unused subcarriers within a given component carrier (e.g., subcarriers used as guard bands), resulting in a time domain sequence of converted IQ data having many more IQ data points that need to be transmitted to the transceiver IC / transceiver IC subarray (e.g., initially transmitted from the BFP and then distributed accordingly among the transceiver ICs in a given transceiver IC subarray). Similarly, for UL signals, the frequency domain IQ data processed via FFT may exclude frequency domain values ​​of unused subcarriers, while the equivalent time domain IQ data associated with the unused subcarriers is a component of the time domain IQ data that may not be removed prior to transmitting the time domain data over a serial data connection as described herein.

[0060] In this regard, depending on the bandwidth of a given communication channel, it may be relatively important to improve the efficiency of conveying frequency domain IQ data relative to the corresponding time domain IQ data. By way of example, for a 20MHz wide LTE channel, the ratio of unused subcarriers to data modulated subcarriers will be greater than a similar ratio under a 100MHz wide LTE channel. Therefore, it becomes more efficient to convey subcarrier specific IQ data in the frequency domain rather than in the time domain. More specifically, as described above, even if a subset of subcarriers remains unused (unmodulated / unloaded with data), the time domain representation of these subcarriers will still result in complex time domain samples, thereby increasing the amount of data that needs to be transmitted on the serial data link. Additionally, the serial data link between the BFP and the transceiver IC subarray and the serial data link of the individual transceiver IC in the interconnected given transceiver subarray may have limited data carrying capacity (e.g., how much data (data rate) can be conveyed on those links per given time period). Therefore, in some embodiments, it may be more desirable to perform IQ packet data transmission from / to the BFP and between the transceiver IC in the frequency domain.

[0061] Nevertheless, various embodiments of the signal processing methods and apparatus described herein may alternatively utilize time-domain IQ data packets. More specifically, in some embodiments, a beamformer processor (BFP) (e.g., BFP 202, 300, 400, etc.) may be configured to include a digital signal processing architecture (e.g., iFFT and FFT processing elements) to transmit and receive time-domain IQ data packets to / from a transceiver IC / transceiver IC subarray. For example, in some embodiments, the beamformer processor may include a digital signal processor (DSP) configured with appropriate programming instructions to execute algorithms for IFFT and FFT operations.

[0062] Figure 3 The transceiver subarray depicted in is one of many such subarrays on the panel, and each serially connected transceiver IC group receives a unique aggregate signal port (or dual signal port or multi-signal port) IQ data packet data stream. Recall that each serially connected transceiver IC group has at least two serially connected transceiver ICs and is physically arranged in a transceiver IC subarray. The transceiver IC subarray is in turn positioned adjacent to a corresponding radiating antenna element arranged in a corresponding antenna subarray in an element-by-element manner.

[0063] The transceiver IC 312 receives a unique aggregate signal port IQ data packet data stream at the serial port receiver 314 and provides the data to the split copy register 318 for further processing. In one embodiment, the split copy register 318 is a packet header processor that is configured to check the packet header to determine whether the IQ data is intended to be processed by its corresponding transceiver IC, and if so, forward the packet to the signal port split processor 320. The signal port split processor 320 (also labeled as H / V split) identifies packets or packet portions destined for different signal ports within the transceiver IC, and it can be H and V polarized signals, or other configurations as described herein. The signal port split processor 320 can be implemented as a register that performs memory write operations on a digital signal processor (DSP) memory space integrated within the transceiver IC 312. In addition, the split copy register 318 can determine that the same packet should also be forwarded to the next transceiver IC in the transceiver IC subarray for processing by one or more serially connected transceiver ICs. To reduce latency, the packet header processor or split copy register 318 need not buffer the entire signal port IQ data packet before determining to forward the packet to the next transceiver IC by sending the data to the serial data transmitter 332 for transmission on the serial link 348. In other embodiments, the packet header processor 318 may be configured to operate in a transparent mode, where all packets are saved for local processing and forwarded out of the second serial transceiver without header inspection.

[0064] For the signal port packet format 302, the aggregated IQ signal port packets are forwarded to each transceiver IC using split replica circuits 318, 352, 368 and are processed collectively by each transceiver IC. Note that transceiver IC 366 is the last transceiver IC in the chain, and in the illustrated embodiment, the split replica register 368 forwards the packet to the corresponding signal port split processor, but the serial transceivers 372 / 374 are not used.

[0065] Each transceiver IC then processes the packets by first separating the IQ data for a first signal port (H IQ data 322) and a second signal port (V IQ data 338) and providing the data to a transmitter within transceivers 321 and 335 for conversion to the time domain via an inverse fast Fourier transform (iFFT). As previously described, separate IQ port specific data may be transmitted in separate packets, in which case the signal port data may be directly stored for further processing without any separation or deinterleaving. The iFFT processing and subsequent time domain processing generates an aggregated signal port discrete time domain baseband data signal, which is then converted to an amplified radio frequency (RF) signal at ports 328, 344. The transmitters of transceivers 321, 335 (which transmit the IQ data with respect to the first signal port) and the second signal port (V IQ data 338) are connected to the transmitters of transceivers 321 and 335. Fig.12 A and Fig.13A The RF transceiver IC (described more fully herein) includes a DSP for computing the iFFT, frequency domain and time domain signal processing elements (cyclic prefix addition, phase and gain adjustment, frequency offset, filtering and sample rate conversion, crest factor reduction (CFR), digital pre-distortion (DPD), etc.), and RF modulation and amplification circuitry in the form of a multi-phase carrier generator and a digital power amplifier. Note that in alternative embodiments involving communication of, for example, aggregated signal port / user IQ data packets in the time domain (as mentioned above), the iFFT processing may be performed at the beamformer processor rather than at the transceiver IC itself.

[0066] Thus, some embodiments may include a method comprising: receiving a unique aggregate signal port IQ data packet data stream at each of a plurality of serially connected transceiver IC groups, each serially connected transceiver IC group comprising at least two serially connected transceiver ICs physically arranged in a transceiver IC subarray and positioned adjacent to corresponding radiating antenna elements arranged in a corresponding antenna subarray in an element-by-element manner; within each serially connected transceiver IC group, forwarding at least a subset of the aggregate signal port IQ data packets from a first transceiver IC to a next serially connected transceiver IC; transceiver IC; and at each transceiver IC of at least two serially connected transceiver ICs within each serially connected transceiver IC group: processing at least some of the aggregate signal port IQ data packets using an integrated inverse fast Fourier transform (IFFT) processor of the transceiver IC to convert the aggregate signal port IQ data packets into an aggregate signal port discrete time-domain baseband data signal; converting the aggregate signal port discrete time-domain baseband data signal into an amplified modulated RF signal using an integrated digital power amplifier and a multi-phase carrier generator of the transceiver IC; and transmitting the amplified modulated RF signal at at least one corresponding adjacent radiating antenna element of the corresponding adjacent radiating antenna elements.

[0067] In addition, some embodiments may include a device including a plurality of transceiver IC subarrays, each transceiver IC subarray including: a first transceiver IC having (i) a first serial digital data port providing a serial data connection to a beamformer processor, the first serial digital data port being configured to receive a unique aggregate signal port IQ data packet data stream; and (ii) a second serial digital data port; and a second transceiver IC having a third serial digital data port connected to the second serial data port of the first transceiver IC and providing a serial data connection to the first transceiver IC. The first transceiver IC and the second transceiver IC may be physically arranged in the transceiver IC subarray and positioned adjacent to a plurality of radiating antenna elements arranged in the antenna subarray in an element-by-element manner. The first transceiver IC in each transceiver IC subarray may further include a packet processor configured to forward at least a subset of the aggregate signal port IQ data packets received from the beamformer processor to a corresponding second transceiver IC. The first transceiver IC and the second transceiver IC may each include: a digital signal processor configured to perform an inverse fast Fourier transform (IFFT) to convert an aggregate signal port IQ data packet into an aggregate signal port discrete time-domain baseband data signal; a time-domain processing circuit configured to convert the aggregate signal port discrete time-domain baseband data signal into an oversampled signal port discrete time-domain data signal; and an integrated digital power amplifier and a multi-phase carrier generator configured to convert the oversampled signal port discrete time-domain data signal into an analog modulated RF signal.

[0068] When receiving an uplink (UL) signal, the receiver portion of the transceiver 321, 335 performs down-conversion and analog-to-digital conversion, followed by further time-domain processing (e.g., sampling rate conversion, quadrature error correction, filtering, frequency offset correction, cyclic prefix detection and removal, etc.), followed by an FFT conversion to frequency-domain IQ data values ​​for each of the multiple subcarriers in the OFDM signal. Thus, in a receive mode of operation, the transceiver IC generates a received RF signal from the received RF signal. Figure 3 IQ data packets 322, 338 depicted in FIG.

[0069] In one embodiment, the transceiver IC includes a digital signal processor (DSP) that not only performs all iFFT calculations to generate downlink (DL) transmission time domain signal port signals, but also processes the received uplink (UL) data samples via FFT to generate receive frequency domain IQ data signals associated with each of the signal ports. With respect to embodiments associated with packet structure 302, the UL frequency domain IQ data from each signal port may first be serialized into a single packet of the format of packet 302, where the H and V portions represent the UL receive frequency domain IQ information generated locally at the transceiver IC. However, when the receive IQ packet is transmitted along the transceiver IC subarray, the receive UL frequency domain IQ packet received from another transceiver IC in the subarray on the serial data link may be combined with the locally generated receive IQ data before transmission to the next transceiver IC. Specifically, when transceiver IC 350 receives a UL IQ packet from transceiver IC 366 on link 362, UL IQ packet processor 358 combines the received IQ data with its locally generated UL IQ data. As described more fully herein, combining may involve sample-by-sample addition (i.e., for each subcarrier, I data samples are added, and Q samples are added), or the I data and Q data of one packet may have a phase rotation added prior to combining. The combined UL IQ data packet received on link 346 via the Serdes receiver 330 is then further combined with the locally generated UL IQ data stored in the UL signal port IQ data concatenator 336 from transceivers 321 and 335. In this manner, for embodiments associated with the packet data format 302, the amount of received data transmitted along the links 362, 346, 310 remains the same for each serial data link along the transceiver IC subarray.

[0070] In another embodiment, a method includes: receiving modulated RF signals at multiple signal ports of each transceiver IC in a serially connected transceiver IC subarray; generating one or more frequency-domain digital data packets of subcarrier IQ data associated with each signal port by demodulating each modulated RF signal from each signal port using an FFT processor within the corresponding transceiver IC; forming multiple combined frequency-domain digital data packets from the transceiver IC using a set of serial data links between transceiver ICs in the serially connected transceiver IC subarray; and transmitting the multiple combined frequency-domain digital data packets from the transceiver IC subarray to a beamformer processor.

[0071] In some embodiments, each transceiver IC may be configured to process signals from two signal ports, such as signals from cross-polarized antenna elements, or sets of parallel elements. Other embodiments may use a transceiver IC with four separate signal ports. In each embodiment, a given signal port may receive multiple modulated carriers (each modulated carrier having a set of subcarriers), and the demodulated frequency domain data may be packetized according to the component carriers received therefrom. Thus, one or more frequency domain digital data packets of subcarrier IQ data associated with each signal port may be packetized together with header information identifying the signal port (such as a signal port id), the component carrier (such as a component carrier id), and additional identification information (e.g., a subcarrier subset id for multi-level beamforming). Each transceiver IC may participate in forming multiple combined frequency domain digital data packets by receiving frequency domain digital data packets of subcarrier IQ data from an adjacent transceiver IC via a serial data link and combining these frequency domain digital data packets with frequency domain digital data packets of subcarrier IQ data generated locally by itself. Depending on the location of a given transceiver IC within the transceiver IC sub-array, some transceiver ICs will actually receive partially formed combinations of frequency domain digital data packets.

[0072] For the embodiment associated with the packet structure 304 (note that the header is not shown for clarity), six separate signal port groups may be provided to the transceiver IC subarray from which six independent transmission signals may be generated. Generally speaking, the ability of the AAU system to generate independent RF transmission signals from the individual digital IQ data associated with each radiating element is referred to herein as full-dimensional beamforming. In this embodiment, representing the full-dimensional digitally beamformed signals, all six groups are received at the receive Serdes 314 at the transceiver IC 312 via link 308 and provided to the segmentation copy processor 318. The split copy processor 308 examines the packet headers and forwards a first set of two signal port packets (the rightmost H / V portions 324, 340 of the format 304) to the signal port split processor 320 for transmission processing of IQ data 324 by transceiver 321 (for port 328) and IQ data 340 by transceiver 335 (for port 344), and forwards the remaining four packets to the Serdes transmitter 332. The next transceiver IC 350 receives the four packets at its Serdes receiver over link 348, and the split copy processor 352 performs packet header analysis to forward the two signal port packets to its signal port split processor 354 within 350, and forwards the remaining two packets to the Serdes transmitter (TX#0 of transceiver IC 350) for transmission over link 364 to transceiver IC 366. The signal port splitting processor 354 provides the H and V signal port IQ data to its transceivers for transmission on signal ports 356, 360, respectively. The transceiver IC 366 receives and processes the remaining two IQ data packets in a similar manner for transmission on ports 370, 378. Note that for the DL IQ data packets, the amount of serial data is reduced along the transceiver IC subarray. In this embodiment, the receive processing does not involve any UL IQ packet data combination. Instead, the packets are only retransmitted from each transceiver IC (using UL IQ packet processor 358 and UL IQ packet processor 334 for concatenation / retransmission) so that all six receive UL signal port IQ packets are transmitted to the beamformer processor on link 310 (the packets may be formatted with separate headers, or may be transmitted as concatenated payloads with a single header). Note that the amount of data increases as packets from transceiver IC 366 on link 362 are concatenated with IQ data from transceiver IC 350 at UL IQ packet processor 358 for transmission on link 346. The amount of data increases again on link 310 when UL IQ data 340 and 324 from UL signal port IQ data concatenator 336 are concatenated by UL IQ packet processor 334.

[0073] In some embodiments, full dimensional beamforming groups unique to each signal port may be provided for smaller bandwidth signals such as 20 MHz data bandwidth. This may be desirable in certain deployments where the AAU panel is already configured with lower rate serial data connections in the transceiver IC subarray. Thus, even systems with lower speed serial data interconnects may support full control of the signal port signals (and corresponding radiating elements) by concatenating the individual IQ data of the interconnected transceiver ICs and extracting the relevant data set at each IC. This will allow support for MU-MIMO in the vertical plane with much higher accuracy, and support use cases associated with aerial drones (drones have data connectivity as users within the system, or by blocking interference from high altitude interfering drones).

[0074] In a third embodiment of the antenna array system, a multi-level beamforming signaling scheme may be used to provide data transmission and reception. In this embodiment, some transmission IQ data packets are processed jointly between multiple transceiver ICs to achieve a first level of beamforming resolution, while additional IQ data packet sets are allocated to each transceiver IC subarray, where each packet in a given additional transmission IQ packet set is processed between fewer (or even one) transceiver ICs in the transceiver IC subarray to obtain a second, higher resolution level of beamforming. Specifically, data format 306 provides a combination of beamforming resolutions, whereby two signal port IQ data packets (e.g., the first two H and V parts of 306, 326, 342) are processed by each of transceiver ICs 312, 350, and 366 for transmission in a manner similar to the signal processing described above with respect to packet format 302. Because the same IQ is transformed and transmitted by multiple corresponding radiating elements in a subarray, these IQ data packets (referred to herein as "commonly processed" IQ data) result in a first level of beamforming resolution, where beams are formed as a result of phase signal contributions emanating from other subarrays (i.e., inter-subarray beamforming). In addition, however, another set of six signal port IQ data packets (three additional H / V data sets of 306) are distributed across a given transceiver IC subarray in a manner similar to the signal processing described above with respect to the packet format 304 of all-digital beamforming data. These additional packets are dedicated to a given signal port and / or transceiver IC, and provide a unique IQ data stream for transmission by each individual signal port in a given transceiver IC subarray, thereby providing transmission and reception of a second level of beamforming resolution. Specifically, wherein beams are formed as a result of phase signal contributions from other transceiver ICs within a given subarray and phase signal contributions from other transceiver ICs within other transceiver IC subarrays (i.e., second level beamforming from both intra-subarray beamforming and inter-subarray beamforming).

[0075] have Figure 3 The packet of format 306 shown in FIG. 1 and as described below with respect to Fig.12 , Fig.13A and Fig. 13B Multi-level beamforming, further described, utilizes processing of two separate signal port IQ packets, such as IQ data 326 and IQ data 327 (and similarly 342, 343), indicated as being combined for transmission on the same signal port. In one embodiment, the separately beamformed IQ packets may include IQ data points for different subcarriers within a set of subcarriers of a single component carrier. Thus, each transceiver IC may form its own unique combined set of IQ data points for its respective signal port prior to iFFT processing. Specifically, transceiver IC 312 combines IQ data 326 and 327 via tandem for transmission on signal port 328, while combining IQ data 342 with IQ data 343 for transmission on signal port 344. The next transceiver IC in the transceiver IC subarray, transceiver IC 350, combines IQ data 326 (same as processed by transceiver 321 of transceiver IC 312) with signal port IQ data 355, and combines IQ data 342 (same commonly processed IQ data processed by transceiver 335 of transceiver IC 312) with signal port IQ data 359. A similar unique serial combination is shown in transceiver IC 366, where IQ signal port data packets 326 and 342 are respectively combined with unique signal port IQ data 369, 377. Within the transceiver IC subarray, the commonly processed IQ packets 326 and 342 provide a first level beamforming component contributed by the subarray, while the additional set of IQ packets distributed within the transceiver IC subarray provide a second level beamforming component associated with the subarray.

[0076] In other embodiments, the individual IQ packets may have overlapping subcarriers, in which case the transceiver IC processing includes forming a weighted average of the overlapping subcarriers prior to iFFT processing. In such embodiments, the beamformer processor may transmit one or more weights for the transceiver IC to use when forming a combination of IQ transmission data for the overlapping subcarriers.

[0077] Thus, in one embodiment, multi-level transmit beamforming includes receiving a first level beamformed IQ packet and a plurality of second level beamformed packets at a plurality of transceiver ICs in a transceiver IC subarray via serial data connections interconnecting the transceiver ICs; and at each transceiver IC: forming a multi-level beamformed packet by combining the first level beamformed IQ packet with at least one second level beamformed packet of the plurality of second level beamformed packets; generating a time domain signal from the multi-level beamformed packet; transmitting the multi-level beamformed signal by transmitting a corresponding amplified RF time domain signal from the transceiver IC in the transceiver IC subarray via a corresponding adjacent antenna element subarray.

[0078] In some embodiments, multi-level beamformed packets are formed by combining the IQ samples of the individual subcarriers via concatenation, followed by processing the packet with the same iFFT operation. In other embodiments, multi-level beamformed packets are formed by combining overlapping subcarriers using weights provided via management plane messages, followed by processing with the same iFFT operation.

[0079] In yet another implementation, the IQ packets conveying data for the second level of beamforming may be associated with subcarriers of a separate component carrier. In such an implementation, the additional higher resolution beamforming data may be processed independently using a separate iFFT before combining the time domain signals of the two levels of beamforming signals. Thus, in one embodiment, multi-level transmit beamforming includes receiving a first level beamformed IQ packet and a plurality of second level beamformed packets at a plurality of transceiver ICs in a transceiver IC subarray via a serial data connection interconnecting the transceiver ICs; and at each transceiver IC: converting the first level (commonly processed) beamformed IQ packet into a time domain signal, and converting at least one of the plurality of second level beamformed IQ packets into a time domain signal individually via a separate iFFT; combining the two time domain signals to form a signal port specific multi-level beamformed time domain signal; transmitting the multi-level beamformed signal by transmitting an amplified RF time domain signal generated from the corresponding signal port specific multi-level beamformed time domain signal from the transceiver IC in the transceiver IC subarray via a corresponding adjacent antenna element subarray. The plurality of transceiver IC subarrays and their corresponding antenna element subarrays cooperatively generate the multi-level beamformed signal.

[0080] In multi-level beamforming using distribution of multi-level IQ packet data among each of a plurality of transceiver IC subarrays, a group of users may be served by aggregated IQ signal port packets that are replicated and forwarded for processing by each transceiver IC along a given transceiver IC subarray, thereby yielding a first level of beamforming resolution (as determined, for example, by the total number of unique independent signal port IQ packet streams sent to the total number of corresponding transceiver IC subarrays for processing by each transceiver IC). However, in addition, a separate group of users may be served by higher resolution beamforming by distributing additional signal port specific IQ data packets along the transceiver IC subarray for separate processing by each separate transceiver IC (i.e., non-commonly processed IQ data).

[0081] In many embodiments, note that the co-processed IQ packets for multi-level beamforming signal processing are unique to a particular transceiver IC subarray. However, in some cases, to achieve certain desired beam radiation patterns (i.e., those with an even lower degree of beamforming resolution), some co-processed IQ packets may be identical for two or more transceiver IC subarrays.

[0082] The receive UL signal processing for multi-level beamforming is also a hybrid of the above-described UL receive signal processing, where IQ data combining may be performed for a first pair of signal port IQ packets, and IQ data concatenation may be performed for additional sets of independent UL signal port IQ data packets. Thus, the first level of beamforming is performed by each transceiver IC participating in forming a UL combined frequency domain digital data packet by receiving frequency domain digital data packets of subcarrier IQ data from an adjacent transceiver IC via a serial data link and combining these frequency domain digital data packets with its own locally generated frequency domain digital data packets of subcarrier IQ data. The second level of beamformer processing involves transmitting the UL receive IQ packets along the transceiver IC subarray without combining, but rather via concatenation (sample-by-sample or packet-by-packet so as not to change the IQ samples).

[0083] In some embodiments of an array of N×M transceiver ICs configured as a set of N transceiver IC subarrays, each having M serially connected transceiver ICs, multi-level beamforming can be characterized by: processing a first aggregated set of beamformed frequency-domain IQ user data according to a first level of beamforming resolution to generate N unique beamformed IQ data packets (or sets of packets, such as an IQ data set for each signal port (e.g., H and V) within the transceiver IC), each beamformed IQ data packet being used for distribution to a corresponding transceiver IC subarray in the N transceiver IC subarrays; while also processing a second set of beamformed aggregated frequency-domain IQ user data sets according to a second level of beamforming resolution to generate N different sets of M unique beamformed IQ data packets (or sets of packets for each set of signal ports of the transceiver IC), and wherein each of the N sets of M packets is distributed to a corresponding transceiver IC subarray in the N transceiver IC subarrays. Each of the various packets is sent to the N transceiver IC subarrays over a respective serial data link. Each transceiver in a given subarray will collectively process packets associated with first level beamforming data in conjunction with only a portion of the individually beamformed second level beamforming packets.

[0084] refer to Fig.16 , shows an embodiment of dual level beamforming whereby the panel may be configured to process UL and DL data according to a first level of beamforming using subarray level beamforming (as shown at 1604) utilizing three dual polarization elements per subarray 1606 and provide beams (e.g., 1612) within a scan range 1614. In the illustrated embodiment, the subarray level beamformer generates beamformed IQ packets for frequency content 1618, which are processed jointly within each respective subarray as described with respect to IQ data 326 and 342. The same panel may simultaneously be configured (as shown at 1600) to provide another or second level of beamforming with higher phase resolution, having a unique beamformed IQ data set for producing a unique signal at each cross-polarization element 1602. In the embodiment shown, the subarray level beamformer generates beamformed IQ packets for frequency content 1618, which are processed jointly within each respective subarray as described with respect to IQ data 326 and 342. Fig.16 In an embodiment of the present invention, frequency content 1616 may be allocated to high-resolution beamforming levels, such as data 327, 343, 355, 359, 369, and 377. The frequency content of frequency range 1616 and frequency range 1618 may correspond to different subcarriers within a single component carrier, or may be separate component carriers, etc., as described herein.

[0085] Note that in the second level of beamforming, due to the higher phase resolution, the individual beams (e.g., 1608) can be steered across a wider scan range 1610. In contrast, the scan angle in subarray beamforming (where multiple signal ports transmit and receive signals processed according to a common IQ beamforming grouping) has a limited scan range due to the increased quantization error in the beamforming weights, as shown in FIG. Fig.17 . Specifically, the scan angles of two representative beams represented by the diagonal lines labeled "desired BF weights" depict two separate beams with different scan angles. In full-dimensional beamforming, IQ data for each signal port is formed using desired weights with phases as indicated, including, for example, points 1702, 1710, and 1706 for lower scan angles and example points 1712, 1720, and 1716 for steeper scan angles (as shown by dashed lines). However, in subarray beamforming, the jointly processed beamformed IQ data may be generated using the average phase of the desired beams across the elements in a given subarray, which is shown by the example phases 1704, 1710, 1708 of one beam and the phases 1714, 1718, 1720 of the steeper beam. The corresponding beamforming weight phase error is shown with the line labeled "BF weight error". Note that steeper scan angles have higher beamformer weight errors. Thus, the second level of beamforming allows for larger scan angles because there are no quantization errors, and the subarray beamforming has a reduced scan range. Note that for a two-element subarray, the beamforming weights used to form the individual beams can be an average between two desired phase values, or a value between two desired weight phases. Finer phase control avoids what is sometimes referred to as "quantization lobes," which result from the applied weights being constrained to be the same for several adjacent elements in the subarray. Quantization lobes increase with increasing scan angle.

[0086] In short, full-dimensional beamforming is done with a higher level of precision in the beamformer weights, whereas subarray beamforming is performed with an average of the desired weights, thereby introducing errors. Therefore, an element with full-dimensional control configured according to 1600 has a larger scanning range than a subarray beamforming configuration 1604 that beamforms using an average bf weight for each given beam (such as a UE-specific beam, or a spatial multiplexing layer beam, etc.).

[0087] The multi-level beamforming described herein can be used to provide high quality service to a group of users (such as those located in a high-rise building within a cell sector) without sacrificing coverage of other user devices located on the ground (e.g., by limiting the allocated bandwidth). Similarly, the system enables support for communications with drones and other high-altitude devices in conjunction with ground-based user devices. The system described herein is configured to provide these alternative beamforming transmissions between user devices within a single radio unit.

[0088] A multi-mode beamforming system may be configured to sequentially or dynamically allocate OFDM transmissions on a slot-by-slot basis according to two or more levels of beamforming resolution. Specifically, a first time transmission time interval (TTI) or even a first OFDM symbol slot may be allocated to a user device that is beamformed according to a first level of subarray-level beamforming such that during transmit signal processing, transmit IQ data packets sent to each transceiver IC subarray are processed jointly by each transceiver IC within each such subarray. Similarly, during signal reception, the processed IQ data packets for each transceiver IC are combined as they are transmitted from transceiver IC to transceiver IC along the serially connected transceiver ICs in each subarray. In a second or subsequent time slot, frequency resource blocks may be allocated to the user equipment for higher resolution beamforming, including fully steered beamforming IQ data according to a second level of higher phase resolution beamforming, wherein separate transmit IQ packets are separately formed for serial data transmission and sent to each transceiver IC subarray for separate processing by specifically addressed transceiver ICs within each such subarray.

[0089] In some embodiments, the transmission bandwidth associated with a fully controlled digital beamforming IQ data packet (i.e., the number of IQ sample pairs corresponding to the number of modulated subcarriers) may be less than the bandwidth utilized by the jointly processed IQ data packets, such as a comparison between the jointly processed packet data 302 and the fully digital beamforming packet data 304. In some embodiments, a method of multi-level beamforming includes: receiving a first level beamforming frequency domain IQ data packet and a plurality of second level beamforming frequency domain IQ data packets at a transceiver IC subarray having a plurality of interconnected transceiver ICs (ICs), the transceiver ICs being interconnected via a plurality of serial data connections; at each transceiver IC of the transceiver IC subarray: forming a multi-level beamforming frequency domain IQ data set by combining beamformed frequency domain IQ data from the first level beamforming frequency domain IQ data packet with beamformed frequency domain IQ data from a selected second level beamforming frequency domain IQ data packet from the plurality of second level beamforming frequency domain IQ data packets; generating a discrete time domain signal from the multi-level beamforming frequency domain IQ data set using a digital signal processor (DSP) within the transceiver IC; generating a modulated radio frequency (RF) signal from the discrete time domain signal; and transmitting the multi-level beamformed signal by transmitting a corresponding modulated RF signal from the transceiver IC in the transceiver IC subarray via a corresponding adjacent antenna element subarray. Transmitting the multi-level beamformed signals may be performed by transmitting respective modulated RF signals from transceiver ICs in a plurality of transceiver IC subarrays via a corresponding plurality of adjacent antenna element subarrays.

[0090] In some embodiments, the method includes receiving a first level beamformed frequency domain IQ data packet and a plurality of second level beamformed frequency domain IQ data packets at a transceiver integrated circuit (IC) subarray, and further includes: forwarding the first level beamformed frequency domain IQ data packets from a first transceiver IC of the transceiver IC subarray to an additional transceiver IC of the transceiver IC subarray for common processing; and forwarding only a subset of the second level beamformed frequency domain IQ data packets of the plurality of second level beamformed frequency domain IQ data packets from the first transceiver IC to the additional transceiver IC. The method may include wherein the subset of the second level beamformed frequency domain IQ data packets is identified according to a packet header. Some methods combine the beamformed frequency domain IQ data from a first level beamforming frequency domain IQ data group with the beamformed frequency domain IQ data from a selected second level beamforming frequency domain IQ data group from a second level beamforming frequency domain IQ data group by concatenating the beamformed frequency domain IQ data from the first level beamforming frequency domain IQ data group with the beamformed frequency domain IQ data from a selected second level beamforming frequency domain IQ data group from the second level beamforming frequency domain IQ data group before frequency domain to time domain conversion. In some examples, combining the beamformed frequency domain IQ data from the first level beamformed frequency domain IQ data packets with the beamformed frequency domain IQ data from the selected second level beamformed frequency domain IQ data packets from the second level beamformed frequency domain IQ data packets is performed by forming a weighted sum of the beamformed frequency domain IQ data from the first level beamformed frequency domain IQ data packets and the beamformed frequency domain IQ data from the selected second level beamformed frequency domain IQ data packets from the second level beamformed frequency domain IQ data packets before frequency domain to time domain conversion. The weighted sum may be calculated based on beamforming weights received from the beamformer.

[0091] In other embodiments, combining the beamformed frequency domain IQ data from the first-level beamforming frequency domain IQ data group with the beamformed frequency domain IQ data from the selected second-level beamforming frequency domain IQ data group from the second-level beamforming frequency domain IQ data group is accomplished in the time domain by: converting the beamformed frequency domain IQ data from the first-level beamforming frequency domain IQ data group into a first-level beamforming time domain signal; converting the beamformed frequency domain IQ data from the selected second-level beamforming frequency domain IQ data group from the second-level beamforming frequency domain IQ data group into a second-level beamforming time domain signal; and adding the first-level beamforming time domain signal to the second-level beamforming time domain signal.

[0092] The first level beamformed frequency domain IQ data packets and the selected second level beamformed frequency domain IQ data packets of the second level beamformed frequency domain IQ data packets may be associated with different component carriers. The method may involve queuing the data packets according to the location of the expected transceiver ICs so that the second level beamformed frequency domain IQ data packets are received for processing by the transceiver IC at the end of the transceiver IC subarray before the second level beamformed frequency domain IQ data packets are received for processing by the transceiver IC at the beginning of the transceiver IC subarray.

[0093] Some example embodiments of an apparatus include: a beamformer processor configured to generate a frequency-domain IQ data packet for a first level of beamforming and a plurality of frequency-domain IQ data packets for a second level of beamforming; a transceiver integrated circuit (IC) subarray connected to the beamformer processor and having a plurality of interconnected transceiver ICs interconnected via a plurality of serial data connections; each transceiver IC of the transceiver IC subarray including: a digital signal processor (DSP) configured to form a frequency-domain IQ data set for multi-level beamforming and to generate a discrete time-domain signal from the frequency-domain IQ data set for multi-level beamforming; an RF modulator configured to generate a modulated RF signal from the discrete time-domain signal; and an antenna element subarray connected to the transceiver IC subarray and configured to transmit the multi-level beamformed signal by transmitting a corresponding modulated RF signal from a transceiver IC in the transceiver IC subarray. The transceiver IC subarray may include a first transceiver IC having a packet header processor configured to forward first level beamformed frequency domain IQ data packets from the first transceiver IC to an additional transceiver IC in the transceiver IC subarray for common processing and configured to forward only a subset of second level beamformed frequency domain IQ data packets from the first transceiver IC to the additional transceiver IC. The packet header processor may be configured to identify the subset of second level beamformed frequency domain IQ data packets based on a packet header.

[0094] The DSP may be configured to combine the beamformed frequency domain IQ data from the first level beamforming frequency domain IQ data group with the beamformed frequency domain IQ data from the selected second level beamforming frequency domain IQ data group from the second level beamforming frequency domain IQ data group before frequency domain to time domain conversion. The DSP may be configured to combine the beamformed frequency domain IQ data from the first level beamformed frequency domain IQ data packets with the beamformed frequency domain IQ data from the selected second level beamformed frequency domain IQ data packets from the second level beamformed frequency domain IQ data packets by forming a weighted sum of the beamformed frequency domain IQ data from the first level beamformed frequency domain IQ data packets and the beamformed frequency domain IQ data from the selected second level beamformed frequency domain IQ data packets from the second level beamformed frequency domain IQ data packets before frequency domain to time domain conversion. The DSP may be configured to calculate the weighted sum based on the beamforming weights received from the beamformer processor.

[0095] In some embodiments, the DSP is configured to: convert beamformed frequency domain IQ data from a frequency domain IQ data group of a first level beamforming into a time domain signal of the first level beamforming; convert beamformed frequency domain IQ data of a selected second level beamforming frequency domain IQ data group from a frequency domain IQ data group of a second level beamforming into a time domain signal of the second level beamforming; and add the time domain signal of the first level beamforming to the time domain signal of the second level beamforming.

[0096] The apparatus may include a packet header processor configured to identify a separate component carrier associated with a selected second-level beamformed frequency-domain IQ data packet of the first-level beamformed frequency-domain IQ data packet and a second-level beamformed frequency-domain IQ data packet. The beamformer processor may be configured to transmit the second-level beamformed frequency-domain IQ data packet for processing by a transceiver IC at an end of the transceiver IC subarray before transmitting the second-level beamformed frequency-domain IQ data packet for processing by a transceiver IC at a beginning of the transceiver IC subarray. The apparatus may also include a plurality of transceiver IC subarrays and a corresponding plurality of adjacent antenna element subarrays configured to transmit multi-level beamformed signals.

[0097] Some embodiments may utilize full-dimensional beamforming data streams in a serially connected transceiver array. In these embodiments, each signal port has a unique signal for fully controlling the beamforming phase. Therefore, unique packets are sent to each transceiver IC subarray, and these unique packets (by a combination of one or more field IDs, or a combination of ID sets) are addressed to each transceiver in the subarray. The packets can be time-ordered to account for latency, so that the IQ packets addressed to the transceiver IC at the end of the serially linked transceiver IC chain are sent first so that they are received at the end of the array. Therefore, the packets can be ordered in a round-robin manner, where the first packet is sent to each transceiver IC so that processing can start at each IC, and then additional packets are sent to each transceiver IC.

[0098] Each transceiver has a serial link and a packet header analyzer circuit for performing header checks, where each stream to each subarray includes a separate data packet with unique digital beamforming data addressed to a separate transceiver within the set of serially connected transceivers. The packet header analyzer within each transceiver Serdes can make per-packet forwarding decisions. In one configuration, packet bandwidth is equally allocated between the two signal paths of each transceiver IC, such as packets for two signal ports (H and V).

[0099] When receiving signals in serially linked transceiver ICs in a subarray, the serial data rate between ICs is limited, and therefore subarray beamforming may include receiving IQ data combinations before transmission back to the beamformer. In some embodiments, combining weights are provided to the transceivers in a given subarray so that these combining weights will adjust the phase as part of receive combining. Electronic tilting is one such case.

[0100] Figure 4 is an alternative embodiment of a radio unit architecture having a hierarchical data distribution topology from the DL / UL beamformer 400 to corresponding serially connected groups of transceiver ICs (e.g., one such transceiver IC subarray is a set of transceiver ICs connected via serial links 418 and 420). In this embodiment, the beamformer 400 has a high rate serial data connection (e.g., 402) to an intermediate SerdesMUX device 404 (as well as connections to 422, 424, 426), each of which then provides a separate serial data connection (e.g., link set 406). The separate serial connections from each Serdes MUX can utilize a lower data rate for connection to a corresponding subset of the transceiver IC subarrays 421a, 421b, 421c, 421d. In Figure 4In an embodiment of the present invention, the subset of transceiver IC subarrays 421a includes eight transceiver IC subarrays, each of which has three transceiver ICs connected to corresponding antenna elements. Note that for clarity, the remaining set of transceiver IC subarrays 421b, 421c, 421d are depicted in a simplified manner (including connectivity to a simplified set of antenna element subarrays).

[0101] Figure 4 The transceiver IC subarray is also configured in a time division duplex (TDD) configuration with a SPDT (single pole double throw) switch 412. The received signal may be filtered via filter 410 and amplified with a low noise amplifier (LNA) 408. Signal couplers (e.g., 414, 416) are also depicted, which provide a signal copy of the transmitted RF signal (typically at a much lower power) to a monitoring or observation transceiver 428 via a calibration port 430.

[0102] Figure 5 Embodiments of a synchronization and clock distribution circuit 500 for use with transceiver ICs distributed across an active antenna array assembly are depicted. More specifically, some embodiments include a method comprising: receiving a clock signal and at least one synchronization pulse signal at each transceiver IC in a plurality of transceiver IC subarrays, wherein each transceiver IC subarray comprises a corresponding set of serially connected transceiver ICs. The method further comprises, at each transceiver IC: (i) synchronizing the transceiver IC with other transceiver ICs in the corresponding set of serially connected transceiver ICs by resetting a delta-sigma modulator (DSM) circuit to a predetermined state based on the received at least one synchronization pulse signal; (ii) generating a carrier frequency signal using a phase-locked loop (PLL) circuit including the DSM circuit; and (iii) processing frequency domain in-phase and quadrature (IQ) data using the generated carrier frequency signal.

[0103] In addition, some embodiments include an apparatus comprising: a plurality of transceiver IC subarrays, wherein each transceiver IC subarray includes a respective set of serially connected transceiver ICs; a beamformer processor coupled to the plurality of transceiver IC subarrays, wherein the beamformer processor is configured to generate at least one synchronization pulse signal and provide the at least one synchronization pulse signal to each transceiver IC; and a plurality of clock buffer circuits coupled to the beamformer processor via a clock distribution circuit, wherein the plurality of clock buffer circuits are configured to output a plurality of clock signals. , and providing a corresponding clock signal to each transceiver IC, and wherein each transceiver IC is configured to: (i) receive the corresponding clock signal and the at least one synchronization pulse signal; (ii) synchronize the transceiver IC with other transceiver ICs in a corresponding set of serially connected transceiver ICs by resetting the delta-sigma modulator (DSM) circuit to a predetermined state according to the received at least one synchronization pulse signal; (ii) generate a carrier frequency signal using a phase-locked loop (PLL) circuit including the delta-sigma modulator (DSM) circuit; and (iv) process frequency domain IQ data using the generated carrier frequency signal.

[0104] Return to reference Figure 5 Within the beamformer processor circuit 502, clock signals may be generated from a clock and data recovery (CDR) circuit 508 using a data interface circuit 506, which may then be provided to a dual PLL clock circuit 512, which provides clock signals 522, 524 for use by the beamformer processor 502, which in turn may generate another clock signal on line 526. The clock signals may be transmitted to the transceiver IC (e.g., Figure 5 Clock signal distribution for one such transceiver IC 540 (depicted in FIG. 5 ) is provided by a clock buffer 536 that receives input from a clock distribution circuit 534 driven by PLL2 532, PLL1 530 in conjunction with a system reference clock based on a selection from MUX 528. Thus, in some embodiments, the clock distribution circuit 534 is driven by the clock signal (on line 526) from the beamformer processor 502 and the system reference clock.

[0105] In some embodiments, the distributed clock signal is a high frequency signal with a frequency range of 50MHz to 150MHz. In addition, in some embodiments, the clock buffer clock circuit 536 is configured to adjust the clock signal timing at the output of each clock buffer circuit so that the corresponding clock signal is received by each transceiver IC at substantially the same time. For example, in an exemplary embodiment, the clock buffer circuit 536 can be programmed and can be configured to adjust the clock signal timing at each output to consider the signal transmission delay associated with the clock signal path so that the clock signal (specifically, the rising edge and / or falling edge transition of the clock signal) arrives at each transceiver IC with a low relative skew. In this regard, low skew means arriving at substantially the same time so that the arrival time is distributed in a range of less than one nanosecond or two nanoseconds from each other. In some embodiments, low skew refers to less than 333 picoseconds (1 / 3 nanosecond). In this regard, the clock buffer 536 can be adjusted according to the calibration process.

[0106] In some embodiments, in addition to receiving substantially synchronized clock signals, transceiver ICs (e.g., transceiver IC 540) are also synchronized with respect to each other at a macro timing level for one or more purposes via the addition of at least one synchronization pulse signal. Specifically, the transceiver ICs (which may be interconnected in a transceiver IC subarray via an asynchronous serial data bus and also directly or indirectly interconnected with the beamformer processor 502, as described herein) have one or more subsystems that may benefit from further synchronization. In some embodiments, such as Figure 5 As shown in , such a synchronization pulse signal (denoted as a "SYNC" pulse signal) is generated by the beamformer processor 502 and provided to each transceiver IC for further synchronization.

[0107] In one aspect, each of the transceiver ICs physically distributed on the antenna array assembly is configured to independently process a low-skew distributed (e.g., high frequency) clock signal and responsively generate a carrier frequency signal for processing transmit and receive modulated RF signals. Thus, a voltage-controlled oscillator (VCO) of each transceiver IC for generating a carrier phase to modulate a transmit signal and mixing / down-converting a received RF signal is closely aligned across the transceiver IC subarrays distributed on the antenna array assembly.

[0108] In some embodiments, the transceiver IC VCO employed herein uses a VCO adjustment loop that includes a phase-locked loop (PLL) circuit having a delta-sigma modulator (DSM) 544, a multi-mode divider (MMD) 546, a phase / frequency detector (PFD) 548, a loop filter 550, a VCO 552, and a divider 554. The fractional divider in the VCO adjustment loop is used to adjust the division modulus (i.e., the division ratio) used by the MMD 546. The MMD 546 utilizes a divisor value sequence obtained from the DSM 544.

[0109] In this regard, as noted above, some embodiments described herein include a method comprising (among other things): synchronizing a transceiver IC with other transceiver ICs in a corresponding set of serially connected transceiver ICs (in a corresponding transceiver subarray) by resetting the DSM circuit to a predetermined state based on at least one received synchronization pulse signal; and generating a carrier frequency signal using a PLL circuit that includes the DSM circuit.

[0110] Additionally, in one embodiment, in order to generate a carrier frequency signal using a PLL circuit (which includes a DSM circuit), each transceiver IC is configured to (i) use the DSM circuit to set the frequency division ratio of the MMD, and (ii) provide the frequency division signal from the MMD to the PFD for comparison with the clock signal to further adjust the frequency division ratio of the MMD. In other embodiments, the DSM circuit includes a plurality of accumulators, and wherein in order to reset the DSM circuit to a predetermined state according to at least one received synchronization pulse signal, each transceiver IC is further configured to set the plurality of accumulators of the DSM circuit according to at least one received synchronization pulse signal.

[0111] In general, various embodiments described herein utilize DSM circuits (such as DSM 544) to increase the frequency resolution of the carrier frequency signal generated by each transceiver IC for processing the transmission and reception modulated RF signals. In this regard, in some embodiments, the DSM circuit is configured to use a time-varying sequence representing a fractional input portion in conjunction with a fixed integer input portion to obtain a relatively high resolution carrier frequency. In one example, when the DSM circuit is used in a PLL circuit, the VCO frequency resolution can be as fine as .114 Hz. The DSM circuit operation is described in more detail below.

[0112] like Figure 5As depicted, the DSM 544 may include a fractional input (FRAC IP) block 572, a DSM accumulator (DSMACC) 574, a fractional output (FRAC OP) block 576, and a summing circuit 578. In operation, the FRACP IP receives an input 570 including a digital fractional input value and generates a corresponding fractional input portion, which is input into the DSMMACC 574. As further shown, the DSM accumulator 574 and the FRAC OP 576 form a loop. Generally speaking, in this loop, the fractional input portion passed to the DSM accumulator 574 at the current time is also referenced from the FRAC OP 576 back to the DSM accumulator. Here, the current fractional output is subtracted from the current fractional input portion value stored in the accumulator 574. Although not shown in FIG. Figure 5 Although not explicitly shown in the exemplary embodiment, DSMACC 574 includes multiple accumulators, each of which can (i) receive a previously stored version of its accumulated output, (ii) use feedback from FRAC OP 576 to subtract the current fractional output, and (iii) pass the result to a subsequent accumulator.

[0113] As a result of the above operations, the total fractional output produced by FRAC OP 576 is provided to summing circuit 578. Then, summing circuit 578 sums (adds) the fractional output portion with the actual integer input portion 580 to generate a desired divisor value, which is provided as an input to MMD 546. In some embodiments, the output of DSM 544 is in the form of a divisor control word (e.g., a set of data bits) that configures what divisor MMD 546 uses. Due to the time-varying nature of the fractional input portion, the control word will also vary over time. However, for a given operating interval, on average, a desired ratio can be achieved.

[0114] As noted above, in one embodiment, transceiver IC 540 is synchronized with other transceiver ICs in its corresponding transceiver IC subarray by resetting a DSM circuit (such as DSM 544) to a predetermined state in response to at least one received synchronization pulse signal. Figure 5 As further shown in the example of , the transceiver 540 is configured to receive such a synchronization pulse signal (here, the "SYNC" pulse signal from the beamformer processor 502), wherein the synchronization pulse signal is provided to the DSMACC 574 so as to set multiple accumulators of the DSMACC 574 according to the synchronization pulse signal.

[0115] In some embodiments, the reset provided by the sync pulse signal is a one-time event performed, for example, during startup.Thereafter, transceiver IC synchronization can be automatically obtained due to the global shared high-speed clock distributed to each transceiver IC (as described above).

[0116] During normal operation, MMD 546 will utilize the divisor ratio sequence obtained from DSM 544. In this way, the divisor sequence used to divide the VCO frequency from VCO 552 (or the divided signal provided by a divider such as divider 554) will be the same across all transceiver ICs. Therefore, in some embodiments, MMD 546 is configured to utilize the divisor ratio sequence provided by DSM 544, where the divisor sequence is synchronized across all transceiver ICs according to the synchronization pulse signal.

[0117] like Figure 5 As further shown, the divided frequency signal from the MMD 546 is provided to a PFD 548 for comparison with the high frequency distributed clock signal from the clock buffer 536. The PFD 548 generates a phase error signal, which is then filtered by a loop filter 550 having a transfer function H(z). The filtered phase error signal is then provided to a VCO 552 to correct the phase error. Synchronization of the VCO phase error measurement circuitry (such as the DSM 544 divisor sequence) across the transceiver ICs reduces jitter in the carrier frequency used for transmit and receive signal processing between the transceiver ICs.

[0118] In addition, if Figure 5 As shown, the output carrier frequency signal of the frequency divider 554 may be provided to a digital delay line (DDL) 556. In some embodiments, the DDL 556 is configured to generate a carrier frequency signal having multiple phases at an output 558. For example, in one embodiment, the multiple phases may include at least four phases of 0 degrees, 45 degrees, 90 degrees, and 135 degrees, wherein the carrier frequency is in the range of 3.6 GHz to 4 GHz. As will be described in further detail below, the generated carrier phases (and, for example, their inversion) may be used by a multi-phase digital power amplifier for RF modulation. More specifically, in some embodiments, a multi-phase DPA may be used to modulate a discrete time domain signal representing DL (downlink) frequency domain IQ data onto a generated carrier frequency signal, wherein the multi-phase DPA uses the selected phase of the generated carrier frequency signal for RF modulation. The phase may be selected based on the discrete time domain signal.

[0119] On the other hand, the transmit and receive signal processing circuits within the transceiver IC may use a numerically controlled oscillator (NCO), such as Figure 5 The NCO 542 shown in FIG. 5 is used to provide frequency shifting (conversion) via time domain complex multiplication, as described herein with respect to FIG. Fig.13A , Fig. 13B as described.

[0120] The NCO may also utilize components that may benefit from synchronization of the SYNC pulse signal. In some embodiments, the NCO utilizes a phase accumulator that is incremented by a frequency control word (FCW) at each clock interval. If the individual NCOs in different transceiver ICs have different phase accumulator values, this may introduce phase offsets in the transmit and receive signal processing. Synchronization of the NCO phase accumulator circuits across transceiver ICs reduces phase offsets in the transmit and receive signal processing between transceiver ICs.

[0121] Return to reference Figure 5 In the example of FIG. 5 , NCO 542 includes FCW register 562, phase accumulator (PACC) 564, and phase-amplitude converter (PAC) 566. Figure 5 As shown, the FCW register 562 can receive the FCW input 560 (e.g., from a DSP, etc.) and responsively generate a FCW to be loaded into the PACC 564 at each clock interval. Generally speaking, the FCW is a series of data bits and represents a phase increment value. In some embodiments, the FCW register 562 will be configured to use the FCW to generate a corresponding phase increment (e.g., via a lookup table, etc.). In some embodiments, the PACC 564 is configured to add the corresponding phase increment to its internal memory register. In this way, the phase value accumulated by the PACC 564 through the step-like phase increment is a binary representation of an angle that starts at 0 degrees, ramps up to 360 degrees, wraps around to 0 degrees again and restarts at the next cycle (clock interval). The output phase value of the PACC 564 is then passed to the PAC 566 for conversion to a complex sine to be output by the NCO 542. PAC 566 is configured to convert the accumulated phase value from PACC 564 into a dual output of a sine and cosine function corresponding to the angle of the phase value, representing the real and imaginary components that form a complex sinusoid at NCO output 568 .

[0122] Additionally, in some embodiments, the NCO 542 receives a synchronization pulse signal to reset the NCO 542 based on the synchronization pulse signal. This can synchronize the NCO phase accumulator circuit across the transceiver IC, as noted above. More specifically, in some embodiments, the phase accumulator of the NCO is reset based on the received synchronization pulse signal. Figure 5 As shown in the example of , the SYNC pulse signal is provided to the PACC 564 of the NCO 542 to reset the PACC 564. With this phase accumulation reset in each transceiver IC, all transceiver ICs distributed across the active antenna array assembly can begin phase value accumulation at 0 degrees.

[0123] Note (as described in conjunction with the operation of the DSM circuit), some embodiments provide a sync pulse signal reset as a one-time event performed, for example, at some time during startup. Thereafter, transceiver IC synchronization may be automatically achieved due to the global shared high-speed clock distributed to each transceiver IC (as described above).

[0124] In addition, the synchronized NCO 542 may be used to provide frequency shifting (conversion) via time domain complex multiplication, as described herein in conjunction with Fig.13A , Fig. 13B For example, the transmission side signal processing ( Fig.13A ), the NCO 542 may be configured to multiply the time domain signal by a complex sine function to perform a frequency shift of the baseband signal to a desired frequency range (such as a separate frequency range that does not overlap with other component carriers). Fig. 13B ), the signal received by the transceiver IC 540 may be shifted to a desired baseband signal via complex multiplication by the NCO 542.

[0125] In additional embodiments, synchronized NCO 542 may be used to operate on frequency domain data to provide incremental phase rotation to subcarrier specific frequency domain IQ data for electronic beam tilt as described herein.Of course, multiple instances of NCO 542 may be used for various signal processing functions as described herein.

[0126] like Figure 6 As depicted in the various embodiments illustrated in , clock distribution is configured according to signal lines routed across panel 102 to provide clock signals to transceiver IC subarrays to reduce clock skew. As noted above, in some embodiments, multiple clock buffer circuits (e.g., 536) may be configured to adjust the timing of the clock signals at the output of each clock buffer circuit so that the corresponding clock signals are received by each transceiver IC at substantially the same time. In some other embodiments, multiple transceiver IC subarrays, beamformer processors (e.g., 502), and multiple clock buffer circuits are all physically co-located within the antenna array assembly, and each clock buffer circuit is physically distributed across the antenna array assembly in a physical location corresponding to the physical location of one or more transceiver IC subarrays.

[0127] For purposes of illustration, in one embodiment, the clock signal distribution has a tree-like structure that symmetrically provides clock signals to each transceiver IC subarray, such as subarray 600 (which may be one or more transceiver IC subarrays). Specifically, in the illustrated embodiment, a given branch clock signal from clock buffer 610 is transmitted to clock signal conductors 606, which are split to provide clock signals on lines 602, 608, which drive another set of clock buffers (e.g., buffer 604 driven by line 602) and are then provided to the transceiver IC subarrays (e.g., 600). In one embodiment, the four clock buffers at level 610 may be provided by the clock distribution circuit 534. In addition, each clock buffer 536 is physically distributed across the antenna array assembly to serve transceiver IC subarrays that are also physically distributed across the antenna array assembly. In the illustrated embodiment, each clock buffer may provide eight separate clock outputs to eight separate transceiver ICs. Figure 6 In the embodiment of FIG. 6 , one clock buffer circuit is depicted as clock buffers 603, 604, which provide clock signals to four transceiver ICs within block 600 and four transceiver ICs below the block, as shown.

[0128] Figure 7 is a block diagram of an ORAN (Open Radio Access Network) based system 700 according to some embodiments, the system including a distributed unit connected to a radio unit via a fronthaul data interface and a hierarchical beamformer architecture within the radio unit. Generally speaking, in an ORAN architecture, base station functions (e.g., functions of a 5G NR Node B (gNB)) can be split between a centralized unit (CU), one or more distributed units (DUs) connected to the CU via a midhaul interface, and one or more radio units (RUs) connected to the DU via a fronthaul interface. For example, Figure 7 A DU (distributed unit) 702 is depicted having, among other things, a baseband transmission unit 706, a precoding / beamforming combination weight calculation unit 710 (which receives a scheduler input 708), a channel estimation unit 714, and a baseband reception unit 716. The DU 702 includes an ORAN interface 712 for connecting to a radio unit (RU) 704 via a fronthaul data interface that carries control information (C-plane (control plane) 718), management information (M-plane (management plane) 720), and user data (U-plane (user plane) 722). In general, an ORAN RU (such as RU 704) may act as a fronthaul gateway (e.g., implemented by an FPGA) that performs various baseband processing associated with the physical (PHY) layer and RF front-end functions for transmission and reception of RF signals over an air interface.

[0129] Also depicted is a hierarchical beamformer architecture 722 within the radio unit 704. The hierarchical beamformer 722 includes a main (primary) beamformer processor 724 (or simply "main (primary) beamformer 724") and a plurality of distributed secondary beamformer processors, such as BF#1 (728), BF#2 (734), BF#3 (736), and BF#4 (738) (or simply "distributed secondary (or second-level) beamformers"), which are connected via serial data links (e.g., link 726 from the main beamformer 724 to BF#1). In the exemplary implementation described below, the main beamformer processor 722 includes a main beamformer processor, and each of the distributed secondary beamformer processors 728, 734, 736, and 738 includes a corresponding distributed secondary beamformer processor connected to the main beamformer processor, all of which are configured for downlink (transmit) communications or uplink (receive) communications, or both. Thus, in some additional implementations, in the hierarchical beamformer architecture 722, the main beamformer processor 724 may include a main receive beamformer processor, and each of the distributed secondary beamformer processors 728, 734, 736, and 738 may also include a distributed secondary receive beamformer processor. Thus, each distributed secondary beamformer processor (e.g., 728, 734, 736, and 738) may perform both transmit and receive beamforming operations.

[0130] In some embodiments of the hierarchical beamformer architecture 722, the main beamformer 724 is configured to, for example, calculate a complete transmit beamforming matrix (e.g., Figures 8 to 10 ) and distributes portions of the transmit beamforming matrix to the second-level beamformers (e.g., BF#1 to 4). In addition, the main beamformer 724 also transmits a user data layer in the form of frequency-domain subcarrier IQ data (frequency-domain subcarrier IQ user data layer) to each of the second-level beamformers 728, 734, 736, and 738. In general, a user data layer refers herein to a set of IQ subcarrier-specific data points (values) representing actual modulation symbols. In some embodiments, the pre-decoding / beamforming combination weight calculation unit 710 located in the DU 702 may be configured to determine beamforming weights and assign these beamforming weights to the RU 702. Each second level beamformer receives a corresponding transmit beamforming sub-matrix and multiple frequency-domain subcarrier IQ user data layers (or, in some places, simply referred to as "user data layers") from the main beamformer 724, and then forms a corresponding plurality of signal port-specific aggregated IQ data packets for the transceiver ICs (or, for example, in some embodiments, a set of transceiver IC subarrays) that they serve by using the corresponding transmit beamforming sub-matrix and multiple frequency-domain subcarrier IQ user data layers.

[0131] In some embodiments, each transmit beamforming submatrix contains transmit beamforming combination weights associated with antenna elements in a corresponding region of the antenna array (panel). In addition, the distributed secondary transmit beamformer processors (e.g., secondary (second level) beamformers 728, 734, 736, and 738 as in the present embodiment) are physically distributed so that each distributed secondary transmit beamformer processor is located within or near a corresponding region of the antenna array associated with a corresponding transmit beamforming submatrix in a plurality of transmit beamforming submatrices. Here, the main beamformer 724 may be configured to transmit a plurality of frequency domain subcarrier IQ user data layers to each of a plurality of distributed secondary transmit beamformer processors so that each distributed secondary transmit beamformer processor receives the same frequency domain subcarrier IQ user data layer. Note that in the frequency domain, the beamforming (combination) weights (or simply "beamforming weights") will be complex values ​​with real and imaginary parts for controlling the I component and the Q component, respectively.

[0132] As will be described in further detail, each distributed secondary (second level) transmit beamformer processor (e.g., BF #1 to 4 (728, 734, 736, and 738)) may then apply different corresponding transmit beamforming combining weights (contained in the received corresponding beamforming sub-matrix) to those frequency-domain subcarrier IQ user data layers to form corresponding multiple beamformed frequency-domain IQ data packets. In addition, the secondary transmit beamformer processor may then distribute the corresponding multiple beamformed frequency-domain IQ data packets to corresponding transceiver ICs or sets of transceiver IC subarrays located within corresponding regions of the antenna array associated with the distributed secondary transmit beamformer processor. In this regard, the corresponding transceiver ICs or sets of transceiver IC subarrays may be coupled to the secondary transmit beamformer processors via, for example, a serial data connection as described in various embodiments herein.

[0133] More specifically, some embodiments disclosed herein include an apparatus comprising: (i) a main transmit beamformer processor configured to separate a transmit beamforming matrix of beamforming combination weights into a plurality of transmit beamforming sub-matrices, each transmit beamforming sub-matrix containing transmit beamforming combination weights associated with antenna elements in a corresponding region of an antenna array; and (ii) a plurality of distributed auxiliary transmit beamformer processors connected to the main transmit beamformer processor. In some embodiments, the plurality of distributed auxiliary transmit beamformer processors are physically distributed so that each distributed auxiliary transmit beamformer processor is located within or near a corresponding region of the antenna array associated with a corresponding transmit beamforming sub-matrix of the plurality of transmit beamforming sub-matrices, which may be desirable to allow for a shorter serial data link. In the apparatus, each distributed secondary transmit beamformer processor is configured to: (i) receive a corresponding transmit beamforming sub-matrix and a plurality of frequency-domain subcarrier IQ user data layers from the primary transmit beamformer processor; and (ii) form a corresponding plurality of beamformed frequency-domain IQ data packets using the corresponding transmit beamforming sub-matrix and the plurality of frequency-domain subcarrier IQ user data layers. In addition, the apparatus includes a plurality of sets of transceiver ICs or transceiver integrated circuit (IC) subarrays connected to the plurality of distributed secondary transmit beamformer processors. In this regard, each set of transceiver ICs or each set of transceiver IC subarrays is connected to a corresponding distributed secondary transmit beamformer processor among the plurality of distributed secondary transmit beamformer processors and is located within a corresponding region of the antenna array associated with the corresponding distributed secondary transmit beamformer processor. In addition, each set of transceiver IC subarrays is configured to receive a corresponding plurality of beamformed frequency-domain IQ data packets from the corresponding distributed secondary transmit beamformer processor, wherein each transceiver IC subarray in the set of transceiver IC subarrays is configured to receive a given portion of the corresponding plurality of beamformed frequency-domain IQ data packets.

[0134] In addition, some embodiments include a method comprising: at a main transmit beamformer processor, separating a transmit beamforming matrix of beamforming combination weights into a plurality of transmit beamforming sub-matrices, each transmit beamforming sub-matrix containing transmit beamforming combination weights associated with antenna elements in a corresponding region of an antenna array; receiving the plurality of transmit beamforming sub-matrices or beamformer weight index values ​​and a plurality of frequency-domain subcarrier IQ user data layers from the main transmit beamformer processor at a plurality of distributed auxiliary transmit beamformer processors, the plurality of distributed auxiliary transmit beamformer processors being physically distributed such that each distributed auxiliary transmit beamformer processor is located within or near a corresponding region of the antenna array associated with a corresponding transmit beamforming sub-matrix in the plurality of transmit beamforming sub-matrices, and each distributed auxiliary transmit beamformer processor receives a corresponding a transmission beamforming sub-matrix and the plurality of frequency-domain subcarrier IQ user data layers; each distributed secondary transmit beamformer processor using the corresponding transmission beamforming sub-matrix and the plurality of frequency-domain subcarrier IQ user data layers to form a corresponding plurality of beamformed frequency-domain IQ data packets; and each distributed secondary transmit beamformer processor providing the corresponding plurality of beamformed frequency-domain IQ data packets to a corresponding set of transceiver integrated circuit (IC) subarrays in a plurality of sets of transceiver integrated circuit (IC) subarrays, (i) the corresponding set of transceiver IC subarrays being located within a corresponding region of the antenna array associated with the distributed secondary transmit beamformer processor, and (ii) each transceiver IC subarray in the corresponding set of transceiver IC subarrays receiving a given portion of the corresponding plurality of beamformed frequency-domain IQ data packets from the distributed secondary transmit beamformer processor.

[0135] Return to reference Figure 7 ,exist Figure 7 In the illustrated embodiment, RU 704 is depicted as having beamformer connections to transceiver IC elements 730, which may be individual transceiver ICs having two, four, or more signal ports for driving antenna elements 732, or may be transceiver IC sub-arrays of serially connected transceiver ICs in accordance with various embodiments described herein. More specifically, as described above, at least two serially connected transceiver ICs may be physically arranged in a transceiver IC sub-array (see, e.g., Figure 2 and its description). Thus, in some embodiments, each transceiver IC element is a set of IC subarrays that include two or more transceiver IC subarrays. In addition, in some embodiments, each of the auxiliary beamformers 728, 734, 736, and 738 may be composed of Figure 4The Serdes mux devices (eg, 404) may each be configured to additionally function as a hierarchical beamformer device (eg, Figure 7 A portion of the beamformer processor of the hierarchical beamformer architecture 722 depicted in FIG.

[0136] In an exemplary embodiment, a main transmit beamformer processor (e.g., main beamformer 724) assigns transmit (downlink) beamforming combining weights (combined with, for example, pre-decoder combining weights, as appropriate) to form a full beamforming matrix (e.g., with respect to Figure 8 ), separates the full beamforming sub-matrix and then distributes portions of the full beamforming matrix to respective secondary transmit beamformer processors (e.g., secondary beamformers 728, 734, 736, and 738). Each portion of the full beamforming matrix constitutes a respective transmit beamforming sub-matrix that is distributed to each corresponding secondary (transmit) beamformer processor. The actual weights may be communicated to the secondary beamformers, or a set of beam indices may be used to identify beamforming weights previously stored in the secondary beamformers. More specifically, in some embodiments, multiple transceiver IC subarrays associated with antenna elements on an antenna panel may be partitioned into multiple sets of transceiver IC subarrays based on their physical locations on the panel (e.g., antenna panel 102), wherein each set of transceiver IC subarrays in a given partition is served by and interconnected with a corresponding secondary beamformer processor, wherein the secondary beamformer processors (e.g., secondary beamformers 728, 734, 736, and 738) may be distributed across the panel to be adjacent to or within a partition. Each distributed secondary beamformer processor also receives a frequency-domain subcarrier IQ user data layer via a corresponding serial data link 726 and applies corresponding distributed beamforming weights in a given transmit beamforming submatrix to the frequency-domain subcarrier IQ user data layer to calculate fully beamformed IQ data points for allocation to its corresponding set of transceiver ICs or transceiver IC subarrays.

[0137] More specifically, in some embodiments, each distributed secondary beamformer processor may be configured to calculate multiple sets of beamformed frequency-domain IQ data points by applying the transmit beamforming combining weights of the corresponding transmit beamforming sub-matrix to the frequency-domain subcarrier IQ user data layer to form corresponding beamformed frequency-domain IQ data packets, such as the signal port-specific aggregate IQ data packets described in conjunction with the various embodiments herein. In this regard, in some embodiments, each distributed secondary transmit beamformer processor may be configured to group each beamformed set of frequency-domain IQ data points to form a corresponding set of beamformed frequency-domain IQ data packets. In addition, each distributed secondary beamformer processor may be configured to distribute the corresponding beamformed set of frequency-domain IQ data packets to a corresponding set of transceiver ICs or transceiver IC subarrays connected to the distributed secondary transmit beamformer processor. Taking advantage of the distributed architecture of the beamformer processors of the present embodiment, the computational processing load typically performed by a RU acting as a fronthaul gateway can be reduced by distributing the computational functionality between a primary beamformer and a plurality of secondary beamformers, each designated to serve a corresponding set of transceiver ICs / IC subarrays.

[0138] Subsequently, each transceiver IC subarray in the corresponding set of transceiver IC subarrays may be configured to receive a corresponding subset of the corresponding set of beamformed frequency-domain IQ data packets. In this regard, the beamformed frequency-domain IQ data packets in each corresponding set of beamformed frequency-domain IQ data packets may have a corresponding header indicating a destination signal port so as to direct the individual data packets to the transceiver IC subarray designated to receive the data packets. Within each transceiver IC subarray, the individual transceiver ICs may be configured, for example, to provide a serial data connection to a beamformer processor and / or a serial digital data port for communicating with other transceiver ICs, appropriate data and signal processing circuits, etc., as described in various embodiments herein. In some embodiments, the corresponding subset of the corresponding set of beamformed frequency-domain IQ data packets includes a single frequency-domain IQ data packet (such as, for example, as combined with Figure 3 In one embodiment, the single frequency-domain IQ data packet is provided to a corresponding transceiver IC subarray in a corresponding set of transceiver IC subarrays. In general, the above-described operations of configuring beamformed packets for distribution to transceiver IC subarrays may be performed within a given time period to generate, for example, a downlink data packet stream, wherein each data packet in the stream represents, for example, a symbol time within a time slot (such as in an LTE communication system).

[0139] Note that, as described above, the beamformer processor within the radio unit may be configured to transmit and receive IQ data packets in the time domain or the frequency domain. Thus, in some alternative embodiments, each distributed secondary transmit beamformer processor (e.g., each secondary beamformer 728, 734, 736, and 738) may be configured to: (i) formulate a corresponding beamformed set of frequency-domain IQ data packets as described above (i.e., by applying the transmit beamforming combining weights in its corresponding transmit beamforming submatrix to the frequency-domain subcarrier IQ user data layer), and (ii) additionally and alternatively convert those beamformed frequency-domain IQ data packets into a corresponding set of data packets containing (beamformed) time-domain IQ data. This set of beamformed time-domain IQ data packets may then be distributed among the transceiver ICs / IC subarrays served by the distributed secondary transmit beamformer processors, as described above (e.g., where a corresponding subset of time-domain IQ data packets (e.g., one data packet) is sent to each transceiver IC subarray in the set of transceiver IC subarrays associated with the distributed secondary transmit beamformer processor). In this regard, each distributed secondary transmit beamformer processor may be configured, for example, with appropriate iFFT processing (e.g., a digital signal processor (DSP) configured with appropriate programming instructions to execute algorithms for IFFT operations) to perform the calculations involved in the conversion of frequency-domain IQ data to time-domain IQ data.

[0140] To perform the various other functions described above, embodiments of each distributed secondary transmit beamformer processor (and in some cases distributed secondary receive beamformer processor) (e.g., each of the secondary beamformers 728, 734, 736, and 738) may include executing software instructions to perform a matrix multiplication operation (see Figure 8The distributed secondary transmit beamformer processor may include a digital signal processor circuit (described in more detail above) or may take the form of data registers interconnected with hardware multiplier circuits to perform matrix operations. The hardware may include a hardware processor, a field programmable gate array (FPGA), dedicated digital logic, or a combination thereof. In addition, in some embodiments, each distributed secondary transmit beamformer processor may include a packet processor (e.g., a dedicated DSP circuit, etc.) that is configured to (i) packetize each set of beamformed frequency-domain IQ data points in a plurality of sets of beamformed frequency-domain IQ data points calculated by a given distributed secondary beamformer processor to form a corresponding set of beamformed frequency-domain IQ data packets, and (ii) distribute the beamformed set of frequency-domain IQ data packets to a corresponding set of transceiver IC subarrays connected to the distributed secondary transmit beamformer processor (as described above). In this regard, the distributed secondary transmit beamformer processor (and in some cases, the distributed secondary receive beamformer processor) may include serial data interface circuitry for communicating with each transceiver IC subarray in the corresponding set of transceiver IC subarrays, respectively. As previously described in more detail, communications between the beamformer processor and the transceiver IC may occur over a serial data connection.

[0141] In some embodiments, the packet processor may also be configured to obtain data layer information including component carrier identification information from the primary transmit beamformer processor. Figure 3 , a data packet carrying subcarrier-specific IQ data for a transceiver IC signal port may include a header (not shown for clarity) identifying various aspects of the type of data contained in the packet, as well as packet identification data (such as one or more of the following: band ID, component carrier ID, signal port ID, and / or transceiver ID).

[0142] Note that in some embodiments, the multiple frequency-domain subcarrier IQ user data layers sent to each distributed secondary beamformer 728, 734, 736, and 738 via the serial data link 726 may be compressed using a so-called "modulation compression" technique, such as defined for use in ORAN. Modulation compression is a lossless compression technique for modulated data transmitted on the user plane (e.g., U-plane 722), and more specifically, applied to DL (downlink) user plane modulated data symbols before they are transmitted on the fronthaul interface. Without modulation compression, both I and Q samples are represented by a given number of bits (referred to as "bit width") that is typically fixed (e.g., 10, 12, 14, 16 or more bits for each I and Q value). Modulation compression allows the bit width to be reduced according to the maximum modulation order used on the DL air interface. That is, in this technique, I and Q constellation points / samples may be represented by a number of (data) bits corresponding to the maximum modulation order used. For example, for 256QAM, the number of bits for both I and Q samples of each subcarrier can be reduced to 8 data bits (where I and Q samples are coded with 4 bits respectively), where the number of eight bits corresponds to the modulation order of M=8.

[0143] Thus, in some embodiments, the DU 702 may be configured with appropriate signal processing to perform modulation compression so that the amount of data contained in each of the multiple frequency-domain subcarrier IQ user data layers sent from the main beamformer 724 (on the U-plane 722) for allocation to each secondary beamformer (e.g., BF#1 to 4) may be significantly reduced. Additionally, as noted above (and described in more detail below), each distributed secondary beamformer may then be configured to apply a corresponding portion of the transmit beamforming matrix (or transmit beamforming sub-matrix) associated with that particular beamformer to the user data layer by performing a complex matrix multiplication.

[0144] Once the complex multiplication is performed (combined with Figures 8 to 10 As beamforming weights are applied (described in more detail above), the amount of data to be transmitted to the transceiver IC or set of transceiver IC subarrays served by a given secondary beamformer will increase as a result of, for example, multiplication and summation operations typically associated with performing matrix multiplications. In one example, the beamformed frequency domain IQ data points may be represented by 24 bits or 32 bits.

[0145] In addition, some alternative embodiments disclosed herein involve storing a predetermined set of beamforming weights at each distributed secondary transmission beamformer processor (e.g., BF#1 to 4 (728, 734, 736, and 738)) in advance, such as, for example, as part of a system setup / initialization phase. Such weights may then be stored at the distributed secondary transmission beamformer processor for relatively long-term use. In some embodiments, the predetermined set of beamforming weights may be transmitted to the distributed secondary transmission beamformer processor via, for example, an M-plane (e.g., M-plane 720) message used in the ORAN to manage radio unit functions. In some other embodiments, the beamforming weights may be communicated from the DU 702 to the RU 704 via a C-plane (e.g., C-plane 718) that typically carries data for controlling user data scheduling and data for controlling beamforming weight selection. Thus, a corresponding predetermined set of beamforming weights for a given distributed secondary transmission beamformer processor may be transmitted to a given distributed secondary transmission beamformer processor before receiving a user data layer for a UE served by the given distributed secondary transmission beamformer processor. In addition, a predetermined set of beamforming weights for the corresponding distributed secondary transmit beamformer processor may be communicated from DU 702 to each distributed secondary transmit beamformer processor via the main transmit beamformer processor, or may be sent directly from DU 702 to each distributed secondary transmit beamformer processor using any suitable connection mechanism (e.g., DU 702 may have a direct communication link to each distributed secondary transmit beamformer processor).

[0146] In some embodiments, a predetermined set of beamforming weights may be stored at a given distributed secondary transmission beamformer processor, for example in the form of a lookup table. Each distributed secondary transmission beamformer processor may load its predetermined set of beamforming weights into such a table for future use. In some embodiments, a beamforming index may be used to index the beamforming weights stored in the lookup table, which beamforming index may then be associated with an incoming frequency-domain subcarrier IQ user data layer to indicate which beamforming weights the distributed secondary transmission beamformer processor should apply to each frequency-domain subcarrier IQ user data layer. For example, a given beamforming index or a given set of beamforming indices may be included in a message sent from the DU 702 and the RU 704 over the fronthaul interface to indicate which beamforming weights each distributed secondary transmission processor should apply to the incoming frequency-domain subcarrier IQ user data layer. In this regard, in some embodiments, each beamforming index may include a beam index corresponding to a given beam identified by a beam ID / beam index (e.g., BeamId / BeamIdx as defined for 5G / ORAN networks, for example).

[0147] Note that the multiple frequency-domain subcarrier IQ user data layers received by each secondary transmission beamformer processor may each include multiple physical resource blocks (PRBs, or simply RBs) for one or more users. Recall also that, as described above, the multiple frequency-domain subcarrier IQ user data layers received by each distributed secondary transmission beamformer processor are identical. Each PRB contains frequency-domain IQ data for twelve (12) subcarriers for a given time period, such as 7 symbol times (or 84 resource elements (REs), each resource element representing an OFDM symbol). In some embodiments, each frequency-domain subcarrier IQ user data layer may be provided to each distributed secondary transmission beamformer processor in its entirety (i.e., as a full frequency-domain subcarrier IQ user data layer) for forming beamforming data. In other embodiments, each frequency-domain subcarrier IQ user data layer may be provided to each distributed secondary transmission beamformer processor in a more granular manner, such as one PRB at a time. In this regard, a single beamforming index will be used within a single PRB. However, each PRB may be assigned a different beamforming index depending on whether the PRB is for the same user equipment (eg, UE) or for another user equipment (eg, UE).

[0148] In this regard, the beamforming index (e.g., beam index (BeamID)) sent to each distributed secondary transmission beamformer processor in association with the frequency-domain subcarrier IQ user layer may be specified in different ways. In some embodiments, a full set of beamforming indices may be specified on a layer-by-layer basis for use across all PRBs (e.g., the beamforming indices may be sent in a "map" type to map these indices across all PRBs in each layer). In other embodiments, the frequency-domain subcarrier IQ user data layer may be transmitted to each distributed secondary transmission beamformer processor in a more granular manner (such as one PRB at a time). In this case, a data packet or data frame carrying a single PRB may specify a beamforming index only for that particular PRB. Thus, for example, once the predetermined beamforming weights are stored at each distributed auxiliary transmission processor for relatively long-term use, when a given frequency-domain IQ data packet (carrying IQ data for a single PRB or full user data layer) is received at the distributed auxiliary transmission processor, the given frequency-domain IQ data packet will include a beamforming index (for that one PRB frequency-domain IQ data packet (e.g., in a packet header)) or a full set of beamforming indices (for a full data layer frequency-domain IQ data packet). The distributed auxiliary transmission beamformer processor will then use those one or more beamforming indices to look up the corresponding beamforming weights, and use those weights to perform complex multiplications (as noted above) to form beamformed IQ data.

[0149] As noted above, a given beamforming index or a given set of beamforming indices may be included in a message sent from DU 702 to RU 704 over the fronthaul interface to indicate which beamforming weights each distributed secondary transmit beamformer processor should apply to the incoming frequency-domain subcarrier IQ user data layer. For example, in ORAN, a C-plane message (such as in, for example, a digital frame format) may have multiple sections, each section including fields for "sectionId", "beamId", "startPrbc", and "numPrbc" (and thus, each section may specify a given PRB and the BeamID associated with that PRB). Similarly, a U-plane data frame may also have multiple sections with multiple fields identifying the PRB carrying IQ data and the corresponding "sectionId". In some embodiments, when a distributed secondary transmit beamformer processor in RU 704 obtains a U-plane data frame, it may be configured to use the "sectionId" field within the U-plane data frame to find the corresponding section information of the C-plane data frame. The distributed secondary transmit beamformer processor may also be configured to read the BeamID (beamforming index) from the "beamld" field, retrieve the beamforming weights indexed by the value of "beamld", and apply these weights to the U-plane PRB data.

[0150] In additional embodiments, as noted above, the main (primary) beamformer processor 724 may also include a main receive beamformer processor, and each of the distributed secondary beamformer processors (distributed secondary beamformers) 728, 734, 736, and 738 may also include a distributed secondary receive beamformer processor.

[0151] In this regard, for uplink signal reception, in some embodiments, the second level beamformers 728, 734, 736, and 738 may each have a corresponding receive beamforming sub-matrix containing receive beamforming combination weights associated with antenna elements in a corresponding region of the antenna array (panel) for each receive user data layer. In addition, the distributed secondary receive beamformer processors (e.g., secondary beamformers 728, 734, 736, and 738 as in the present embodiment) are physically distributed so that each distributed secondary receive beamformer processor is located within or near a corresponding region of the antenna array associated with a corresponding receive beamforming sub-matrix. As will be described in further detail, each distributed secondary (second level) receive beamformer processor may receive packet data carrying a corresponding set of frequency domain IQ data points from the corresponding set of transceiver IC subarrays it serves. Each distributed secondary receive beamformer processor may apply different corresponding receive beamforming combining weights (contained in its corresponding beamforming sub-matrix) to the set of frequency-domain IQ data points to calculate a corresponding set of receive partial beamformed frequency-domain IQ data points, and may then transmit the corresponding set of receive partial beamformed frequency-domain IQ data points to the main receive beamformer processor.

[0152] In another embodiment, the primary receive beamformer processor may then combine (e.g., add (sum)) the corresponding receive partial beamformed frequency-domain IQ data point sets received from all multiple distributed secondary receive beamformer processors to form multiple frequency-domain subcarrier IQ user data layers (e.g., up to eight (8) such layers on the uplink (receive) side). In some embodiments, the corresponding set of receive partial beamformed frequency-domain IQ data points formed at each secondary receive beamformer processor represents the corresponding multiple partial beamformed frequency-domain subcarrier IQ user data layers. More specifically, each set of receive partial beamforming frequency-domain IQ data points represents a corresponding partial frequency-domain subcarrier IQ user data layer (e.g., a first set of receive partial beamforming frequency-domain IQ data points represents a first partial frequency-domain subcarrier IQ user data layer, a second set of receive partial beamforming frequency-domain IQ data points represents a second different partial frequency-domain subcarrier IQ user data layer, and so on (e.g., up to 8 partial frequency-domain subcarrier IQ user data layers). In this way, each secondary receive beamformer processor may calculate a partially beamformed frequency-domain subcarrier IQ user data layer for each frequency-domain subcarrier IQ user data layer. Then, the main receive beamformer processor may add the partially beamformed frequency-domain IQ data points for each user data layer to obtain a corresponding fully beamformed data layer.

[0153] Thus, some embodiments disclosed herein include an apparatus comprising: (i) a main receive beamformer processor; (ii) a plurality of distributed secondary receive beamformer processors connected to the main receive beamformer processor, and (iii) a plurality of transceiver integrated circuits (ICs) or transceiver IC subarray sets connected to the plurality of distributed secondary receive beamformer processors. In the apparatus, the plurality of distributed secondary receive beamformer processors are physically distributed such that each distributed secondary receive beamformer processor is located within or near a corresponding region of an antenna array associated with a corresponding receive beamforming submatrix in a plurality of receive beamforming submatrices, and each receive beamforming submatrix contains receive beamforming combination weights associated with antenna elements in a corresponding region of the antenna array. In this regard, each set of transceiver ICs / IC subarrays is connected to a corresponding distributed secondary receive beamformer processor in a plurality of distributed secondary receive beamformer processors and is located within a corresponding region of the antenna array associated with the corresponding distributed secondary receive beamformer processor. Furthermore, in the apparatus, each distributed secondary receive beamformer processor is configured to (i) receive a corresponding set of frequency-domain IQ data points from a corresponding set of transceiver ICs / IC subarrays, and (ii) form corresponding multiple sets of receive partial beamformed frequency-domain IQ data points using the corresponding set of frequency-domain IQ data points and the corresponding receive beamforming sub-matrix, and transmit the corresponding multiple sets of receive partial beamformed frequency-domain IQ data points to the main receive beamformer processor.

[0154] A method, the method comprising: (i) receiving, at each of a plurality of distributed secondary receive beamformer processors connected to a primary receive beamformer processor, a respective set of frequency domain IQ data points from a corresponding set of transceiver integrated circuit (IC) subarrays in a plurality of sets of transceiver integrated circuit (IC) subarrays, wherein the plurality of distributed secondary receive beamformer processors are physically distributed such that each distributed secondary receive beamformer processor is located within or adjacent to a respective region of an antenna array associated with a respective receive beamforming submatrix in a plurality of receive beamforming submatrices, each receive beamforming submatrix being located within or adjacent to a respective region of an antenna array associated with a respective receive beamforming submatrix in a plurality of receive beamforming submatrices; The matrix comprises receive beamforming combination weights associated with antenna elements in a corresponding region of the antenna array, and wherein a corresponding set of transceiver IC subarrays are located within a corresponding region of the antenna array associated with a distributed secondary receive beamformer processor; (ii) computing, by each distributed secondary receive beamformer processor, corresponding multiple sets of frequency domain IQ data points for receive partial beamforming using the corresponding set of frequency domain IQ data points and the corresponding receive beamforming submatrix; and (iii) transmitting, by each distributed secondary receive beamformer processor, the corresponding multiple sets of frequency domain IQ data points for receive partial beamforming to the main receive beamformer processor.

[0155] In subarray beamforming as previously described herein, during reception (thus on the uplink side), each transceiver IC in a given subarray may generate, for example, frequency domain IQ data packets that are aggregated at each transceiver IC as they traverse the set of cascaded transceiver ICs in the subarray on their way toward the beamforming processor. As described above (see, e.g., Figure 3 ), the IQ packet data from each transceiver IC in the subarray can be, for example, concatenated or combined IQ data for multiple signal ports (e.g., horizontal (H) and vertical (V) ports). The received signal processed collectively by the transceiver IC subarray is an aggregate signal having components from multiple data layers, multiple individual beams, and possibly multiple users.

[0156] On the uplink side, the hierarchical beamformer 722 may receive, for example, up to 8 user data layers in one symbol time (e.g., 66.7 μs). In this regard, in some embodiments, each secondary receive beamformer processor (e.g., each of the secondary beamformers 728, 734, 736, and 738) will receive packets carrying IQ data points from a corresponding set of transceiver IC subarrays connected to the secondary receive beamformer processor. In some embodiments, the data packets may be in the time domain or the frequency domain. Here, each distributed secondary receive beamformer processor may, for example, be configured with appropriate FFT processing (e.g., a digital signal processor (DSP) configured with appropriate programming instructions to execute algorithms for FFT operations) to perform the calculations involved in the conversion of time domain IQ data to frequency domain IQ data. In addition, each distributed secondary receive beamformer processor may be configured with appropriate logic to process the received packets to retrieve the IQ data.

[0157] In an exemplary embodiment, each secondary receive beamformer processor receives IQ data packets from each transceiver IC / IC subarray it serves that have not been combined in any way before recovering the fully beamformed user data layer from the IQ data packets received from the transceiver IC / IC subarrays across the entire antenna array. Due to the distributed nature of the hierarchical beamformer 722, no one secondary receive beamformer processor has access to all receive signals (e.g., 64 uplink signals) received by multiple sets of transceiver IC / IC subarrays associated with antenna elements across the entire antenna subarray. For example, in conjunction with Figure 2 , each distributed auxiliary receive beamformer (e.g., each of BF#1 to 4) will have access to only 16 (sixteen) receive signals (8 receive signals from a set of 8 corresponding transceiver IC subarrays, one each for H-polarization and V-polarization signal ports).

[0158] In some embodiments, as noted above, each distributed secondary receive beamformer processor is configured to receive a corresponding set of frequency domain IQ data points (carried in, for example, IQ data packets) and a corresponding receive beamforming sub-matrix from a corresponding set of transceiver IC sub-arrays located within a given area of ​​the antenna array associated with the distributed secondary receive beamformer processor, and to form multiple sets of frequency domain IQ data points for receive partial beamforming of the distributed secondary receive beamformer processor using the corresponding set of frequency domain IQ data points and the corresponding transmit beamforming sub-matrix. More specifically, in some embodiments, each distributed secondary transmit beamformer processor is further configured to calculate a corresponding set of partial beamforming frequency domain IQ data points by applying receive beamforming combining weights of the corresponding receive beamforming sub-matrix to the corresponding set of frequency domain IQ data points (such as by performing matrix multiplication). In some embodiments, each set of partial beamformed frequency domain IQ data points represents a given partial beamformed frequency domain subcarrier IQ user data layer for each frequency domain subcarrier IQ user data layer. By applying the receive beamforming combining weights of the receive beamforming matrix to its set of frequency-domain IQ data points via matrix multiplication, each secondary receive beamforming processor may form a given number of subsets (partial sums) of the frequency-domain IQ data points representing a corresponding number of partially beamformed frequency-domain subcarrier IQ data layers.

[0159] Thereafter, in some embodiments, each distributed secondary receive beamformer processor may transmit a corresponding set of receive partial beamformed frequency-domain IQ data points calculated by the secondary receive beamformer processor to the primary receive beamformer processor. In some embodiments, the primary receive beamformer processor (e.g., 722) is then configured to combine corresponding sets of receive partial beamformed frequency-domain IQ data points received from all distributed secondary receive beamformer processors (e.g., 728, 734, 736, and 738) to form frequency-domain subcarrier IQ user data layers (e.g., up to eight layers). In this regard, in some embodiments, the primary receive beamformer processor may combine (e.g., add) corresponding sets of receive partial beamformed frequency-domain IQ data points received from all secondary receive beamformer processors for each user data layer to obtain each fully beamformed frequency-domain subcarrier IQ user data layer.

[0160] More specifically, the primary receive beamformer processor may add together the partially beamformed frequency domain IQ data point sets for user data layer 1 received from each secondary receive beamformer processor to obtain fully beamformed user data layer 1, add together the partially beamformed frequency domain IQ data point sets for user data layer 2 received from each secondary receive beamformer processor to obtain fully beamformed user data layer 2, and so on. The primary receive beamformer processor may perform this process up to a specified number of uplink user data layers to recover all fully beamformed uplink user data layers. In some embodiments, the primary receive beamformer processor may combine up to 8 data layers in each symbol time.

[0161] In some embodiments, each distributed secondary receive beamformer processor may transmit its locally formed set of receive partial beamformed frequency domain IQ data points to the primary receive beamformer processor as packetized data. In this regard, in some embodiments, each distributed secondary receive beamformer processor may include a packet processor (e.g., a dedicated DSP circuit, etc.) configured to use the locally formed set of receive partial beamformed frequency domain IQ data points to form corresponding receive partial beamformed frequency domain IQ data packets for transmission to the primary receive beamformer processor. Furthermore, in some embodiments, the packets have a header indicating at least component carrier information.

[0162] Note that, as noted above, each distributed secondary receive beamformer processor is configured to form a set of frequency domain IQ data points for receive partial beamforming using a receive beamforming sub-matrix. In this regard, in some embodiments, the primary receive beamformer processor may be configured to separate a receive beamforming matrix of beamforming combination weights into a plurality of receive beamforming sub-matrices in a manner similar to that described above with respect to downlink (transmit) beamforming operations, and transmit each respective receive beamforming sub-matrix to a corresponding distributed secondary receive beamformer processor in the distributed secondary receive beamformer processors. In other embodiments, a predetermined set of receive beamforming combination weights may alternatively be stored at a given distributed secondary transmit beamformer processor in the form of, for example, a lookup table in a manner similar to that described above with respect to downlink (transmit) beamforming operations.

[0163] Thus, in summary, in accordance with the embodiments described herein, each distributed secondary receive beamformer processor is able to access a given portion of a receive signal (e.g., a portion of an uplink signal generated by a subset of transceivers (e.g., 2 of 4, 4 of 8, 4 of 16, or 16 of 64, etc.)) and is therefore able to form partially beamformed frequency-domain IQ data layers for each of a plurality of specified uplink layers (e.g., 8 layers). Each distributed secondary receive beamformer processor (of which there may be 2, 3, 4, 8, or more, depending on the size of the system) may then send a specified number of partially beamformed frequency-domain subcarrier IQ data layers to the primary receive beamformer processor (e.g., via link 726). The primary receive beamformer processor may then combine the respective partially beamformed frequency-domain subcarrier IQ data layers from all of the distributed secondary receive beamformer processors to form a specified number of fully beamformed user data layers. Thus, the main receive beamformer processor may form a specified number of separate IQ sample data combinations, where each combination corresponds to a frequency domain subcarrier IQ user data layer.

[0164] Figure 8 8 is a graphical representation of a downlink transmit beamforming operation. User data is represented by data layers along dimension 818, with subcarrier-specific IQ data for each such layer depicted along dimension 816. In some embodiments, the user data layers along dimension 818 are frequency-domain IQ data layers (e.g., such as data layers distributed over corresponding links 726 to separate secondary beamformers, as in conjunction with Figure 7 816). Each data layer (such as layers 820, 822) may actually be aggregate user data for one or more users, with different users being assigned / allocated different subcarrier subsets represented along dimension 816. In addition, a given user may be assigned one or more data layers (along dimension 818), such as in the case of spatial multiplexing. In this regard, as noted above, each (user) data layer may include subcarrier-specific IQ data allocated between PRBs (with each RB (as previously defined)) for one or more users.

[0165] In some embodiments, a beamformer (e.g., 202, 300, 400, 724 (primary beamformer), etc.) computes beamforming weights for a set of carriers along dimension 802, specific to a user data layer represented by IQ data along dimension 800, and for a signal port along dimension 804. Note that in embodiments involving pre-storing beamforming weights at each secondary beamformer, the beamforming weight calculation at the primary beamformer is omitted. Figure 8As shown in , the beamforming weights depicted on the top layer of the matrix (i.e., the horizontal slice of the matrix along dimension 802 by 800) are applied to the data layer (816×818) according to the matrix multiplication to generate the top layer (at the top of dimension 826) of beamformed IQ data, where the subcarriers are along dimension 824. Note that for simplicity, the rows or layers along the beamforming dimension 804 alternate between H and V polarizations, such that, for example, elements 806, 808 each include separate signal port weights, such as "H" weights and "V" weights, which are then independently used to combine data layers, such as layers 820, 822, respectively. The H / V weight pairs depicted as interleaved in the matrix columns in the vertical direction (dimension 804) may be related in some operating modes, or may be completely independently selected beams for the H and V components (i.e., signal ports). The columns of the beamforming matrix, such as columns 807 or 809, may be applied to a given set of subcarriers in a corresponding given data layer according to the desired beamforming operation. Note that the beamforming matrix may also be incorporated into the precoding matrix calculation to form a linear combination of the data layer according to the desired precoding matrix. In this manner, the beamformer matrix is ​​used to operate on the user data layer to generate signal port specific IQ data.

[0166] exist Figure 8 In the illustrated embodiment, each set of beamformed IQ data points is packetized and transmitted to a corresponding transceiver IC / IC subarray, as described with respect to Figure 3 In some embodiments, the packetized IQ data may be maintained in the frequency domain. However, in other embodiments, the packetized IQ data may be converted to time domain IQ data instead. In some embodiments, the IQ data for the 64 signal ports along dimension 826 includes IQ data for 32 H signal ports and 32 V signal ports. Each of the four signal port specific IQ data segments 828, 830, 832, and 834 of 826 contains 16 beamformed IQ data packets, which may be combined via concatenation into a format similar to Figure 3 Each of the eight H / V IQ packets contains time domain or frequency domain IQ data and is transmitted through Single serial data link sent to the corresponding transceiver IC sub-array, such as along Figure 28a. The IQ data of sections 830, 832, and 834 are each similarly packetized into eight unique IQ data packet streams and sent to eight corresponding transceiver subarrays within transceiver subarray rows 238b, 238c, and 238d, respectively. In this embodiment, each dual signal port IQ data packet may be processed jointly by two serially connected transceiver ICs. Alternatively, each of the eight H / V packets obtained from section 828 may be sent to Figure 4 The corresponding transceiver IC subarrays in the first row of transceiver IC subarray 421a of FIG. 4, wherein the dual signal port IQ groups are similarly allocated to the rows of transceiver IC subarrays 421b, 421c, 421d. Figure 4 In an embodiment of the present invention, each beamformed IQ data packet is processed jointly by three serially connected transceiver ICs.

[0167] By way of example, in operation, a 64-TRX (transmit / receive) massive MIMO RU (e.g., RU 704) may support 16 downlink beamforming layers and 8 uplink beamforming layers. (Note that in Figure 8 , for simplicity, only eight layers across 818 are depicted). A downlink (DL) beamformer (e.g., one of the secondary beamformers BF#1 to 4) may be configured to receive a [16x1] complex vector for the user data layer as input for each subcarrier, and then multiply the complex vector by a transmit beamforming submatrix [64x16] containing complex beamforming weights to output a [64x1] complex vector for each subcarrier within each physical transmission (TX) antenna stream in a physical transmission (TX) antenna stream. In this regard, a stream refers to a sequence of frequency-domain IQ data packets for a given signal path (as noted above, further conversion to the time domain is possible). The matrix calculation for one subcarrier is shown below, and in practice, the matrix calculation will be extended to the entire set of subcarriers. For example, for one subcarrier:

[0168]

[0169]

[0170] The [64×1] output vector is divided into physical antenna stream groups, where one group is used for the set of transmission antenna streams specified for each transceiver IC subarray. In an embodiment in which each transceiver IC can generate two unique transmission signal paths (or only signals) and in which each subarray has two transceiver IC devices, each group will include packets associated with four separate physical antenna streams. In other embodiments in which each transceiver IC device can generate four unique transmission signals and each subarray has two transceiver devices, each group will include packets associated with eight separate physical antenna streams. In yet another embodiment in which each transceiver IC device can generate four unique transmission signals and each subarray has only one transceiver IC device, each group will include packets associated with four separate physical antenna streams. In some embodiments, for each PRB (Physical Resource Block), a packet is generated. piece - A set of 12 subcarriers for one slot of seven symbols, for a total of eighty-four resource elements (REs)) specifying the complex beamforming weights of the beamforming matrix.

[0171] For illustration, in one example implementation, each distributed secondary beamformer within the hierarchical beamformer architecture (described above) may be configured to: (i) take as input a [16×1] complex vector of the (frequency domain subcarrier IQ) user data layer, (ii) multiply the complex vector by a [4×16], beamforming transmit submatrix of complex beamforming weights, and (iii) output a [4×1] complex vector for each subcarrier of the four physical transmit antenna (signal) streams. An example calculation is shown below:

[0172]

[0173] With respect to the multi-level beamformed IQ data packets 850 (which represent beamformed IQ data for one embodiment of a transceiver IC subarray), the beamformer processor may be configured to generate a commonly processed IQ data packet 864 (in a time domain or frequency domain format) for one signal port (representing, for example, subcarrier IQ data for all subcarriers or a subset of subcarriers of one component carrier of a signal port) and a second commonly processed IQ data packet 866 for a second signal port (wherein the second commonly processed IQ data packet 866 is in a time domain or frequency domain format, depending on, for example, the format of the commonly processed IQ data packet 864 for the first port) for use by the transceiver ICs to process signals according to the first level of beamforming, which transceiver ICs are also simultaneously generating a second level of higher resolution beamforming. The second level of beamforming is based on the beamforming for the individual transceiver ICs and their respective horizontal signal ports (H1, H2, H3, etc.) Figure 8) and for use by individual transceiver ICs and their corresponding vertical signal ports (V1, V2, V3, as indicated in FIG. Figure 8 858, 860, 862 of the fully digital beamforming (indicated in FIG. 1 ) as previously described with respect to Figure 3 Furthermore, as previously described, the second level beamformed IQ data packet may include subcarriers associated with the same component carrier as the co-processed IQ data packet, or subcarriers associated with a second component carrier.

[0174] More specifically, the first beamformed IQ data packet may include IQ data 864 (labeled Hc, where "c" indicates IQ data for common processing), 866 (Vc) for common processing by all transceiver ICs in a given transceiver IC subarray (e.g., three separate transceiver ICs, each capable of 2T2R operation). Three additional packets of transceiver IC-specific IQ data, respectively including data 852 concatenated with data 858; data 854 concatenated with data 860; and data 856 concatenated with data 862, are also transmitted to the transceiver IC subarray, wherein a first transceiver IC combines the common processed data 864 with data 852 and the common processed data 866 with data 858. Another transceiver IC combines the common processed data 864 with data 854 and the common processed data 866 with data 860, and a third transceiver IC combines the common processed data 864 with data 856 and the common processed data 866 with data 862.

[0175] Fig. 9 904 of dimension L (i.e., the number of layers) to beamformed downlink transmission IQ data packets at a logical baseband port 926 represented by a matrix [Z] 904 of dimension M. In some embodiments, the user data layers 906, 916, 918 remain in frequency domain format until the data associated therewith is beamformed. After the beamforming operation is complete, in some embodiments, the beamformed downlink transmission IQ data may be packetized to form beamformed frequency domain IQ data packets. As noted above, in some other embodiments, the beamformed frequency domain IQ data packets may be further converted to beamformed time domain IQ data packets for transmission to a corresponding transceiver IC or transceiver IC subarray (e.g., such as Fig. 9 The transceiver subarray 914 in FIG. Fig. 9, data layer [X] 900 is precoded by matrix PM 920 according to a precoding operation to obtain logical antenna port signals 922 represented by matrix [Y] 902, followed by a beamforming operation by digital beamforming matrix DB 924 using various beamforming beam indices (e.g., "BeamIdx") with weights such as "Beam 1" 910, which applies the beam weights and distributes the appropriately weighted precoded signals at node 908 (which are precoded linear combinations of data layers 906, 916, 918) over various logical baseband ports 926 (also depicted as IQ information 828, 830, 832, 834) represented by matrix [Z] 904. Each beamformed packet of matrix [Z] (such as IQ data packet 912) is transmitted to its corresponding transceiver IC subarray 914. As described above, data packet 912 may contain frequency domain IQ data or time domain IQ data.

[0176] Fig.10 1000 is an illustration of a conversion of a user data layer to a beamformed IQ data stream according to a generalized combined precoding and beamforming matrix 1012 operation 1000 resulting from matrix multiplication of a precoding matrix PM 920 and a beamforming matrix DB 924. A user IQ data layer [X] 1004 is provided by a processor 1002 which provides user IQ data that has been processed according to standard coding, cyclic redundancy check (CRC), rate matching (RM), and resource element (RE) mapping. The data layer [X] 1004 is processed in the transform 1000 according to the generalized spatial multiplexer / beamformer matrix PM to generate a logical baseband port IQ signal packet 1014 represented by a signal port IQ data matrix [Z] 1006 for transmission to a transceiver IC subarray (such as subarray 1008) over a corresponding serial data link. As used herein, the terms "beamforming" and "beamforming matrix" refer to the described combined beamforming / precoding operation, whether implemented in a single matrix operation or in multiple separate matrix operations. Fig. 9 As depicted, the IQ data packets transmitted from each respective logical baseband port 1014 (and thus after beamforming / precoding operations) to its corresponding transceiver IC subarray 1008 may be frequency domain IQ data packets or time domain IQ data packets (if converted to the time domain).

[0177] Fig.111104. FIG. 1105 is an illustration of receive uplink signal processing including receive beamforming and layer decoding. Each transceiver IC subarray 1108 provides received IQ data to the beamformer processor as a logical baseband port 1116 represented by the matrix [Z] 1106. Virtual antenna port signals 1112 may be formed according to the matrix [Y] 1104. Finally, individual data layers 1110 represented by the matrix [X] 1102 may be recovered.

[0178] Fig.12 A block diagram of a transceiver IC device architecture is depicted, and it is also suitable for forming a serially connected transceiver group. The transceiver IC is suitable for operation in FDD mode and TDD mode, and Fig.12 The configuration depicted in is connected for operation in TDD mode. Each transceiver IC 1200 includes multiple signal processing paths for both transmit signal processing and receive signal processing. For DL ​​transmit signal processing, the transceiver IC 1200 includes a serial data receiver RX#0 1202 for receiving frequency domain IQ data packets via a serial data receiver 1202. The serial data receiver 1202 includes: a data buffer for storing a plurality of deserialized data words; and a data analysis circuit for performing packet header analysis to determine whether the received packet is intended to be processed by the current transceiver IC and / or whether it is intended to be processed by one or more other transceiver ICs in the transceiver IC subarray. In the case where the packet is to be processed locally, the packet is forwarded to a DSP memory 1210 that can be accessed by an integrated digital signal processor (DSP) 1215 via 1206 (such as via memory storage or direct memory access (DMA) operation). In an alternative embodiment, the header check may be performed by the DSP 1215, which places data in the DSP memory 1210 that is destined for retransmission via the serdes transmitter TX#1 1262.

[0179] The DSP 1215 includes programming stored in non-volatile memory that, when executed, causes the DSP 1215 to execute an algorithm 1214 for converting frequency-domain digital IQ data into time-domain digital data. The stored algorithm instructions include processor instructions for iFFT operations 1214 and also include instructions for extending the converted data by adding a cyclic prefix (CP).

[0180] In subarray beamforming as described herein, each IC in a given subarray processes the same frequency-domain IQ packets for transmission (referred to herein as "commonly processed" IQ data), and during reception generates frequency-domain IQ packets that are aggregated at each transceiver IC as they traverse the cascaded set of transceiver ICs on their way toward the beamformer processor. Because the signal processed jointly by the transceiver ICs is an aggregated beamformed signal having components from multiple data layers and multiple individual beams, it is not possible to adjust the individual beams within a given subarray of the jointly processed IQ data packets. However, a unique phase rotation may be applied to the aggregated beamformed signal at each element (i.e., each signal port) in the subarray, which will have the effect of tilting the entire composite / aggregated beamformed signal. Thus, when beam tilt is desired, the transceiver is configured to incrementally adjust the phase of each jointly processed IQ data packet according to the position of the radiating element driven by the transceiver IC in the IC subarray. Without incremental adjustment of the phase at each subarray element, true tilt cannot be obtained because only one element will likely be aligned, and for a given downward (upward) tilt, the wavefronts from the remaining elements will be incrementally advanced (or delayed) according to their positions in the subarray. In this way, beam tilt can be obtained by baseband signal processing without directly adjusting any signal components in the analog domain (including not adjusting the VCO phase).

[0181] More specifically, when a linear array of antenna elements is physically "tilted" (a vertical array tilted up / down in altitude, or a horizontal array tilted left / right in azimuth), the result can be viewed as an incremental time delay of signal transmission (or reception) across the antenna elements of the array, thereby changing the direction in which the propagating wavefronts constructively add to form the main lobe (and destructively combine to form the null). Electronic tilting is the process of applying appropriate signal delays without actually physically repositioning the antenna. The relationship between the time delay and the corresponding signal phase change depends on the tilt angle as well as the frequency of the signal. That is, a given time delay between two signals is equivalent to a linear phase shift in the frequency content of the signals, where a given time delay results in a lower phase change at lower frequencies within the signal and a linear higher phase change at higher frequencies. Thus, for narrowband signals, a specific time delay roughly translates into a specific phase shift between the delayed signals. But for wideband signals, such as 50MHz or 100MHz or larger OFDM signals, a given time delay affects the phase of the OFDM subcarriers differently. In a phased array, each subcarrier is still rotated by the same phase, which results in a nonlinear phase characteristic commonly referred to as beam squint. In OFDM signals with bandwidths of approximately 100 MHz, a certain amount of beam squint is acceptable.

[0182] Thus, electronic beam tilt in a physically static array can be achieved by various methods performed by individual transceivers as described herein, including: (i) applying incremental phase rotation to each subcarrier frequency domain IQ data point (e.g., via an NCO), (ii) applying a constant phase rotation to each subcarrier frequency domain IQ data point (e.g., via complex multiplication), (iii) applying a constant phase rotation to each sample of the baseband time domain signal (e.g., via complex multiplication), (iv) applying a time delay in the discrete time domain signal of the transmitted baseband signal, or (v) a combination of the above methods. Note that methods (ii) and (iii) will result in a certain amount of beam squint deformation.

[0183] In this regard, beam tilting may be achieved by applying a linearly increasing phase rotation across the subcarriers by a complex multiplier 1212, which is implemented as Figure 5 The NCO 542 of the embodiment of the present invention is a numerically controlled oscillator (NCO) described herein. The NCO 1212 is configured to provide a complex sequence with a linearly increasing phase for multiplication with a corresponding subcarrier frequency domain IQ data point sequence. For a desired beam tilt, an initial phase and an incremental rate at which the phase increases from subcarrier to subcarrier are determined, and these values ​​are loaded into the NCO phase accumulator 564 and the FCW register 562, respectively. The phase increment value may be determined based on one or more different factors, including (i) the desired beam tilt angle, (ii) the subcarrier spacing, (iii) the carrier frequency, and (iv) the location of a particular radiating element driven by the transceiver IC. In general, to achieve a beam tilt of an angle φ, for a given subcarrier frequency (1 / λ), at a position n within the array, the phase rotation θ is given by:

[0184] θ=nπ(λ c / λ)sin(φ),

[0185] For the carrier wavelength λ c , the distance between the elements is d = λ c / 2. In receive beam tilt operation, the NCO may be implemented in the complex multiplier 1238 after FFT processing.

[0186] Alternatively, the complex multiplication 1212 may be configured to provide a constant phase rotation to each frequency domain IQ data point prior to transformation via the iFFT 1214 to implement an approximate time delay to achieve beam tilt. For a desired beam tilt, a frequency domain phase rotation represented by a single complex number is determined and loaded into the complex multiplier 1212. The frequency domain phase value may be determined based on one or more different factors, including (i) the desired beam tilt angle, (ii) the array position of a particular radiating element driven by the transceiver IC, and (iii) the carrier frequency. In a receive beam tilt operation, a constant phase rotation may be implemented in the complex multiplier 1238 after FFT processing.

[0187] In some embodiments, beam tilt is implemented by applying a constant phase rotation to each sample of the baseband time domain signal (e.g., via complex multiplication). For a desired beam tilt, a time domain phase rotation represented by a single complex number is determined and loaded into a complex multiplier 1306 (which may also simultaneously implement a gain function). The time domain phase value may be determined based on one or more different factors, including (i) the desired beam tilt angle, and (ii) the location of a particular radiating element driven by the transceiver IC. In a receive beam tilt operation, a constant phase rotation may be implemented in a complex multiplier 1386 (which may also simultaneously implement a gain function) prior to FFT processing.

[0188] In some embodiments, beam tilt is achieved by applying a time delay in a discrete time domain signal of the transmit baseband signal. For a desired beam tilt, a time domain delay is determined and the value is loaded into a delay buffer 1312. The time domain delay value may be determined based on one or more different factors, including (i) the desired beam tilt angle, (ii) the time domain sampling rate, and (iii) the location of the specific radiating element driven by the transceiver IC. In a receive beam tilt operation, a time delay may be implemented in a delay buffer 1378.

[0189] In other embodiments, a combination of the above methods may be used. In one particular embodiment, the electronic beam tilt may consist of a coarse adjustment and a fine adjustment, where the coarse beam tilt may be implemented by applying a linearly increasing phase rotation across the subcarriers by a complex multiplier 1212 implemented as an NCO using a finite resolution or a finite number of bits, and the fine resolution may be implemented by further adjustments in the time domain, such as a time delay or a time domain constant phase rotation.

[0190] For various embodiments of beam tilt phase adjustment, the phase rotation may be specified by a control message provided to the transceiver IC. A specific phase value may be provided, or a phase index value may be included in the control message, or in the header of the IQ data packet itself. The phase index value may be used to retrieve a pre-calculated phase value from, for example, a lookup table. In some embodiments, the transceiver IC may combine factors to calculate a specific rotation to be applied (e.g., a desired tilt angle may be provided, and the transceiver IC may adjust the phase rotation based on its predetermined position within an array and / or transceiver IC subarray). Such phase rotation may be used to implement beam tilt phase rotation.

[0191] In some embodiments, beam tilt can be achieved using a combination of linear phase rotation applied in the frequency domain, a constant phase rotation in the time domain followed by an iFFT transformation, or a time delay in the time domain. In some embodiments, frequency domain rotation can achieve coarse tilt or an approximation of the desired beam tilt, while time domain rotation can achieve fine tilt. This can be particularly useful when larger tilt angles are desired.

[0192] In other embodiments, dynamic adjustment of the tilt angle may be achieved on a slot-by-slot basis, greatly enhancing the available scan range and coverage from the panel array using subarray beamforming. In such embodiments, the beam tilt information and which slots, subcarriers, or component carriers to use may be specified via a control message.

[0193] In one embodiment, electronic antenna beam tilt is implemented in a transceiver subarray by distributing beamformed IQ data packets to multiple serially connected transceiver ICs for common processing by the transceivers. The IQ data packets have individual IQ values ​​for corresponding multiple subcarriers. At each transceiver IC, an electronic beam tilt phase rotation is applied. In some embodiments, the application of beam tilt phase rotation is accomplished by changing the phase of each IQ modulated subcarrier based on the desired antenna tilt and array position. The phase change can be a constant phase rotation applied to all subcarriers, or it can be a linearly increasing phase rotation increased from subcarrier to subcarrier. Phase adjustment can be specified according to one or more control messages. The control message can be specific to a given subarray, a transceiver IC within a subarray, or specific to a separate transceiver IC. Phase adjustment can be specified according to time delay, frequency domain multiplication rotation, or time domain complex rotation, or equivalent data. A given transceiver IC can also combine phase adjustment data with array position data unique to the transceiver IC to calculate the final phase adjustment.

[0194] Return to reference Fig.12 , the time domain IQ data is stored in the DSP memory 1216, which can be accessed by the transmission time domain signal processing circuit 1217 (about Fig.13Afurther described). Fig.12 In the implementation scheme, circuit 1217 includes two parallel component carrier processing circuits 1218, 1228 and corresponding time domain signal processing circuits 1220, 1230, which each provide a baseband time domain OFDM signal (each signal is a single component carrier signal or a multi-component carrier signal) to a corresponding digital power amplifier (DPA) circuit 1222, 1232.

[0195] In one embodiment, DPA 1220, 1232 performs simultaneous RF modulation and amplification, which can be the final power amplification of the RF signal. In some embodiments, the DPA provides pre-amplification of the RF signal, which is then applied to an external power amplifier that drives the radiating antenna element. The external power amplifier is adjacently distributed on the active antenna panel assembly in an element-by-element manner. DPA 1220, 1232 is provided with multiple RF carrier phases, which are derived from a system phase-locked loop (SYSPLL) and further processed by a synchronous RF PLL 1262, which drives an RF carrier generator VCO1260. The selected RF carrier phase is used to switch the amplifier unit within the DPA. As described herein, a specific RF carrier phase and the corresponding number of activated cells that determine their relative amplitudes are selected based on the time domain IQ data points provided by circuits 1220, 1230.

[0196] The transceiver IC 1200 also includes a receive time domain signal processing circuit 1241 (regarding Fig. 13B 1250), which is used to downconvert the analog RF signal via an IQ mixer driven by VCO 1260, and which generates separate baseband I and Q analog signals for sampling by analog-to-digital converters (ADCs) within circuits 1244, 1252. The sampled signals are then processed by time domain filtering and downsampling circuits 1242, 1250. The processed time domain signals are then stored in DSP memory 1216 for further processing, including CP removal and filtering via an FFT algorithm ( Fig.12 The DSP 1215 includes programming stored in non-volatile memory that, when executed, causes the DSP 1215 to execute an algorithm for converting the time domain digital data to frequency domain digital IQ data. A linearly increasing phase rotation may then be applied to each frequency domain IQ (i.e., subcarrier) value using an NCO (e.g., 1238), which is also an embodiment of electronic beam tilting. The received IQ frequency domain data is then processed by the MUX / combining circuit 1264 for transmission to the serial data bus via serial transmitter TX#0 1204.

[0197] Fig.13A1300 is a block diagram of the time domain signal processing circuit 1217. Frequency domain IQ data is received from the DSP memory via line 1302 (and similarly, 1304, 1344, 1346) and applied to the signal path power detector and to the gain unit 1306 for adjusting the power level. In some embodiments, the gain multiplier may also include a complex phase that rotates each time domain value by the same phase. This time domain phase rotation can be used to apply an approximate time delay, which can be used to implement an electronic beam tilt. Although this corresponds to a phase rotation of the same phase of each constituent subcarrier, rather than a linearly increasing phase rotation, this is accurate enough for a bandwidth of approximately 100 MHz in the frequency range of the frequency band used for LTE and 5G signals. The signal is filtered by an FIR filter stage 1308, which also includes an interpolation stage in a plurality of interpolation stages to increase the sampling rate of the discrete time domain signal. The discrete time digital UL signal is then processed by a numerically controlled oscillator (NCO) 1310. The NCO (e.g., 1310) may be configured to multiply the time domain signal by a complex sine function to perform a frequency shift of the baseband signal to a desired frequency range (such as a separate frequency range that does not overlap with other component carriers). In some embodiments, one transmission signal may be slightly shifted upward in frequency, while another transmission signal (such as a separate component carrier provided on connection 1304) may be slightly shifted downward using a corresponding NCO, so that two time domain signals representing, for example, two component carriers may be added together without the frequency content of one signal overlapping the frequency content of the other signal. The signal is further processed by a delay buffer 1312, which allows for precise time offset adjustment of the transmission signal. In some embodiments, the delay buffer 1312 is used to provide per-carrier delay adjustment. The delay buffer 1312 compensates for different processing times for different supported subcarrier spacings (SCS) and bandwidths. Assuming that all filtering is performed with an FIR filter for each carrier, the adjustable delay per carrier is the difference between the larger delay and the shortest delay, which is approximately 10 μs. However, sharing the function with a window relaxes this requirement.

[0198] The other discrete time domain signals 1304, 1344, 1346 resulting from the frequency domain conversion to the time domain of the DSP 1215 are similarly processed. These signals may then be combined and / or routed to the transmit signal processing circuits 1316, 1348 via the MUX / ADD circuit 1314 for crest factor reduction (e.g., CFR 1318), further FIR filtering (including further upsampling / interpolation), and IQ multiplication to perform phase adjustment and / or correction (e.g., FIR IQ circuit 1322). The signals may also undergo digital predistortion (DPD, e.g., DPD circuit 1324) to correct for phase and amplitude distortion present in the modulator / amplifier DPA 1328a, 1328b of the first signal port 1342 from the RF signal adder 1340 (and DPA 1328c, 1328d of the signal port 1350). Each section 1328 a - 1328 d of the DPA includes a clock domain crossing circuit 1330 , a cascaded integrator-comb (CIC) filter 1332 , a mapper circuit 1334 , a delay circuit 1336 , and a final DPA stage 1338 .

[0199] Fig. 13B The receive signal processing portion of the transceiver is depicted. The digital samples from the ADC are received by a clock domain crossing circuit 1362 and adjusted for DC offset by a DC offset circuit 1364. An IQ multiplier 1366 can be used to provide automatic gain control of the baseband time domain signal in response to the power measured by a power detector PD 1368. A quadrature error compensation circuit (QEC 1370) provides compensation for frequency-dependent quadrature errors in the RX analog front end. In one embodiment, the QEC block 1370 divides the time domain signal (having a sampling rate of, for example, 245.76 MHz) into 16 frequency bins, each of which is 15.36 MHz. Each frequency bin is added to the mirror frequency bin content shaped by a complex multiplier. A notch filter 1372 can be used to reduce any undesirable out-of-band signals.

[0200] MUX 1374 may be configured to selectively direct receive signal samples from path RX0 (1360) or RX1 (1394) to any or all of RX signal paths 1376, 1392, 1396, or 1398. Some examples of different possibilities are: RX0 to all 4 RX signal paths; RX1 to all 4 RX signal paths; RX0 to RX signal paths 1376 and 1392 and RX1 to RX signal paths 1396 and 1398; and RX0 to RX signal path 1376 and RX1 to RX signal paths 1392, 1396, and 1398. Each RX signal path includes a delay buffer (e.g., 1378), an NCO (e.g., 1380), a FIR filter and downsampler (e.g., 1384, 1382), and a power detector (e.g., PD 1390). Note that the gain multiplier (e.g., 1386) may also implement a constant phase rotation on the time domain signal. In such an embodiment, this is equivalent to a constant phase shift applied to each subcarrier, rather than a linearly increasing phase shift across the subcarriers, but still provides a suitable approximation of the time delay for the purpose of achieving electronic beam tilt. FIR 1382 may also include a notch filter for removing component carriers that are not processed by a given signal path. In some embodiments, NCO 1380 may be used to apply a time domain frequency shift that moves the desired component carrier to the low passband of notch filter 1382.

[0201] Fig.14 Depicted according to some embodiments Fig.12 13 and a generalized configuration of an example signal processing for dual-carrier, dual-polarization communication signals of a transceiver IC device. More specifically, Fig.14 The example of the signal processing configuration shown in may be applicable in embodiments involving communication of data packets associated with two different carriers (e.g., two component carriers), where each carrier signal has two polarizations (e.g., horizontal and vertical polarizations as described above). In an exemplary embodiment, the transceiver device is a transceiver IC. In addition, in Fig.14 In an example configuration, the transceiver IC operates in a TDD mode within an OFDM modulated wireless network such as an LTE-based or 5G-based communication system.

[0202] like Fig.14 As shown, the transceiver device (IC) 1400 includes a first serial communication port 1406 (eg, a first serial port transmitter / receiver, such as a Serdes transmitter / receiver) (in Fig.14 0) and a second serial communication port 1434 (eg, a second serial port transmitter / receiver, such as a Serdes transmitter / receiver) (in Fig.14Note, however, that although the transceiver IC is shown as having two separate serial communication ports (1406 and 1434), Fig.14 In the embodiment of the present invention, only one of ports 1406 and 1436 is used. More specifically, as shown, only serial communication port 1406 is connected to serial data links 1402 and 1404 for communicating data to / from the transceiver IC, while serial communication port 1434 is not actively used. However, in some embodiments, the transceiver IC may also be serially connected to a second transceiver IC via port 1434 (e.g., as described in various embodiments herein).

[0203] Generally speaking, as previously indicated, the transceiver IC can be configured to process four separate transmit component carriers and four separate receive component carriers. The transceiver IC is configured with at least two separate transmit signal port paths (chains) and at least two separate receive signal port paths (chains) typically associated with two corresponding antenna radiating elements, but other configurations are possible, as described herein. In addition, generally speaking, the transceiver IC includes numerous signal processing elements, in particular, an integrated digital signal processor (DSP) for converting frequency domain digital data to / from time domain digital data (via multiple iFFTs and FFTs) and for cyclic prefix addition and removal, multiple integrated modulated digital power amplifiers (DPAs) for converting digital baseband time domain signals into amplified analog RF signals, analog RF downconverters, and analog-to-digital converters, etc.

[0204] refer to Fig.14In some embodiments, the serial communication port 1406 may receive a data packet stream (e.g., four multiplexed data packet streams) for DL ​​(downlink) transmission via the serial data link 1402 (e.g., from a beamformer processor), wherein the packets include packets for a first component carrier (hereinafter, "carrier C1") for each of the horizontal (H) and vertical (V) polarizations and IQ data packets for a second different component carrier (hereinafter, "carrier C2"). For simplicity, the combination of two different component carriers and horizontal and vertical polarizations are denoted herein as "C1H", "C2H", "C1V", and "C2V", respectively. In the UL (uplink) direction, the serial communication port 1406 may receive an IQ data packet stream (e.g., four multiplexed IQ data sets for four OFDM subcarrier sets) for each of the two H and V polarizations for each of the two carriers C1 and C2, and transmit these IQ data packet streams via the serial data link 1404 (e.g., to the beamformer processor). In an exemplary embodiment, packets received at or transmitted from the serial port communication port 1406 contain frequency domain sub-carrier specific digital IQ data. In some embodiments, different carrier packets destined for the same transceiver IC may contain unique carrier IDs and be addressed to the same transceiver IC.

[0205] like Fig.14 As shown in FIG. 1 , the serial communication port 1406 may be coupled to a signal processing unit 1408, which includes several elements configured to provide various digital signal processing functions, such as those previously described in conjunction with FIG. Fig.12 13. In some embodiments, the signal processing unit 1408 may be a single digital signal processor (DSP) that performs all iFFT and FFT calculations as well as other signal processing functions (not explicitly shown) associated with, for example, frequency / time domain I / Q data signals.

[0206] In operation, in the downlink (DL) transmission direction, an IQ packet data stream for DL ​​transmission received via link 0 (1406) may be provided to a demultiplexer (or similar element, such as a memory segment according to a memory map) 1410, which may separate the received data into two corresponding data streams for two separate transmission chains: one IQ data stream for a dual-carrier horizontally polarized signal (C1H / C2H signal) to be transmitted from a signal port coupled to a radiating element 1422, and another IQ data stream for a dual-carrier vertically polarized signal (C1V / C2V signal) to be transmitted from a signal port coupled to a radiating element 1430. Element 1412 (e.g., in the form of DSP memory) may further separate the horizontal and vertical frequency domain components (data points) of the subcarriers of each corresponding component carrier C1 and C2, which are then sent to four separate iFFT / CP (IFFT / cyclic prefix) elements 1414 for frequency domain to time domain conversion to generate four separate discrete time domain baseband data signals, two signals per carrier frequency and two signals per signal polarization. Although not explicitly shown, additional time domain and frequency domain processing may include, for example, cyclic prefix addition, frequency offset, phase and gain adjustment, filtering, and sampling rate conversion.

[0207] In practice, as described above, incoming data is split into four separate transmission paths. More specifically, Fig.14 As shown, the output of unit 1408 includes (i) two separate discrete time-domain baseband data signals 1416 and 1418, represented as C1H (1416) and C2H (1418), and (ii) two separate discrete time-domain baseband data signals 1426 and 1428, represented as C1V (1426) and C2V (1428). As shown, after frequency domain to time domain conversion, time domain signals C1H (1416) and C2H (1418) are added (summed) in time, and C1V (1426) and C2V (1428) are added (summed) in time, and the result of the signal addition is provided to a corresponding TX / DPA element 1420, which generally represents a transmit RF chain and a digital power amplifier, to generate an amplified analog RF signal C1H / C2H (1424) for a horizontal signal port and an amplified analog RF signal C1V / C2V (1432) for a vertical signal port. Signals 1424 and 1432 are then provided to corresponding radiating elements 1422 and 1430 via corresponding SPDTs for transmission. Note that, although not explicitly shown, as previously described herein, additional time domain processing may include, for example, additional sampling rate conversion, crest factor reduction (CFR), digital pre-distortion (DPD), etc.

[0208] In operation, in the receive direction, the data modulated dual component carrier RF uplink signal can be received by the transceiver IC (1400) at the horizontal and vertical signal ports via the radiating elements 1422 and 1430. For ease of discussion and for example only, assume that the amplified analog RF signal C1H / C2H (1424) and the amplified analog RF signal C1V / C2V (1432) are now the uplink signals received by the transceiver IC. Fig.14 As shown in FIG. 14 , horizontally and vertically polarized RF signals may be provided to separate LNA / DC / ADC elements 1446 via respective SPDTs. The LNA / DC / ADC elements 1446 may perform RF to baseband signal conversion, analog to digital signal conversion, followed by, for example, further time domain processing (e.g., quadrature error correction, filtering, etc. (not explicitly shown)).

[0209] As further shown, the output of element 1446 includes two copies of the discrete time domain baseband data signal. These two signals are filtered by FIR filters 1442, 1444, but one of these signals is first shifted in frequency by the NCO (within filter 1442 or 1444) to separate the component carriers. The separated carriers are represented as C1H (1442) and C2H (1444). Two additional identical discrete time domain baseband data signals are provided to filters 1426 and 1428, and time domain signals representing the component carrier time domain signals (after NCO conversion and FIR filtering) are generated, which are represented as C1V (provided by filter 1448) and C2V (provided by filter 1450). These four separate time domain baseband signals 1442, 1444, 1148 and 1450 (two signals per carrier and two signals per polarization) are then input into the DSP 1408 for signal processing, including CP removal and conversion from time domain IQ signal samples to frequency domain IQ data, which represents the amplitude and phase of the corresponding subcarriers of the corresponding component carrier.

[0210] Thus, the receive RF signal is effectively split into four discrete time-domain baseband data signals for processing on four separate receive paths. More specifically, the C1H signal (1442), C2H signal (1444), C1V signal (1448), and C2V signal (1450) are parsed, for example, by memory mapping, for four separate FFT signal processing operations (e.g., 1440) for time-domain to frequency-domain conversion (via FFT) to generate four separate frequency-domain IQ data packets (or packet streams, where each packet in the stream represents a symbol time within a time slot) for each of the two component carrier frequencies and for each signal polarization.

[0211] Although not explicitly shown, other time-frequency pre-conversion signal processing may include, for example, sampling rate conversion, filtering, cyclic prefix detection and removal, etc., as described above. After the conversion performed by FFT element 1440, elements 1436, 1438 (e.g., in the form of DSP memory and digital logic) may then formulate IQ data packets for each polarization (H or V) for different component carriers associated with both component carriers C1 and C2.

[0212] As further illustration of other embodiments, Fig.15 Depicted according to some embodiments Fig.12 13 to generate a generalized configuration of an example signal processing of a four-carrier, dual-polarized communication signal. More specifically, Fig.15 1 shows a transceiver device architecture 1500 including a first transceiver device 1504a and a second transceiver device 1504b. Fig.14 As shown, in an exemplary embodiment, the transceiver device is a transceiver IC and operates in TDD mode within an OFDM modulation system such as a 5G-based or LTE-based communication system. Fig.14 The various operating principles and nomenclature described apply to Fig.15 Therefore, some operational details will be omitted or summarized for ease of discussion.

[0213] refer to Fig.15 , the first transceiver device (IC) 1504a includes a first serial communication port 1506 (eg, a first serial port transmitter / receiver, such as a Serdes transmitter / receiver) (in Fig.15 0) and a second serial communication port 1530 (e.g., a second serial port transmitter / receiver, such as a Serdes transmitter / receiver) (in Fig.15 Similarly, the second transceiver device (IC) 1504b includes a first serial communication port 1546 (eg, a first serial port transmitter / receiver, such as a Serdes transmitter / receiver) (in Fig.15 0) and a second serial communication port 1562 (e.g., a second serial port transmitter / receiver, such as a Serdes transmitter / receiver) (in Fig.15 1 ). Transceiver devices (ICs) 1504a and 1504b are serially connected via a bidirectional serial data link 1544.

[0214] In some embodiments, the serial communication port 1506 may receive an IQ data packet stream (eight sets of IQ data, grouped into four carrier-specific H / V combinations, or in the depicted embodiment, into eight separate data packet streams) for DL ​​transmission via a bidirectional serial data link 1502 (e.g., from a beamformer processor), wherein the packets include IQ subcarrier data for four different component carriers (hereinafter, "carrier C1," "carrier C2," "carrier C3," and "carrier C4") for each of the horizontal (H) and vertical (V) polarizations. For simplicity, the combinations of four different carriers on the horizontal and vertical polarizations are denoted herein as "C1H," "C2H," "C3H," "C4H," "C1V," "C2V," "C3V," and "C4V," respectively. In the UL (uplink) direction, the serial communication port 1506 may receive data packet streams for each of the four carriers C1, C2, C3, and C4 for each of the two H and V polarizations (e.g., eight multiplexed data packet streams) and transmit these data packet streams (e.g., to a beamformer processor) via the same bidirectional serial data link 1502. In an exemplary embodiment, packets received at or transmitted from the serial port communication port 1506 include frequency domain digital IQ data.

[0215] In operation, in the DL transmission direction, the first transceiver IC (1504a) receives a packetized IQ data stream for DL ​​transmission via port 1506. The first transceiver IC is configured to process data associated with the first two carriers (i.e., C1H, C2H, C1V, and C2V) for each polarization. Fig.14 In the described transmission operation, the first transceiver IC performs signal processing to separate (via a demultiplexer or similar element (1508)) the received IQ data for carriers C1 and C2 into respective data sets for two separate transmission paths: one IQ data stream for a dual-carrier horizontally polarized signal (C1H / C2H signal) and another IQ data stream for a dual-carrier vertically polarized signal (C1V / C2V signal). As generally shown by elements 1510 and 1520 (denoted as "C1H / C2H" and "C1V / C2"), as shown Fig.14, the horizontal and vertical frequency domain components of the subcarriers of each corresponding component carrier C1 and C2 can be further split and processed by four separate iFFT / CP elements to generate four separate discrete time-domain baseband data signals (two signals for each component carrier and two signals for each signal polarization), which are then added in pairs in time, where the results of the signal addition (C1H+C2H and C1V+C2V) are provided to the corresponding TX / DPA elements 1512 and 1522 to generate modulated and amplified analog RF signals C1H / C2H for the horizontal signal port of the transceiver IC 1504a and amplified analog RF signals C1V / C2V for the vertical signal port of the transceiver IC 1504a.

[0216] and Fig.14 Unlike the embodiments of the present invention, the packet data associated with the other two carriers C3 and C4 received at port 1506 is forwarded to the second transceiver IC (1504b) for processing. More specifically, the first transceiver IC may be configured to forward the IQ data packets for carriers C3 and C4 for each polarization (i.e., C3H, C4H, C3V, and C4V) to the second transceiver IC 1504b for processing. In some embodiments, different carrier packets destined for the first transceiver IC or the second transceiver IC may contain a unique carrier ID and be addressed to the corresponding transceiver IC through one or more identification fields in the IQ data packets. Therefore, the first transceiver may be configured to examine the incoming packets to determine which packets are intended for the first transceiver IC and which packets are to be forwarded to the second transceiver IC.

[0217] In some embodiments, the first transceiver IC may forward those packets via internal path 1532 to its second serial communication port 1530, which is serially interconnected with a second transceiver IC (i.e., serial communication port 1546 within the second transceiver IC) via serial data link 1544. The second transceiver IC performs similar signal processing as the first transceiver IC (but with respect to carriers C3 and C4) via elements 1548, 1550, 1556, 1552, and 1558 to output amplified analog RF signals C3H / C4H and C3V / C4V on two signal ports of transceiver IC 1504b.

[0218] Subsequently, (i) the two signals C1H / C2H and C3H / C4H for horizontal polarization can be combined via summing element 1514 to produce a combined signal 1518, which is provided to radiating element 1516 for transmission via the first SPDT, and (ii) the two signals C1V / C2V and C3V / C4V for vertical polarization can be combined via summing element 1524 to produce a combined signal 1528, which is provided to radiating element 1526 for transmission via the second SPDT.

[0219] Similarly, in the receive direction, the data modulated four-carrier dual-polarized RF uplink signal may be received by two serially connected transceiver ICs (1504a and 1504b) via radiating elements 1516 and 1526 corresponding to the horizontal and vertical signal ports, respectively. Fig.14 In the present invention, for ease of discussion and for example only, it is assumed that the analog RF signals C1H / C2H / C3H / C4H (1518) and the analog RF signals C1V / C2V / C3V / C4V (1628) are now the received uplink signals.

[0220] like Fig.15 As shown in FIG. , the RF signal (1518) received on the horizontally polarized antenna element 1516 is provided to the RX / LNA element 1538 within the first transceiver IC (1504a) via the corresponding SPDT, and the RF signal (1528) received on the vertically polarized antenna element is provided to the RX / LNA element 1570 within the second transceiver IC (1504b) via the corresponding SPDT. Fig.14 , each of the corresponding horizontal and vertical receive RX / LNA chains can be configured to perform RF to baseband signal conversion, analog to digital signal conversion, etc. to output a first four-carrier discrete time domain signal on the horizontal receive path and a second four-carrier discrete time domain signal on the vertical path. Thus, in some embodiments, the output of the RX / LNA 1538 element can be a first four-carrier discrete time domain signal on the horizontal polarization receive path, and the output of the RX / LNA element 1570 can be a second four-carrier discrete time domain signal on the vertical polarization receive path. Note that in this embodiment, each transceiver IC processes four component carriers in one of the RX / LNA elements, while the other RX / LNA elements (1542, 1576) are disabled.

[0221] Return to reference Fig.15, with respect to horizontal polarization, the output of the RX / LNA element 1538 includes discrete time-domain baseband data signals 1536 and 1540 to be processed on two separate signal processing branches, wherein (i) carriers C1 and C2 represented as C1H / C2H (1536) are processed on one branch, and (ii) carriers C3 and C4 represented as C3H / C4H (1540) are processed on the other branch. Similarly, with respect to vertical polarization, the output of the RX / LNA element 1570 may include discrete time-domain baseband data signals 1568 and 1574 to be processed on two separate signal processing branches, wherein (i) carriers C1 and C2 represented as C1V / C2V (1568) are processed on one branch, and carriers C3 and C4 represented as C3V / C4V (1574) are processed on the other branch.

[0222] As combined Fig.14 The various principles of operation of the described receive signal processing (including the conversion from time domain signals to frequency domain IQ data) will similarly apply to Fig.15 , and will not be repeated in detail here. For illustration, in some embodiments, the received C1H / C2H signal (1536) for horizontal polarization can be separated from C3H / C4H by time domain FIR filtering, notch filtering, etc., and further separated into constituent component carriers C1H and C2H by time domain filtering in one signal path to remove the C2H component to obtain C1H, while another path includes complex multiplication via a numerically controlled oscillator (NCO) frequency to shift the C2H component to the desired baseband signal, followed by additional filtering to remove the residual component of C1H. Thus, one transceiver IC 1504a can receive four component carriers on a single receive RF signal port (e.g., via either of the H or V polarized antenna elements) and parse the signal into four separate component carriers. In the illustrated embodiment, the four separate component carriers C1H, C2H, C3H, C4H are all separated using time domain signal processing and then sent to four separate FFT operations (in some embodiments, all performed by a single DSP processor) for time domain to frequency domain conversion. Similarly, the C1V / C2V / C3V / C4V signals (1528) for vertical polarization, initially processed by a single LNA and ADC 1570, are processed via filtering, frequency offset (i.e., NCO modulation), and further filtering to be conditioned for four separate FFT operations for time domain to frequency domain conversion. Although not explicitly shown, other time-frequency pre-conversion signal processing may include, for example, sample rate conversion, filtering, cyclic prefix detection and removal, etc., as described above.

[0223] After the time domain to frequency domain conversion, elements 1534 and 1566 (on the horizontal and vertical paths, respectively) then route and / or store in memory the IQ data points of the subcarriers associated with the individual component carriers C1, C2, C3, and C4 for each respective polarization (H or V). The frequency domain IQ data for all four component carriers per polarization may be further combined into packet data streams (e.g., eight packet data streams, or four combined V / H packet streams) for transmission (e.g., to a beamformer processor) from two serially connected transceiver ICs (1504a and 1504b) over a bidirectional serial link 1502.

[0224] More specifically, in this regard, frequency domain IQ packet data corresponding to vertically polarized signals of four carriers C1, C2, C3, and C4 may be received at the serial communication port 1562 of the second transceiver IC (1504b). The second transceiver IC may be configured to forward those data packets to its other serial communication port 1546 via an internal link 1564, which is serially interconnected with the first transceiver IC (i.e., the serial communication port 1530 within the first transceiver IC) via a serial data link 1544. Although not in Fig.15 1502. Although not explicitly shown in the figures, in some embodiments, the packet data output by element 1534 (for horizontal polarizations of all four carriers C1, C2, C3, C4) may be combined by multiplexing packet data corresponding to vertically polarized signals of the four carriers C1, C2, C3, and C4 received at the serial communication port 1530 to produce an IQ data packet stream to be sent on data link 1532 to the serial data link transceiver 1506 for communication to the beamformer processor via the serial communication link 1502.

[0225] Note that Fig.15In an embodiment, DL and UL signal processing are not performed symmetrically across the serially connected transceiver ICs: DL transmit signal processing is divided according to component carrier (both H and V polarities of C1 and C2 are processed in transceiver IC 1504a, and both polarities of C3 and C4 are processed in transceiver IC 1504b), while UL receive signal processing is divided according to polarity (all H polarities of C1, C2, C3 and C4 are processed by transceiver IC 1504a, and all V polarities of C1, C2, C3 and C4 are processed by transceiver IC 1504b). This has the advantage on the transmit side of relaxing the bandwidth requirements on the transmit modulator to span only two component carriers (C1, C2 processed in transceiver IC 1504a, and C3, C4 processed in transceiver IC 1504b), while having the advantage on the receive side of not splitting the receive signal to two different signal ports of two different transceiver ICs prior to processing via down-conversion and sampling via ADC. Thus, in the described embodiment, a dual-polarized four-component carrier system can be implemented using the wideband capabilities of the receiver portion of the transceiver IC to process receive signals having a bandwidth of four component carriers, while also relaxing the transmit modulator / amplifier bandwidth requirements to accommodate transmit signals having a bandwidth of only two component carriers.

Claims

1. A device, comprising: main beamformer processor; a plurality of secondary beamformer processors connected to the primary beamformer processor, each of the plurality of secondary beamformer processors being associated with a respective region of an antenna array and further associated with a respective beamforming sub-matrix of a plurality of beamforming sub-matrices, each beamforming sub-matrix containing beamforming combining weights associated with antenna elements in the respective region of the antenna array; and A plurality of sets of transceiver integrated circuits (ICs) connected to a plurality of distributed secondary beamformer processors, wherein: each set of transceiver ICs is connected to a corresponding secondary beamformer processor of the plurality of secondary beamformer processors and is located within the respective region of the antenna array associated with the corresponding secondary beamformer processor, and Each secondary beamformer processor is configured to receive a respective set of frequency-domain IQ data points and to form a respective plurality of beamformed frequency-domain IQ data points using the respective set of frequency-domain IQ data points and the respective beamforming sub-matrix.

2. The apparatus of claim 1 , wherein the primary beamformer processor is configured as a transmit beamformer processor, and wherein the secondary beamformer processor is configured as a secondary transmit beamformer processor having a beamforming sub-matrix for transmit beamforming, and wherein the frequency domain IQ data packet is a user data layer, and the secondary transmit beamformer generates beamformed frequency domain IQ data points.

3. The apparatus of claim 1 , wherein the primary beamformer processor is configured as a primary receive beamformer processor, and the plurality of secondary receive beamformer processors are configured as secondary receive beamformer processors and are configured with beamforming sub-matrices for receive beamforming, and wherein the frequency domain IQ data packets are frequency domain IQ data received from a transceiver IC, and the secondary transmit beamformers are configured to generate partially beamformed frequency domain IQ data points, and the primary receive beamformer processor is configured to combine corresponding sets of received partially beamformed frequency domain IQ data points received from all secondary receive beamformer processors to form a plurality of fully beamformed frequency domain subcarrier IQ user data layers.

4. The apparatus of claim 3, wherein the primary receive beamformer processor is configured to separate a receive beamforming matrix of beamforming combination weights into the plurality of receive beamforming sub-matrices, and to transmit each respective receive beamforming sub-matrix to a corresponding secondary receive beamformer processor among the plurality of secondary receive beamformer processors.

5. The apparatus of claim 3 , wherein each distributed secondary receive beamformer processor is further configured to form corresponding multiple sets of partially beamformed frequency-domain IQ data points by applying receive beamforming combining weights of the corresponding receive beamforming sub-matrix to corresponding sets of the frequency-domain IQ data points.

6. The apparatus of claim 1, wherein the transceiver ICs are serially connected into a subarray of transceiver ICs.

7. A method comprising: receiving, at each of a plurality of distributed secondary receive beamformer processors connected to a primary receive beamformer processor, a respective set of frequency-domain IQ data points from a respective set of transceiver integrated circuits (ICs) in a plurality of sets of transceiver integrated circuits (ICs), wherein the plurality of secondary receive beamformer processors are associated with respective regions of an antenna array associated with respective receive beamforming sub-matrices in a plurality of receive beamforming sub-matrices, each receive beamforming sub-matrix containing receive beamforming combining weights associated with antenna elements in the respective region of the antenna array, and wherein the respective set of transceiver ICs is located within the respective region of the antenna array associated with the secondary receive beamformer processor; forming, by each secondary receive beamformer processor, respective sets of frequency domain IQ data points for receive partial beamforming using the respective sets of frequency domain IQ data points and the respective receive beamforming sub-matrix; as well as A respective plurality of sets of the receive partially beamformed frequency-domain IQ data points are transmitted by each distributed secondary receive beamformer processor to the primary receive beamformer processor.

8. The method according to claim 7, further comprising: Corresponding sets of receive partially beamformed frequency-domain IQ data points received from all of the plurality of distributed secondary receive beamformer processors are combined by the primary receive beamformer processor to form a plurality of frequency-domain IQ user data layers.

9. The method according to claim 7, further comprising: A receive beamforming matrix of beamforming combination weights is partitioned into the plurality of receive beamforming sub-matrices by the primary receive beamformer processor, and each respective receive beamforming sub-matrix is ​​transmitted to a corresponding secondary receive beamformer processor of the plurality of secondary receive beamformer processors.

10. A method comprising: at a main transmit beamforming processor, partitioning a transmit beamforming matrix of beamforming combination weights into a plurality of transmit beamforming sub-matrices, each transmit beamforming sub-matrix containing transmit beamforming combination weights associated with antenna elements in a corresponding region of the antenna array; providing (i) the transmit beamforming sub-matrices and (ii) one or more frequency domain IQ (FDIQ) user data layers to a plurality of secondary transmit beamformer processors coupled to a transmit primary beamforming processor; as well as calculating a beamformed transmit FDIQ data packet at each secondary transmit beamformer processor; as well as The beamformed transmit FDIQ data packets are transmitted to a plurality of sets of transceiver integrated circuits, each set of transceiver integrated circuits being located within a respective region of the array panel and connected to a corresponding secondary transmit beamformer processor of the plurality of secondary transmit beamformer processors.

11. The method of claim 10, wherein the primary transmit beamformer processor is configured to transmit the transmit beamforming sub-matrix to corresponding secondary transmit beamformer processors, and to transmit the frequency domain subcarrier IQ user data layer to all of the distributed secondary transmit beamformer processors.

12. The method of claim 11, wherein each distributed auxiliary transmit beamformer processor is configured to receive the frequency domain subcarrier IQ user data layer and the corresponding transmit beamforming submatrix, and calculate a beamformed frequency domain IQ data point set by applying the corresponding beamforming weights of the beamforming submatrix to the IQ user data layer, and distribute the beamformed frequency domain IQ data point set to a corresponding set of transceiver ICs arranged in a transceiver IC subarray, wherein the transceiver IC subarray is located within a corresponding region of the auxiliary beamformer processor.

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