A general test method, device and readable storage medium for an isolation chip

Abstract

The present application discloses a general testing method, device and readable storage medium for isolation chips, relating to the technical field of electronic device testing, including a test daughter board which connects the pins of the isolation chip to be tested to a test base board; the test base board is provided with a maximum number of pins, a maximum number of isolation channels according to the pin distribution rule of the isolation chip, and the isolation channel direction is set to be bidirectional; the test daughter board is connected above the test base board and the resource extraction board of the CTA8280F analog test machine is connected below. The function of the test daughter board is to connect the pins of different models of isolation chips to the test base board. Only by replacing different test daughter boards can different models of isolation chips be tested, which can reduce the difficulty and cycle of test development.

Description

Technical Field

[0001] This application relates to the technical field of electronic device testing, and particularly to a general test method, device, and readable storage medium for isolation chips. Background Art

[0002] The traditional method for testing isolation chips is as follows: on a CTA8280F simulation machine platform, corresponding test programs are written according to the specific model of the isolation chip for testing. However, due to different models of isolation chips on the market, their packaging forms and the number of pins are different. Specifically, currently, isolation chips on the market include 2-channel, 4-channel, and 6-channel isolation. On this basis, there are also input-output configurations in different directions. For example, a 2-channel isolation chip includes a first configuration mode where both of the 2 channels are left-input right-output, a second configuration mode where 1 channel is left-input right-output and the other channel is right-input left-output, and a third configuration mode where both of the 2 channels are right-input left-output. The 4-channel and 6-channel isolation chips are similar. The packaging forms are also divided into multiple forms such as SSOP, SOIC, and SOICW; this leads to disadvantages such as non-portability of test development, high test development difficulty, and long cycle;

[0003] In view of this, there is an urgent need for a general test method for isolation chips that can complete the automated testing of isolation chips with different numbers of pins and different packages using a set of test systems. It is convenient for program transplantation and reduces the difficulty and cycle of test development. Summary of the Invention

[0004] In view of the above-mentioned disadvantages of the prior art, this application proposes a general test method, device, and readable storage medium for isolation chips, which solves the problem in the prior art that it is impossible to complete the automated testing of isolation chips with different numbers of pins and different packages using a set of test systems.

[0005] To achieve the above object, this application specifically adopts the following technical solutions:

[0006] A general test method for isolation chips includes a test daughter board that connects the pins of the isolation chip to be tested to a test base board; the test base board is set with the maximum number of pins, the maximum number of isolation channels, and the isolation channel direction is set to be bidirectional according to the pin distribution rule of the isolation chip; the test daughter board is connected above the test base board, and the resource extraction board of the CTA8280F analog test machine platform is connected below; the processing terminal of the CTA8280F analog test machine platform tests the DC parameters and AC parameters of the isolation chip to be tested.

[0007] As an alternative technical solution, the testing process of the DC parameters and AC parameters includes performing the non-isolated side test and the isolated side test of the isolation chip to be tested through resource configuration on the CTA8280F analog test machine. Among them, the non-isolated side test of the isolation chip to be tested is as follows:

[0008] DC parameter test: Turn on the non-isolated side DC channel relay, select the number of channels and connect to the floating source to perform all DC parameter tests; turn off the non-isolated side DC channel relay and disconnect from the floating source. The DC parameters include power supply current IDD, input high-level voltage threshold VIH, input low-level voltage threshold VIL, output high-level voltage value VOH, and output low-level voltage value VOL.

[0009] AC parameter test: Turn on the non-isolated side AC channel relay, select the number of channels and connect to the time test board to perform the tests of transmission delay and output waveform rise and fall. Turn on the non-isolated side channel output state configuration relay, select the corresponding load state, and perform the transmission delay test from the enable signal to the output signal. The AC parameters include maximum rate fMAX, transmission delay tPLH / tPHL, rise time tR, fall time tF, enable transmission time tPZH / tPZL, and disable transmission time tPHZ / tPLZ.

[0010] The isolated side test of the isolation chip to be tested is as follows:

[0011] DC parameter test: Turn on the isolated side DC channel relay, select the number of channels and connect to the floating source to perform all DC parameter tests; turn off the isolated side DC channel relay and disconnect from the floating source. The DC parameters include power supply current IDD, input high-level voltage threshold VIH, input low-level voltage threshold VIL, output high-level voltage value VOH, and output low-level voltage value VOL.

[0012] AC parameter test: Turn on the isolated side AC channel relay, select the number of channels and connect to the time test board to perform the tests of transmission delay and output waveform rise and fall. Turn on the isolated side channel output state configuration relay, select the corresponding load state, and perform the transmission delay test from the enable signal to the output signal. The AC parameters include maximum rate fMAX, transmission delay tPLH / tPHL, rise time tR, fall time tF, enable transmission time tPZH / tPZL, and disable transmission time tPHZ / tPLZ.

[0013] After the non-isolated side test and the isolated side test operations of the isolation chip to be tested are completed, all resources of the CTA8280F analog test machine are powered off and disconnected from the pins of the isolation chip to be tested.

[0014] As an alternative technical solution, when performing tests on transmission delay and the rise and fall of the output waveform, the input pin is the input signal and the output pin is the detection signal.

[0015] As an alternative technical solution, when performing the transmission delay test of the enable signal to the output signal, the enable pin is the input signal and the output pin is the detection signal.

[0016] As an alternative technical solution, the test daughter board is a first PCB substrate, including an upper surface and a lower surface opposite to each other. The upper surface is provided with a test socket for fixing the isolation chip to be tested, and the lower surface is provided with a European connector plug.

[0017] As an alternative technical solution, the test base board is a second PCB substrate. The upper surface of the second PCB substrate is provided with a socket matching the European connector plug on the lower surface of the first PCB substrate. The second PCB substrate is provided with a plurality of connection holes, and the lower surface of the second PCB substrate is provided with a pogo pin connector.

[0018] As an alternative technical solution, the resource extraction board is a third PCB substrate. The third PCB substrate is provided with a plurality of connection holes, which correspond one by one to the connection holes on the second PCB substrate. The third PCB substrate and the second PCB substrate are detachably connected through a connecting member;

[0019] The third PCB substrate includes an upper surface and a lower surface opposite to each other. The upper surface includes a pogo pin connection area matching the pogo pin connector on the second PCB substrate, and the lower surface is connected to the CTA8280F analog test machine.

[0020] An electronic device includes: one or more processors, a memory, and one or more computer programs, wherein the one or more computer programs are stored in the memory, and the one or more computer programs include instructions that, when executed by the electronic device, cause the one or more processors to execute the described method.

[0021] A computer-readable storage medium has a computer program stored thereon, which, when executed by a processor, implements the described method.

[0022] The beneficial effects of the present application include:

[0023] The function of the test daughter board is to connect the pins of isolation chips of different models to the test base board. If isolation chips of different models need to be tested, only different test daughter boards need to be replaced, which reduces the difficulty and cycle of test development. Moreover, the isolation chip test program selects the number of isolation channels and the direction of isolation channels according to the general test program framework for isolation chips. Only by selecting the corresponding relay bit numbers in the general test program framework can a test program with different numbers of isolation channels and different directions of isolation channels be configured, that is, the so-called test programs for isolation chips of different models. With this general test program framework, the development cycle can be greatly reduced, and even beginners can quickly develop the program.

[0024] Other beneficial effects or advantages of this application will be described in detail in combination with the specific structure in the specific implementation manner. BRIEF DESCRIPTION OF THE DRAWINGS

[0025] In order to more clearly illustrate the technical solutions in the embodiments of the present application or the prior art, the following will briefly introduce the drawings required for use in the description of the embodiments or the prior art. Obviously, the following drawings are only some embodiments of the present application. For those skilled in the art, without creative efforts, other drawings can be obtained based on these drawings. In addition, it should be understood that the proportional relationships of the various components in the drawings of this specification do not represent the proportional relationships in actual material selection and design. It is only a schematic diagram of the structure or position, where:

[0026] Figure 1 It is the schematic diagram of the isolation chip test principle in this application. DETAILED DESCRIPTION OF THE EMBODIMENTS

[0027] To make the objectives, technical solutions, and advantages of the embodiments of the present application clearer, the following will clearly and completely describe the technical solutions in the embodiments of the present application in combination with the drawings in the embodiments of the present application. Obviously, the described embodiments are some, rather than all, of the embodiments of the present application. Usually, the components of the embodiments of the present application described and shown in the drawings here can be arranged and designed in various different configurations.

[0028] Therefore, the following detailed description of the embodiments of the present application provided in the drawings is not intended to limit the scope of the present application claimed, but merely represents the selected embodiments of the present application. Based on the embodiments in the present application, all other embodiments obtained by those of ordinary skill in the art without creative efforts fall within the scope of protection of the present application.

[0029] In the description of this application, it should be noted that the terms used, such as "top" and "bottom", refer to the part closer to the upper side when this application is in use as the top, and the part closer to the lower side as the bottom; the terms used, such as "first" and "second", are only for distinguishing expressions, rather than indicating or implying any difference in importance or order; the terms used, such as "inner" and "outer", refer to the inside and outside of the specific contour. The use of the above terms is only for clearly and simply expressing the technical solution of this application, and should not be construed as a limitation to this application.

[0030] Embodiment 1:

[0031] As Figure 1 shown, the present invention discloses a general test method for an isolation chip, including a test daughter board that connects the pins of the isolation chip to be tested to a test base board; the test base board is provided with a maximum number of pins, a maximum number of isolation channels according to the pin distribution rule of the isolation chip, and the isolation channel direction is set to be bidirectional; the test daughter board is connected above the test base board, and the resource extraction board of the CTA8280F analog test machine is connected below; the processing terminal of the CTA8280F analog test machine tests the DC parameters and AC parameters of the isolation chip to be tested.

[0032] It should be particularly explained that although some basic content has been mentioned in the published document CN117632609B, the general test of the microprocessor chip mentioned in the published document is completely different from the general test of the isolation chip described in this article. The general test of the microprocessor chip is based on the maximum number of pins because the pins of the microprocessor chip can be multiplexed for other functions, such as ADC, DAC, timer, etc., so the maximum number of pins needs to be used as a limiting condition for downward-compatible general tests. The function of the isolation chip is only to isolate the signals on the input side and the output side, and its pins do not have multiplexing functions. Therefore, in addition to the maximum number of pins as a limiting condition for downward-compatible general tests, the maximum number of isolation channels and the isolation direction also need to be used as limiting conditions for downward-compatible general tests. The essence is that the microprocessor chip and the isolation channel chip are different types of chips, and the ideas used in testing are different.

[0033] The traditional isolation chip test is:

[0034] Since the isolation chips have 2-channel, 4-channel, and 6-channel isolation, and on this basis, there are also input and output configurations in different directions. For example, the 2-channel isolation chip includes the first configuration mode where both of the 2 channels are left-input and right-output, the second configuration mode where 1 channel is left-input and right-output and the other channel is right-input and left-output, and the third configuration mode where both of the 2 channels are right-input and left-output. The 4-channel and 6-channel isolation chips are similar. The package forms are also divided into multiple forms such as SSOP, SOIC, and SOICW. The current test method is to write corresponding test programs according to the specific model of the isolation chip on the CTA8280F simulation machine for testing. Here, there is a problem that for isolation chips of different models, their package forms and the number of pins (the number of isolation channels) are different, which leads to disadvantages such as non-portability of test development, high difficulty in test development, and long cycle;

[0035] After the improvement of this solution, it can achieve general testing for different channels and different output directions:

[0036] By setting the maximum number of pins, the maximum number of isolation channels, and setting the isolation channel direction to bidirectional on the test base plate according to the pin distribution rule of the isolation chip, the problem of non-general testing at the hardware level is solved;

[0037] Furthermore, the test sub-board is connected above the test base plate, and the resource extraction board of the CTA8280F simulation test machine is connected below; the processing terminal of the CTA8280F simulation test machine tests the DC parameters and AC parameters of the isolation chip to be tested, solving the disadvantages that for isolation chips of different models, their package forms and the number of pins are different, which leads to non-portability of test development, high difficulty in test development, and long cycle.

[0038] It can be understood that the solution described in the present invention improves the traditional one-to-one test device into a general device, specifically as follows:

[0039] The CTA8280F simulation test machine has advantages such as high test accuracy, fast test speed, good stability, high reliability, and strong anti-interference ability, and is suitable for various analog circuits and mixed-signal circuits such as linear circuits like operational amplifiers, power amplifier circuits, motor drive circuits, power management circuits, and radio circuits, meeting the test requirements of isolation chips. The test base plate sets the maximum of 6 channels according to the pin distribution rule of the isolation chip, and the isolation channel direction is set to bidirectional, and is led out and connected to the resource extraction board of the CTA8280F simulation test machine for DC parameter and AC parameter testing.

[0040] The resource lead-out board on the CTA8280F simulation test machine does not have a test function. It can only lead the test resources out of the CTA8280F simulation test machine. It must be connected to the test baseboard before starting the test.

[0041] The test sub-board is multi-modal in shape, and each mode includes a test socket. Each test socket can match a group of isolation chips to be tested with the same number of isolation channels. The function of the test sub-board is to connect the isolation channels of isolation chips of different models to the test baseboard. If you want to test different types of isolation chips, you only need to replace different test sub-boards, which reduces the difficulty and cycle of test development.

[0042] It should be noted that: traditional testing does not use universal test boards. Each time a chip model is tested, a large base board needs to be drawn and many chips need to be soldered. Now the operator only needs to replace the upper test sub-board to complete the test work. It is understandable that the main categories of isolation chips are 2-channel, 4-channel, and 6-channel isolation, so the number of test sub-boards will not be too many. Several test sub-boards can be combined with a fixed bottom test board to achieve the test purpose, reducing the difficulty and cycle of test development.

[0043] As an optional technical solution, the test process of the DC parameters and AC parameters includes performing non-isolated side test and isolated side test of the isolation chip to be tested through resource configuration on a CTA8280F simulation test machine, wherein the non-isolated side test of the isolation chip to be tested is:

[0044] DC parameter test, open the non-isolated side DC channel relay, select the channel number and connect it to the floating source to perform all DC parameter tests: close the non-isolated side DC channel relay and disconnect it from the floating source; the DC parameters include power supply current IDD, input high level voltage threshold VIH, input low level voltage threshold VIL, output high level voltage value VOH, and output low level voltage value VOL.

[0045] AC parameter test, turn on the AC channel relay on the non-isolated side, select the number of channels and connect it to the time test board, perform transmission delay and output waveform rise and fall tests, turn on the output state configuration relay on the non-isolated side channel, select the corresponding load state, and perform a transmission delay test from the enable signal to the output signal; the AC parameters include the maximum rate fMAX, transmission delay tPLH / tPHL, rising edge time tR, falling edge time tF, enable transmission time tPZH / tPZL, and disable transmission time tPHZ / tPLZ.

[0046] The isolation side test of the isolation chip to be tested is:

[0047] For DC parameter testing, turn on the DC channel relay on the isolated side, select the channel number and connect it to the floating source to perform all DC parameter tests: turn off the DC channel relay on the isolated side and disconnect it from the floating source; the DC parameters include supply current IDD, input high-level voltage threshold VIH, input low-level voltage threshold VIL, output high-level voltage value VOH, and output low-level voltage value VOL.

[0048] For AC parameter testing, turn on the AC channel relay on the isolated side, select the channel number and connect it to the time test board to perform tests on transmission delay and the rise and fall of the output waveform. Turn on the output status configuration relay on the isolated side channel, select the corresponding load status, and perform the transmission delay test from the enable signal to the output signal; the AC parameters include maximum rate fMAX, transmission delay tPLH / tPHL, rise time tR, fall time tF, enable transmission time tPZH / tPZL, and disable transmission time tPHZ / tPLZ.

[0049] After the non-isolated side test and the isolated side test operations of the isolated chip to be tested are completed, power down all resources of the CTA8280F analog test machine and disconnect it from the pins of the isolated chip to be tested.

[0050] As an optional technical solution, when performing tests on transmission delay and the rise and fall of the output waveform, the input pin is the input signal and the output pin is the detection signal. When performing the transmission delay test from the enable signal to the output signal, the enable pin is the input signal and the output pin is the detection signal.

[0051] It should be particularly noted that: the input pin here is the input of the isolated channel of the isolated chip, the output pin here is the output of the isolated channel of the isolated chip, and the enable pin here is the enable signal control pin of the isolated chip. The chip works when the level is high and does not work when the level is low. The time tests for all chips are like this. The chip is installed on the test daughter board.

[0052] As an optional technical solution, the test sub-board is a first PCB substrate, including a relative upper surface and a lower surface, the upper surface is provided with a test socket that can fix the isolation chip to be tested, and the lower surface is provided with a European connector plug. The test base plate is a second PCB substrate, the upper surface of the second PCB substrate is provided with a socket that matches the European connector plug on the lower surface of the first PCB substrate, the second PCB substrate is provided with a plurality of connection holes, and the lower surface of the second PCB substrate is provided with a pogo pin connector. The resource lead-out board is a third PCB substrate, the third PCB substrate is provided with a plurality of connection holes that correspond to the connection holes on the second PCB substrate one by one, and the third PCB substrate is detachably connected to the second PCB substrate through a connector; the third PCB substrate includes a relative upper surface and a lower surface, the upper surface includes a pogo pin connection area that matches the pogo pin connector on the second PCB substrate, and the lower surface is connected to the CTA8280F simulation test machine.

[0053] Further explain how the three PCB substrates are connected. From top to bottom, they are the first PCB substrate, the second PCB substrate and the third PCB substrate. The first PCB substrate and the second PCB substrate are specially designed to achieve the purpose of this solution. By designing the first PCB substrate and the second PCB substrate, it is achieved that to test different types of isolation chips, only different test sub-boards need to be replaced, thereby reducing the difficulty and cycle of test development; due to the chip characteristics on the second PCB substrate, the test baseboard described in this solution can accommodate up to 6 isolation channels; and the third PCB substrate is the resource lead-out board that comes with the CTA8280F simulation test machine. The CTA8280F simulation test machine is an existing product, and the test baseboard of this solution is designed one-to-one for the CTA8280F simulation test machine.

[0054] When specifically designing the first PCB substrate and the second PCB substrate, it is only necessary to meet the above test purpose without making any specific structural restrictions. For example, the design may be as follows:

[0055] The test sub-board, i.e., the first PCB substrate, has an upper surface core including a test socket and a lower surface core including a capacitor;

[0056] The test base plate, i.e., the second PCB substrate, has a core on the upper surface including resistors, capacitors, LEDs, relays, SMA sockets, TPS modules, horn sockets, European connectors, and high-speed comparator chips; the core on the lower surface includes relays, resistors, capacitors, and LDO chips;

[0057] The function of the test seat is to place the isolation chip to be tested;

[0058] The resistor includes a pull-up resistor, a pull-down resistor, and a current-limiting resistor. Among them, the pull-up resistor is a resistor connected in series between the power supply voltage and the pin, and the state of the current pin is default to 1; the pull-down resistor is a resistor connected in series between the ground and the pin, and the state of the current pin is default to 0; the current-limiting resistor is a resistor connected in series between the power supply voltage and the LED, reducing the current flowing through the LED to prevent the LED from burning out due to excessive current.

[0059] The capacitor includes a filtering capacitor and a storage capacitor. Among them, the filtering capacitor filters out the noise on the power supply voltage to keep the power supply voltage in a stable state, and a filtering capacitor needs to be connected in parallel at the power supply pin. The storage capacitor: when the load current of the chip suddenly increases, the power supply current will also suddenly increase. To prevent the power supply voltage from suddenly dropping steeply at this time, a storage capacitor needs to be connected in parallel at the power supply pin;

[0060] The function of the LED lamp is to display the on-off state of the relay;

[0061] The function of the relay is to control the connection and disconnection between the pins of the isolation chip under test and the floating source of CTA8280F; control the connection and disconnection between the pins of the isolation chip under test and the time test board of CTA8280F.

[0062] The function of the SMA socket is to connect the signal sent by the CTA8280F analog test machine to the bottom board and then to the isolation chip under test through the daughter board; the signal sent by the isolation chip under test enters the bottom board through the daughter board and returns to the CTA8280F analog test machine through the SMA socket.

[0063] The function of the TPS module is a time waveform processing and calculation module, which can calculate the time difference between the input signal and the output signal, the time of the rising edge and falling edge of the signal, etc.;

[0064] The function of the pin header is to physically connect the resources of the test bottom board and the CTA8280F analog test machine;

[0065] The function of the European connector is to physically connect the test bottom board and the test daughter board;

[0066] The function of the high-speed comparator chip is to make the rising edge and falling edge of the signal sent by the CTA8280F analog test machine steeper, so that the measured time parameters are more accurate;

[0067] The function of the LDO chip is to convert the 15V voltage to 12V voltage to supply power to the TPS module;

[0068] An electronic device, comprising: one or more processors, a memory, and one or more computer programs, wherein the one or more computer programs are stored in the memory, and the one or more computer programs include instructions that, when executed by the electronic device, cause the one or more processors to execute the method proposed in this application.

[0069] From the description of the above embodiments, those skilled in the art can clearly understand that all or part of the steps in the above implementation methods can be implemented by means of software plus a necessary general hardware platform. Based on this understanding, the above computer program product may include, but is not limited to, an APP;

[0070] A computer-readable storage medium, on which a computer program is stored, and when the computer program is executed by a processor, the method proposed in this application is implemented.

[0071] In several embodiments provided by the present invention, if any function is implemented in the form of a software functional unit and sold or used as an independent product, it can be stored in a computer-readable storage medium. Based on this understanding, some technical solutions of the present invention, in essence, or the part that contributes to the prior art, or part of this technical solution, can be embodied in the form of the following software products.

[0072] Continuing from the previous text, the above device / terminal may be a computer device, and the hardware structure of this computer device may specifically further include: at least one processor, at least one communication interface, at least one memory, and at least one communication bus; the processor, communication interface, and memory can all complete communication with each other through the communication bus. Among them, the processor may be a central processing unit CPU, DSP, microcontroller, or digital signal processor, and may also include a GPU, an embedded neural network processor NPU, and an image signal processor ISP. The processor may also include a specific integrated circuit ASIC, or one or more integrated circuits configured to implement the embodiments of the present invention. In addition, the processor may have the function of operating one or more software programs, and the software programs may be stored in storage media such as the memory; and the aforementioned memory / storage medium may include: non-volatile memory, such as non-removable disks, USB flash drives, mobile hard disks, optical discs, etc., as well as read-only memory ROM, random access memory RAM, etc.

[0073] Those skilled in the art can realize that the various modules, units, and method steps described in the embodiments disclosed in this specification can be implemented by a combination of electronic hardware, computer software, and electronic hardware. Whether these functions are executed in a hardware or software manner depends on the specific application and design constraints of the technical solution. Those skilled in the art can use different methods to implement the described functions for each specific application, but such implementation should not be considered to exceed the scope of the present invention.

[0074] The above embodiments are only illustrative of the principles and effects of the present invention, and are not intended to limit the present invention. Any person familiar with this technology can modify or change the above embodiments without departing from the spirit and scope of the present invention. Therefore, all equivalent modifications or changes completed by those with ordinary knowledge in the technical field without departing from the spirit and technical idea disclosed by the present invention should still be covered by the claims of the present invention.

Claims

1. A universal testing method for an isolation chip, characterized in that: It includes a test sub-board, which connects the pins of the isolation chip to be tested to the test base board; The test base plate sets the maximum number of pins and the maximum number of isolation channels according to the pin distribution rules of the isolation chip, and the isolation channel direction is set to bidirectional; The upper part of the test baseboard is connected to the test sub-board, and the lower part is connected to the resource lead-out board of the CTA8280F simulation test machine; The processing terminal of the CTA8280F simulation test machine performs DC parameter and AC parameter tests on the isolation chip to be tested; the DC parameter and AC parameter test process includes performing non-isolated side test and isolated side test on the isolation chip to be tested through resource configuration on the CTA8280F simulation test machine, wherein: The non-isolated side test of the isolated chip to be tested is: DC parameter test: open the non-isolated DC channel relay, select the channel number and connect it to the floating source to test all DC parameters: close the non-isolated DC channel relay and disconnect it from the floating source; the DC parameters include power supply current IDD, input high level voltage threshold VIH, input low level voltage threshold VIL, output high level voltage value VOH, and output low level voltage value VOL; AC parameter test: turn on the AC channel relay on the non-isolated side, select the number of channels and connect it to the time test board, perform transmission delay and output waveform rise and fall tests, turn on the output state configuration relay on the non-isolated side channel, select the corresponding load state, and perform a transmission delay test from the enable signal to the output signal; the AC parameters include the maximum rate fMAX, transmission delay tPLH / tPHL, rising edge time tR, falling edge time tF, enable transmission time tPZH / tPZL, and disable transmission time tPHZ / tPLZ; The isolation side test of the isolation chip to be tested is: DC parameter test: open the DC channel relay on the isolation side, select the channel number and connect it to the floating source to test all DC parameters: close the DC channel relay on the isolation side and disconnect it from the floating source; the DC parameters include power supply current IDD, input high level voltage threshold VIH, input low level voltage threshold VIL, output high level voltage value VOH, and output low level voltage value VOL; AC parameter test: turn on the AC channel relay on the isolation side, select the number of channels and connect it to the time test board, perform transmission delay and output waveform rise and fall tests, turn on the output state configuration relay of the isolation side channel, select the corresponding load state, and perform a transmission delay test from the enable signal to the output signal; the AC parameters include the maximum rate fMAX, transmission delay tPLH / tPHL, rising edge time tR, falling edge time tF, enable transmission time tPZH / tPZL, and disable transmission time tPHZ / tPLZ; After the non-isolated side test and the isolated side test of the isolation chip to be tested are completed, all resources of the CTA8280F simulation test machine are powered off and disconnected from the pins of the isolation chip to be tested.

2. A universal testing method for an isolation chip as claimed in claim 1, characterized in that: When testing the transmission delay and the rise and fall of the output waveform, the input pin is the input signal and the output pin is the detection signal.

3. A universal testing method for an isolation chip as claimed in claim 1, characterized in that: When performing a transmission delay test from an enable signal to an output signal, the enable pin is the input signal and the output pin is the detection signal.

4. A universal testing method for an isolation chip as claimed in claim 1, characterized in that: The test sub-board is a first PCB substrate, comprising an upper surface and a lower surface relative to each other, wherein a test socket capable of fixing the isolation chip to be tested is arranged on the upper surface, and a European connector plug is arranged on the lower surface.

5. A universal testing method for an isolation chip as claimed in claim 1, characterized in that: The test base plate is a second PCB substrate, the upper surface of the second PCB substrate is provided with a socket matching the European connector plug on the lower surface of the first PCB substrate, a plurality of connection holes are provided on the second PCB substrate, and a pogo pin connector is provided on the lower surface of the second PCB substrate.

6. A universal testing method for an isolation chip as claimed in claim 1, characterized in that: The resource lead-out board is a third PCB substrate, a plurality of connection holes are arranged on the third PCB substrate, corresponding one-to-one with the connection holes on the second PCB substrate, and the third PCB substrate is detachably connected to the second PCB substrate via a connector; The third PCB substrate includes an upper surface and a lower surface relative to each other, the upper surface includes a pogo pin connection area matching the pogo pin connector on the second PCB substrate, and the lower surface is connected to the CTA8280F simulation test machine.

7. An electronic device, characterized in that: include: One or more processors, a memory, and one or more computer programs, wherein the one or more computer programs are stored in the memory, and the one or more computer programs include instructions, which, when executed by the electronic device, cause the one or more processors to perform the method described in any one of claims 1 to 6.

8. A computer-readable storage medium having a computer program stored thereon, characterized in that: When the computer program is executed by a processor, the method according to any one of claims 1 to 6 is implemented.

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