Generation method of active sonar hyperbolic frequency modulation signal
MATLAB calculates the instantaneous frequency of the HFM signal and caches the DDS frequency control word. The ROM of the FPGA realizes the addition operation frequency control, which solves the problem of high resource consumption when FPGA generates hyperbolic frequency tuned signals, and realizes efficient and accurate signal generation.
Patent Information
- Application Number
- CN202411712717.9
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2024-11-27
- Publication Date
- 2025-04-04
AI Technical Summary
In the field of water acoustic detection, FPGA chips are used to generate active sonar hyperbolic frequency tuned signals, and it is difficult to efficiently obtain high-precision instantaneous frequency and consume a large amount of computing resources.
The instantaneous frequency of the HFM signal is calculated by MATLAB, and its corresponding DDS frequency control word is cached into the ROM of the FPGA, and frequency control is realized using addition operations to avoid division operations.
It realizes the generation of hyperbolic frequency tuned signals with high precision on FPGA, saves computing resources, avoids complex division operations, and improves the efficiency of signal generation.
Smart Images
Figure CN119758311A_ABST
Abstract
Description
Technical Field
[0001] The invention belongs to the technical field of underwater acoustic detection, and in particular relates to a method for generating an active sonar hyperbolic frequency modulation signal. Background Art
[0002] In the field of underwater acoustic detection, active sonar signals are usually used to detect targets. Active sonar sends different active signals and receives target echoes to detect and track targets. Commonly used active sonar signals include single-frequency rectangular pulses (CW), linear frequency modulation signals (LFM), and hyperbolic frequency modulation signals (HFM). Among them, the HFM signal is a Doppler invariant signal, which has better detection performance in mobile communications than other signals.
[0003] In the digital age, with the continuous development of digital signal processing technology, digital modulation has been rapidly developed and applied in the signal transmission system in the field of underwater acoustic detection. Therefore, active sonar signal generation technology based on FPGA chips has been widely used. However, FPGA chips are digital signal processors, and obtaining high-precision division results requires a lot of resources. When generating HFM signals, obtaining instantaneous frequency requires continuous division operations, so a method that can obtain high-precision instantaneous frequency while saving a lot of resources is needed. Summary of the invention
[0004] In view of this, the present invention provides a method for generating an active sonar hyperbolic frequency modulation signal, which realizes the generation of an active sonar hyperbolic frequency modulation signal on an FPGA, can obtain a high-precision instantaneous frequency, and save a large amount of computing resources.
[0005] The technical solution of the present invention is:
[0006] A method for generating an active sonar hyperbolic frequency modulation signal is implemented based on FPGA and includes the following steps:
[0007] S101: Calculate the instantaneous frequency of the HFM signal using MATLAB;
[0008] S102: Calculate the DDS frequency control word in the FPGA corresponding to the instantaneous frequency using MATLAB;
[0009] S103: MATLAB saves the positions where two adjacent frequency control words change to 1;
[0010] S104: MATLAB writes the saved data into a file based on the format of the file that can be read by the ROM of the FPGA;
[0011] S105: At the starting moment of the preset pulse width, the frequency control word corresponding to the starting frequency of the HFM signal is input to the DDS; the FPGA reads the position recorded in the file data of the ROM, and each time the clock count reaches the recorded position, the frequency control word at the DDS input end is increased by 1, and the read address of the ROM is increased by 1 at the same time, until the clock count reaches the preset pulse width time.
[0012] Furthermore, the method for calculating the instantaneous frequency of the HFM signal using MATLAB specifically includes the following steps:
[0013] S101.1: Input the parameters of the HFM signal into the MATLAB tool, including pulse width T, starting frequency f L and the stop frequency f H ;
[0014] S101.2: Calculate the instantaneous frequency of the HFM signal, which is expressed as:
[0015]
[0016] Where f(t) is the instantaneous frequency of the HFM signal, The accuracy of t depends on the FPGA clock rate f clk , the discrete expression of t is:
[0017]
[0018] Further, the method for calculating the DDS frequency control word in the FPGA corresponding to the instantaneous frequency is specifically as follows:
[0019] Assuming the number of bits of the frequency control word is N, the frequency control word corresponding to the instantaneous frequency is expressed as:
[0020] C[n]=round(f(t[n]) / f clk ×2 N ),n=1,2,…,Tf clk
[0021] Where C[n] is the frequency control word corresponding to the instantaneous frequency, and round(*) is the rounding operation.
[0022] Furthermore, the S103 is specifically as follows:
[0023] Calculate the change value ΔC[n] between two adjacent frequency control words, and record n whenever ΔC[n]=C[n]-C[n-1]=1.
[0024] Furthermore, the S104 is specifically as follows: writing all the recorded n into a file based on the format of a file readable by the ROM of the FPGA.
[0025] Furthermore, the S105 is specifically as follows:
[0026] In FPGA, use IP core DDS to generate a sine wave signal; let the number of bits of the frequency control word be N, the pulse start time, and the DDS input end be the starting frequency f of the HFM signal L Corresponding frequency control word
[0027] After that, the ROM reads the recorded n in sequence. Every time the clock count reaches n, the frequency control word at the DDS input end is increased by 1, and the read address of the ROM is increased by 1 at the same time, until the clock count reaches the pulse width time.
[0028] Furthermore, in the FPGA, at the pulse start time, the DDS input terminal is the starting frequency f L The corresponding frequency control word C fL , ROM reads the recorded n in sequence. Whenever the clock count reaches mn, the frequency control word at the DDS input end is increased by 1, and the read address of ROM is increased by 1 at the same time, until the clock count reaches the pulse width time.
[0029] Furthermore, when the preset pulse width changes and is m times the original preset pulse width, where m is an integer, the FPGA still uses the file saved in the ROM by MATLAB to perform the frequency modulation operation. The specific method is:
[0030] The FPGA reads the recorded position in the file data of the ROM. Whenever the clock count reaches m times the recorded position, the frequency control word at the DDS input end is increased by 1, and the read address of the ROM is increased by 1 at the same time, until the clock count reaches the new preset pulse width time.
[0031] Beneficial effects of the present invention:
[0032] This can avoid the FPGA from using division operations when generating HFM signals, and only addition operations can be used to complete the task. At the same time, since the cache is the position where the control word is added by 1, the number of cached values is round((f H -f L ) / f clk ×2 N ), compared with directly caching the frequency control word of the instantaneous frequency, the storage resources are greatly reduced. BRIEF DESCRIPTION OF THE DRAWINGS
[0033] In order to more clearly illustrate the technical solutions of the embodiments of the present disclosure, the drawings required for use in the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present disclosure. For ordinary technicians in this field, other drawings can be obtained based on these drawings without creative work.
[0034] Figure 1 This is a flow chart of a method for generating active sonar hyperbolic frequency modulation signals based on FPGA. DETAILED DESCRIPTION
[0035] The embodiments of the present disclosure are described in detail below with reference to the accompanying drawings.
[0036] The following describes the embodiments of the present disclosure through specific examples, and those skilled in the art can easily understand other advantages and effects of the present disclosure from the contents disclosed in this specification. Obviously, the described embodiments are only a part of the embodiments of the present disclosure, rather than all of the embodiments. The present disclosure can also be implemented or applied through other different specific embodiments, and the details in this specification can also be modified or changed in various ways based on different viewpoints and applications without departing from the spirit of the present disclosure. It should be noted that the following embodiments and features in the embodiments can be combined with each other without conflict. Based on the embodiments in the present disclosure, all other embodiments obtained by ordinary technicians in the field without making creative work are within the scope of protection of the present disclosure.
[0037] It should be noted that various aspects of the embodiments within the scope of the appended claims are described below. It should be apparent that the aspects described herein can be embodied in a wide variety of forms, and any specific structure and / or function described herein is merely illustrative. Based on the present disclosure, it should be understood by those skilled in the art that an aspect described herein can be implemented independently of any other aspect, and two or more of these aspects can be combined in various ways. For example, any number of aspects described herein can be used to implement the device and / or practice the method. In addition, other structures and / or functionalities other than one or more of the aspects described herein can be used to implement this device and / or practice this method.
[0038] It should also be noted that the illustrations provided in the following embodiments are only schematic illustrations of the basic concept of the present disclosure. The illustrations only show components related to the present disclosure rather than being drawn according to the number, shape and size of components in actual implementation. In actual implementation, the type, quantity and proportion of each component may be changed arbitrarily, and the component layout may also be more complicated.
[0039] Additionally, in the following description, specific details are provided to facilitate a thorough understanding of the examples. However, it will be understood by those skilled in the art that the aspects described may be practiced without these specific details.
[0040] In one embodiment of the present invention, a method for generating an active sonar hyperbolic frequency modulation signal is proposed, which is implemented based on FPGA and includes the following steps:
[0041] S101: Calculate the instantaneous frequency of the HFM signal using MATLAB;
[0042] S102: Calculate the DDS frequency control word in the FPGA corresponding to the instantaneous frequency using MATLAB;
[0043] S103: MATLAB saves the positions where two adjacent frequency control words change to 1;
[0044] S104: MATLAB writes the saved data into a file based on the format of the file that can be read by the ROM of the FPGA;
[0045] S105: At the starting moment of the preset pulse width, the frequency control word corresponding to the starting frequency of the HFM signal is input to the DDS; the FPGA reads the position recorded in the file data of the ROM, and each time the clock count reaches the recorded position, the frequency control word at the DDS input end is increased by 1, and the read address of the ROM is increased by 1 at the same time, until the clock count reaches the preset pulse width time.
[0046] In this embodiment, the method for calculating the instantaneous frequency of the HFM signal using MATLAB specifically includes the following steps:
[0047] S101.1: Input the parameters of the HFM signal into the MATLAB tool, including pulse width T, starting frequency f L and the stop frequency f H ;
[0048] S101.2: Calculate the instantaneous frequency of the HFM signal, which is expressed as:
[0049]
[0050] Where f(t) is the instantaneous frequency of the HFM signal, The accuracy of t depends on the FPGA clock rate f clk , the discrete expression of t is:
[0051]
[0052] In this embodiment, the method for calculating the DDS frequency control word in the FPGA corresponding to the instantaneous frequency is specifically as follows:
[0053] Assuming the number of bits of the frequency control word is N, the frequency control word corresponding to the instantaneous frequency is expressed as:
[0054] C[n]=round(f(t[n]) / f clk ×2 N ),n=1,2,…,Tf clk
[0055] Where C[n] is the frequency control word corresponding to the instantaneous frequency, and round(*) is the rounding operation.
[0056] In this embodiment, the S103 is specifically:
[0057] Calculate the change value ΔC[n] between two adjacent frequency control words, and record n whenever ΔC[n]=C[n]-C[n-1]=1.
[0058] In this embodiment, S104 specifically includes: writing all recorded n into a file based on the format of a file readable by the ROM of the FPGA.
[0059] In this embodiment, the S105 is specifically:
[0060] In FPGA, use IP core DDS to generate a sine wave signal; let the number of bits of the frequency control word be N, the pulse start time, and the DDS input end be the starting frequency f of the HFM signal L Corresponding frequency control word
[0061] After that, the ROM reads the recorded n in sequence. Every time the clock count reaches n, the frequency control word at the DDS input end is increased by 1, and the read address of the ROM is increased by 1 at the same time, until the clock count reaches the pulse width time.
[0062] In this embodiment, in the FPGA, at the pulse start time, the DDS input terminal is the starting frequency f L The corresponding frequency control word C fL , ROM reads the recorded n in sequence. Whenever the clock count reaches mn, the frequency control word at the DDS input end is increased by 1, and the read address of ROM is increased by 1 at the same time, until the clock count reaches the pulse width time.
[0063] In this embodiment, when the preset pulse width changes and is m times the original preset pulse width, where m is an integer, the FPGA still uses the file saved in the ROM by MATLAB to perform the frequency modulation operation. The specific method is:
[0064] The FPGA reads the recorded position in the file data of the ROM. Whenever the clock count reaches m times the recorded position, the frequency control word at the DDS input end is increased by 1, and the read address of the ROM is increased by 1 at the same time, until the clock count reaches the new preset pulse width time.
[0065] This embodiment implements the calculation and storage of the frequency control word change parameters in MATLAB, and directly reads the parameters through ROM when FPGA generates HFM signals, which can avoid the FPGA from using complex division operations and complete signal generation using only addition operations.
[0066] This embodiment implements the calculation of the frequency control word change parameter in MATLAB, which is a floating-point operation. Compared with the integer operation of FPGA, it can effectively ensure the accuracy of parameter calculation.
[0067] The HFM signal generated in this embodiment has a frequency accuracy of f clk / 2 N , which is the optimal accuracy that can be achieved by a DDS with a bit number of N, and can ensure the accuracy of the signal.
[0068] The parameter saved in this embodiment is the position where the frequency control word changes, which greatly reduces storage resources compared to directly saving the frequency control word.
[0069] This embodiment can achieve the expansion of the same parameters to different pulse widths. Different pulse widths can achieve HFM signal generation by simply multiplying the parameters by coefficients.
[0070] The present invention is described in detail below by taking the actual parameters of the HFM signal generated by FPGA as an example.
[0071] The bandwidth of the HFM signal is 200Hz, and the starting frequency f L is 1325Hz, the end frequency f H is 1525Hz, the pulse width T is 0.1s; the clock frequency of FPGA is f clk The frequency control word number N of DDS is 28.
[0072] The signal of this embodiment is demodulated according to the above steps.
[0073] In this embodiment, step 1) specifically includes: inputting the parameters of the HFM signal in the matlab () tool, including the pulse width T=0.1, the starting frequency f L =1325 and the end frequency f H =1525;
[0074] This embodiment calculates the instantaneous frequency of the HFM signal according to the formula;
[0075] This embodiment calculates the frequency control word of the DDS corresponding to the instantaneous frequency according to the formula;
[0076] In this embodiment, the change values of two adjacent frequency control words are calculated, and n is recorded whenever ΔC[n]=C[n]-C[n-1]=1;
[0077] This embodiment writes all recorded n into a file that can be read by the ROM IP core in the FPGA; the file format written in the embodiment of the present invention is a dat file;
[0078] In this embodiment, in the FPGA, at the pulse start time, the DDS input terminal is the starting frequency fL The corresponding frequency control word C fL =14820, ROM reads the recorded n in sequence. Whenever the clock count reaches n, the frequency control word at the DDS input end is increased by 1, and the read address of ROM is increased by 1 at the same time, until the clock count reaches the pulse width time.
[0079] This embodiment can also use the same cache data to expand to different pulse widths. If the pulse width T is 0.1s*m, step 6) can specifically include: in the FPGA, at the pulse start time, the DDS input end is the starting frequency f L Corresponding frequency control word The ROM reads the recorded n in sequence. Whenever the clock count reaches mn, the frequency control word at the DDS input is increased by 1, and the read address of the ROM is increased by 1 at the same time, until the clock count reaches the pulse width time.
[0080] The above is only a specific implementation of the present disclosure, but the protection scope of the present disclosure is not limited thereto. Any changes or substitutions that can be easily thought of by a person skilled in the art within the technical scope disclosed in the present disclosure should be included in the protection scope of the present disclosure. Therefore, the protection scope of the present disclosure should be based on the protection scope of the claims.
Claims
1. A method for generating an active sonar hyperbolic frequency modulation signal, based on FPGA, characterized in that: The following steps are involved: S101: Calculate the instantaneous frequency of the HFM signal using MATLAB; S102: Calculate the DDS frequency control word in the FPGA corresponding to the instantaneous frequency using MATLAB; S103: MATLAB saves the positions where two adjacent frequency control words change to 1; S104: MATLAB writes the saved data into a file based on the format of the file that can be read by the ROM of the FPGA; S105: At the starting moment of the preset pulse width, the frequency control word corresponding to the starting frequency of the HFM signal is input to the DDS; the FPGA reads the position recorded in the file data of the ROM, and each time the clock count reaches the recorded position, the frequency control word at the DDS input end is increased by 1, and the read address of the ROM is increased by 1 at the same time, until the clock count reaches the preset pulse width time.
2. The method for generating an active sonar hyperbolic frequency modulation signal according to claim 1, characterized in that: The method of calculating the instantaneous frequency of the HFM signal using MATLAB specifically includes the following steps: S101.1: Input the parameters of the HFM signal into the MATLAB tool, including pulse width T, starting frequency f L and the stop frequency f H ; S101.2: Calculate the instantaneous frequency of the HFM signal, which is expressed as: Where f(t) is the instantaneous frequency of the HFM signal, The accuracy of t depends on the FPGA clock rate f clk , the discrete expression of t is:
3. The method for generating an active sonar hyperbolic frequency modulation signal according to claim 2, characterized in that: The method for calculating the DDS frequency control word in the FPGA corresponding to the instantaneous frequency is as follows: Assuming the number of bits of the frequency control word is N, the frequency control word corresponding to the instantaneous frequency is expressed as: C[n]=round(f(t[n]) / fclk×2 N ),n=1,2,…,Tfclk Where C[n] is the frequency control word corresponding to the instantaneous frequency, and round(*) is the rounding operation.
4. The method for generating an active sonar hyperbolic frequency modulation signal according to claim 3, characterized in that: The S103 is specifically: Calculate the change value ΔC[n] between two adjacent frequency control words, and record n whenever ΔC[n]=C[n]-C[n-1]=1.
5. The method for generating an active sonar hyperbolic frequency modulation signal according to claim 4, characterized in that: The S104 is specifically as follows: all the recorded n are written into a file based on the format of a file readable by the ROM of the FPGA.
6. The method for generating an active sonar hyperbolic frequency modulation signal according to claim 5, characterized in that: The S105 is specifically as follows: In FPGA, use IP core DDS to generate a sine wave signal; let the number of bits of the frequency control word be N, the pulse start time, and the DDS input end be the starting frequency f of the HFM signal L Corresponding frequency control word After that, the ROM reads the recorded n in sequence. Every time the clock count reaches n, the frequency control word at the DDS input end is increased by 1, and the read address of the ROM is increased by 1 at the same time, until the clock count reaches the pulse width time.
7. The method for generating an active sonar hyperbolic frequency modulation signal according to claim 6, characterized in that: In FPGA, at the pulse start time, the DDS input terminal is the starting frequency f L The corresponding frequency control word C fL， The ROM reads the recorded n in sequence. Whenever the clock count reaches mn, the frequency control word at the DDS input is increased by 1, and the read address of the ROM is increased by 1 at the same time, until the clock count reaches the pulse width time.
8. The method for generating an active sonar hyperbolic frequency modulation signal according to claim 7, characterized in that: When the preset pulse width changes and is m times the original preset pulse width, where m is an integer, the FPGA still uses the file saved in ROM by MATLAB to perform the frequency modulation operation. The specific method is: The FPGA reads the recorded position in the file data of the ROM. Whenever the clock count reaches m times the recorded position, the frequency control word at the DDS input end is increased by 1, and the read address of the ROM is increased by 1 at the same time, until the clock count reaches the new preset pulse width time.