Single power rail over-current protection circuit, LDO chip and over-current protection method
By connecting the drains of the sampling transistor and the power transistor to the LDO input and using a clamping module to clamp the source, the problem of needing an additional power rail in traditional LDO chips is solved, achieving single power rail power supply, simplifying the circuit structure and expanding the application range.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Patents(China)
- Current Assignee / Owner
- ZHEJIANG HANGXINYUAN INTEGRATED CIRCUIT TECH CO LTD
- Filing Date
- 2024-12-27
- Publication Date
- 2026-07-24
Smart Images
Figure CN119759173B_ABST
Abstract
Description
Technical Field
[0001] This invention relates to the field of overcurrent protection technology, and in particular to a single-power-rail overcurrent protection circuit, an LDO chip, and an overcurrent protection method. Background Technology
[0002] In the use of LDO linear regulator chips, the current limiting circuit typically clamps the first-stage mirror circuit to accurately sample the load current. Since the voltage difference between the gate and source of a MOSFET has a greater impact on the current than the drain-source voltage, the power transistor and the sampling transistor are usually connected to their sources to ensure the gate-source voltages are the same, thus clamping the drain voltage. However, this approach has significant limitations. When the power transistor is an NMOS transistor, both the power transistor and the sampling transistor's sources are connected to the LDO output voltage. The drain voltage of the sampling transistor needs to be clamped to the LDO input voltage. Therefore, to ensure the clamping module functions correctly, its supply voltage must be higher than the LDO input voltage VIN. This requires an additional power rail to power the clamping module, increasing the complexity of the peripheral circuitry and limiting its application range.
[0003] Therefore, there is an urgent need for a single-power-rail overcurrent protection circuit. Summary of the Invention
[0004] To address the issue that traditional LDO chip current limiting circuits require clamping the sampling tube drain voltage to the LDO input voltage, and that the clamping module's power supply voltage needs to be higher than the LDO input voltage to ensure proper operation, thus necessitating the addition of an extra power rail around the chip, this invention provides a single power rail overcurrent protection circuit, an LDO chip, and an overcurrent protection method.
[0005] In a first aspect, embodiments of the present invention provide a single-rail overcurrent protection circuit applied to an LDO chip. The overcurrent protection circuit includes at least: a first-stage mirror module that uses a sampling transistor to mirror the load current flowing through the power transistor; the first-stage mirror module includes a power transistor, a sampling transistor, and a clamping module.
[0006] The gates of the sampling transistor and the power transistor are shorted and connected to the output of the error amplifier inside the LDO chip.
[0007] The sources of the sampling transistor and the power transistor are respectively connected to the two input terminals of the clamping module for clamping, so that the source voltage of the sampling transistor is equal to the output voltage of the LDO; wherein, the source of the power transistor is connected to the output terminal of the LDO;
[0008] The drains of both the sampling transistor and the power transistor are connected to the LDO input terminal. The load current flows through the power transistor. Since the source voltage of the sampling transistor and the output voltage of the LDO are both less than the input voltage of the LDO, the clamping module is powered by the input voltage of the LDO.
[0009] Secondly, embodiments of the present invention also provide an LDO chip, comprising: a reference source, an error amplifier, a power transistor, and an overcurrent protection circuit as described in any embodiment of this specification; a feedback network and a load are connected to the output terminal of the LDO;
[0010] The non-inverting input of the error amplifier is connected to the reference voltage output of the reference source, the inverting input is connected to the feedback network, and the output of the error amplifier is connected to the overcurrent protection circuit and the gate of the power transistor, respectively.
[0011] The source of the power transistor is connected to the output of the LDO, and the drain is connected to the input of the LDO.
[0012] The other end of the overcurrent protection circuit is connected to the LDO input.
[0013] Thirdly, embodiments of the present invention also provide an overcurrent protection method based on the overcurrent protection circuit described in any embodiment of this specification, the method comprising:
[0014] Connect the drains of both the sampling transistor and the power transistor to the LDO input.
[0015] A clamping module is used to clamp the sources of the sampling transistor and the power transistor so that the source voltage of the sampling transistor is equal to the output voltage of the LDO. Since both the source voltage of the sampling transistor and the output voltage of the LDO are less than the input voltage of the LDO, the LDO input voltage is used to power the clamping module. The source of the power transistor is connected to the output terminal of the LDO.
[0016] The load current of the power transistor is precisely mirrored using the sampling tube and the clamping module.
[0017] This invention provides a single-power-rail overcurrent protection circuit, an LDO chip, and an overcurrent protection method. The drain terminals of the sampling transistor and the power transistor are connected to the LDO input voltage. A clamping module clamps the sources of the sampling transistor and the power transistor. Since the power transistor's source terminal is connected to the LDO output voltage, the voltage at the sampling transistor's source terminal equals the LDO output voltage. Therefore, the LDO output voltage is less than the LDO input voltage, and the clamping module can directly utilize the LDO input voltage for power supply without the need for an additional power rail. Thus, this solution provides single-power-rail power supply, which not only reduces the complexity of the chip's peripheral application circuitry but also expands the application range of the LDO chip. Attached Figure Description
[0018] To more clearly illustrate the technical solutions in the embodiments of the present invention or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.
[0019] Figure 1 This is a circuit diagram of a single power rail overcurrent protection circuit provided in an embodiment of the present invention;
[0020] Figure 2 This is a transient simulation diagram of single-power-rail adaptive overcurrent protection provided in an embodiment of the present invention;
[0021] Figure 3 This is an overall architecture diagram of an LDO chip provided in an embodiment of the present invention;
[0022] Figure 4 This is a flowchart of an overcurrent protection method provided in an embodiment of the present invention;
[0023] Among them, M SENSE -Sampling tube; M POWER - Power transistor; 10 - Secondary mirror module; 20 - Tertiary mirror module. Detailed Implementation
[0024] To make the objectives, technical solutions, and advantages of the embodiments of the present invention clearer, the technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are some embodiments of the present invention, but not all embodiments. All other embodiments obtained by those skilled in the art based on the embodiments of the present invention without creative effort are within the scope of protection of the present invention.
[0025] The following describes the specific implementation of the above concept.
[0026] Please refer to Figure 1 This invention provides a single-rail overcurrent protection circuit for LDO chips. The circuit includes at least: a sampling tube M... SENSE For the power transistor M POWER Load current I LOAD A primary mirror module for mirror sampling; the primary mirror module includes a power transistor, a sampling transistor, and a clamping module;
[0027] The gates of the sampling transistor and the power transistor are shorted and then connected to the output of the internal error amplifier of the LDO;
[0028] The sources of the sampling transistor and the power transistor are connected to the two input terminals of the clamping module for clamping, so that the source voltage of the sampling transistor is equal to the output voltage of the LDO; the source of the power transistor is connected to the output terminal of the LDO.
[0029] The drains of both the sampling transistor and the power transistor are connected to the LDO input. Since the source voltage of the sampling transistor and the output voltage of the LDO are both less than the input voltage of the LDO, the LDO input voltage is used to power the clamping module.
[0030] In this embodiment of the invention, the drain terminals of the sampling transistor and the power transistor are connected to the LDO input voltage. A clamping module clamps the sources of the sampling transistor and the power transistor. Since the power transistor's source terminal is connected to the LDO output voltage, the voltage at the sampling transistor's source terminal equals the LDO output voltage. Therefore, the LDO output voltage is less than the LDO input voltage, and the clamping module can directly utilize the LDO input voltage for power supply without needing an additional power rail. Thus, this solution provides single-power-rail power supply, reducing the complexity of the chip's peripheral application circuitry and expanding the application range of the LDO chip.
[0031] It should be noted that there are multiple implementations of the clamping module; the one listed in this embodiment is... Figure 1 Clamping is achieved using a clamping operational amplifier. The implementation methods of the remaining clamping modules are also within the scope of protection required by this solution.
[0032] The following is based on Figure 1 The circuit diagram shown is used for illustration.
[0033] In some embodiments, reference may be made to Figure 1 The single-rail overcurrent protection circuit also includes: a secondary mirror module, a tertiary mirror module, and a switching transistor M0;
[0034] The secondary mirror module is connected between the primary mirror module and the tertiary mirror module. The secondary mirror module is used to map the sampled current of the primary mirror module to the tertiary mirror module.
[0035] The third-level mirror module is connected between the second-level mirror module and the switching transistor M0. The switching transistor M0 is connected to the first-level mirror module. The third-level mirror module is used to form a current mirror to reduce the mapped current of the second-level mirror module proportionally and output a target current to reflect the magnitude of the load current. The target current is compared with the reference current connected to the gate of the switching transistor M0 to control the operating state of the switching transistor M0, and thus control the operating state of the power transistor.
[0036] In this embodiment, reference can be made to Figure 1 , Figure 1The sampled current is reduced twice, first by the secondary mirror module 10 and then by the tertiary mirror module 20. By proportionally reducing the sampled current, circuit power consumption is minimized, resulting in a target current that is compared with the reference current. The target current reflects the magnitude of the actual load current, and its comparison with the reference current determines the operating state of the switching transistor M0, thereby controlling the power transistor M0. POWER Gate voltage control.
[0037] In this embodiment of the invention, when the load current is less than the current limiting point, the sampled current is reduced to less than the reference current after passing through the secondary mirror module and the tertiary mirror module. The gate of the switching transistor M0 is at a low voltage, so the switching transistor M0 is in the off state and the overcurrent protection circuit does not work.
[0038] When the load current exceeds the current limiting point, the sampled current is reduced by the secondary and tertiary mirror modules and is greater than the reference current. The gate of the switching transistor M0 is at a high voltage, which makes the switching transistor M0 conduct. At the same time, the gate of the power transistor is pulled low, the overcurrent protection circuit starts to work, and the LDO enters the current limiting state.
[0039] In this embodiment, sampling tube M is used. SENSE The load current is sampled and proportionally reduced using three mirror modules. The load current is compared with the reference current to determine whether it exceeds the current limit set by the LDO. If it does not exceed the limit, the overcurrent protection circuit does not work; if it does exceed the limit, the gate potential of the power transistor is pulled low, and the circuit enters the current limiting state.
[0040] However, during the use of LDO linear regulator chips, occasional erroneous operations such as directly shorting the output to ground or excessive load leading to current-limiting state may occur. In this situation, the voltage difference across the chip's power transistor is very large, approximately equal to the input voltage. Traditional overcurrent protection circuits do not adaptively change the power transistor's current-limiting point; it is set above the maximum load current. Therefore, even if the load current is limited to the current-limiting point, significant power consumption will still occur, and the resulting heat can burn out the chip, leading to permanent failure. Such erroneous operations not only pose a danger during chip use but also increase the additional cost of chip applications, resulting in economic losses.
[0041] Therefore, in this embodiment of the invention, when the LDO output terminal is hard short-circuited or overloaded, the LDO output voltage VOUT is pulled low, the secondary mirror module 10 generates an over-mirror, triggering the LDO current limiting point adaptive adjustment mechanism to reduce the current limiting point.
[0042] This embodiment enables the secondary mirror module 10 to generate an over-mirror when the LDO output is hard short-circuited or overloaded. This can adaptively and significantly reduce the current limiting point, alleviate the heat generation of the chip under large voltage difference, reduce the risk of damage, and improve the safety of chip application.
[0043] In some implementations, the secondary mirror module 10 contains two MOSFETs. When the LDO output is hard short-circuited or overloaded, the two MOSFETs in the secondary mirror module operate in different states, one in the linear region and the other in the saturation region, resulting in over-mirroring.
[0044] When the chip output is hard short-circuited to ground, the two MOSFETs in the internal secondary mirror module 10 operate in different states. One enters the linear region due to insufficient voltage margin, while the other operates in the saturation region. This difference leads to a larger mirror ratio, resulting in over-mirroring. With the reference current remaining constant, the power transistor M... POWER A smaller load current will trigger overcurrent protection, meaning the lower the output voltage, the higher the overcurrent protection ratio. The current limiting point decreases as the output voltage VOUT decreases. Ultimately, this achieves a hard short circuit by limiting the power transistor M... POWER The current flowing through is limited to a small value, which alleviates the heat generation of the chip under large voltage differences and protects the chip.
[0045] In the embodiments of the present invention, reference continues to be made. Figure 1 The secondary mirror module 10 includes: MOSFET M3 and MOSFET M4;
[0046] The gates of transistors M3 and M4 are connected to the output of the clamping module. The drain of transistor M3 is connected to the source of the sampling transistor, and the source of transistor M3 is grounded.
[0047] The drain of the M4 transistor is connected to the three-stage mirror module, and the source of the M4 transistor is grounded.
[0048] In this embodiment, the precise sampling current flows through transistor M3. Transistor M4 has the same gate-source voltage as transistor M3. The sampling current is mapped to the branches where transistors M4 and M1 are located and flows into the three-stage mirror module 20.
[0049] In some implementations, when the LDO output is hard short-circuited or overloaded, the source voltage of the sampling transistor follows the LDO output voltage to an extremely low level, and the drain voltage of the M3 transistor is extremely low. This results in the drain-source voltage difference of the M3 transistor being less than the difference between the gate-source voltage difference of the M3 transistor and the threshold voltage of the M3 transistor, causing the M3 transistor to be in a non-saturated state and operate in the linear region. At the same time, the drain-source voltage difference of the M4 transistor is greater than the difference between the gate-source voltage difference of the M4 transistor and the threshold voltage of the M4 transistor, causing the M4 transistor to operate in the saturation region.
[0050] In this embodiment, from Figure 1As shown in the circuit schematic, as long as the LDO input voltage VIN is normally supplied, the clamping module can work normally regardless of the output voltage VOUT. The source voltage VSENSE of the sampling transistor follows the output voltage VOUT. The source voltage VSENSE of the sampling transistor affects the operating state of the M3 transistor. When the output is hard short-circuited, the VSENSE voltage is very low, that is, the drain voltage of the M3 transistor is very low, which makes the drain-source voltage difference of the M3 transistor less than the difference between the gate-source voltage difference of the M3 transistor and the threshold voltage of the M3 transistor, that is, VDS3 < VGS3 - VTH3. The M3 transistor is in a non-saturated state and operates in the linear region or even the deep linear region.
[0051] At this time, the drain voltage of transistor M4 is VIN-VSG1. Correspondingly, the drain-source voltage difference of transistor M4 is greater than the difference between the gate-source voltage difference of transistor M4 and the threshold voltage of transistor M4, that is, VDS4>VGS4-VTH4, and transistor M4 is operating in the saturation region.
[0052] According to the drain current formula of a MOSFET in the saturation region: ID = μCoxW / L(VGS - VTH) 2 / 2 and the drain current formula for the linear region MOSFET: ID=μCoxW / L[(VGS-VTH)VDS-VDS] 2 / 2], where μ is the electron mobility, Cox is the gate oxide capacitance per unit area, and W / L is the aspect ratio.
[0053] As shown in the above equation, under the same gate-source voltage conditions, the leakage current of the MOSFET in the saturation region is greater than that in the linear region. Therefore, M4 over-mirrors the secondary image of M3. That is, when the width-to-length ratios of the two MOSFETs are the same, the current of M4 will be larger than that of M3. Consequently, the target current output by M2, compared with the reference current, will also be larger, ultimately resulting in a lower load current I. LOAD Overcurrent protection can be triggered immediately upon a hard short circuit, reducing the load current I during a hard short circuit. LOAD The lower the hard short-circuit resistance, the greater the I of the hard short-circuit current limiting clamp. LOAD The lower the current, the more adaptively the current limiting point is lowered.
[0054] In the embodiments of the present invention, reference continues to be made. Figure 1 The three-level mirror module 20 includes: MOSFET M1 and MOSFET M2;
[0055] The gates of transistors M1 and M2 are connected. The drain of transistor M1 is connected to the gate connection line of transistors M1 and M2 and the drain of transistor M4. The source of transistor M1 is connected to the input terminal of LDO.
[0056] The drain of transistor M2 is connected to the gate of switching transistor M0 and the reference current terminal, respectively, and the source of transistor M2 is connected to the input terminal of LDO.
[0057] In this embodiment, the current mirror composed of M1 and M2 scales down the mapped current of the secondary mirror module to minimize circuit power consumption, thus obtaining the target current for comparison with the reference current. It can be seen that transistors M1 and M2 in the tertiary mirror circuit can also operate directly powered by the LDO input voltage VIN, avoiding the introduction of an additional power rail.
[0058] Finally, transient simulation was performed on the single-rail overcurrent protection circuit proposed in this scheme to verify the adaptive adjustment capability of the current limiting point to changes in output voltage. The simulation results are as follows: Figure 2 As shown in the diagram. The simulation takes the LDO's normal output voltage of 1V as an example. The first 4ms represent the chip's normal output under zero-load conditions. Subsequently, the load current increases linearly at a slope of 2A / ms. When the load current reaches 7.6A, overcurrent protection is triggered, the output voltage is pulled down, and the power transistor current IPOWER is limited to no longer increase with the load. After the load current decreases, the overcurrent protection is released, and the chip is allowed to operate stably under a 4A load for a period of time. At 15ms, the NMOS transistor connected in series between the LDO output and ground is instantaneously turned on to simulate the chip being hard short-circuited. At the moment of short circuit, the LDO output voltage drops to zero, and the sampling voltage is also almost zero. The power transistor current surges to 22A and is then limited to around 1.13A, which is much lower than the conventional current limit of 7.6A. The adaptive overcurrent protection circuit has achieved the expected protection function, dynamically controlling the power consumption on the power transistor, greatly reducing the power consumption of the chip during hard short circuit, and improving the reliability of the chip application.
[0059] like Figure 3 As shown, this embodiment also provides an LDO chip, including: a reference source, an error amplifier, a power transistor, and an overcurrent protection circuit as described in any embodiment of the specification; a feedback network and a load are connected to the LDO output terminal;
[0060] The non-inverting input of the error amplifier is connected to the reference voltage output of the reference source, the inverting input is connected to the feedback network, and the output of the error amplifier is connected to the overcurrent protection circuit and the gate of the power transistor, respectively.
[0061] The source of the power transistor is connected to the output of the LDO, and the drain is connected to the input of the LDO.
[0062] The other end of the overcurrent protection circuit is connected to the LDO input.
[0063] It should be noted that the above LDO chip embodiment and the overcurrent protection circuit embodiment belong to the same concept. The specific implementation process is detailed in the overcurrent protection circuit embodiment, and will not be repeated here.
[0064] like Figure 4 As shown, this embodiment also provides an overcurrent protection method based on the overcurrent protection circuit of this specification, the method including:
[0065] Step 400: Connect the drains of both the sampling transistor and the power transistor to the LDO input terminal;
[0066] Step 402: Clamp the sources of the sampling transistor and the power transistor using the clamping module to make the source voltage of the sampling transistor equal to the output voltage of the LDO. Since both the source voltage of the sampling transistor and the output voltage of the LDO are less than the input voltage of the LDO, the LDO input voltage is used to power the clamping module. The source of the power transistor is connected to the output of the LDO.
[0067] Step 404: Use the sampling tube and clamping module to perform precise mirror sampling of the load current of the power tube.
[0068] It should be noted that the above method embodiments and the overcurrent protection circuit embodiments belong to the same concept, and their specific implementation process is detailed in the overcurrent protection circuit embodiments, which will not be repeated here.
[0069] It should be noted that, in this document, relational terms such as "first" and "second" are used only to distinguish one entity or operation from another, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Furthermore, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or apparatus. Without further limitations, an element defined by the phrase "comprising one..." does not exclude the presence of other identical elements in the process, method, article, or apparatus that includes said element.
[0070] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention, and not to limit them; although the present invention has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some of the technical features; and these modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the spirit and scope of the technical solutions of the embodiments of the present invention.
Claims
1. A single-power-rail overcurrent protection circuit, characterized in that, For LDO chips, the overcurrent protection circuit includes at least: a first-stage mirror module that uses a sampling transistor to mirror the load current flowing into the power transistor; the first-stage mirror module includes the power transistor, the sampling transistor, and a clamping module; The gates of the sampling transistor and the power transistor are shorted and connected to the output of the error amplifier inside the LDO chip. The sources of the sampling transistor and the power transistor are respectively connected to the two input terminals of the clamping module for clamping, so that the source voltage of the sampling transistor is equal to the output voltage of the LDO; wherein, the source of the power transistor is connected to the output terminal of the LDO; The drains of both the sampling transistor and the power transistor are connected to the LDO input terminal. The load current flows through the power transistor. Since the source voltage of the sampling transistor and the output voltage of the LDO are both less than the input voltage of the LDO, the clamping module is powered by the input voltage of the LDO. It also includes: a secondary mirror module, a tertiary mirror module, and a switching transistor M0; The secondary mirror module is connected between the primary mirror module and the tertiary mirror module, and the secondary mirror module is used to map the sampling current of the primary mirror module to the tertiary mirror module; The third-level mirror module is connected between the second-level mirror module and the switching transistor M0. The switching transistor M0 is connected to the first-level mirror module. The third-level mirror module is used to form a current mirror to reduce the mapped current of the second-level mirror module proportionally and output a target current to reflect the magnitude of the load current. The target current is compared with the reference current connected to the gate of the switching transistor M0 to control the operating state of the switching transistor M0, thereby controlling the operating state of the power transistor. When the LDO output terminal is hard short-circuited or overloaded, the LDO output voltage is pulled low, the secondary mirror module generates an over-mirror, triggering the adaptive adjustment mechanism of the power transistor current limit point to reduce the current limit point; The secondary mirror module contains two MOSFETs. When the LDO output is hard short-circuited or overloaded, the two MOSFETs in the secondary mirror module operate in different states, one in the linear region and the other in the saturation region, resulting in over-mirroring. The secondary mirror module includes: MOS transistor M3 and MOS transistor M4; The gates of transistors M3 and M4 are connected to the output of the clamping module. The drain of transistor M3 is connected to the source of the sampling transistor, and the source of transistor M3 is grounded. The drain of the M4 transistor is connected to the three-stage mirror module, and the source of the M4 transistor is grounded. When the LDO output is hard short-circuited or overloaded, the source voltage of the sampling transistor follows the LDO output voltage to an extremely low level, and the drain voltage of transistor M3 is extremely low. This results in the drain-source voltage difference of transistor M3 being less than the difference between the gate-source voltage difference and the threshold voltage of transistor M3, causing transistor M3 to be in a non-saturated state and operating in the linear region. Simultaneously, the drain-source voltage difference of transistor M4 is greater than the difference between the gate-source voltage difference and the threshold voltage of transistor M4, causing transistor M4 to operate in the saturation region. The operating state of transistor M3 automatically switches between the non-saturated and saturated regions based on the output voltage VOUT value. When the LDO output is hard short-circuited or overloaded, the following applies: When the LDO input voltage VIN is normally supplied, the drain-source voltage difference of transistor M3 is less than the difference between the gate-source voltage difference and the threshold voltage of transistor M3, i.e., VDS3 < VGS3 - VTH3. Transistor M3 is in a non-saturated state, operating in the linear region or even the deep linear region. At this time, the drain voltage of transistor M4 is VIN - VSG1. Correspondingly, the drain-source voltage difference of transistor M4 is greater than the difference between the gate-source voltage difference and the threshold voltage of transistor M4, i.e., VDS4 > VGS4 - VTH4. Transistor M4 is operating in the saturation region. Based on the drain current formula for a saturated MOSFET: ID = μCoxW / L(VGS - VTH). 2 / 2 and the drain current formula for the linear region MOSFET: ID = μCoxW / L[(VGS-VTH)VDS-VDS] 2 / 2], where μ is the electron mobility, Cox is the gate oxide capacitance per unit area, and W / L is the width-to-length ratio; Under the same gate-source voltage conditions, the leakage current of the MOS transistor in the saturation region is greater than that in the linear region. Therefore, M4 over-mirrors the secondary image of M3, that is, under the condition that the width-to-length ratios of the two MOS transistors are the same, the current of M4 will be larger than that of M3, and thus the target current output by M2 compared with the reference current will also be larger. The lower the hard short-circuit resistance, the better the hard short-circuit current limiting clamping. The lower the current, the lower the load current. Overcurrent protection can be triggered immediately upon lowering the current limiting point, thus reducing the load current during a hard short circuit. Electric current.
2. The overcurrent protection circuit according to claim 1, characterized in that, When the load current is less than the current limiting point, the sampled current is reduced to less than the reference current after being reduced by the secondary mirror module and the tertiary mirror module. The gate of the switching transistor M0 is at a low voltage, so that the switching transistor M0 is in the off state and the overcurrent protection circuit does not work. When the load current exceeds the current limiting point, the sampled current, after being reduced by the secondary mirror module and the tertiary mirror module, is greater than the reference current. The gate of the switching transistor M0 is at a high voltage, making the switching transistor M0 in the conducting state. At the same time, the gate of the power transistor is pulled low, the overcurrent protection circuit starts to work, and the LDO enters the current limiting state.
3. The overcurrent protection circuit according to claim 1, characterized in that, The three-level mirror module includes: MOS transistor M1 and MOS transistor M2; The gates of transistors M1 and M2 are connected, the drain of transistor M1 is connected to the gate connection line of transistors M1 and M2 and the drain of transistor M4, and the source of transistor M1 is connected to the input terminal of the LDO. The drain of transistor M2 is connected to the gate and the reference current terminal of the switching transistor M0, respectively, and the source of transistor M2 is connected to the input terminal of the LDO.
4. An LDO chip, characterized in that, include: A reference source, an error amplifier, a power transistor, and an overcurrent protection circuit as described in any one of claims 1-3; The LDO output is connected to a feedback network and a load. The non-inverting input of the error amplifier is connected to the reference voltage output of the reference source, the inverting input is connected to the feedback network, and the output of the error amplifier is connected to the overcurrent protection circuit and the gate of the power transistor, respectively. The source of the power transistor is connected to the output of the LDO, and the drain is connected to the input of the LDO. The other end of the overcurrent protection circuit is connected to the LDO input.
5. An overcurrent protection method based on the overcurrent protection circuit according to any one of claims 1-3, characterized in that, The methods include: Connect the drains of both the sampling transistor and the power transistor to the LDO input. A clamping module is used to clamp the sources of the sampling transistor and the power transistor so that the source voltage of the sampling transistor is equal to the output voltage of the LDO. Since both the source voltage of the sampling transistor and the output voltage of the LDO are less than the input voltage of the LDO, the LDO input voltage is used to power the clamping module. The source of the power transistor is connected to the output terminal of the LDO. The load current of the power transistor is precisely mirrored using the sampling tube and the clamping module.