Energy storage control method and energy storage control system

Abstract

The invention relates to an energy storage control method and system, and the method comprises the steps: carrying out the data information transmission between CPUs in dual-core DSP chips through an inter-process communication IPC, and carrying out the data information transmission between the two dual-core DSP chips through an FPGA shared space; each dual-core DSP chip is connected with the FPGA chip, each CPU is provided with a respective CLA coprocessor, the two CPUs operate independently, and the FPGA chip is connected with the peripheral expansion unit through a port. The method has the advantages that each CPU is provided with the respective CLA coprocessor, so that the operation process of the control system is accelerated, the execution efficiency of the CPU is improved, and the response speed and accuracy of the control system are ensured; the FPGA chip is introduced, so that the capability of data interaction between the main controller and the peripheral expansion unit is enhanced, and the data reading time and the control information issuing time are shortened; in order to achieve efficient data interaction between the two DSP chips, fast and reliable data transmission is achieved through an FPGA shared space, and each dual-core DSP chip is connected with the FPGA chip.

Description

Technical Field

[0001] The present invention relates to the technical field of power electronic energy storage, and in particular to an energy storage control method and an energy storage control system. Background Art

[0002] With the continuous improvement of energy storage battery capacity and the increasingly improved functions of battery management systems (BMS) and energy management systems (EMS), high-power energy storage applications have been widely promoted. Compared with low-voltage energy storage systems, high-voltage direct-mounted (cascade) energy storage products are showing broad application prospects in large-capacity thermal storage frequency regulation, new energy distribution storage, and grid side due to their significant advantages such as low cost, high safety, high conversion efficiency, and compact footprint.

[0003] High-voltage direct-mounted energy storage products do not require auxiliary equipment such as step-up transformers and DC combiner cabinets, and use more optimized and lower-cost liquid cooling systems and energy storage converters (PCS), which not only reduce the cost of energy storage system products, but also improve the efficiency of charge and discharge cycles, thereby effectively reducing the investment cost of energy storage projects. This type of energy storage product uses a cascaded energy storage converter (PCS) and does not require a grid-connected transformer. It can be directly operated in a power system with a voltage level of 3kV and above through a grid-connected reactor, which brings a new development path for energy storage technology and is particularly suitable for building large-capacity megawatt-level energy storage systems.

[0004] High-voltage direct-mounted energy storage products are composed of energy storage units consisting of battery clusters and PCS converter units. The PCS converter unit adopts the classic H-bridge series connection method to achieve high voltage output through amplitude and phase control. The DC voltage output by each battery cluster passes through the bidirectional converter unit PCS to achieve bidirectional energy flow, converting DC power into several hundred volts of AC output. Multiple single-phase PCSs with the same structure are connected in series on the AC side to form a single-phase high-voltage energy storage product, which is further combined into a three-phase symmetrical high-voltage AC power that matches the grid voltage, thereby supporting the grid power and having multiple functions such as frequency and voltage regulation, peak shaving and valley filling.

[0005] However, with the increasing control requirements of high-voltage and large-capacity energy storage systems, traditional control systems based on single-chip single-core DSP and FPGA face challenges. With the increase in the number of power units and battery clusters, this type of control system needs to add multiple sub-control systems to meet the requirements of data processing timeliness and algorithm execution cycle, which increases the complexity of system coordination control. Therefore, in order to meet the control requirements of large-capacity high-voltage direct-mounted energy storage systems, higher requirements are placed on the control system's data processing timeliness and algorithm execution cycle. The ideal control system should be able to process information from no less than 150 PCS power units and battery clusters at the same time, and ensure that the execution cycle of the algorithm program is within 50 microseconds to ensure stable operation and efficient performance of the system.

[0006] At present, most control systems use a single-chip single-core DSP and FPGA control core architecture. This type of architecture requires a multi-level sub-controller to form a complete control system in a high-voltage direct-mounted energy storage system. This architecture has the following defects:

[0007] 1. It is necessary to use multi-level sub-controllers. The coordination between the controllers is relatively complicated. At the same time, the number of failure points of the control system increases, and maintenance is cumbersome.

[0008] 2. High cost. Each phase requires a sub-controller and a main controller. The number of boards and the number of chips required increase.

[0009] 3. The algorithm execution efficiency is reduced. After the main controller executes the algorithm, it needs to be passed to the sub-controller, and then passed to each unit by the sub-controller. Adding a sub-controller link in the middle will cause a certain lag in the control algorithm.

[0010] 4. The high-voltage direct-mounted energy storage system requires a large number of external ports, mainly including BMS, EMS, air conditioning, water cooling system, fire protection, switch cabinet status, power information, etc., which increases the data processing burden of the main control chip and increases the execution time of the algorithm program. Summary of the invention

[0011] The purpose of the present invention is to provide an energy storage control method and an energy storage control system, which abandons the traditional complex and inefficient hierarchical control architecture, adopts a centralized control architecture based on a core main controller, simplifies the overall structure of the control system, and greatly improves the operating efficiency of the system.

[0012] To achieve the above object, the present invention is implemented through the following technical solutions:

[0013] A method for energy storage control, wherein the CPUs in a dual-core DSP chip transmit data information through inter-process communication (IPC), and the two dual-core DSP chips transmit data information using FPGA shared space, as follows:

[0014] The first CPU of the first dual-core DSP chip is responsible for processing the data information of the digital and analog boards of the peripheral expansion unit and executing fault protection through the FPGA chip, and reading the commands and parameters transmitted by the first CPU of the second dual-core DSP chip, completing the calculation of the energy storage converter and off-grid control, and transmitting the calculation results to the FPGA chip;

[0015] The second CPU of the first dual-core DSP chip is responsible for reading the SOC information of each battery cluster, performing intra-phase SOC balancing control, and transmitting the calculated power unit modulation wave variation coefficient to the FPGA chip;

[0016] The first CPU of the second dual-core DSP chip exchanges data with the host computer;

[0017] The second CPU of the second dual-core DSP chip receives the commands and parameters transmitted by the first CPU of the second dual-core DSP chip, executes the system state machine, and transmits the commands and parameters to the first CPU of the first dual-core DSP chip. The second CPU of the second dual-core DSP chip is also responsible for reading and processing the power unit and battery cluster information, and performing fault protection; and transmits the commands and parameters to the first CPU of the first dual-core DSP chip through the FPGA shared space.

[0018] The states corresponding to the system state machine include initialization, self-test, charging preparation, closing standby, operation, shutdown, fault, and reset.

[0019] Fault protection includes stopping charging and discharging, reducing power, fault shutdown, and bypass protection; fault records include waveform records, fault record status indicator lights, etc.

[0020] The energy storage control system includes a main controller, which includes two dual-core DSP chips. Each dual-core DSP chip is connected to an FPGA chip. Each dual-core DSP chip includes two CPUs. Each CPU has its own CLA coprocessor. The two CPUs operate independently. The FPGA chip is connected to a peripheral expansion unit through a port.

[0021] Two dual-core DSP chips are connected to the FPGA chip via a bus.

[0022] The peripheral expansion unit includes a communication board, a touch screen, a digital quantity board, an analog quantity board, a fiber optic expansion board, a unit expansion board and a power unit board.

[0023] The analog board is used to capture real-time data of grid voltage, current and energy storage device current; the digital board is used to collect digital input signals of external devices and transmit them to the first CPU of the first dual-core DSP chip, and is also responsible for sending digital output signals to external devices; the communication board is connected to the whole machine BMS battery management system through a port, and sends the battery cluster information collected by the BMS battery management system to the second CPU of the first dual-core DSP chip.

[0024] The fiber optic extension board is connected to the power unit through a port. Each fiber optic extension board is connected to several power unit boards. The power unit board and the power unit are connected through a port to control the start and stop of the power unit. The fiber optic extension board is responsible for distributing the control information of the main controller to each power unit, and at the same time collects and integrates the status information of the power unit and uploads it to the main controller; the unit expansion board is used to expand the number of connections between the main controller and the power unit.

[0025] A computer device comprises: at least one processor, and a memory connected to the at least one processor in communication, wherein the memory stores instructions executable by the at least one processor, and the instructions are executed by the at least one processor so that the at least one processor executes any one of the energy storage control methods in claims 1-8.

[0026] A computer-readable storage medium, wherein the computer-readable storage medium stores computer instructions, and the computer instructions are used to enable a computer to execute any energy storage control method in claims 1-8.

[0027] Compared with the prior art, the present invention has the following beneficial effects:

[0028] 1. Each CPU has its own CLA coprocessor, which accelerates the calculation process of the control system and improves the execution efficiency of the CPU, thus ensuring the response speed and accuracy of the control system;

[0029] 2. The introduction of FPGA chips enhances the ability of the main controller to interact with the peripheral expansion unit, shortening the time for data reading and control information delivery;

[0030] 3. In order to achieve efficient data interaction between the two DSP chips, the shared space of FPGA is used to achieve fast and reliable data transmission. Each dual-core DSP chip is connected to the FPGA chip;

[0031] 4. The two CPUs inside each dual-core DSP chip run independently of each other, and data transmission between the two cores is realized through IPC, which further improves the parallel processing capability of the system;

[0032] 5. Through the centralized management of the main controller, various functions are executed in a more coordinated and unified manner, thereby improving the reliability and robustness of the energy storage equipment;

[0033] 6. The main controller has powerful processing capabilities and can process information of more than 150 battery clusters and power units at the same time, fully meeting the application requirements of large-capacity energy storage equipment. What is more worth mentioning is that its control frequency is as high as 20kHz, which ensures the rapidity and accuracy of the control system response;

[0034] 7. In terms of algorithm operation speed, the execution content of four CPU cores and four CLA cores is reasonably allocated to shorten the algorithm execution time, laying a solid foundation for high-performance and high-precision control effects;

[0035] 8. The control system is highly scalable and can be easily connected to a variety of external expansion boards to further enrich and expand the system functions. In addition, all system information can be summarized in the main controller for unified processing, making the management and use of information more convenient and efficient. BRIEF DESCRIPTION OF THE DRAWINGS

[0036] Figure 1 This is a schematic diagram of the internal structure of the high-voltage direct-mounted energy storage main controller based on FPGA and two dual-core DSPs.

[0037] Figure 2 It is an energy storage control method and an energy storage control system architecture. DETAILED DESCRIPTION

[0038] The present invention is described in detail below in conjunction with the accompanying drawings, but it should be noted that the implementation of the present invention is not limited to the following embodiments.

[0039] The following examples are implemented on the premise of the technical solution of the present invention, and provide detailed implementation methods and specific operation processes, but the protection scope of the present invention is not limited to the following examples. The methods used in the following examples are conventional methods unless otherwise specified.

[0040] [Example 1]

[0041] In view of the technical deficiencies in the existing energy storage control systems with a grid voltage range of 3kV to 35kV, a new scheme for high-voltage direct-mounted energy storage control systems is proposed. This scheme abandons the traditional complex and inefficient hierarchical control architecture and instead adopts a centralized control architecture with a core main controller as the main body, thereby significantly simplifying the overall structure of the control system and greatly improving the system's operating efficiency.

[0042] A method for controlling energy storage includes a main controller, wherein the main controller includes two dual-core DSP chips. Figure 1, the two CPUs inside each dual-core DSP chip run independently of each other, and realize data transmission between the two cores through IPC (Inter-Process Communication), further improving the parallel processing capability of the system; the two dual-core DSP chips are connected to the FPGA chip through a bus, and use the FPGA shared space to achieve high-speed and reliable data interaction, which is suitable for large-scale data transmission. Each dual-core DSP chip includes two CPUs, and each CPU has its own CLA coprocessor, which enables the control system to quickly process complex calculations and data, thereby ensuring the efficient operation of the control system. The application of CLA coprocessor further accelerates the calculation speed and improves the CPU execution efficiency; the two CPUs inside each dual-core DSP chip run independently of each other, and realize data transmission between the two cores through IPC inter-process communication, further improving the system The parallel processing capability of the system; the FPGA chip is connected to the peripheral expansion unit through a port. The introduction of the FPGA chip enhances the ability of the main controller and the peripheral expansion unit to interact with each other, shortens the time for data reading and control information issuance, and all external information is gathered to the main controller for overall processing, and the main controller issues control instructions uniformly, which improves the overall control efficiency and response speed of the control system, and provides strong technical support for high-voltage and large-capacity direct-mounted energy storage systems; the peripheral expansion unit includes a communication board, a touch screen, a digital quantity board, an analog quantity board, a fiber optic expansion board, a unit expansion board and a power unit board; the unit expansion board is used to expand the number of connections of the main controller; the DSP chip model is F28379d, and the FPGA chip model is Xilinx xc6slx150.

[0043] In the main controller, see Figure 1 The first CPU core is DSP2_CPU1, which focuses on the external communication port function and is responsible for the communication of three RS485 ports and one network port to realize data interaction with local and remote host computers, including real-time waveform upload and fault recording. DSP2_CPU1 interacts with the host computer through the port. The CPU of DSP2_CPU1 is responsible for transmitting the collection and calculation information of other control cores to the touch screen HMI or remote system EMS through the RS485 port, so that users can view the energy storage system status, information, fault records, waveforms and parameter settings in real time.

[0044] The second CPU core is DSP2_CPU2, which mainly processes external instructions, manages the system state machine, reads power unit and battery cluster information, performs fault protection, and calculates display information; DSP2_CPU2 receives host computer instructions and parameters transmitted by DSP2_CPU1, executes the system state machine, and transmits host computer parameters and instructions to the other two CPU cores; in addition, the CPU is also responsible for reading and processing power unit and battery cluster information, performing fault protection, and uploading relevant information to the local or remote interface.

[0045] The third CPU core is DSP1_CPU2, which is mainly responsible for the battery cluster SOC calculation and balancing control strategy; it reads the SOC information of each battery cluster, performs intra-phase SOC balancing control according to the current SOC status of each cluster, the system charging and discharging status and the core algorithm execution results, calculates the power unit modulation wave change coefficient and sends it to the FPGA processor.

[0046] The fourth CPU core is DSP1_CPU1, which is mainly responsible for digital and analog signal processing, fault protection and control algorithm execution; it exchanges data with the digital board and analog board through the FPGA chip, executes fault protection strategies, and reads the configuration parameters and instructions of the host computer; at the same time, it completes the calculation of the control algorithm and passes the results to the FPGA chip.

[0047] As a key hub, the FPGA chip of the main controller is not only responsible for the optical fiber communication with the external expansion unit, but also ensures the real-time interaction of information between the two DSP chips. The FPGA chip pre-processes the received data and accurately distributes the sent data to ensure the efficient operation of the system. More importantly, the FPGA chip can quickly respond to changes in the power unit state and immediately execute fault protection actions, significantly improving the system's protection response speed to the power unit. In the control system, the FPGA chip plays a bridging role, effectively transferring information between the DSP chip and the peripheral control board and the power unit. In addition, the FPGA has a strong expansion capability, supporting six-way optical fiber interface to connect with the communication board, analog board and digital board, and can be expanded to 36-way optical fiber interface to connect the unit expansion board to ensure the flexibility and scalability of the system.

[0048] A type of energy storage control, see Figure 2 The entire high-voltage direct-mounted energy storage control system implements a centralized control architecture around the main controller. The external expansion board serves as an auxiliary device of the main controller. Fiber optic communication is used between the external expansion board and the main controller, and the communication protocol is a custom protocol. The external expansion board mainly includes analog sampling board, digital board, communication board, fiber optic expansion board, and power unit board.

[0049] The analog sampling board is specially used to accurately capture the real-time data of grid voltage, current and energy storage device current. Its sampling frequency is as high as 80kHz to ensure the real-time and accuracy of the data. The sampling results are transmitted to the DS P1_CPU1 of the main controller at high speed via optical fiber, and the data is updated every 50 microseconds, providing timely and reliable analog sampling information for the control system.

[0050] The digital quantity board is responsible for collecting external digital quantity input signals and transmitting them to DSP1_CPU1, and is also responsible for sending digital quantity output signals to external devices.

[0051] The communication board plays a key role in the collection of battery cluster information and the issuance of high-voltage box closing commands; the battery management system adopts a three-level architecture, from the PACK level to the cluster level and then to the whole machine BMS management system, layer by layer, to ensure that the battery information of the entire system is fully and accurately monitored. The communication board is connected to the whole machine BMS management system, responsible for collecting the battery information of each cluster, and summarizing it to the DSP2_CPU2 of the main controller to achieve accurate execution of battery protection and balancing control.

[0052] The spare fiber optic expansion board is directly connected to the main controller and has the ability to expand communication connection peripherals; the 3-way spare fiber optic expansion board has customization capabilities and can replace communication solutions according to different application scenarios.

[0053] The fiber optic expansion board serves as a bridge between the main controller and the power unit and has powerful expansion capabilities. The main controller can be connected to up to 36 fiber optic expansion boards, each of which can be connected to 7 power unit boards, thus building a huge system that can control 252 power units. The fiber optic expansion board is responsible for distributing the control information of the main controller to each power unit, while collecting and integrating the status information of the power unit and uploading it to the main controller to achieve efficient transmission and processing of information.

[0054] The power unit board is the execution unit of the control system, responsible for controlling and protecting the power unit and collecting information.

[0055] As mentioned above, the high-voltage direct-mounted energy storage control system of the present invention takes the main controller as the core and adopts a centralized control architecture. The functions of each expansion board are clear, the core main controller has a fast computing speed, and the external expansion functions are rich, which facilitates system development and maintenance.

[0056] Each CPU of the present invention has its own CLA coprocessor, which accelerates the operation process of the control system and improves the execution efficiency of the CPU, thereby ensuring the response speed and accuracy of the control system; the introduction of the FPGA chip enhances the ability of the main controller to interact with the peripheral expansion unit, shortening the time for data reading and control information issuance; in order to achieve efficient data interaction between the two DSP chips, the shared space of the FPGA is used to achieve fast and reliable data transmission, and each dual-core DSP chip is connected to the FPGA chip; the two CPUs inside each dual-core DSP chip run independently of each other, and data transmission between the dual cores is achieved through IPC, further improving the parallel processing capability of the system; through the centralized management of the main controller, various functions are executed in a more coordinated and unified manner The main controller has powerful processing capabilities and can process information of more than 150 battery clusters and power units at the same time, which fully meets the application needs of large-capacity energy storage equipment. What is more worth mentioning is that its control frequency is as high as 20kHz, which ensures the rapidity and accuracy of the control system response. In terms of algorithm operation speed, the execution content of four CPU cores and four CLA cores is reasonably allocated to shorten the algorithm execution time, laying a solid foundation for high-performance and high-precision control effects. The control system is highly scalable and can easily connect to a variety of external expansion boards to further enrich and expand system functions. In addition, all system information can be aggregated to the main controller for unified processing, making information management and use more convenient and efficient.

Claims

1. A method for controlling energy storage, characterized in that: The CPUs in the dual-core DSP chip transmit data information through inter-process communication IPC, and the two dual-core DSP chips use FPGA shared space to transmit data information. The content is as follows: The first CPU of the first dual-core DSP chip is responsible for processing the data information of the digital and analog boards of the peripheral expansion unit and executing fault protection through the FPGA chip, and reading the commands and parameters transmitted by the first CPU of the second dual-core DSP chip, completing the calculation of the energy storage converter and off-grid control, and transmitting the calculation results to the FPGA chip; The second CPU of the first dual-core DSP chip is responsible for reading the SOC information of each battery cluster, performing intra-phase SOC balancing control, and transmitting the calculated power unit modulation wave variation coefficient to the FPGA chip; The first CPU of the second dual-core DSP chip exchanges data with the host computer; The second CPU of the second dual-core DSP chip receives the commands and parameters transmitted by the first CPU of the second dual-core DSP chip, executes the system state machine, and transmits the commands and parameters to the first CPU of the first dual-core DSP chip. The second CPU of the second dual-core DSP chip is also responsible for reading and processing the power unit and battery cluster information, and performing fault protection; the commands and parameters are transmitted to the first CPU of the first dual-core DSP chip through the FPGA shared space.

2. The energy storage control method according to claim 1, characterized in that: The states corresponding to the system state machine include initialization, self-check, charging preparation, closing standby, operation, shutdown, fault, and reset.

3. The energy storage control method according to claim 1, characterized in that: The fault protection includes stopping charging and discharging, reducing power, fault shutdown, and bypass protection; the fault record includes waveform record, fault record status indicator light, etc.

4. An energy storage control system for implementing the method according to any one of claims 1 to 3, characterized in that: It includes a main controller, which includes two dual-core DSP chips. Each dual-core DSP chip is connected to an FPGA chip. Each dual-core DSP chip includes two CPUs. Each CPU has its own CLA coprocessor. The two CPUs operate independently. The FPGA chip is connected to a peripheral expansion unit through a port.

5. An energy storage control system according to claim 4, characterized in that: The two dual-core DSP chips are connected to the FPGA chip via a bus.

6. An energy storage control system according to claim 4, characterized in that: The peripheral expansion unit includes a communication board, a touch screen, a digital quantity board, an analog quantity board, an optical fiber expansion board, a unit expansion board and a power unit board.

7. An energy storage control system according to claim 6, characterized in that: The analog quantity board is used to capture real-time data of grid voltage, current and energy storage device current; the digital quantity board is used to collect digital input signals of external devices and transmit them to the first CPU of the first dual-core DSP chip, and is also responsible for sending digital output signals to external devices; the communication board is connected to the whole machine BMS battery management system through a port, and sends the information of each battery cluster collected by the BMS battery management system to the second CPU of the first dual-core DSP chip.

8. An energy storage control system according to claim 6, characterized in that: The optical fiber extension board is connected to the power unit through a port, each optical fiber extension board is connected to several power unit boards, and the power unit board and the power unit are connected through a port to control the start and stop of the power unit. The optical fiber extension board is responsible for distributing the control information of the main controller to each power unit, and at the same time collecting and integrating the status information of the power unit and uploading it to the main controller; the unit expansion board is used to expand the number of connections between the main controller and the power unit.

9. A computer device, characterized in that: include: At least one processor, and a memory communicatively connected to the at least one processor, wherein the memory stores instructions executable by the at least one processor, and the instructions are executed by the at least one processor so that the at least one processor executes the energy storage control method described in any one of claims 1-8.

10. A computer-readable storage medium, characterized in that The computer-readable storage medium stores computer instructions, and the computer instructions are used to enable the computer to execute the energy storage control method described in any one of claims 1-8.

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