Energy storage control method and energy storage control system

Abstract

The application relates to an energy storage control method and an energy storage control system. Data information is transmitted between CPUs in a dual-core DSP chip through inter-process communication (IPC), and data information is transmitted between two dual-core DSP chips through FPGA shared space. Each dual-core DSP chip is connected with an FPGA chip, each CPU has a respective CLA coprocessor, two CPUs independently run, and the FPGA chip is connected with a peripheral expansion unit through a port. The application has the following advantages: each CPU has a respective CLA coprocessor, the operation process of the control system is accelerated, the execution efficiency of the CPU is improved, the response speed and accuracy of the control system are ensured; the introduction of the FPGA chip enhances the data interaction capability of the main controller and the peripheral expansion unit, shortens the data reading and control information issuing time; in order to realize efficient data interaction between two DSP chips, the FPGA shared space is used to realize fast and reliable data transmission, and each dual-core DSP chip is connected with an FPGA chip.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of power electronic energy storage, and in particular to an energy storage control method and an energy storage control system. BACKGROUND

[0002] With the continuous improvement of the capacity of energy storage batteries and the increasing perfection of the functions of battery management systems (BMS) and energy management systems (EMS), high-power energy storage applications have been widely promoted. Compared with low-voltage energy storage systems, high-voltage direct-hanging (cascade) energy storage products are showing broad application prospects in large-capacity thermal storage frequency modulation, new energy storage and grid-side fields due to their significant advantages of low cost, high safety, high conversion efficiency and compact footprint.

[0003] High-voltage direct-hanging energy storage products do not require auxiliary equipment such as step-up transformers and DC bus cabinets, and use more optimized and lower-cost liquid cooling systems and energy storage converters (PCS), which not only reduce the cost of energy storage system products, but also improve the charge and discharge cycle efficiency, thereby effectively reducing the investment cost of energy storage projects. This kind of energy storage product uses a cascade energy storage converter (PCS) and does not need to pass through a grid-connected transformer, but directly operates in a 3kV and above voltage level power system through a grid-connected reactor, bringing a new development path to energy storage technology, and is particularly suitable for building large-capacity megawatt energy storage systems.

[0004] A high-voltage direct-hanging energy storage product is composed of an energy storage unit composed of a battery cluster and a converter unit PCS, wherein the converter unit PCS adopts a classic H-bridge series connection method to achieve high-voltage output through amplitude and phase control. The direct current output by each cluster of batteries realizes the bidirectional flow of energy through the bidirectional converter unit PCS, converting the direct current into several hundred volts of alternating current output. Multiple single-phase PCSs with the same structure are connected in series on the alternating current side to form a single-phase high-voltage energy storage product, which is further combined into a three-phase symmetrical high-voltage alternating current matching the grid voltage, thereby realizing the support of grid power and having multiple functions such as frequency and voltage regulation, peak clipping and valley filling.

[0005] However, with the increasing control requirements of high-voltage large-capacity energy storage systems, the traditional control system based on single-chip single-core DSP and FPGA is facing challenges. In the case of an increase in the number of power units and battery clusters, such a control system needs to increase multiple sub-control systems to meet the requirements of data processing timeliness and algorithm execution period, which increases the complexity of system coordinated control. Therefore, in order to meet the control requirements of large-capacity high-voltage direct-hanging energy storage systems, higher requirements are put forward for the data processing timeliness and algorithm execution period of the control system. An ideal control system should be able to process the information of not less than 150 PCS power units and battery clusters at the same time, and ensure that the execution period of the algorithm program is within 50 microseconds, so as to ensure the stable operation and high efficiency of the system.

[0006] Most of the current control systems adopt single-chip single-core DSP and FPGA control core architecture, which needs to adopt multi-level sub-controllers to form a complete control system in the high-voltage direct hanging energy storage system. Such architecture has the following defects:

[0007] 1. Multi-level sub-controllers are needed, the coordination between each controller is more complex, and the fault points of the control system increase, which is troublesome to maintain.

[0008] 2. High cost, each phase needs a sub-controller, and a main controller is also needed, the number of board cards and chips increases.

[0009] 3. The algorithm execution efficiency is reduced, the main controller needs to pass the algorithm to the sub-controller, and then the sub-controller passes it to each unit, which increases the lag of the control algorithm.

[0010] 4. The high-voltage direct hanging energy storage system needs more external ports, mainly including BMS, EMS, air conditioner, water cooling system, fire fighting, switch cabinet state, electric energy information, etc., which increases the data processing burden of the main control chip and the execution time of the algorithm program. SUMMARY

[0011] The purpose of the present application is to provide an energy storage control method and an energy storage control system, which discards the traditional complex and inefficient hierarchical control architecture and adopts a centralized control architecture with a core main controller, simplifying the overall structure of the control system and greatly improving the operation efficiency of the system.

[0012] To achieve the above purpose, the present application realizes the following technical scheme:

[0013] An energy storage control method, the CPU in the dual-core DSP chip transmits data information through inter-process communication IPC, and the two dual-core DSP chips transmit data information through FPGA shared space, as follows:

[0014] The first CPU of the first dual-core DSP chip is responsible for processing the data information of the digital and analog boards of the peripheral expansion unit, executing fault protection, reading the commands and parameters transmitted by the first CPU of the second dual-core DSP chip, completing the calculation of the energy storage converter and off-grid control, and transmitting the calculation results to the FPGA chip;

[0015] The second CPU of the first dual-core DSP chip is responsible for reading the SOC information of each battery cluster, performing intra-phase SOC balancing control, and transmitting the calculated power unit modulation wave variation coefficient to the FPGA chip;

[0016] The first CPU of the second dual-core DSP chip interacts with the upper computer;

[0017] The second CPU of the second dual-core DSP chip receives the command and parameter transmitted by the first CPU of the second dual-core DSP chip, executes the system state machine, and transmits the command and parameter to the first CPU of the first dual-core DSP chip. The second CPU of the second dual-core DSP chip is also responsible for reading and processing power unit and battery cluster information, and performing fault protection; and transmits the command and parameter to the first CPU of the first dual-core DSP chip through the FPGA shared space.

[0018] The corresponding states of the system state machine include initialization, self-checking, charging preparation, closing standby, running, shutdown, fault, and reset.

[0019] The fault protection includes stopping charging and discharging, reducing power, fault shutdown, and bypass protection; the fault record includes waveform record, fault record state indicator, etc.

[0020] The energy storage control system comprises a main controller, the main controller comprises two dual-core DSP chips, each dual-core DSP chip is connected with an FPGA chip, each dual-core DSP chip comprises two CPUs, each CPU has a CLA coprocessor, the two CPUs independently run, and the FPGA chip is connected with a peripheral expansion unit through a port.

[0021] The two dual-core DSP chips are connected with the FPGA chip through a bus.

[0022] The peripheral expansion unit comprises a communication board, a touch screen, a digital quantity board, an analog quantity board, a fiber expansion board, a unit expansion board, and a power unit board.

[0023] The analog quantity board is used for capturing real-time data of grid voltage, current and energy storage device current; the digital quantity board is used for collecting external device digital quantity input signals and transmitting the signals to the first CPU of the first dual-core DSP chip, and is also responsible for sending digital quantity output signals to external devices; the communication board is connected with a whole machine BMS battery management system through a port, and transmits each cluster battery information collected by the BMS battery management system to the second CPU of the first dual-core DSP chip.

[0024] The fiber expansion board is connected with the power unit through a port, each fiber expansion board is connected with a plurality of power unit boards, the power unit board is connected with the power unit through a port, and is used for controlling the start and stop of the power unit, the fiber expansion board is responsible for distributing the control information of the main controller to each power unit, collecting and integrating the state information of the power unit, and uploading the state information to the main controller; the unit expansion board is used for expanding the connection quantity between the main controller and the power unit.

[0025] A computer device comprises at least one processor and a memory connected with the at least one processor in communication, wherein the memory stores instructions executable by the at least one processor, and the instructions are executed by the at least one processor to enable the at least one processor to perform the energy storage control method in any one of claims 1-8.

[0026] A computer readable storage medium stores computer instructions for enabling a computer to perform the energy storage control method in any one of claims 1-8.

[0027] Compared with the prior art, the present application has the following beneficial effects:

[0028] 1. Each CPU has a respective CLA coprocessor, which accelerates the operation process of the control system, improves the execution efficiency of the CPU, and thus ensures the response speed and accuracy of the control system.

[0029] 2. The introduction of the FPGA chip enhances the data interaction capability of the main controller and the peripheral expansion unit, and shortens the data reading and control information issuing time.

[0030] 3. In order to realize efficient data interaction between the two DSP chips, the shared space of the FPGA is utilized to realize fast and reliable data transmission, and each dual-core DSP chip is connected with the FPGA chip.

[0031] 4. The two CPUs inside each dual-core DSP chip operate independently and realize data transmission between the dual cores through IPC, further improving the parallel processing capability of the system.

[0032] 5. Through centralized management of the main controller, each function is executed more coordinately and uniformly, thereby improving the reliability and robustness of the energy storage device.

[0033] 6. The main controller has strong processing capability and can simultaneously process information of more than 150 battery clusters and power units, fully meeting the application requirements of large-capacity energy storage devices, and more notably, its control frequency is as high as 20 kHz or above, ensuring the rapidness and accuracy of the control system response.

[0034] 7. In terms of algorithm operation speed, the execution contents of the four CPU cores and four CLA cores are reasonably allocated to shorten the algorithm execution time and lay a solid foundation for high-performance and high-precision control effect.

[0035] 8. The control system has high expandability and can easily access various external expansion boards to further enrich and expand the system functions, and in addition, all system information can be aggregated to the main controller for unified processing, making the management and use of information more convenient and efficient. BRIEF DESCRIPTION OF DRAWINGS

[0036] Figure 1 is a high-voltage direct-hanging energy storage main controller internal structure schematic diagram based on FPGA and two dual-core DSPs.

[0037] Figure 2 is an energy storage control method and an energy storage control system architecture. DETAILED DESCRIPTION

[0038] The application will be described in detail below with reference to the accompanying drawings of the specification, but it should be pointed out that the implementation of the application is not limited to the following embodiments.

[0039] The following examples are implemented on the premise of the technical solutions of the application, and detailed implementation methods and specific operation processes are given, but the protection scope of the application is not limited to the following examples. The methods used in the following examples are all conventional methods unless otherwise specified.

[0040]

Example 1

[0041] In view of the technical deficiencies in the existing energy storage control system with a voltage range of 3kV to 35kV, a new scheme of high-voltage direct-hanging energy storage control system is proposed. This scheme abandons the traditional complex and inefficient hierarchical control architecture, and instead adopts a centralized control architecture with a core main controller as the main part, thereby significantly simplifying the overall structure of the control system and greatly improving the operating efficiency of the system.

[0042] An energy storage control method includes a main controller, the main controller includes two dual-core DSP chips, see Figure 1The two CPUs in each dual-core DSP chip run independently of each other and realize data transmission between the dual cores through IPC (Inter-Process Communication), further improving the parallel processing capability of the system; the two dual-core DSP chips are connected with the FPGA chip through a bus, and high-speed and reliable data interaction is realized by using the FPGA shared space, which is suitable for large-scale data transmission; each dual-core DSP chip includes two CPUs, and each CPU has a respective CLA coprocessor, so that the control system can quickly process complex calculations and data, thereby ensuring efficient operation of the control system; the application of the CLA coprocessor further accelerates the calculation speed and improves the CPU execution efficiency; the two CPUs in each dual-core DSP chip run independently of each other and realize data transmission between the dual cores through IPC (Inter-Process Communication), further improving the parallel processing capability of the system; the FPGA chip is connected with the peripheral expansion unit through a port, and the introduction of the FPGA chip enhances the data interaction capability of the main controller and the peripheral expansion unit, shortens the data reading and control information issuing time, and all external information is gathered to the main controller for overall processing, and the main controller uniformly issues control instructions, thereby improving the overall control efficiency and response speed of the control system and providing strong technical support for the high-voltage large-capacity direct-hanging energy storage system; the peripheral expansion unit includes a communication board, a touch screen, a digital quantity board, an analog quantity board, a fiber expansion board, a unit expansion board and a power unit board; the unit expansion board is used to expand the connection quantity of the main controller; the DSP chip model is F28379d, and the FPGA chip model is Xilinx xc6slx150.

[0043] In the main controller, as shown in Figure 1 , the first CPU core is DSP2_CPU1, which is dedicated to external communication port functions and is responsible for communication of three RS485 ports and one network port, realizes data interaction with local and remote host computers, including real-time waveform uploading and fault recording, DSP2_CPU1 performs data interaction with the host computer through the port, and the CPU of DSP2_CPU1 is responsible for transmitting the collection and calculation information of other control cores to the touch screen HMI or remote system EMS through the RS485 port, so that the user can view the energy storage system state, information, fault record, waveform and parameter setting in real time.

[0044] The second CPU core is DSP2_CPU2, mainly processing external instructions, managing system state machine, reading power unit and battery cluster information, executing fault protection, calculating display information; DSP2_CPU2 receives the host computer instructions and parameters transmitted by DSP2_CPU1, executes the system state machine, and transmits the host computer parameters and instructions to the other two CPU cores; in addition, the CPU is also responsible for reading and processing power unit and battery cluster information, and performing fault protection, while uploading relevant information to the local or remote interface.

[0045] The third CPU core is DSP1_CPU2, mainly responsible for battery cluster SOC calculation and equalization control strategy; it reads the SOC information of each battery cluster, performs intra-battery SOC equalization control according to the current SOC of each cluster, system charging and discharging state and core algorithm execution result, calculates the power unit modulation wave variation coefficient and sends it to the FPGA processor.

[0046] The fourth CPU core is DSP1_CPU1, mainly responsible for digital and analog signal processing, fault protection and control algorithm execution; it interacts with the digital and analog boards through the FPGA chip, executes the fault protection strategy, and reads the host computer configuration parameters and instructions; at the same time, it completes the calculation of the control algorithm and transmits the results to the FPGA chip.

[0047] The FPGA chip of the main controller not only takes charge of the fiber communication with the external expansion unit, but also ensures the real-time interaction of information between the two DSP chips. The FPGA chip pre-processes the received data and accurately allocates and issues data to ensure the efficient operation of the system. What is particularly important is that the FPGA chip can quickly respond to the state changes of the power unit and immediately execute fault protection actions, significantly improving the protection response speed of the system to the power unit. In the control system, the FPGA chip plays a bridge role between the DSP chip and the peripheral control board and the power unit, effectively transferring information between them. In addition, the FPGA has strong expansion capability, supporting six fiber interfaces and connecting with the communication board, analog board and digital board, and can be expanded to 36 fiber interfaces to connect unit expansion boards, to ensure the flexibility and scalability of the system.

[0048] A kind of energy storage control, see Figure 2 The entire high-voltage direct-hanging energy storage control system realizes centralized control architecture around the main controller, the external expansion board card is used as the auxiliary equipment of the main controller, and the communication between the external expansion board card and the main controller is all in the form of fiber communication, and the communication protocol is a self-defined protocol; the external expansion board card mainly includes an analog sampling board, a digital board, a communication board, a fiber expansion board and a power unit board.

[0049] The analog sampling board is specially used for accurately capturing real-time data of grid voltage, current and energy storage device current, and has a sampling frequency of up to 80 kHz, ensuring the real-time and accuracy of the data; the sampling result is transmitted to the DSP1_CPU1 of the main controller through optical fiber at a high speed, and the data is updated every 50 microseconds, so as to provide timely and reliable analog sampling information for the control system.

[0050] The digital board is responsible for collecting external digital input signals and transmitting them to the DSP1_CPU1, and is also responsible for sending digital output signals to external devices.

[0051] The communication board plays a key role in battery cluster information collection and high-voltage box closing command issuance; the battery management system adopts a three-level architecture, from PACK level to cluster level to whole machine BMS management system, and layer by layer, to ensure that the battery information of the whole system is comprehensively and accurately monitored. The communication board is connected with the whole machine BMS management system, responsible for collecting battery information of each cluster and summarizing to the DSP2_CPU2 of the main controller, to realize accurate execution of battery protection and balancing control.

[0052] The backup optical fiber expansion board is directly connected with the main controller and has the ability to expand the communication connection of external devices; the 3-way backup optical fiber expansion board has customization capability and can change the communication scheme according to different application scenarios.

[0053] The optical fiber expansion board serves as a bridge between the main controller and the power unit, and has strong expansion capability; the main controller can be connected with up to 36 optical fiber expansion boards, and each expansion board can be connected with 7 power unit boards, thereby constructing a large system capable of controlling 252 power units; the optical fiber expansion board is responsible for distributing the control information of the main controller to each power unit, collecting and integrating the state information of the power unit and uploading it to the main controller, to realize efficient transmission and processing of information.

[0054] The power unit board is the execution unit of the control system, responsible for controlling and protecting the power unit and collecting information.

[0055] As described above, the high-voltage direct-hanging energy storage control system of the present application takes the main controller as the core, adopts a centralized control architecture, each expansion board has a clear function, the core main controller has a high operation speed, and the external expansion function is rich, which is convenient for the development and maintenance of the system.

[0056] The application has the CLA coprocessor for each CPU, so that the control system accelerates the operation process, improves the execution efficiency of the CPU, thereby ensuring the response speed and accuracy of the control system; the introduction of the FPGA chip enhances the data interaction capability of the main controller and the peripheral expansion unit, shortens the data reading and control information issuing time; in order to realize the efficient data interaction between the two DSP chips, the shared space of the FPGA is used to realize the fast and reliable data transmission, and each dual-core DSP chip is connected with the FPGA chip; the two CPUs in each dual-core DSP chip run independently, and the data transmission between the dual cores is realized through the IPC, thereby further improving the parallel processing capability of the system; through the centralized management of the main controller, the functions are more coordinated and unified, thereby improving the reliability and robustness of the energy storage equipment; the main controller has strong processing capability, can simultaneously process the information of more than 150 battery clusters and power units, fully meets the demand of large-capacity energy storage equipment application, and more worth mentioning is that the control frequency is as high as 20 kHz or more, thereby ensuring the rapidness and accuracy of the control system response; in terms of algorithm operation speed, the execution content of the four CPU cores and the four CLA cores is reasonably distributed, the algorithm execution time is shortened, and a solid foundation is laid for the high-performance and high-precision control effect; the control system has high expansibility, can conveniently access various external expansion boards, realizes the further enrichment and expansion of the system functions, and in addition, all system information can be collected to the main controller for unified processing, so that the information management and use are more convenient and efficient.

Claims

1. An energy storage control method, characterized by, The CPUs in the dual-core DSP chip transfer data information through inter-process communication (IPC), and the two dual-core DSP chips transfer data information through FPGA shared space, as follows: The first CPU of the first dual-core DSP chip is responsible for processing data information of digital and analog boards of the peripheral expansion unit and executing fault protection, and reading commands and parameters transmitted by the first CPU of the second dual-core DSP chip, completing calculation of the energy storage converter and off-grid control, and transmitting the calculation results to the FPGA chip; The second CPU of the first dual-core DSP chip is responsible for reading SOC information of each battery cluster, performing intra-phase SOC balancing control, and transmitting the calculated power unit modulation wave variation coefficient to the FPGA chip; The first CPU of the second dual-core DSP chip interacts with the upper computer for data; The second CPU of the second dual-core DSP chip receives commands and parameters transmitted by the first CPU of the second dual-core DSP chip, executes a system state machine, and transmits the commands and parameters to the first CPU of the first dual-core DSP chip, and the second CPU of the second dual-core DSP chip is also responsible for reading and processing power unit and battery cluster information, and performing fault protection; the commands and parameters are transmitted to the first CPU of the first dual-core DSP chip through the FPGA shared space.

2. The energy storage control method of claim 1, wherein, The states corresponding to the system state machine include initialization, self-checking, charging preparation, closing standby, running, shutdown, fault, and reset.

3. The energy storage control method of claim 1, wherein, The fault protection includes stopping charging and discharging, reducing power, fault shutdown, and bypass protection; fault recording includes waveform recording, fault recording state indicator light, etc.

4. An energy storage control system for implementing the method of any one of claims 1-3, characterized by The system includes a main controller, the main controller includes two dual-core DSP chips, each dual-core DSP chip is connected with an FPGA chip, each dual-core DSP chip includes two CPUs, each CPU has a CLA coprocessor, the two CPUs run independently, and the FPGA chip is connected with a peripheral expansion unit through a port.

5. An energy storage control system according to claim 4, wherein, The two dual-core DSP chips are connected with the FPGA chip through a bus.

6. The energy storage control system of claim 4, wherein, The peripheral expansion unit includes a communication board, a touch screen, a digital board, an analog board, a fiber expansion board, a unit expansion board, and a power unit board.

7. An energy storage control system according to claim 6, wherein, The analog board is used to capture real-time data of grid voltage, current, and energy storage device current; the digital board is used to collect external device digital input signals and transmit them to the first CPU of the first dual-core DSP chip, and is also responsible for sending digital output signals to external devices; the communication board is connected with a whole machine BMS battery management system through a port, and transmits each cluster battery information collected by the BMS battery management system to the second CPU of the first dual-core DSP chip.

8. The energy storage control system of claim 6, wherein, The optical fiber expansion board is connected with the power unit through a port, each optical fiber expansion board is connected with several power unit boards, the power unit board is connected with the power unit through a port, and the power unit board is used for controlling start and stop of the power unit; the optical fiber expansion board is responsible for distributing control information of a main controller to each power unit, collecting and integrating state information of the power unit, and uploading the state information to the main controller; and the unit expansion board is used for expanding the connection quantity of the main controller and the power unit.

9. A computer device, comprising: Comprise: At least one processor, and a memory connected with the at least one processor in communication, wherein the memory stores instructions executable by the at least one processor, and the instructions are executed by the at least one processor to cause the at least one processor to perform the energy storage control method of any one of claims 1-3.

10. A computer readable storage medium, characterized in that, The computer readable storage medium stores computer instructions, and the computer instructions are used to cause the computer to execute the energy storage control method of any one of claims 1-3.

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